1 //===- XCoreInstrInfo.h - XCore Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef XCOREINSTRUCTIONINFO_H
15 #define XCOREINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "XCoreRegisterInfo.h"
22 class XCoreInstrInfo : public TargetInstrInfoImpl {
23 const XCoreRegisterInfo RI;
27 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
28 /// such, whenever a client has an instance of instruction info, it should
29 /// always be able to get register info as well (through this method).
31 virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
33 /// isLoadFromStackSlot - If the specified machine instruction is a direct
34 /// load from a stack slot, return the virtual or physical register number of
35 /// the destination along with the FrameIndex of the loaded stack slot. If
36 /// not, return 0. This predicate must return 0 if the instruction has
37 /// any side effects other than loading from the stack slot.
38 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
39 int &FrameIndex) const;
41 /// isStoreToStackSlot - If the specified machine instruction is a direct
42 /// store to a stack slot, return the virtual or physical register number of
43 /// the source reg along with the FrameIndex of the loaded stack slot. If
44 /// not, return 0. This predicate must return 0 if the instruction has
45 /// any side effects other than storing to the stack slot.
46 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
47 int &FrameIndex) const;
49 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
50 MachineBasicBlock *&FBB,
51 SmallVectorImpl<MachineOperand> &Cond,
52 bool AllowModify) const;
54 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
55 MachineBasicBlock *FBB,
56 const SmallVectorImpl<MachineOperand> &Cond,
59 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
61 virtual void copyPhysReg(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator I, DebugLoc DL,
63 unsigned DestReg, unsigned SrcReg,
66 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
67 MachineBasicBlock::iterator MI,
68 unsigned SrcReg, bool isKill, int FrameIndex,
69 const TargetRegisterClass *RC,
70 const TargetRegisterInfo *TRI) const;
72 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator MI,
74 unsigned DestReg, int FrameIndex,
75 const TargetRegisterClass *RC,
76 const TargetRegisterInfo *TRI) const;
78 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator MI,
80 const std::vector<CalleeSavedInfo> &CSI,
81 const TargetRegisterInfo *TRI) const;
83 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MI,
85 const std::vector<CalleeSavedInfo> &CSI,
86 const TargetRegisterInfo *TRI) const;
88 virtual bool ReverseBranchCondition(
89 SmallVectorImpl<MachineOperand> &Cond) const;