1 //===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the XCore instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
35 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>;
38 def SDT_XCoreEhRet : SDTypeProfile<0, 2,
39 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
40 def XCoreEhRet : SDNode<"XCoreISD::EH_RETURN", SDT_XCoreEhRet,
41 [SDNPHasChain, SDNPOptInGlue]>;
43 def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
44 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
46 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,
49 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,
52 def SDT_XCoreAddress : SDTypeProfile<1, 1,
53 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
55 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
58 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
61 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
64 def frametoargsoffset : SDNode<"XCoreISD::FRAME_TO_ARGS_OFFSET", SDTIntLeaf,
67 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
68 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
69 [SDNPHasChain, SDNPMayStore]>;
71 // These are target-independent nodes, but have target-specific formats.
72 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
73 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
76 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
81 def SDT_XCoreMEMBARRIER : SDTypeProfile<0, 0, []>;
83 def XCoreMemBarrier : SDNode<"XCoreISD::MEMBARRIER", SDT_XCoreMEMBARRIER,
86 //===----------------------------------------------------------------------===//
87 // Instruction Pattern Stuff
88 //===----------------------------------------------------------------------===//
90 def div4_xform : SDNodeXForm<imm, [{
91 // Transformation function: imm/4
92 assert(N->getZExtValue() % 4 == 0);
93 return getI32Imm(N->getZExtValue()/4);
96 def msksize_xform : SDNodeXForm<imm, [{
97 // Transformation function: get the size of a mask
98 assert(isMask_32(N->getZExtValue()));
99 // look for the first non-zero bit
100 return getI32Imm(32 - countLeadingZeros((uint32_t)N->getZExtValue()));
103 def neg_xform : SDNodeXForm<imm, [{
104 // Transformation function: -imm
105 uint32_t value = N->getZExtValue();
106 return getI32Imm(-value);
109 def bpwsub_xform : SDNodeXForm<imm, [{
110 // Transformation function: 32-imm
111 uint32_t value = N->getZExtValue();
112 return getI32Imm(32-value);
115 def div4neg_xform : SDNodeXForm<imm, [{
116 // Transformation function: -imm/4
117 uint32_t value = N->getZExtValue();
118 assert(-value % 4 == 0);
119 return getI32Imm(-value/4);
122 def immUs4Neg : PatLeaf<(imm), [{
123 uint32_t value = (uint32_t)N->getZExtValue();
124 return (-value)%4 == 0 && (-value)/4 <= 11;
127 def immUs4 : PatLeaf<(imm), [{
128 uint32_t value = (uint32_t)N->getZExtValue();
129 return value%4 == 0 && value/4 <= 11;
132 def immUsNeg : PatLeaf<(imm), [{
133 return -((uint32_t)N->getZExtValue()) <= 11;
136 def immUs : PatLeaf<(imm), [{
137 return (uint32_t)N->getZExtValue() <= 11;
140 def immU6 : PatLeaf<(imm), [{
141 return (uint32_t)N->getZExtValue() < (1 << 6);
144 def immU10 : PatLeaf<(imm), [{
145 return (uint32_t)N->getZExtValue() < (1 << 10);
148 def immU16 : PatLeaf<(imm), [{
149 return (uint32_t)N->getZExtValue() < (1 << 16);
152 def immU20 : PatLeaf<(imm), [{
153 return (uint32_t)N->getZExtValue() < (1 << 20);
156 def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;
158 def immBitp : PatLeaf<(imm), [{
159 uint32_t value = (uint32_t)N->getZExtValue();
160 return (value >= 1 && value <= 8)
166 def immBpwSubBitp : PatLeaf<(imm), [{
167 uint32_t value = (uint32_t)N->getZExtValue();
168 return (value >= 24 && value <= 31)
174 def lda16f : PatFrag<(ops node:$addr, node:$offset),
175 (add node:$addr, (shl node:$offset, 1))>;
176 def lda16b : PatFrag<(ops node:$addr, node:$offset),
177 (sub node:$addr, (shl node:$offset, 1))>;
178 def ldawf : PatFrag<(ops node:$addr, node:$offset),
179 (add node:$addr, (shl node:$offset, 2))>;
180 def ldawb : PatFrag<(ops node:$addr, node:$offset),
181 (sub node:$addr, (shl node:$offset, 2))>;
183 // Instruction operand types
184 def pcrel_imm : Operand<i32>;
185 def pcrel_imm_neg : Operand<i32> {
186 let DecoderMethod = "DecodeNegImmOperand";
188 def brtarget : Operand<OtherVT>;
189 def brtarget_neg : Operand<OtherVT> {
190 let DecoderMethod = "DecodeNegImmOperand";
194 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
197 def MEMii : Operand<i32> {
198 let MIOperandInfo = (ops i32imm, i32imm);
202 def InlineJT : Operand<i32> {
203 let PrintMethod = "printInlineJT";
206 def InlineJT32 : Operand<i32> {
207 let PrintMethod = "printInlineJT32";
210 //===----------------------------------------------------------------------===//
211 // Instruction Class Templates
212 //===----------------------------------------------------------------------===//
214 // Three operand short
216 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
217 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
218 !strconcat(OpcStr, " $dst, $b, $c"),
219 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
220 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
221 !strconcat(OpcStr, " $dst, $b, $c"),
222 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
225 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
226 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
227 !strconcat(OpcStr, " $dst, $b, $c"), []>;
228 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
229 !strconcat(OpcStr, " $dst, $b, $c"), []>;
232 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
234 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
235 !strconcat(OpcStr, " $dst, $b, $c"),
236 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
237 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
238 !strconcat(OpcStr, " $dst, $b, $c"),
239 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
242 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
243 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
244 !strconcat(OpcStr, " $dst, $b, $c"),
245 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
247 class F3R_np<bits<5> opc, string OpcStr> :
248 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
249 !strconcat(OpcStr, " $dst, $b, $c"), []>;
250 // Three operand long
252 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
253 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
255 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
256 !strconcat(OpcStr, " $dst, $b, $c"),
257 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
258 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
259 !strconcat(OpcStr, " $dst, $b, $c"),
260 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
263 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
264 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
266 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
267 !strconcat(OpcStr, " $dst, $b, $c"),
268 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
269 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
270 !strconcat(OpcStr, " $dst, $b, $c"),
271 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
274 class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
275 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
276 !strconcat(OpcStr, " $dst, $b, $c"),
277 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
280 // Operand register - U6
281 multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> {
282 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
283 !strconcat(OpcStr, " $a, $b"), []>;
284 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
285 !strconcat(OpcStr, " $a, $b"), []>;
288 multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> {
289 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b),
290 !strconcat(OpcStr, " $a, $b"), []>;
291 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b),
292 !strconcat(OpcStr, " $a, $b"), []>;
297 multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> {
298 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
299 [(OpNode immU6:$a)]>;
300 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
301 [(OpNode immU16:$a)]>;
304 multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> {
305 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
307 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
311 multiclass FU6_LU6_np<bits<10> opc, string OpcStr> {
312 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
313 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
318 class F2R_np<bits<6> opc, string OpcStr> :
319 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),
320 !strconcat(OpcStr, " $dst, $b"), []>;
324 //===----------------------------------------------------------------------===//
325 // Pseudo Instructions
326 //===----------------------------------------------------------------------===//
328 let Defs = [SP], Uses = [SP] in {
329 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
330 "# ADJCALLSTACKDOWN $amt",
331 [(callseq_start timm:$amt)]>;
332 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
333 "# ADJCALLSTACKUP $amt1",
334 [(callseq_end timm:$amt1, timm:$amt2)]>;
337 let isReMaterializable = 1 in
338 def FRAME_TO_ARGS_OFFSET : PseudoInstXCore<(outs GRRegs:$dst), (ins),
339 "# FRAME_TO_ARGS_OFFSET $dst",
340 [(set GRRegs:$dst, (frametoargsoffset))]>;
342 let isReturn = 1, isTerminator = 1, isBarrier = 1 in
343 def EH_RETURN : PseudoInstXCore<(outs), (ins GRRegs:$s, GRRegs:$handler),
344 "# EH_RETURN $s, $handler",
345 [(XCoreEhRet GRRegs:$s, GRRegs:$handler)]>;
347 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
348 "# LDWFI $dst, $addr",
349 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
351 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
352 "# LDAWFI $dst, $addr",
353 [(set GRRegs:$dst, ADDRspii:$addr)]>;
355 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
356 "# STWFI $src, $addr",
357 [(store GRRegs:$src, ADDRspii:$addr)]>;
359 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
360 // instruction selection into a branch sequence.
361 let usesCustomInserter = 1 in {
362 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
363 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
364 "# SELECT_CC PSEUDO!",
366 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
369 let hasSideEffects = 1 in
370 def Int_MemBarrier : PseudoInstXCore<(outs), (ins), "#MEMBARRIER",
371 [(XCoreMemBarrier)]>;
373 //===----------------------------------------------------------------------===//
375 //===----------------------------------------------------------------------===//
377 // Three operand short
378 defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
379 defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;
380 let neverHasSideEffects = 1 in {
381 defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">;
382 def LSS_3r : F3R_np<0b11000, "lss">;
383 def LSU_3r : F3R_np<0b11001, "lsu">;
385 def AND_3r : F3R<0b00111, "and", and>;
386 def OR_3r : F3R<0b01000, "or", or>;
389 def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),
390 (ins GRRegs:$addr, GRRegs:$offset),
391 "ldw $dst, $addr[$offset]", []>;
393 def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst),
394 (ins GRRegs:$addr, i32imm:$offset),
395 "ldw $dst, $addr[$offset]", []>;
397 def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),
398 (ins GRRegs:$addr, GRRegs:$offset),
399 "ld16s $dst, $addr[$offset]", []>;
401 def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst),
402 (ins GRRegs:$addr, GRRegs:$offset),
403 "ld8u $dst, $addr[$offset]", []>;
407 def STW_l3r : _FL3R<0b000001100, (outs),
408 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
409 "stw $val, $addr[$offset]", []>;
411 def STW_2rus : _F2RUS<0b0000, (outs),
412 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
413 "stw $val, $addr[$offset]", []>;
416 defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
417 defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
419 // The first operand is treated as an immediate since it refers to a register
420 // number in another thread.
421 def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c),
422 "set t[$c]:r$a, $b", []>;
424 // Three operand long
425 def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),
426 (ins GRRegs:$addr, GRRegs:$offset),
427 "ldaw $dst, $addr[$offset]",
429 (ldawf GRRegs:$addr, GRRegs:$offset))]>;
431 let neverHasSideEffects = 1 in
432 def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst),
433 (ins GRRegs:$addr, i32imm:$offset),
434 "ldaw $dst, $addr[$offset]", []>;
436 def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst),
437 (ins GRRegs:$addr, GRRegs:$offset),
438 "ldaw $dst, $addr[-$offset]",
440 (ldawb GRRegs:$addr, GRRegs:$offset))]>;
442 let neverHasSideEffects = 1 in
443 def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst),
444 (ins GRRegs:$addr, i32imm:$offset),
445 "ldaw $dst, $addr[-$offset]", []>;
447 def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst),
448 (ins GRRegs:$addr, GRRegs:$offset),
449 "lda16 $dst, $addr[$offset]",
451 (lda16f GRRegs:$addr, GRRegs:$offset))]>;
453 def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst),
454 (ins GRRegs:$addr, GRRegs:$offset),
455 "lda16 $dst, $addr[-$offset]",
457 (lda16b GRRegs:$addr, GRRegs:$offset))]>;
459 def MUL_l3r : FL3R<0b001111100, "mul", mul>;
460 // Instructions which may trap are marked as side effecting.
461 let hasSideEffects = 1 in {
462 def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>;
463 def DIVU_l3r : FL3R<0b010011100, "divu", udiv>;
464 def REMS_l3r : FL3R<0b110001100, "rems", srem>;
465 def REMU_l3r : FL3R<0b110011100, "remu", urem>;
467 def XOR_l3r : FL3R<0b000011100, "xor", xor>;
468 defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>;
470 let Constraints = "$src1 = $dst" in
471 def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst),
472 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
473 "crc32 $dst, $src2, $src3",
475 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
479 def ST16_l3r : _FL3R<0b100001100, (outs),
480 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
481 "st16 $val, $addr[$offset]", []>;
483 def ST8_l3r : _FL3R<0b100011100, (outs),
484 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
485 "st8 $val, $addr[$offset]", []>;
488 def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a),
489 (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c",
492 def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs),
493 (ins GRRegs:$a, GRRegs:$b, i32imm:$c),
494 "outpw res[$b], $a, $c", []>;
497 let Constraints = "$e = $a,$f = $b" in {
498 def MACCU_l4r : _FL4RSrcDstSrcDst<
499 0b000001, (outs GRRegs:$a, GRRegs:$b),
500 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>;
502 def MACCS_l4r : _FL4RSrcDstSrcDst<
503 0b000010, (outs GRRegs:$a, GRRegs:$b),
504 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>;
507 let Constraints = "$e = $b" in
508 def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b),
509 (ins GRRegs:$e, GRRegs:$c, GRRegs:$d),
510 "crc8 $b, $a, $c, $d", []>;
514 def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2),
515 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
516 "ladd $dst2, $dst1, $src1, $src2, $src3",
519 def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2),
520 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
521 "lsub $dst2, $dst1, $src1, $src2, $src3", []>;
523 def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2),
524 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
525 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
529 def LMUL_l6r : _FL6R<
530 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2),
531 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
532 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
536 //let Uses = [DP] in ...
537 let neverHasSideEffects = 1, isReMaterializable = 1 in
538 def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b),
539 "ldaw $a, dp[$b]", []>;
541 let isReMaterializable = 1 in
542 def LDAWDP_lru6: _FLRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b),
544 [(set RRegs:$a, (dprelwrapper tglobaladdr:$b))]>;
547 def LDWDP_ru6: _FRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b),
548 "ldw $a, dp[$b]", []>;
550 def LDWDP_lru6: _FLRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b),
552 [(set RRegs:$a, (load (dprelwrapper tglobaladdr:$b)))]>;
555 def STWDP_ru6 : _FRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b),
556 "stw $a, dp[$b]", []>;
558 def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b),
560 [(store RRegs:$a, (dprelwrapper tglobaladdr:$b))]>;
562 //let Uses = [CP] in ..
563 let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in {
564 def LDWCP_ru6 : _FRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b),
565 "ldw $a, cp[$b]", []>;
566 def LDWCP_lru6: _FLRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b),
568 [(set RRegs:$a, (load (cprelwrapper tglobaladdr:$b)))]>;
573 def STWSP_ru6 : _FRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b),
575 [(XCoreStwsp RRegs:$a, immU6:$b)]>;
577 def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b),
579 [(XCoreStwsp RRegs:$a, immU16:$b)]>;
583 def LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),
584 "ldw $a, sp[$b]", []>;
586 def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),
587 "ldw $a, sp[$b]", []>;
590 let neverHasSideEffects = 1 in {
591 def LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
592 "ldaw $a, sp[$b]", []>;
594 def LDAWSP_lru6 : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
595 "ldaw $a, sp[$b]", []>;
599 let isReMaterializable = 1 in {
600 def LDC_ru6 : _FRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b),
601 "ldc $a, $b", [(set RRegs:$a, immU6:$b)]>;
603 def LDC_lru6 : _FLRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b),
604 "ldc $a, $b", [(set RRegs:$a, immU16:$b)]>;
607 def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
609 [(int_xcore_setc GRRegs:$a, immU6:$b)]>;
611 def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
613 [(int_xcore_setc GRRegs:$a, immU16:$b)]>;
615 // Operand register - U6
616 let isBranch = 1, isTerminator = 1 in {
617 defm BRFT: FRU6_LRU6_branch<0b011100, "bt">;
618 defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">;
619 defm BRFF: FRU6_LRU6_branch<0b011110, "bf">;
620 defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">;
624 let Defs = [SP], Uses = [SP] in {
625 let neverHasSideEffects = 1 in
626 defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">;
629 defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">;
631 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
632 defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>;
636 let neverHasSideEffects = 1 in
637 defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">;
639 let Uses = [R11], isCall=1 in
640 defm BLAT : FU6_LU6_np<0b0111001101, "blat">;
642 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
643 def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>;
645 def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>;
647 def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
649 def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
652 //let Uses = [CP] in ...
653 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
654 def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]",
657 let Defs = [R11], isReMaterializable = 1 in
658 def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]",
659 [(set R11, (cprelwrapper tglobaladdr:$a))]>;
662 defm GETSR : FU6_LU6_np<0b0111111100, "getsr r11,">;
664 defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>;
666 defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>;
668 // setsr may cause a branch if it is used to enable events. clrsr may
669 // branch if it is executed while events are enabled.
670 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
671 isCodeGenOnly = 1 in {
672 defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">;
673 defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">;
676 defm KCALL : FU6_LU6_np<0b0111001111, "kcall">;
678 let Uses = [SP], Defs = [SP], mayStore = 1 in
679 defm KENTSP : FU6_LU6_np<0b0111101110, "kentsp">;
681 let Uses = [SP], Defs = [SP], mayLoad = 1 in
682 defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">;
686 let Defs = [R11], isReMaterializable = 1 in {
687 let neverHasSideEffects = 1 in
688 def LDAPF_u10 : _FU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", []>;
690 def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a",
691 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
693 let neverHasSideEffects = 1 in
694 def LDAPB_u10 : _FU10<0b110111, (outs), (ins pcrel_imm_neg:$a), "ldap r11, $a",
697 let neverHasSideEffects = 1 in
698 def LDAPB_lu10 : _FLU10<0b110111, (outs), (ins pcrel_imm_neg:$a),
700 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
702 let isCodeGenOnly = 1 in
703 def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a",
704 [(set R11, (pcrelwrapper tblockaddress:$a))]>;
708 // All calls clobber the link register and the non-callee-saved registers:
709 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
710 def BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>;
712 def BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>;
714 def BLRF_u10 : _FU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a",
715 [(XCoreBranchLink immU10:$a)]>;
717 def BLRF_lu10 : _FLU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a",
718 [(XCoreBranchLink immU20:$a)]>;
720 def BLRB_u10 : _FU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>;
722 def BLRB_lu10 : _FLU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>;
725 let Defs = [R11], mayLoad = 1, isReMaterializable = 1,
726 neverHasSideEffects = 1 in {
727 def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>;
729 def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]",
734 def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),
735 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;
737 def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),
738 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
740 let Constraints = "$src1 = $dst" in {
742 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
744 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
748 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
750 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
753 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
755 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
759 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
761 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
764 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
765 "andnot $dst, $src2",
766 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
769 let isReMaterializable = 1, neverHasSideEffects = 1 in
770 def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size),
771 "mkmsk $dst, $size", []>;
773 def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),
775 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
777 def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type),
779 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
781 def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r),
782 "getts $dst, res[$r]",
783 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
785 def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val),
786 "setpt res[$r], $val",
787 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
789 def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),
790 "outct res[$r], $val",
791 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
793 def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val),
794 "outct res[$r], $val",
795 [(int_xcore_outct GRRegs:$r, immUs:$val)]>;
797 def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val),
798 "outt res[$r], $val",
799 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
801 def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val),
803 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
805 let Constraints = "$src = $dst" in
807 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
808 "outshr res[$r], $src",
809 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
811 def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r),
812 "inct $dst, res[$r]",
813 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
815 def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r),
817 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
819 def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r),
821 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;
823 let Constraints = "$src = $dst" in
825 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
826 "inshr $dst, res[$r]",
827 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
829 def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),
830 "chkct res[$r], $val",
831 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
833 def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val),
834 "chkct res[$r], $val",
835 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
837 def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src),
838 "testct $dst, res[$src]",
839 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>;
841 def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src),
842 "testwct $dst, res[$src]",
843 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>;
845 def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val),
846 "setd res[$r], $val",
847 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
849 def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
850 "setpsc res[$src1], $src2",
851 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
853 def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r),
854 "getst $dst, res[$r]",
855 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;
857 def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t),
858 "init t[$t]:sp, $src",
859 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;
861 def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t),
862 "init t[$t]:pc, $src",
863 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;
865 def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t),
866 "init t[$t]:cp, $src",
867 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;
869 def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t),
870 "init t[$t]:dp, $src",
871 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
873 def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src),
874 "peek $dst, res[$src]",
875 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;
877 def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src),
878 "endin $dst, res[$src]",
879 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
881 def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b),
882 "eef $a, res[$b]", []>;
884 def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b),
885 "eet $a, res[$b]", []>;
887 def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b),
888 "tsetmr r$a, $b", []>;
891 def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),
893 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
895 def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src),
896 "byterev $dst, $src",
897 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
899 def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src),
901 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
903 def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src),
904 "getd $dst, res[$src]", []>;
906 def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src),
907 "getn $dst, res[$src]", []>;
909 def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val),
910 "setc res[$r], $val",
911 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;
913 def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val),
914 "settw res[$r], $val",
915 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;
917 def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src),
918 "get $dst, ps[$src]",
919 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>;
921 def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
922 "set ps[$src1], $src2",
923 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;
925 def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t),
926 "init t[$t]:lr, $src",
927 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>;
929 def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2),
930 "setclk res[$src1], $src2",
931 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;
933 def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
934 "setn res[$src1], $src2", []>;
936 def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
937 "setrdy res[$src1], $src2",
938 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
940 def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src),
941 "testlcl $dst, res[$src]", []>;
944 def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
946 [(int_xcore_msync GRRegs:$a)]>;
947 def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a),
949 [(int_xcore_mjoin GRRegs:$a)]>;
951 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
952 def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a),
954 [(brind GRRegs:$a)]>;
956 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
957 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
959 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;
961 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
962 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
964 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
966 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
967 def BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>;
969 let Defs=[SP], neverHasSideEffects=1 in
970 def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>;
972 let neverHasSideEffects=1 in
973 def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>;
975 let neverHasSideEffects=1 in
976 def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>;
978 let hasCtrlDep = 1 in
979 def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a),
983 let hasCtrlDep = 1 in
984 def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a),
989 // All calls clobber the link register and the non-callee-saved registers:
990 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
991 def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a),
993 [(XCoreBranchLink GRRegs:$a)]>;
996 def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a),
998 [(int_xcore_syncr GRRegs:$a)]>;
1000 def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a),
1002 [(int_xcore_freer GRRegs:$a)]>;
1005 def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a),
1006 "setv res[$a], r11",
1007 [(int_xcore_setv GRRegs:$a, R11)]>;
1009 def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),
1010 "setev res[$a], r11",
1011 [(int_xcore_setev GRRegs:$a, R11)]>;
1014 def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>;
1016 def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", []>;
1018 def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
1020 [(int_xcore_eeu GRRegs:$a)]>;
1022 def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>;
1024 def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>;
1026 def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>;
1028 def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>;
1030 def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", []>;
1032 // Zero operand short
1034 def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
1036 def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>;
1038 let Defs = [SP], Uses = [SP] in
1039 def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>;
1042 def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>;
1044 def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>;
1046 def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>;
1048 let Defs = [R11] in {
1049 def GETID_0R : _F0R<0b0001001110, (outs), (ins),
1051 [(set R11, (int_xcore_getid))]>;
1053 def GETED_0R : _F0R<0b0000111110, (outs), (ins),
1055 [(set R11, (int_xcore_geted))]>;
1057 def GETET_0R : _F0R<0b0000111111, (outs), (ins),
1059 [(set R11, (int_xcore_getet))]>;
1061 def GETKEP_0R : _F0R<0b0001001111, (outs), (ins),
1062 "get r11, kep", []>;
1064 def GETKSP_0R : _F0R<0b0001011100, (outs), (ins),
1065 "get r11, ksp", []>;
1069 def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>;
1071 let Uses = [SP], mayLoad = 1 in {
1072 def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>;
1074 def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>;
1076 def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>;
1078 def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>;
1082 def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>;
1084 def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),
1086 [(int_xcore_ssync)]>;
1088 let Uses = [SP], mayStore = 1 in {
1089 def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>;
1091 def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>;
1093 def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>;
1095 def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>;
1098 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
1099 hasSideEffects = 1 in
1100 def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),
1102 [(brind (int_xcore_waitevent))]>;
1104 //===----------------------------------------------------------------------===//
1105 // Non-Instruction Patterns
1106 //===----------------------------------------------------------------------===//
1108 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BLRF_lu10 tglobaladdr:$addr)>;
1109 def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>;
1112 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
1113 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
1114 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
1117 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1118 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1119 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1121 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1122 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1123 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1125 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
1126 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
1127 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
1128 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1129 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
1132 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1133 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1134 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1135 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1136 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1137 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1140 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
1141 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1142 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
1143 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1145 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
1146 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1147 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
1148 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1150 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
1151 (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1152 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
1153 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
1154 def : Pat<(store GRRegs:$val, GRRegs:$addr),
1155 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
1158 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
1161 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
1167 // unconditional branch
1168 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
1170 // direct match equal/notequal zero brcond
1171 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
1172 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
1173 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
1174 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
1176 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1177 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1178 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1179 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1180 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1181 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1182 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1183 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1184 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1185 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1186 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
1187 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
1189 // generic brcond pattern
1190 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
1197 // direct match equal/notequal zero select
1198 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1199 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1201 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1202 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1204 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1205 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1206 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1207 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1208 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1209 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1210 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1211 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1212 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1213 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1214 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
1215 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
1218 /// setcc patterns, only matched when none of the above brcond
1222 // setcc 2 register operands
1223 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
1224 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1225 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
1226 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1228 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1229 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
1230 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
1231 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
1233 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
1234 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1235 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
1236 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1238 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
1239 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
1240 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
1241 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
1243 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
1244 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1246 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
1247 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
1249 // setcc reg/imm operands
1250 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
1251 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
1252 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
1253 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
1256 def : Pat<(add GRRegs:$addr, immUs4:$offset),
1257 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1259 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
1260 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1262 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
1263 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
1265 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1266 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
1267 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
1269 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
1270 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
1276 def : Pat<(mul GRRegs:$src, 3),
1277 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
1279 def : Pat<(mul GRRegs:$src, 5),
1280 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
1282 def : Pat<(mul GRRegs:$src, -3),
1283 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
1285 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
1286 def : Pat<(sra GRRegs:$src, 31),
1287 (ASHR_l2rus GRRegs:$src, 32)>;
1289 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1290 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1292 // setge X, 0 is canonicalized to setgt X, -1
1293 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1294 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1296 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1297 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
1299 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1300 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
1302 def : Pat<(setgt GRRegs:$lhs, -1),
1303 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
1305 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
1306 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;
1308 def : Pat<(load (cprelwrapper tconstpool:$b)),
1309 (LDWCP_lru6 tconstpool:$b)>;
1311 def : Pat<(cprelwrapper tconstpool:$b),
1312 (LDAWCP_lu6 tconstpool:$b)>;