1 //===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the XCore instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
35 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>;
38 def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
41 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,
44 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,
47 def SDT_XCoreAddress : SDTypeProfile<1, 1,
48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
53 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
56 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
59 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
60 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
61 [SDNPHasChain, SDNPMayStore]>;
63 // These are target-independent nodes, but have target-specific formats.
64 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
65 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
68 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
69 [SDNPHasChain, SDNPOutGlue]>;
70 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
71 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
73 //===----------------------------------------------------------------------===//
74 // Instruction Pattern Stuff
75 //===----------------------------------------------------------------------===//
77 def div4_xform : SDNodeXForm<imm, [{
78 // Transformation function: imm/4
79 assert(N->getZExtValue() % 4 == 0);
80 return getI32Imm(N->getZExtValue()/4);
83 def msksize_xform : SDNodeXForm<imm, [{
84 // Transformation function: get the size of a mask
85 assert(isMask_32(N->getZExtValue()));
86 // look for the first non-zero bit
87 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue()));
90 def neg_xform : SDNodeXForm<imm, [{
91 // Transformation function: -imm
92 uint32_t value = N->getZExtValue();
93 return getI32Imm(-value);
96 def bpwsub_xform : SDNodeXForm<imm, [{
97 // Transformation function: 32-imm
98 uint32_t value = N->getZExtValue();
99 return getI32Imm(32-value);
102 def div4neg_xform : SDNodeXForm<imm, [{
103 // Transformation function: -imm/4
104 uint32_t value = N->getZExtValue();
105 assert(-value % 4 == 0);
106 return getI32Imm(-value/4);
109 def immUs4Neg : PatLeaf<(imm), [{
110 uint32_t value = (uint32_t)N->getZExtValue();
111 return (-value)%4 == 0 && (-value)/4 <= 11;
114 def immUs4 : PatLeaf<(imm), [{
115 uint32_t value = (uint32_t)N->getZExtValue();
116 return value%4 == 0 && value/4 <= 11;
119 def immUsNeg : PatLeaf<(imm), [{
120 return -((uint32_t)N->getZExtValue()) <= 11;
123 def immUs : PatLeaf<(imm), [{
124 return (uint32_t)N->getZExtValue() <= 11;
127 def immU6 : PatLeaf<(imm), [{
128 return (uint32_t)N->getZExtValue() < (1 << 6);
131 def immU10 : PatLeaf<(imm), [{
132 return (uint32_t)N->getZExtValue() < (1 << 10);
135 def immU16 : PatLeaf<(imm), [{
136 return (uint32_t)N->getZExtValue() < (1 << 16);
139 def immU20 : PatLeaf<(imm), [{
140 return (uint32_t)N->getZExtValue() < (1 << 20);
143 def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;
145 def immBitp : PatLeaf<(imm), [{
146 uint32_t value = (uint32_t)N->getZExtValue();
147 return (value >= 1 && value <= 8)
153 def immBpwSubBitp : PatLeaf<(imm), [{
154 uint32_t value = (uint32_t)N->getZExtValue();
155 return (value >= 24 && value <= 31)
161 def lda16f : PatFrag<(ops node:$addr, node:$offset),
162 (add node:$addr, (shl node:$offset, 1))>;
163 def lda16b : PatFrag<(ops node:$addr, node:$offset),
164 (sub node:$addr, (shl node:$offset, 1))>;
165 def ldawf : PatFrag<(ops node:$addr, node:$offset),
166 (add node:$addr, (shl node:$offset, 2))>;
167 def ldawb : PatFrag<(ops node:$addr, node:$offset),
168 (sub node:$addr, (shl node:$offset, 2))>;
170 // Instruction operand types
171 def calltarget : Operand<i32>;
172 def calltarget_neg : Operand<i32> {
173 let DecoderMethod = "DecodeNegImmOperand";
175 def brtarget : Operand<OtherVT>;
176 def brtarget_neg : Operand<OtherVT> {
177 let DecoderMethod = "DecodeNegImmOperand";
181 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
184 def MEMii : Operand<i32> {
185 let MIOperandInfo = (ops i32imm, i32imm);
189 def InlineJT : Operand<i32> {
190 let PrintMethod = "printInlineJT";
193 def InlineJT32 : Operand<i32> {
194 let PrintMethod = "printInlineJT32";
197 //===----------------------------------------------------------------------===//
198 // Instruction Class Templates
199 //===----------------------------------------------------------------------===//
201 // Three operand short
203 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
204 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
205 !strconcat(OpcStr, " $dst, $b, $c"),
206 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
207 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
208 !strconcat(OpcStr, " $dst, $b, $c"),
209 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
212 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
213 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
214 !strconcat(OpcStr, " $dst, $b, $c"), []>;
215 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
216 !strconcat(OpcStr, " $dst, $b, $c"), []>;
219 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
221 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
222 !strconcat(OpcStr, " $dst, $b, $c"),
223 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
224 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
225 !strconcat(OpcStr, " $dst, $b, $c"),
226 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
229 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
230 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
231 !strconcat(OpcStr, " $dst, $b, $c"),
232 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
234 class F3R_np<bits<5> opc, string OpcStr> :
235 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
236 !strconcat(OpcStr, " $dst, $b, $c"), []>;
237 // Three operand long
239 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
240 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
242 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
243 !strconcat(OpcStr, " $dst, $b, $c"),
244 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
245 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
246 !strconcat(OpcStr, " $dst, $b, $c"),
247 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
250 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
251 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
253 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
254 !strconcat(OpcStr, " $dst, $b, $c"),
255 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
256 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
257 !strconcat(OpcStr, " $dst, $b, $c"),
258 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
261 class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
262 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
263 !strconcat(OpcStr, " $dst, $b, $c"),
264 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
267 // Operand register - U6
268 multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> {
269 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
270 !strconcat(OpcStr, " $a, $b"), []>;
271 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
272 !strconcat(OpcStr, " $a, $b"), []>;
275 multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> {
276 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b),
277 !strconcat(OpcStr, " $a, $b"), []>;
278 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b),
279 !strconcat(OpcStr, " $a, $b"), []>;
282 multiclass FRU6_LRU6_cp<bits<6> opc, string OpcStr> {
283 def _ru6: _FRU6<opc, (outs RRegs:$a), (ins i32imm:$b),
284 !strconcat(OpcStr, " $a, cp[$b]"), []>;
285 def _lru6: _FLRU6<opc, (outs RRegs:$a), (ins i32imm:$b),
286 !strconcat(OpcStr, " $a, cp[$b]"), []>;
290 multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> {
291 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
292 [(OpNode immU6:$a)]>;
293 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
294 [(OpNode immU16:$a)]>;
297 multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> {
298 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
300 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
304 multiclass FU6_LU6_np<bits<10> opc, string OpcStr> {
305 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
306 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
311 class F2R_np<bits<6> opc, string OpcStr> :
312 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),
313 !strconcat(OpcStr, " $dst, $b"), []>;
317 //===----------------------------------------------------------------------===//
318 // Pseudo Instructions
319 //===----------------------------------------------------------------------===//
321 let Defs = [SP], Uses = [SP] in {
322 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
323 "# ADJCALLSTACKDOWN $amt",
324 [(callseq_start timm:$amt)]>;
325 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
326 "# ADJCALLSTACKUP $amt1",
327 [(callseq_end timm:$amt1, timm:$amt2)]>;
330 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
331 "# LDWFI $dst, $addr",
332 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
334 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
335 "# LDAWFI $dst, $addr",
336 [(set GRRegs:$dst, ADDRspii:$addr)]>;
338 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
339 "# STWFI $src, $addr",
340 [(store GRRegs:$src, ADDRspii:$addr)]>;
342 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
343 // instruction selection into a branch sequence.
344 let usesCustomInserter = 1 in {
345 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
346 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
347 "# SELECT_CC PSEUDO!",
349 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
352 //===----------------------------------------------------------------------===//
354 //===----------------------------------------------------------------------===//
356 // Three operand short
357 defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
358 defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;
359 let neverHasSideEffects = 1 in {
360 defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">;
361 def LSS_3r : F3R_np<0b11000, "lss">;
362 def LSU_3r : F3R_np<0b11001, "lsu">;
364 def AND_3r : F3R<0b00111, "and", and>;
365 def OR_3r : F3R<0b01000, "or", or>;
368 def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),
369 (ins GRRegs:$addr, GRRegs:$offset),
370 "ldw $dst, $addr[$offset]", []>;
372 def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst),
373 (ins GRRegs:$addr, i32imm:$offset),
374 "ldw $dst, $addr[$offset]", []>;
376 def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),
377 (ins GRRegs:$addr, GRRegs:$offset),
378 "ld16s $dst, $addr[$offset]", []>;
380 def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst),
381 (ins GRRegs:$addr, GRRegs:$offset),
382 "ld8u $dst, $addr[$offset]", []>;
386 def STW_l3r : _FL3R<0b000001100, (outs),
387 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
388 "stw $val, $addr[$offset]", []>;
390 def STW_2rus : _F2RUS<0b0000, (outs),
391 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
392 "stw $val, $addr[$offset]", []>;
395 defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
396 defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
398 // The first operand is treated as an immediate since it refers to a register
399 // number in another thread.
400 def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c),
401 "set t[$c]:r$a, $b", []>;
403 // Three operand long
404 def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),
405 (ins GRRegs:$addr, GRRegs:$offset),
406 "ldaw $dst, $addr[$offset]",
408 (ldawf GRRegs:$addr, GRRegs:$offset))]>;
410 let neverHasSideEffects = 1 in
411 def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst),
412 (ins GRRegs:$addr, i32imm:$offset),
413 "ldaw $dst, $addr[$offset]", []>;
415 def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst),
416 (ins GRRegs:$addr, GRRegs:$offset),
417 "ldaw $dst, $addr[-$offset]",
419 (ldawb GRRegs:$addr, GRRegs:$offset))]>;
421 let neverHasSideEffects = 1 in
422 def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst),
423 (ins GRRegs:$addr, i32imm:$offset),
424 "ldaw $dst, $addr[-$offset]", []>;
426 def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst),
427 (ins GRRegs:$addr, GRRegs:$offset),
428 "lda16 $dst, $addr[$offset]",
430 (lda16f GRRegs:$addr, GRRegs:$offset))]>;
432 def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst),
433 (ins GRRegs:$addr, GRRegs:$offset),
434 "lda16 $dst, $addr[-$offset]",
436 (lda16b GRRegs:$addr, GRRegs:$offset))]>;
438 def MUL_l3r : FL3R<0b001111100, "mul", mul>;
439 // Instructions which may trap are marked as side effecting.
440 let hasSideEffects = 1 in {
441 def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>;
442 def DIVU_l3r : FL3R<0b010011100, "divu", udiv>;
443 def REMS_l3r : FL3R<0b110001100, "rems", srem>;
444 def REMU_l3r : FL3R<0b110011100, "remu", urem>;
446 def XOR_l3r : FL3R<0b000011100, "xor", xor>;
447 defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>;
449 let Constraints = "$src1 = $dst" in
450 def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst),
451 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
452 "crc32 $dst, $src2, $src3",
454 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
458 def ST16_l3r : _FL3R<0b100001100, (outs),
459 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
460 "st16 $val, $addr[$offset]", []>;
462 def ST8_l3r : _FL3R<0b100011100, (outs),
463 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
464 "st8 $val, $addr[$offset]", []>;
467 def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a),
468 (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c",
471 def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs),
472 (ins GRRegs:$a, GRRegs:$b, i32imm:$c),
473 "outpw res[$b], $a, $c", []>;
476 let Constraints = "$e = $a,$f = $b" in {
477 def MACCU_l4r : _FL4RSrcDstSrcDst<
478 0b000001, (outs GRRegs:$a, GRRegs:$b),
479 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>;
481 def MACCS_l4r : _FL4RSrcDstSrcDst<
482 0b000010, (outs GRRegs:$a, GRRegs:$b),
483 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>;
486 let Constraints = "$e = $b" in
487 def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b),
488 (ins GRRegs:$e, GRRegs:$c, GRRegs:$d),
489 "crc8 $b, $a, $c, $d", []>;
493 def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2),
494 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
495 "ladd $dst2, $dst1, $src1, $src2, $src3",
498 def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2),
499 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
500 "lsub $dst2, $dst1, $src1, $src2, $src3", []>;
502 def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2),
503 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
504 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
508 def LMUL_l6r : _FL6R<
509 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2),
510 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
511 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
515 //let Uses = [DP] in ...
516 let neverHasSideEffects = 1, isReMaterializable = 1 in
517 def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b),
518 "ldaw $a, dp[$b]", []>;
520 let isReMaterializable = 1 in
521 def LDAWDP_lru6: _FLRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b),
523 [(set RRegs:$a, (dprelwrapper tglobaladdr:$b))]>;
526 def LDWDP_ru6: _FRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b),
527 "ldw $a, dp[$b]", []>;
529 def LDWDP_lru6: _FLRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b),
531 [(set RRegs:$a, (load (dprelwrapper tglobaladdr:$b)))]>;
534 def STWDP_ru6 : _FRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b),
535 "stw $a, dp[$b]", []>;
537 def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b),
539 [(store RRegs:$a, (dprelwrapper tglobaladdr:$b))]>;
541 //let Uses = [CP] in ..
542 let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in
543 defm LDWCP : FRU6_LRU6_cp<0b011011, "ldw">;
547 def STWSP_ru6 : _FRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b),
549 [(XCoreStwsp RRegs:$a, immU6:$b)]>;
551 def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b),
553 [(XCoreStwsp RRegs:$a, immU16:$b)]>;
557 def LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),
558 "ldw $a, sp[$b]", []>;
560 def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),
561 "ldw $a, sp[$b]", []>;
564 let neverHasSideEffects = 1 in {
565 def LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
566 "ldaw $a, sp[$b]", []>;
568 def LDAWSP_lru6 : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
569 "ldaw $a, sp[$b]", []>;
573 let isReMaterializable = 1 in {
574 def LDC_ru6 : _FRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b),
575 "ldc $a, $b", [(set RRegs:$a, immU6:$b)]>;
577 def LDC_lru6 : _FLRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b),
578 "ldc $a, $b", [(set RRegs:$a, immU16:$b)]>;
581 def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
583 [(int_xcore_setc GRRegs:$a, immU6:$b)]>;
585 def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
587 [(int_xcore_setc GRRegs:$a, immU16:$b)]>;
589 // Operand register - U6
590 let isBranch = 1, isTerminator = 1 in {
591 defm BRFT: FRU6_LRU6_branch<0b011100, "bt">;
592 defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">;
593 defm BRFF: FRU6_LRU6_branch<0b011110, "bf">;
594 defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">;
598 let Defs = [SP], Uses = [SP] in {
599 let neverHasSideEffects = 1 in
600 defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">;
603 defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">;
605 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
606 defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>;
610 let neverHasSideEffects = 1 in
611 defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">;
613 let Uses = [R11], isCall=1 in
614 defm BLAT : FU6_LU6_np<0b0111001101, "blat">;
616 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
617 def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>;
619 def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>;
621 def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
623 def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
626 //let Uses = [CP] in ...
627 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
628 def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]",
631 let Defs = [R11], isReMaterializable = 1 in
632 def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]",
633 [(set R11, (cprelwrapper tglobaladdr:$a))]>;
636 defm GETSR : FU6_LU6_np<0b0111111100, "getsr r11,">;
638 defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>;
640 defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>;
642 // setsr may cause a branch if it is used to enable events. clrsr may
643 // branch if it is executed while events are enabled.
644 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
645 isCodeGenOnly = 1 in {
646 defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">;
647 defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">;
650 defm KCALL : FU6_LU6_np<0b0111001111, "kcall">;
652 let Uses = [SP], Defs = [SP], mayStore = 1 in
653 defm KENTSP : FU6_LU6_np<0b0111101110, "kentsp">;
655 let Uses = [SP], Defs = [SP], mayLoad = 1 in
656 defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">;
660 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
661 def LDAPF_u10 : _FU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", []>;
663 let Defs = [R11], isReMaterializable = 1 in
664 def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a",
665 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
667 let Defs = [R11], isReMaterializable = 1, isCodeGenOnly = 1 in
668 def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a",
669 [(set R11, (pcrelwrapper tblockaddress:$a))]>;
672 // All calls clobber the link register and the non-callee-saved registers:
673 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
674 def BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>;
676 def BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>;
678 def BLRF_u10 : _FU10<0b110100, (outs), (ins calltarget:$a), "bl $a",
679 [(XCoreBranchLink immU10:$a)]>;
681 def BLRF_lu10 : _FLU10<0b110100, (outs), (ins calltarget:$a), "bl $a",
682 [(XCoreBranchLink immU20:$a)]>;
684 def BLRB_u10 : _FU10<0b110101, (outs), (ins calltarget_neg:$a), "bl $a", []>;
686 def BLRB_lu10 : _FLU10<0b110101, (outs), (ins calltarget_neg:$a), "bl $a", []>;
689 let Defs = [R11], mayLoad = 1, isReMaterializable = 1,
690 neverHasSideEffects = 1 in {
691 def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>;
693 def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]",
698 def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),
699 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;
701 def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),
702 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
704 let Constraints = "$src1 = $dst" in {
706 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
708 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
712 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
714 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
717 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
719 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
723 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
725 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
728 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
729 "andnot $dst, $src2",
730 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
733 let isReMaterializable = 1, neverHasSideEffects = 1 in
734 def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size),
735 "mkmsk $dst, $size", []>;
737 def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),
739 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
741 def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type),
743 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
745 def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r),
746 "getts $dst, res[$r]",
747 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
749 def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val),
750 "setpt res[$r], $val",
751 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
753 def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),
754 "outct res[$r], $val",
755 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
757 def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val),
758 "outct res[$r], $val",
759 [(int_xcore_outct GRRegs:$r, immUs:$val)]>;
761 def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val),
762 "outt res[$r], $val",
763 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
765 def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val),
767 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
769 let Constraints = "$src = $dst" in
771 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
772 "outshr res[$r], $src",
773 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
775 def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r),
776 "inct $dst, res[$r]",
777 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
779 def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r),
781 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
783 def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r),
785 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;
787 let Constraints = "$src = $dst" in
789 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
790 "inshr $dst, res[$r]",
791 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
793 def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),
794 "chkct res[$r], $val",
795 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
797 def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val),
798 "chkct res[$r], $val",
799 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
801 def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src),
802 "testct $dst, res[$src]",
803 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>;
805 def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src),
806 "testwct $dst, res[$src]",
807 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>;
809 def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val),
810 "setd res[$r], $val",
811 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
813 def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
814 "setpsc res[$src1], $src2",
815 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
817 def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r),
818 "getst $dst, res[$r]",
819 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;
821 def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t),
822 "init t[$t]:sp, $src",
823 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;
825 def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t),
826 "init t[$t]:pc, $src",
827 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;
829 def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t),
830 "init t[$t]:cp, $src",
831 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;
833 def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t),
834 "init t[$t]:dp, $src",
835 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
837 def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src),
838 "peek $dst, res[$src]",
839 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;
841 def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src),
842 "endin $dst, res[$src]",
843 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
845 def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b),
846 "eef $a, res[$b]", []>;
848 def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b),
849 "eet $a, res[$b]", []>;
851 def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b),
852 "tsetmr r$a, $b", []>;
855 def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),
857 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
859 def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src),
860 "byterev $dst, $src",
861 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
863 def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src),
865 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
867 def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src),
868 "getd $dst, res[$src]", []>;
870 def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src),
871 "getn $dst, res[$src]", []>;
873 def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val),
874 "setc res[$r], $val",
875 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;
877 def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val),
878 "settw res[$r], $val",
879 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;
881 def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src),
882 "get $dst, ps[$src]",
883 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>;
885 def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
886 "set ps[$src1], $src2",
887 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;
889 def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t),
890 "init t[$t]:lr, $src",
891 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>;
893 def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2),
894 "setclk res[$src1], $src2",
895 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;
897 def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
898 "setn res[$src1], $src2", []>;
900 def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
901 "setrdy res[$src1], $src2",
902 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
904 def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src),
905 "testlcl $dst, res[$src]", []>;
908 def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
910 [(int_xcore_msync GRRegs:$a)]>;
911 def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a),
913 [(int_xcore_mjoin GRRegs:$a)]>;
915 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
916 def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a),
918 [(brind GRRegs:$a)]>;
920 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
921 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
923 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;
925 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
926 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
928 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
930 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
931 def BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>;
933 let Defs=[SP], neverHasSideEffects=1 in
934 def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>;
936 let neverHasSideEffects=1 in
937 def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>;
939 let neverHasSideEffects=1 in
940 def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>;
942 let hasCtrlDep = 1 in
943 def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a),
947 let hasCtrlDep = 1 in
948 def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a),
953 // All calls clobber the link register and the non-callee-saved registers:
954 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
955 def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a),
957 [(XCoreBranchLink GRRegs:$a)]>;
960 def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a),
962 [(int_xcore_syncr GRRegs:$a)]>;
964 def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a),
966 [(int_xcore_freer GRRegs:$a)]>;
969 def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a),
971 [(int_xcore_setv GRRegs:$a, R11)]>;
973 def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),
974 "setev res[$a], r11",
975 [(int_xcore_setev GRRegs:$a, R11)]>;
978 def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>;
980 def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", []>;
982 def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
984 [(int_xcore_eeu GRRegs:$a)]>;
986 def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>;
988 def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>;
990 def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>;
992 def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>;
994 def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", []>;
996 // Zero operand short
998 def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
1000 def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>;
1002 let Defs = [SP], Uses = [SP] in
1003 def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>;
1006 def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>;
1008 def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>;
1010 def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>;
1012 let Defs = [R11] in {
1013 def GETID_0R : _F0R<0b0001001110, (outs), (ins),
1015 [(set R11, (int_xcore_getid))]>;
1017 def GETED_0R : _F0R<0b0000111110, (outs), (ins),
1019 [(set R11, (int_xcore_geted))]>;
1021 def GETET_0R : _F0R<0b0000111111, (outs), (ins),
1023 [(set R11, (int_xcore_getet))]>;
1025 def GETKEP_0R : _F0R<0b0001001111, (outs), (ins),
1026 "get r11, kep", []>;
1028 def GETKSP_0R : _F0R<0b0001011100, (outs), (ins),
1029 "get r11, ksp", []>;
1033 def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>;
1035 let Uses = [SP], mayLoad = 1 in {
1036 def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>;
1038 def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>;
1040 def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>;
1042 def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>;
1046 def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>;
1048 def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),
1050 [(int_xcore_ssync)]>;
1052 let Uses = [SP], mayStore = 1 in {
1053 def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>;
1055 def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>;
1057 def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>;
1059 def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>;
1062 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
1063 hasSideEffects = 1 in
1064 def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),
1066 [(brind (int_xcore_waitevent))]>;
1068 //===----------------------------------------------------------------------===//
1069 // Non-Instruction Patterns
1070 //===----------------------------------------------------------------------===//
1072 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BLRF_lu10 tglobaladdr:$addr)>;
1073 def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>;
1076 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
1077 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
1078 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
1081 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1082 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1083 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1085 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1086 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1087 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1089 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
1090 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
1091 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
1092 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1093 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
1096 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1097 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1098 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1099 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1100 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1101 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1104 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
1105 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1106 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
1107 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1109 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
1110 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1111 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
1112 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1114 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
1115 (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1116 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
1117 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
1118 def : Pat<(store GRRegs:$val, GRRegs:$addr),
1119 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
1122 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
1125 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
1131 // unconditional branch
1132 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
1134 // direct match equal/notequal zero brcond
1135 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
1136 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
1137 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
1138 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
1140 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1141 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1142 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1143 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1144 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1145 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1146 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1147 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1148 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1149 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1150 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
1151 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
1153 // generic brcond pattern
1154 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
1161 // direct match equal/notequal zero select
1162 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1163 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1165 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1166 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1168 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1169 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1170 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1171 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1172 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1173 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1174 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1175 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1176 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1177 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1178 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
1179 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
1182 /// setcc patterns, only matched when none of the above brcond
1186 // setcc 2 register operands
1187 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
1188 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1189 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
1190 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1192 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1193 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
1194 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
1195 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
1197 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
1198 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1199 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
1200 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1202 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
1203 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
1204 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
1205 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
1207 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
1208 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1210 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
1211 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
1213 // setcc reg/imm operands
1214 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
1215 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
1216 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
1217 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
1220 def : Pat<(add GRRegs:$addr, immUs4:$offset),
1221 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1223 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
1224 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1226 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
1227 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
1229 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1230 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
1231 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
1233 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
1234 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
1240 def : Pat<(mul GRRegs:$src, 3),
1241 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
1243 def : Pat<(mul GRRegs:$src, 5),
1244 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
1246 def : Pat<(mul GRRegs:$src, -3),
1247 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
1249 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
1250 def : Pat<(sra GRRegs:$src, 31),
1251 (ASHR_l2rus GRRegs:$src, 32)>;
1253 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1254 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1256 // setge X, 0 is canonicalized to setgt X, -1
1257 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1258 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1260 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1261 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
1263 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1264 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
1266 def : Pat<(setgt GRRegs:$lhs, -1),
1267 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
1269 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
1270 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;