1 //===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the XCore instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // Feature predicates.
27 //===----------------------------------------------------------------------===//
29 // HasXS1A - This predicate is true when the target processor supports XS1A
31 def HasXS1A : Predicate<"Subtarget.isXS1A()">;
33 // HasXS1B - This predicate is true when the target processor supports XS1B
35 def HasXS1B : Predicate<"Subtarget.isXS1B()">;
37 //===----------------------------------------------------------------------===//
38 // XCore specific DAG Nodes.
42 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
43 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
44 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
46 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTNone,
47 [SDNPHasChain, SDNPOptInFlag]>;
49 def SDT_XCoreAddress : SDTypeProfile<1, 1,
50 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
52 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
55 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
58 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
61 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
62 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
65 // These are target-independent nodes, but have target-specific formats.
66 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
67 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
70 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
71 [SDNPHasChain, SDNPOutFlag]>;
72 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
73 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
75 //===----------------------------------------------------------------------===//
76 // Instruction Pattern Stuff
77 //===----------------------------------------------------------------------===//
79 def div4_xform : SDNodeXForm<imm, [{
80 // Transformation function: imm/4
81 assert(N->getZExtValue() % 4 == 0);
82 return getI32Imm(N->getZExtValue()/4);
85 def msksize_xform : SDNodeXForm<imm, [{
86 // Transformation function: get the size of a mask
87 assert(isMask_32(N->getZExtValue()));
88 // look for the first non-zero bit
89 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue()));
92 def neg_xform : SDNodeXForm<imm, [{
93 // Transformation function: -imm
94 uint32_t value = N->getZExtValue();
95 return getI32Imm(-value);
98 def div4neg_xform : SDNodeXForm<imm, [{
99 // Transformation function: -imm/4
100 uint32_t value = N->getZExtValue();
101 assert(-value % 4 == 0);
102 return getI32Imm(-value/4);
105 def immUs4Neg : PatLeaf<(imm), [{
106 uint32_t value = (uint32_t)N->getZExtValue();
107 return (-value)%4 == 0 && (-value)/4 <= 11;
110 def immUs4 : PatLeaf<(imm), [{
111 uint32_t value = (uint32_t)N->getZExtValue();
112 return value%4 == 0 && value/4 <= 11;
115 def immUsNeg : PatLeaf<(imm), [{
116 return -((uint32_t)N->getZExtValue()) <= 11;
119 def immUs : PatLeaf<(imm), [{
120 return (uint32_t)N->getZExtValue() <= 11;
123 def immU6 : PatLeaf<(imm), [{
124 return (uint32_t)N->getZExtValue() < (1 << 6);
127 def immU10 : PatLeaf<(imm), [{
128 return (uint32_t)N->getZExtValue() < (1 << 10);
131 def immU16 : PatLeaf<(imm), [{
132 return (uint32_t)N->getZExtValue() < (1 << 16);
135 def immU20 : PatLeaf<(imm), [{
136 return (uint32_t)N->getZExtValue() < (1 << 20);
139 // FIXME check subtarget. Currently we check if the immediate
140 // is in the common subset of legal immediate values for both
142 def immMskBitp : PatLeaf<(imm), [{
143 uint32_t value = (uint32_t)N->getZExtValue();
144 if (!isMask_32(value)) {
147 int msksize = 32 - CountLeadingZeros_32(value);
148 return (msksize >= 1 && msksize <= 8)
154 // FIXME check subtarget. Currently we check if the immediate
155 // is in the common subset of legal immediate values for both
157 def immBitp : PatLeaf<(imm), [{
158 uint32_t value = (uint32_t)N->getZExtValue();
159 return (value >= 1 && value <= 8)
165 def lda16f : PatFrag<(ops node:$addr, node:$offset),
166 (add node:$addr, (shl node:$offset, 1))>;
167 def lda16b : PatFrag<(ops node:$addr, node:$offset),
168 (sub node:$addr, (shl node:$offset, 1))>;
169 def ldawf : PatFrag<(ops node:$addr, node:$offset),
170 (add node:$addr, (shl node:$offset, 2))>;
171 def ldawb : PatFrag<(ops node:$addr, node:$offset),
172 (sub node:$addr, (shl node:$offset, 2))>;
174 // Instruction operand types
175 def calltarget : Operand<i32>;
176 def brtarget : Operand<OtherVT>;
177 def pclabel : Operand<i32>;
180 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
181 def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper],
183 def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper],
187 def MEMii : Operand<i32> {
188 let PrintMethod = "printMemOperand";
189 let MIOperandInfo = (ops i32imm, i32imm);
192 //===----------------------------------------------------------------------===//
193 // Instruction Class Templates
194 //===----------------------------------------------------------------------===//
196 // Three operand short
198 multiclass F3R_2RUS<string OpcStr, SDNode OpNode> {
200 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
201 !strconcat(OpcStr, " $dst, $b, $c"),
202 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
204 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
205 !strconcat(OpcStr, " $dst, $b, $c"),
206 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
209 multiclass F3R_2RUS_np<string OpcStr> {
211 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
212 !strconcat(OpcStr, " $dst, $b, $c"),
215 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
216 !strconcat(OpcStr, " $dst, $b, $c"),
220 multiclass F3R_2RBITP<string OpcStr, SDNode OpNode> {
222 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
223 !strconcat(OpcStr, " $dst, $b, $c"),
224 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
226 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
227 !strconcat(OpcStr, " $dst, $b, $c"),
228 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
231 class F3R<string OpcStr, SDNode OpNode> : _F3R<
232 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
233 !strconcat(OpcStr, " $dst, $b, $c"),
234 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
236 class F3R_np<string OpcStr> : _F3R<
237 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
238 !strconcat(OpcStr, " $dst, $b, $c"),
240 // Three operand long
242 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
243 multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> {
245 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
246 !strconcat(OpcStr, " $dst, $b, $c"),
247 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
248 def _l2rus : _FL2RUS<
249 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
250 !strconcat(OpcStr, " $dst, $b, $c"),
251 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
254 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
255 multiclass FL3R_L2RBITP<string OpcStr, SDNode OpNode> {
257 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
258 !strconcat(OpcStr, " $dst, $b, $c"),
259 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
260 def _l2rus : _FL2RUS<
261 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
262 !strconcat(OpcStr, " $dst, $b, $c"),
263 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
266 class FL3R<string OpcStr, SDNode OpNode> : _FL3R<
267 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
268 !strconcat(OpcStr, " $dst, $b, $c"),
269 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
272 // Operand register - U6
273 multiclass FRU6_LRU6_branch<string OpcStr> {
275 (outs), (ins GRRegs:$cond, brtarget:$dest),
276 !strconcat(OpcStr, " $cond, $dest"),
279 (outs), (ins GRRegs:$cond, brtarget:$dest),
280 !strconcat(OpcStr, " $cond, $dest"),
284 multiclass FRU6_LRU6_cp<string OpcStr> {
286 (outs GRRegs:$dst), (ins i32imm:$a),
287 !strconcat(OpcStr, " $dst, cp[$a]"),
290 (outs GRRegs:$dst), (ins i32imm:$a),
291 !strconcat(OpcStr, " $dst, cp[$a]"),
296 multiclass FU6_LU6<string OpcStr, SDNode OpNode> {
298 (outs), (ins i32imm:$b),
299 !strconcat(OpcStr, " $b"),
300 [(OpNode immU6:$b)]>;
302 (outs), (ins i32imm:$b),
303 !strconcat(OpcStr, " $b"),
304 [(OpNode immU16:$b)]>;
307 multiclass FU6_LU6_np<string OpcStr> {
309 (outs), (ins i32imm:$b),
310 !strconcat(OpcStr, " $b"),
313 (outs), (ins i32imm:$b),
314 !strconcat(OpcStr, " $b"),
319 multiclass FU10_LU10_np<string OpcStr> {
321 (outs), (ins i32imm:$b),
322 !strconcat(OpcStr, " $b"),
325 (outs), (ins i32imm:$b),
326 !strconcat(OpcStr, " $b"),
332 class F2R_np<string OpcStr> : _F2R<
333 (outs GRRegs:$dst), (ins GRRegs:$b),
334 !strconcat(OpcStr, " $dst, $b"),
339 //===----------------------------------------------------------------------===//
340 // Pseudo Instructions
341 //===----------------------------------------------------------------------===//
343 let Defs = [SP], Uses = [SP] in {
344 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
345 "${:comment} ADJCALLSTACKDOWN $amt",
346 [(callseq_start timm:$amt)]>;
347 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
348 "${:comment} ADJCALLSTACKUP $amt1",
349 [(callseq_end timm:$amt1, timm:$amt2)]>;
352 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
353 // scheduler into a branch sequence.
354 let usesCustomDAGSchedInserter = 1 in {
355 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
356 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
357 "${:comment} SELECT_CC PSEUDO!",
359 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
362 //===----------------------------------------------------------------------===//
364 //===----------------------------------------------------------------------===//
366 // Three operand short
367 defm ADD : F3R_2RUS<"add", add>;
368 defm SUB : F3R_2RUS<"sub", sub>;
369 let neverHasSideEffects = 1 in {
370 defm EQ : F3R_2RUS_np<"eq">;
371 def LSS_3r : F3R_np<"lss">;
372 def LSU_3r : F3R_np<"lsu">;
374 def AND_3r : F3R<"and", and>;
375 def OR_3r : F3R<"or", or>;
378 def LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
379 "ldw $dst, $addr[$offset]",
382 def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset),
383 "ldw $dst, $addr[$offset]",
386 def LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
387 "ld16s $dst, $addr[$offset]",
390 def LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
391 "ld8u $dst, $addr[$offset]",
396 def STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
397 "stw $val, $addr[$offset]",
400 def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
401 "stw $val, $addr[$offset]",
405 defm SHL : F3R_2RBITP<"shl", shl>;
406 defm SHR : F3R_2RBITP<"shr", srl>;
409 // Three operand long
410 def LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
411 "ldaw $dst, $addr[$offset]",
412 [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>;
414 let neverHasSideEffects = 1 in
415 def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst),
416 (ins GRRegs:$addr, i32imm:$offset),
417 "ldaw $dst, $addr[$offset]",
420 def LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
421 "ldaw $dst, $addr[-$offset]",
422 [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>;
424 let neverHasSideEffects = 1 in
425 def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst),
426 (ins GRRegs:$addr, i32imm:$offset),
427 "ldaw $dst, $addr[-$offset]",
430 def LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
431 "lda16 $dst, $addr[$offset]",
432 [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>;
434 def LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
435 "lda16 $dst, $addr[-$offset]",
436 [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>;
438 def MUL_l3r : FL3R<"mul", mul>;
439 // Instructions which may trap are marked as side effecting.
440 let hasSideEffects = 1 in {
441 def DIVS_l3r : FL3R<"divs", sdiv>;
442 def DIVU_l3r : FL3R<"divu", udiv>;
443 def REMS_l3r : FL3R<"rems", srem>;
444 def REMU_l3r : FL3R<"remu", urem>;
446 def XOR_l3r : FL3R<"xor", xor>;
447 defm ASHR : FL3R_L2RBITP<"ashr", sra>;
448 // TODO crc32, crc8, inpw, outpw
450 def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
451 "st16 $val, $addr[$offset]",
454 def ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
455 "st8 $val, $addr[$offset]",
460 let Predicates = [HasXS1B], Constraints = "$src1 = $dst1,$src2 = $dst2" in {
461 def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
462 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
464 "maccu $dst1, $dst2, $src3, $src4",
467 def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
468 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
470 "maccs $dst1, $dst2, $src3, $src4",
476 let Predicates = [HasXS1B] in {
477 def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
478 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
479 "ladd $dst1, $dst2, $src1, $src2, $src3",
482 def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
483 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
484 "lsub $dst1, $dst2, $src1, $src2, $src3",
487 def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
488 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
489 "ldiv $dst1, $dst2, $src1, $src2, $src3",
495 def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
496 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
498 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
501 let Predicates = [HasXS1A] in
502 def MACC_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
503 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
505 "macc $dst1, $dst2, $src1, $src2, $src3, $src4",
510 //let Uses = [DP] in ...
511 let neverHasSideEffects = 1, isReMaterializable = 1 in
512 def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
516 let isReMaterializable = 1 in
517 def LDAWDP_lru6: _FLRU6<
518 (outs GRRegs:$dst), (ins MEMii:$a),
520 [(set GRRegs:$dst, ADDRdpii:$a)]>;
523 def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
527 def LDWDP_lru6: _FLRU6<
528 (outs GRRegs:$dst), (ins MEMii:$a),
530 [(set GRRegs:$dst, (load ADDRdpii:$a))]>;
533 def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
534 "stw $val, dp[$addr]",
537 def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
538 "stw $val, dp[$addr]",
539 [(store GRRegs:$val, ADDRdpii:$addr)]>;
541 //let Uses = [CP] in ..
542 let mayLoad = 1, isReMaterializable = 1 in
543 defm LDWCP : FRU6_LRU6_cp<"ldw">;
547 def STWSP_ru6 : _FRU6<
548 (outs), (ins GRRegs:$dst, MEMii:$b),
552 def STWSP_lru6 : _FLRU6<
553 (outs), (ins GRRegs:$dst, MEMii:$b),
555 [(store GRRegs:$dst, ADDRspii:$b)]>;
558 def STWSP_ru6_2 : _FRU6<
559 (outs), (ins GRRegs:$dst, i32imm:$b),
563 def STWSP_lru6_2 : _FLRU6<
564 (outs), (ins GRRegs:$dst, i32imm:$b),
566 [(store GRRegs:$dst, ADDRspii:$b)]>;
569 def LDWSP_ru6 : _FRU6<
570 (outs GRRegs:$dst), (ins MEMii:$b),
574 def LDWSP_lru6 : _FLRU6<
575 (outs GRRegs:$dst), (ins MEMii:$b),
577 [(set GRRegs:$dst, (load ADDRspii:$b))]>;
579 let neverHasSideEffects = 1 in
580 def LDAWSP_ru6 : _FRU6<
581 (outs GRRegs:$dst), (ins MEMii:$b),
585 def LDAWSP_lru6 : _FLRU6<
586 (outs GRRegs:$dst), (ins MEMii:$b),
588 [(set GRRegs: $dst, ADDRspii:$b)]>;
590 let neverHasSideEffects = 1 in {
591 def LDAWSP_ru6_RRegs : _FRU6<
592 (outs RRegs:$dst), (ins i32imm:$b),
596 def LDAWSP_lru6_RRegs : _FLRU6<
597 (outs RRegs:$dst), (ins i32imm:$b),
603 let isReMaterializable = 1 in {
605 (outs GRRegs:$dst), (ins i32imm:$b),
607 [(set GRRegs:$dst, immU6:$b)]>;
609 def LDC_lru6 : _FLRU6<
610 (outs GRRegs:$dst), (ins i32imm:$b),
612 [(set GRRegs:$dst, immU16:$b)]>;
615 // Operand register - U6
617 let isBranch = 1, isTerminator = 1 in {
618 defm BRFT: FRU6_LRU6_branch<"bt">;
619 defm BRBT: FRU6_LRU6_branch<"bt">;
620 defm BRFF: FRU6_LRU6_branch<"bf">;
621 defm BRBF: FRU6_LRU6_branch<"bf">;
625 let Defs = [SP], Uses = [SP] in {
626 let neverHasSideEffects = 1 in
627 defm EXTSP : FU6_LU6_np<"extsp">;
629 defm ENTSP : FU6_LU6_np<"entsp">;
631 let isReturn = 1, isTerminator = 1, mayLoad = 1 in {
632 defm RETSP : FU6_LU6<"retsp", XCoreRetsp>;
636 // TODO extdp, kentsp, krestsp, blat, setsr
637 // clrsr, getsr, kalli
638 let isBranch = 1, isTerminator = 1 in {
641 (ins brtarget:$target),
645 def BRBU_lu6 : _FLU6<
647 (ins brtarget:$target),
653 (ins brtarget:$target),
657 def BRFU_lu6 : _FLU6<
659 (ins brtarget:$target),
664 //let Uses = [CP] in ...
665 let Predicates = [HasXS1B], Defs = [R11], neverHasSideEffects = 1,
666 isReMaterializable = 1 in
667 def LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a),
671 let Predicates = [HasXS1B], Defs = [R11], isReMaterializable = 1 in
672 def LDAWCP_lu6: _FLRU6<
673 (outs), (ins MEMii:$a),
675 [(set R11, ADDRcpii:$a)]>;
678 // TODO ldwcpl, blacp
680 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
681 def LDAP_u10 : _FU10<
687 let Defs = [R11], isReMaterializable = 1 in
688 def LDAP_lu10 : _FLU10<
692 [(set R11, (pcrelwrapper tglobaladdr:$addr))]>;
695 // All calls clobber the the link register and the non-callee-saved registers:
696 Defs = [R0, R1, R2, R3, R11, LR] in {
699 (ins calltarget:$target, variable_ops),
701 [(XCoreBranchLink immU10:$target)]>;
703 def BL_lu10 : _FLU10<
705 (ins calltarget:$target, variable_ops),
707 [(XCoreBranchLink immU20:$target)]>;
712 def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
714 [(set GRRegs:$dst, (not GRRegs:$b))]>;
716 def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
718 [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
720 // TODO setd, eet, eef, getts, setpt, outct, inct, chkct, outt, intt, out,
721 // in, outshr, inshr, testct, testwct, tinitpc, tinitdp, tinitsp, tinitcp,
722 // tsetmr, sext (reg), zext (reg)
723 let isTwoAddress = 1 in {
724 let neverHasSideEffects = 1 in
725 def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
729 let neverHasSideEffects = 1 in
730 def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
734 def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
735 "andnot $dst, $src2",
736 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
739 let isReMaterializable = 1, neverHasSideEffects = 1 in
740 def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size),
744 def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size),
746 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>;
749 // TODO settw, setclk, setrdy, setpsc, endin, peek,
750 // getd, testlcl, tinitlr, getps, setps
751 def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
753 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
755 def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
756 "byterev $dst, $src",
757 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
759 def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
761 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
764 // TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp
765 // bru, setdp, setcp, setv, setev, kcall
767 let isBranch=1, isIndirectBranch=1, isTerminator=1 in
768 def BAU_1r : _F1R<(outs), (ins GRRegs:$addr),
770 [(brind GRRegs:$addr)]>;
772 let Defs=[SP], neverHasSideEffects=1 in
773 def SETSP_1r : _F1R<(outs), (ins GRRegs:$src),
777 let isBarrier = 1, hasCtrlDep = 1 in
778 def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src),
782 let isBarrier = 1, hasCtrlDep = 1 in
783 def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src),
788 // All calls clobber the the link register and the non-callee-saved registers:
789 Defs = [R0, R1, R2, R3, R11, LR] in {
790 def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops),
792 [(XCoreBranchLink GRRegs:$addr)]>;
795 // Zero operand short
796 // TODO waiteu, clre, ssync, freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
797 // stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret,
801 def GETID_0R : _F0R<(outs), (ins),
803 [(set R11, (int_xcore_getid))]>;
805 //===----------------------------------------------------------------------===//
806 // Non-Instruction Patterns
807 //===----------------------------------------------------------------------===//
809 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
810 def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
811 def : Pat<(XCoreStwsp GRRegs:$val, immU6:$index),
812 (STWSP_ru6_2 GRRegs:$val, immU6:$index)>;
813 def : Pat<(XCoreStwsp GRRegs:$val, immU16:$index),
814 (STWSP_lru6_2 GRRegs:$val, immU16:$index)>;
817 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
818 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
819 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
822 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
823 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
824 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
826 def : Pat<(zextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
827 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
828 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
830 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
831 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
832 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
833 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
834 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
837 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
838 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
839 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
840 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
841 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
842 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
845 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
846 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
847 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
848 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
850 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
851 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
852 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
853 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
855 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
856 (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
857 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
858 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
859 def : Pat<(store GRRegs:$val, GRRegs:$addr),
860 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
863 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
866 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
872 // unconditional branch
873 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
875 // direct match equal/notequal zero brcond
876 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
877 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
878 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
879 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
881 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
882 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
883 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
884 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
885 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
886 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
887 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
888 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
889 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
890 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
891 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
892 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
894 // generic brcond pattern
895 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
902 // direct match equal/notequal zero select
903 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
904 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
906 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
907 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
909 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
910 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
911 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
912 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
913 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
914 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
915 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
916 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
917 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
918 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
919 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
920 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
923 /// setcc patterns, only matched when none of the above brcond
927 // setcc 2 register operands
928 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
929 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
930 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
931 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
933 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
934 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
935 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
936 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
938 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
939 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
940 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
941 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
943 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
944 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
945 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
946 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
948 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
949 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
951 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
952 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
954 // setcc reg/imm operands
955 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
956 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
957 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
958 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
961 def : Pat<(add GRRegs:$addr, immUs4:$offset),
962 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
964 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
965 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
967 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
968 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
970 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
971 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
972 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
974 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
975 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
981 def : Pat<(mul GRRegs:$src, 3),
982 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
984 def : Pat<(mul GRRegs:$src, 5),
985 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
987 def : Pat<(mul GRRegs:$src, -3),
988 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
990 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
991 def : Pat<(sra GRRegs:$src, 31),
992 (ASHR_l2rus GRRegs:$src, 32)>;