1 //===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the XCore instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
35 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad]>;
38 def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
41 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,
44 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,
47 def SDT_XCoreAddress : SDTypeProfile<1, 1,
48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
53 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
56 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
59 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
60 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
61 [SDNPHasChain, SDNPMayStore]>;
63 // These are target-independent nodes, but have target-specific formats.
64 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
65 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
68 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
69 [SDNPHasChain, SDNPOutGlue]>;
70 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
71 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
73 //===----------------------------------------------------------------------===//
74 // Instruction Pattern Stuff
75 //===----------------------------------------------------------------------===//
77 def div4_xform : SDNodeXForm<imm, [{
78 // Transformation function: imm/4
79 assert(N->getZExtValue() % 4 == 0);
80 return getI32Imm(N->getZExtValue()/4);
83 def msksize_xform : SDNodeXForm<imm, [{
84 // Transformation function: get the size of a mask
85 assert(isMask_32(N->getZExtValue()));
86 // look for the first non-zero bit
87 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue()));
90 def neg_xform : SDNodeXForm<imm, [{
91 // Transformation function: -imm
92 uint32_t value = N->getZExtValue();
93 return getI32Imm(-value);
96 def bpwsub_xform : SDNodeXForm<imm, [{
97 // Transformation function: 32-imm
98 uint32_t value = N->getZExtValue();
99 return getI32Imm(32-value);
102 def div4neg_xform : SDNodeXForm<imm, [{
103 // Transformation function: -imm/4
104 uint32_t value = N->getZExtValue();
105 assert(-value % 4 == 0);
106 return getI32Imm(-value/4);
109 def immUs4Neg : PatLeaf<(imm), [{
110 uint32_t value = (uint32_t)N->getZExtValue();
111 return (-value)%4 == 0 && (-value)/4 <= 11;
114 def immUs4 : PatLeaf<(imm), [{
115 uint32_t value = (uint32_t)N->getZExtValue();
116 return value%4 == 0 && value/4 <= 11;
119 def immUsNeg : PatLeaf<(imm), [{
120 return -((uint32_t)N->getZExtValue()) <= 11;
123 def immUs : PatLeaf<(imm), [{
124 return (uint32_t)N->getZExtValue() <= 11;
127 def immU6 : PatLeaf<(imm), [{
128 return (uint32_t)N->getZExtValue() < (1 << 6);
131 def immU10 : PatLeaf<(imm), [{
132 return (uint32_t)N->getZExtValue() < (1 << 10);
135 def immU16 : PatLeaf<(imm), [{
136 return (uint32_t)N->getZExtValue() < (1 << 16);
139 def immU20 : PatLeaf<(imm), [{
140 return (uint32_t)N->getZExtValue() < (1 << 20);
143 def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;
145 def immBitp : PatLeaf<(imm), [{
146 uint32_t value = (uint32_t)N->getZExtValue();
147 return (value >= 1 && value <= 8)
153 def immBpwSubBitp : PatLeaf<(imm), [{
154 uint32_t value = (uint32_t)N->getZExtValue();
155 return (value >= 24 && value <= 31)
161 def lda16f : PatFrag<(ops node:$addr, node:$offset),
162 (add node:$addr, (shl node:$offset, 1))>;
163 def lda16b : PatFrag<(ops node:$addr, node:$offset),
164 (sub node:$addr, (shl node:$offset, 1))>;
165 def ldawf : PatFrag<(ops node:$addr, node:$offset),
166 (add node:$addr, (shl node:$offset, 2))>;
167 def ldawb : PatFrag<(ops node:$addr, node:$offset),
168 (sub node:$addr, (shl node:$offset, 2))>;
170 // Instruction operand types
171 def calltarget : Operand<i32>;
172 def brtarget : Operand<OtherVT>;
173 def pclabel : Operand<i32>;
176 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
177 def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper],
179 def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper],
183 def MEMii : Operand<i32> {
184 let PrintMethod = "printMemOperand";
185 let DecoderMethod = "DecodeMEMiiOperand";
186 let MIOperandInfo = (ops i32imm, i32imm);
190 def InlineJT : Operand<i32> {
191 let PrintMethod = "printInlineJT";
194 def InlineJT32 : Operand<i32> {
195 let PrintMethod = "printInlineJT32";
198 //===----------------------------------------------------------------------===//
199 // Instruction Class Templates
200 //===----------------------------------------------------------------------===//
202 // Three operand short
204 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
205 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
206 !strconcat(OpcStr, " $dst, $b, $c"),
207 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
208 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
209 !strconcat(OpcStr, " $dst, $b, $c"),
210 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
213 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
214 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
215 !strconcat(OpcStr, " $dst, $b, $c"), []>;
216 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
217 !strconcat(OpcStr, " $dst, $b, $c"), []>;
220 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
222 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
223 !strconcat(OpcStr, " $dst, $b, $c"),
224 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
225 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
226 !strconcat(OpcStr, " $dst, $b, $c"),
227 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
230 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
231 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
232 !strconcat(OpcStr, " $dst, $b, $c"),
233 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
235 class F3R_np<bits<5> opc, string OpcStr> :
236 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
237 !strconcat(OpcStr, " $dst, $b, $c"), []>;
238 // Three operand long
240 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
241 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
243 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
244 !strconcat(OpcStr, " $dst, $b, $c"),
245 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
246 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
247 !strconcat(OpcStr, " $dst, $b, $c"),
248 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
251 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
252 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
254 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
255 !strconcat(OpcStr, " $dst, $b, $c"),
256 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
257 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
258 !strconcat(OpcStr, " $dst, $b, $c"),
259 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
262 class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
263 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
264 !strconcat(OpcStr, " $dst, $b, $c"),
265 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
268 // Operand register - U6
269 multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> {
270 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
271 !strconcat(OpcStr, " $a, $b"), []>;
272 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
273 !strconcat(OpcStr, " $a, $b"), []>;
276 multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> {
277 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
278 !strconcat(OpcStr, " $a, -$b"), []>;
279 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
280 !strconcat(OpcStr, " $a, -$b"), []>;
283 multiclass FRU6_LRU6_cp<bits<6> opc, string OpcStr> {
284 def _ru6: _FRU6<opc, (outs GRRegs:$a), (ins i32imm:$b),
285 !strconcat(OpcStr, " $a, cp[$b]"), []>;
286 def _lru6: _FLRU6<opc, (outs GRRegs:$a), (ins i32imm:$b),
287 !strconcat(OpcStr, " $a, cp[$b]"), []>;
291 multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> {
292 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
293 [(OpNode immU6:$a)]>;
294 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
295 [(OpNode immU16:$a)]>;
298 multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> {
299 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
301 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
305 multiclass FU6_LU6_np<bits<10> opc, string OpcStr> {
306 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
307 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
312 class F2R_np<bits<6> opc, string OpcStr> :
313 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),
314 !strconcat(OpcStr, " $dst, $b"), []>;
318 //===----------------------------------------------------------------------===//
319 // Pseudo Instructions
320 //===----------------------------------------------------------------------===//
322 let Defs = [SP], Uses = [SP] in {
323 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
324 "# ADJCALLSTACKDOWN $amt",
325 [(callseq_start timm:$amt)]>;
326 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
327 "# ADJCALLSTACKUP $amt1",
328 [(callseq_end timm:$amt1, timm:$amt2)]>;
331 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
332 "# LDWFI $dst, $addr",
333 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
335 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
336 "# LDAWFI $dst, $addr",
337 [(set GRRegs:$dst, ADDRspii:$addr)]>;
339 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
340 "# STWFI $src, $addr",
341 [(store GRRegs:$src, ADDRspii:$addr)]>;
343 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
344 // instruction selection into a branch sequence.
345 let usesCustomInserter = 1 in {
346 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
347 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
348 "# SELECT_CC PSEUDO!",
350 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
353 //===----------------------------------------------------------------------===//
355 //===----------------------------------------------------------------------===//
357 // Three operand short
358 defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
359 defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;
360 let neverHasSideEffects = 1 in {
361 defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">;
362 def LSS_3r : F3R_np<0b11000, "lss">;
363 def LSU_3r : F3R_np<0b11001, "lsu">;
365 def AND_3r : F3R<0b00111, "and", and>;
366 def OR_3r : F3R<0b01000, "or", or>;
369 def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),
370 (ins GRRegs:$addr, GRRegs:$offset),
371 "ldw $dst, $addr[$offset]", []>;
373 def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst),
374 (ins GRRegs:$addr, i32imm:$offset),
375 "ldw $dst, $addr[$offset]", []>;
377 def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),
378 (ins GRRegs:$addr, GRRegs:$offset),
379 "ld16s $dst, $addr[$offset]", []>;
381 def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst),
382 (ins GRRegs:$addr, GRRegs:$offset),
383 "ld8u $dst, $addr[$offset]", []>;
387 def STW_l3r : _FL3R<0b000001100, (outs),
388 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
389 "stw $val, $addr[$offset]", []>;
391 def STW_2rus : _F2RUS<0b0000, (outs),
392 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
393 "stw $val, $addr[$offset]", []>;
396 defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
397 defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
400 // Three operand long
401 def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),
402 (ins GRRegs:$addr, GRRegs:$offset),
403 "ldaw $dst, $addr[$offset]",
405 (ldawf GRRegs:$addr, GRRegs:$offset))]>;
407 let neverHasSideEffects = 1 in
408 def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst),
409 (ins GRRegs:$addr, i32imm:$offset),
410 "ldaw $dst, $addr[$offset]", []>;
412 def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst),
413 (ins GRRegs:$addr, GRRegs:$offset),
414 "ldaw $dst, $addr[-$offset]",
416 (ldawb GRRegs:$addr, GRRegs:$offset))]>;
418 let neverHasSideEffects = 1 in
419 def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst),
420 (ins GRRegs:$addr, i32imm:$offset),
421 "ldaw $dst, $addr[-$offset]", []>;
423 def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst),
424 (ins GRRegs:$addr, GRRegs:$offset),
425 "lda16 $dst, $addr[$offset]",
427 (lda16f GRRegs:$addr, GRRegs:$offset))]>;
429 def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst),
430 (ins GRRegs:$addr, GRRegs:$offset),
431 "lda16 $dst, $addr[-$offset]",
433 (lda16b GRRegs:$addr, GRRegs:$offset))]>;
435 def MUL_l3r : FL3R<0b001111100, "mul", mul>;
436 // Instructions which may trap are marked as side effecting.
437 let hasSideEffects = 1 in {
438 def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>;
439 def DIVU_l3r : FL3R<0b010011100, "divu", udiv>;
440 def REMS_l3r : FL3R<0b110001100, "rems", srem>;
441 def REMU_l3r : FL3R<0b110011100, "remu", urem>;
443 def XOR_l3r : FL3R<0b000011100, "xor", xor>;
444 defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>;
446 let Constraints = "$src1 = $dst" in
447 def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst),
448 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
449 "crc32 $dst, $src2, $src3",
451 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
456 def ST16_l3r : _FL3R<0b100001100, (outs),
457 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
458 "st16 $val, $addr[$offset]", []>;
460 def ST8_l3r : _FL3R<0b100011100, (outs),
461 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
462 "st8 $val, $addr[$offset]", []>;
466 let Constraints = "$src1 = $dst1,$src2 = $dst2" in {
467 def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
468 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
470 "maccu $dst1, $dst2, $src3, $src4",
473 def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
474 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
476 "maccs $dst1, $dst2, $src3, $src4",
480 let Constraints = "$src1 = $dst2" in
481 def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
482 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
483 "crc8 $dst2, $dst1, $src2, $src3",
488 def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2),
489 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
490 "ladd $dst2, $dst1, $src1, $src2, $src3",
493 def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2),
494 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
495 "lsub $dst2, $dst1, $src1, $src2, $src3", []>;
497 def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2),
498 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
499 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
503 def LMUL_l6r : _FL6R<
504 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2),
505 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
506 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
510 //let Uses = [DP] in ...
511 let neverHasSideEffects = 1, isReMaterializable = 1 in
512 def LDAWDP_ru6: _FRU6<0b011000, (outs GRRegs:$a), (ins MEMii:$b),
513 "ldaw $a, dp[$b]", []>;
515 let isReMaterializable = 1 in
516 def LDAWDP_lru6: _FLRU6<0b011000, (outs GRRegs:$a), (ins MEMii:$b),
518 [(set GRRegs:$a, ADDRdpii:$b)]>;
521 def LDWDP_ru6: _FRU6<0b010110, (outs GRRegs:$a), (ins MEMii:$b),
522 "ldw $a, dp[$b]", []>;
524 def LDWDP_lru6: _FLRU6<0b010110, (outs GRRegs:$a), (ins MEMii:$b),
526 [(set GRRegs:$a, (load ADDRdpii:$b))]>;
529 def STWDP_ru6 : _FRU6<0b010100, (outs), (ins GRRegs:$a, MEMii:$b),
530 "stw $a, dp[$b]", []>;
532 def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins GRRegs:$a, MEMii:$b),
534 [(store GRRegs:$a, ADDRdpii:$b)]>;
536 //let Uses = [CP] in ..
537 let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in
538 defm LDWCP : FRU6_LRU6_cp<0b011011, "ldw">;
542 def STWSP_ru6 : _FRU6<0b010101, (outs), (ins GRRegs:$a, i32imm:$b),
544 [(XCoreStwsp GRRegs:$a, immU6:$b)]>;
546 def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins GRRegs:$a, i32imm:$b),
548 [(XCoreStwsp GRRegs:$a, immU16:$b)]>;
552 def LDWSP_ru6 : _FRU6<0b010111, (outs GRRegs:$a), (ins i32imm:$b),
553 "ldw $a, sp[$b]", []>;
555 def LDWSP_lru6 : _FLRU6<0b010111, (outs GRRegs:$a), (ins i32imm:$b),
556 "ldw $a, sp[$b]", []>;
559 let neverHasSideEffects = 1 in {
560 def LDAWSP_ru6 : _FRU6<0b011001, (outs GRRegs:$a), (ins i32imm:$b),
561 "ldaw $a, sp[$b]", []>;
563 def LDAWSP_lru6 : _FLRU6<0b011001, (outs GRRegs:$a), (ins i32imm:$b),
564 "ldaw $a, sp[$b]", []>;
566 let isCodeGenOnly = 1 in
567 def LDAWSP_ru6_RRegs : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
568 "ldaw $a, sp[$b]", []>;
570 let isCodeGenOnly = 1 in
571 def LDAWSP_lru6_RRegs : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
572 "ldaw $a, sp[$b]", []>;
576 let isReMaterializable = 1 in {
577 def LDC_ru6 : _FRU6<0b011010, (outs GRRegs:$a), (ins i32imm:$b),
578 "ldc $a, $b", [(set GRRegs:$a, immU6:$b)]>;
580 def LDC_lru6 : _FLRU6<0b011010, (outs GRRegs:$a), (ins i32imm:$b),
581 "ldc $a, $b", [(set GRRegs:$a, immU16:$b)]>;
584 def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
586 [(int_xcore_setc GRRegs:$a, immU6:$b)]>;
588 def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
590 [(int_xcore_setc GRRegs:$a, immU16:$b)]>;
592 // Operand register - U6
593 let isBranch = 1, isTerminator = 1 in {
594 defm BRFT: FRU6_LRU6_branch<0b011100, "bt">;
595 defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">;
596 defm BRFF: FRU6_LRU6_branch<0b011110, "bf">;
597 defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">;
601 let Defs = [SP], Uses = [SP] in {
602 let neverHasSideEffects = 1 in
603 defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">;
605 defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">;
607 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
608 defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>;
612 // TODO extdp, kentsp, krestsp, blat
614 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
615 def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>;
617 def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>;
619 def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
621 def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
624 //let Uses = [CP] in ...
625 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
626 def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]",
629 let Defs = [R11], isReMaterializable = 1 in
630 def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]",
631 [(set R11, ADDRcpii:$a)]>;
633 defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>;
635 defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>;
637 // setsr may cause a branch if it is used to enable events. clrsr may
638 // branch if it is executed while events are enabled.
639 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
640 isCodeGenOnly = 1 in {
641 defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">;
642 defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">;
646 // TODO ldwcpl, blacp
648 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
649 def LDAPF_u10 : _FU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", []>;
651 let Defs = [R11], isReMaterializable = 1 in
652 def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a",
653 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
655 let Defs = [R11], isReMaterializable = 1, isCodeGenOnly = 1 in
656 def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a",
657 [(set R11, (pcrelwrapper tblockaddress:$a))]>;
660 // All calls clobber the link register and the non-callee-saved registers:
661 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
662 def BLRF_u10 : _FU10<0b110100, (outs), (ins calltarget:$a), "bl $a",
663 [(XCoreBranchLink immU10:$a)]>;
665 def BLRF_lu10 : _FLU10<0b110100, (outs), (ins calltarget:$a), "bl $a",
666 [(XCoreBranchLink immU20:$a)]>;
670 // TODO eet, eef, tsetmr
671 def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),
672 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;
674 def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),
675 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
677 let Constraints = "$src1 = $dst" in {
679 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
681 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
685 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
687 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
690 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
692 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
696 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
698 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
701 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
702 "andnot $dst, $src2",
703 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
706 let isReMaterializable = 1, neverHasSideEffects = 1 in
707 def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size),
708 "mkmsk $dst, $size", []>;
710 def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),
712 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
714 def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type),
716 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
718 def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r),
719 "getts $dst, res[$r]",
720 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
722 def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val),
723 "setpt res[$r], $val",
724 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
726 def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),
727 "outct res[$r], $val",
728 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
730 def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val),
731 "outct res[$r], $val",
732 [(int_xcore_outct GRRegs:$r, immUs:$val)]>;
734 def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val),
735 "outt res[$r], $val",
736 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
738 def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val),
740 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
742 let Constraints = "$src = $dst" in
744 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
745 "outshr res[$r], $src",
746 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
748 def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r),
749 "inct $dst, res[$r]",
750 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
752 def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r),
754 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
756 def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r),
758 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;
760 let Constraints = "$src = $dst" in
762 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
763 "inshr $dst, res[$r]",
764 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
766 def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),
767 "chkct res[$r], $val",
768 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
770 def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val),
771 "chkct res[$r], $val",
772 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
774 def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src),
775 "testct $dst, res[$src]",
776 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>;
778 def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src),
779 "testwct $dst, res[$src]",
780 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>;
782 def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val),
783 "setd res[$r], $val",
784 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
786 def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
787 "setpsc res[$src1], $src2",
788 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
790 def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r),
791 "getst $dst, res[$r]",
792 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;
794 def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t),
795 "init t[$t]:sp, $src",
796 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;
798 def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t),
799 "init t[$t]:pc, $src",
800 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;
802 def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t),
803 "init t[$t]:cp, $src",
804 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;
806 def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t),
807 "init t[$t]:dp, $src",
808 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
810 def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src),
811 "peek $dst, res[$src]",
812 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;
814 def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src),
815 "endin $dst, res[$src]",
816 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
820 def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),
822 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
824 def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src),
825 "byterev $dst, $src",
826 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
828 def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src),
830 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
832 def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val),
833 "setc res[$r], $val",
834 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;
836 def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val),
837 "settw res[$r], $val",
838 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;
840 def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src),
841 "get $dst, ps[$src]",
842 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>;
844 def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
845 "set ps[$src1], $src2",
846 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;
848 def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t),
849 "init t[$t]:lr, $src",
850 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>;
852 def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2),
853 "setclk res[$src1], $src2",
854 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;
856 def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
857 "setrdy res[$src1], $src2",
858 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
861 // TODO edu, eeu, waitet, waitef, tstart, clrtp
862 // setdp, setcp, setev, kcall
864 def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
866 [(int_xcore_msync GRRegs:$a)]>;
867 def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a),
869 [(int_xcore_mjoin GRRegs:$a)]>;
871 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
872 def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a),
874 [(brind GRRegs:$a)]>;
876 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
877 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
879 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;
881 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
882 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
884 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
886 let Defs=[SP], neverHasSideEffects=1 in
887 def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a),
891 let hasCtrlDep = 1 in
892 def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a),
896 let hasCtrlDep = 1 in
897 def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a),
902 // All calls clobber the link register and the non-callee-saved registers:
903 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
904 def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a),
906 [(XCoreBranchLink GRRegs:$a)]>;
909 def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a),
911 [(int_xcore_syncr GRRegs:$a)]>;
913 def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a),
915 [(int_xcore_freer GRRegs:$a)]>;
918 def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a),
920 [(int_xcore_setv GRRegs:$a, R11)]>;
922 def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),
923 "setev res[$a], r11",
924 [(int_xcore_setev GRRegs:$a, R11)]>;
927 def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
929 [(int_xcore_eeu GRRegs:$a)]>;
931 // Zero operand short
932 // TODO freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
933 // stet, getkep, getksp, setkep, getid, kret, dcall, dret,
936 def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
938 let Defs = [R11] in {
939 def GETID_0R : _F0R<0b0001001110, (outs), (ins),
941 [(set R11, (int_xcore_getid))]>;
943 def GETED_0R : _F0R<0b0000111110, (outs), (ins),
945 [(set R11, (int_xcore_geted))]>;
947 def GETET_0R : _F0R<0b0000111111, (outs), (ins),
949 [(set R11, (int_xcore_getet))]>;
952 def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),
954 [(int_xcore_ssync)]>;
956 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
957 hasSideEffects = 1 in
958 def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),
960 [(brind (int_xcore_waitevent))]>;
962 //===----------------------------------------------------------------------===//
963 // Non-Instruction Patterns
964 //===----------------------------------------------------------------------===//
966 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BLRF_lu10 tglobaladdr:$addr)>;
967 def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>;
970 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
971 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
972 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
975 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
976 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
977 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
979 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
980 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
981 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
983 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
984 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
985 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
986 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
987 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
990 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
991 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
992 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
993 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
994 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
995 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
998 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
999 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1000 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
1001 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1003 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
1004 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1005 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
1006 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1008 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
1009 (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1010 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
1011 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
1012 def : Pat<(store GRRegs:$val, GRRegs:$addr),
1013 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
1016 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
1019 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
1025 // unconditional branch
1026 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
1028 // direct match equal/notequal zero brcond
1029 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
1030 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
1031 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
1032 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
1034 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1035 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1036 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1037 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1038 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1039 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1040 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1041 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1042 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1043 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1044 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
1045 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
1047 // generic brcond pattern
1048 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
1055 // direct match equal/notequal zero select
1056 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1057 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1059 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1060 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1062 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1063 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1064 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1065 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1066 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1067 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1068 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1069 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1070 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1071 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1072 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
1073 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
1076 /// setcc patterns, only matched when none of the above brcond
1080 // setcc 2 register operands
1081 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
1082 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1083 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
1084 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1086 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1087 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
1088 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
1089 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
1091 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
1092 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1093 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
1094 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1096 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
1097 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
1098 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
1099 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
1101 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
1102 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1104 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
1105 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
1107 // setcc reg/imm operands
1108 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
1109 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
1110 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
1111 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
1114 def : Pat<(add GRRegs:$addr, immUs4:$offset),
1115 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1117 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
1118 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1120 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
1121 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
1123 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1124 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
1125 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
1127 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
1128 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
1134 def : Pat<(mul GRRegs:$src, 3),
1135 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
1137 def : Pat<(mul GRRegs:$src, 5),
1138 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
1140 def : Pat<(mul GRRegs:$src, -3),
1141 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
1143 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
1144 def : Pat<(sra GRRegs:$src, 31),
1145 (ASHR_l2rus GRRegs:$src, 32)>;
1147 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1148 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1150 // setge X, 0 is canonicalized to setgt X, -1
1151 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1152 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1154 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1155 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
1157 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1158 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
1160 def : Pat<(setgt GRRegs:$lhs, -1),
1161 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
1163 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
1164 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;