1 //===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the XCore instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
35 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>;
38 def SDT_XCoreEhRet : SDTypeProfile<0, 2,
39 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
40 def XCoreEhRet : SDNode<"XCoreISD::EH_RETURN", SDT_XCoreEhRet,
41 [SDNPHasChain, SDNPOptInGlue]>;
43 def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
44 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
46 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,
49 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,
52 def SDT_XCoreAddress : SDTypeProfile<1, 1,
53 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
55 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
58 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
61 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
64 def frametoargsoffset : SDNode<"XCoreISD::FRAME_TO_ARGS_OFFSET", SDTIntLeaf,
67 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
68 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
69 [SDNPHasChain, SDNPMayStore]>;
71 def SDT_XCoreLdwsp : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
72 def XCoreLdwsp : SDNode<"XCoreISD::LDWSP", SDT_XCoreLdwsp,
73 [SDNPHasChain, SDNPMayLoad]>;
75 // These are target-independent nodes, but have target-specific formats.
76 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
77 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
80 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
81 [SDNPHasChain, SDNPOutGlue]>;
82 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
83 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
85 def SDT_XCoreMEMBARRIER : SDTypeProfile<0, 0, []>;
87 def XCoreMemBarrier : SDNode<"XCoreISD::MEMBARRIER", SDT_XCoreMEMBARRIER,
90 //===----------------------------------------------------------------------===//
91 // Instruction Pattern Stuff
92 //===----------------------------------------------------------------------===//
94 def div4_xform : SDNodeXForm<imm, [{
95 // Transformation function: imm/4
96 assert(N->getZExtValue() % 4 == 0);
97 return getI32Imm(N->getZExtValue()/4);
100 def msksize_xform : SDNodeXForm<imm, [{
101 // Transformation function: get the size of a mask
102 assert(isMask_32(N->getZExtValue()));
103 // look for the first non-zero bit
104 return getI32Imm(32 - countLeadingZeros((uint32_t)N->getZExtValue()));
107 def neg_xform : SDNodeXForm<imm, [{
108 // Transformation function: -imm
109 uint32_t value = N->getZExtValue();
110 return getI32Imm(-value);
113 def bpwsub_xform : SDNodeXForm<imm, [{
114 // Transformation function: 32-imm
115 uint32_t value = N->getZExtValue();
116 return getI32Imm(32-value);
119 def div4neg_xform : SDNodeXForm<imm, [{
120 // Transformation function: -imm/4
121 uint32_t value = N->getZExtValue();
122 assert(-value % 4 == 0);
123 return getI32Imm(-value/4);
126 def immUs4Neg : PatLeaf<(imm), [{
127 uint32_t value = (uint32_t)N->getZExtValue();
128 return (-value)%4 == 0 && (-value)/4 <= 11;
131 def immUs4 : PatLeaf<(imm), [{
132 uint32_t value = (uint32_t)N->getZExtValue();
133 return value%4 == 0 && value/4 <= 11;
136 def immUsNeg : PatLeaf<(imm), [{
137 return -((uint32_t)N->getZExtValue()) <= 11;
140 def immUs : PatLeaf<(imm), [{
141 return (uint32_t)N->getZExtValue() <= 11;
144 def immU6 : PatLeaf<(imm), [{
145 return (uint32_t)N->getZExtValue() < (1 << 6);
148 def immU10 : PatLeaf<(imm), [{
149 return (uint32_t)N->getZExtValue() < (1 << 10);
152 def immU16 : PatLeaf<(imm), [{
153 return (uint32_t)N->getZExtValue() < (1 << 16);
156 def immU20 : PatLeaf<(imm), [{
157 return (uint32_t)N->getZExtValue() < (1 << 20);
160 def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;
162 def immBitp : PatLeaf<(imm), [{
163 uint32_t value = (uint32_t)N->getZExtValue();
164 return (value >= 1 && value <= 8)
170 def immBpwSubBitp : PatLeaf<(imm), [{
171 uint32_t value = (uint32_t)N->getZExtValue();
172 return (value >= 24 && value <= 31)
178 def lda16f : PatFrag<(ops node:$addr, node:$offset),
179 (add node:$addr, (shl node:$offset, 1))>;
180 def lda16b : PatFrag<(ops node:$addr, node:$offset),
181 (sub node:$addr, (shl node:$offset, 1))>;
182 def ldawf : PatFrag<(ops node:$addr, node:$offset),
183 (add node:$addr, (shl node:$offset, 2))>;
184 def ldawb : PatFrag<(ops node:$addr, node:$offset),
185 (sub node:$addr, (shl node:$offset, 2))>;
187 // Instruction operand types
188 def pcrel_imm : Operand<i32>;
189 def pcrel_imm_neg : Operand<i32> {
190 let DecoderMethod = "DecodeNegImmOperand";
192 def brtarget : Operand<OtherVT>;
193 def brtarget_neg : Operand<OtherVT> {
194 let DecoderMethod = "DecodeNegImmOperand";
198 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
201 def MEMii : Operand<i32> {
202 let MIOperandInfo = (ops i32imm, i32imm);
206 def InlineJT : Operand<i32> {
207 let PrintMethod = "printInlineJT";
210 def InlineJT32 : Operand<i32> {
211 let PrintMethod = "printInlineJT32";
214 //===----------------------------------------------------------------------===//
215 // Instruction Class Templates
216 //===----------------------------------------------------------------------===//
218 // Three operand short
220 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
221 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
222 !strconcat(OpcStr, " $dst, $b, $c"),
223 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
224 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
225 !strconcat(OpcStr, " $dst, $b, $c"),
226 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
229 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
230 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
231 !strconcat(OpcStr, " $dst, $b, $c"), []>;
232 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
233 !strconcat(OpcStr, " $dst, $b, $c"), []>;
236 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
238 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
239 !strconcat(OpcStr, " $dst, $b, $c"),
240 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
241 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
242 !strconcat(OpcStr, " $dst, $b, $c"),
243 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
246 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
247 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
248 !strconcat(OpcStr, " $dst, $b, $c"),
249 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
251 class F3R_np<bits<5> opc, string OpcStr> :
252 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
253 !strconcat(OpcStr, " $dst, $b, $c"), []>;
254 // Three operand long
256 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
257 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
259 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
260 !strconcat(OpcStr, " $dst, $b, $c"),
261 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
262 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
263 !strconcat(OpcStr, " $dst, $b, $c"),
264 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
267 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
268 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
270 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
271 !strconcat(OpcStr, " $dst, $b, $c"),
272 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
273 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
274 !strconcat(OpcStr, " $dst, $b, $c"),
275 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
278 class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
279 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
280 !strconcat(OpcStr, " $dst, $b, $c"),
281 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
284 // Operand register - U6
285 multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> {
286 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
287 !strconcat(OpcStr, " $a, $b"), []>;
288 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
289 !strconcat(OpcStr, " $a, $b"), []>;
292 multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> {
293 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b),
294 !strconcat(OpcStr, " $a, $b"), []>;
295 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b),
296 !strconcat(OpcStr, " $a, $b"), []>;
301 multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> {
302 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
303 [(OpNode immU6:$a)]>;
304 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
305 [(OpNode immU16:$a)]>;
308 multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> {
309 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
311 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
315 multiclass FU6_LU6_np<bits<10> opc, string OpcStr> {
316 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
317 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
322 class F2R_np<bits<6> opc, string OpcStr> :
323 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),
324 !strconcat(OpcStr, " $dst, $b"), []>;
328 //===----------------------------------------------------------------------===//
329 // Pseudo Instructions
330 //===----------------------------------------------------------------------===//
332 let Defs = [SP], Uses = [SP] in {
333 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
334 "# ADJCALLSTACKDOWN $amt",
335 [(callseq_start timm:$amt)]>;
336 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
337 "# ADJCALLSTACKUP $amt1",
338 [(callseq_end timm:$amt1, timm:$amt2)]>;
341 let isReMaterializable = 1 in
342 def FRAME_TO_ARGS_OFFSET : PseudoInstXCore<(outs GRRegs:$dst), (ins),
343 "# FRAME_TO_ARGS_OFFSET $dst",
344 [(set GRRegs:$dst, (frametoargsoffset))]>;
346 let isReturn = 1, isTerminator = 1, isBarrier = 1 in
347 def EH_RETURN : PseudoInstXCore<(outs), (ins GRRegs:$s, GRRegs:$handler),
348 "# EH_RETURN $s, $handler",
349 [(XCoreEhRet GRRegs:$s, GRRegs:$handler)]>;
351 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
352 "# LDWFI $dst, $addr",
353 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
355 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
356 "# LDAWFI $dst, $addr",
357 [(set GRRegs:$dst, ADDRspii:$addr)]>;
359 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
360 "# STWFI $src, $addr",
361 [(store GRRegs:$src, ADDRspii:$addr)]>;
363 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
364 // instruction selection into a branch sequence.
365 let usesCustomInserter = 1 in {
366 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
367 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
368 "# SELECT_CC PSEUDO!",
370 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
373 let hasSideEffects = 1 in
374 def Int_MemBarrier : PseudoInstXCore<(outs), (ins), "#MEMBARRIER",
375 [(XCoreMemBarrier)]>;
377 //===----------------------------------------------------------------------===//
379 //===----------------------------------------------------------------------===//
381 // Three operand short
382 defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
383 defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;
384 let neverHasSideEffects = 1 in {
385 defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">;
386 def LSS_3r : F3R_np<0b11000, "lss">;
387 def LSU_3r : F3R_np<0b11001, "lsu">;
389 def AND_3r : F3R<0b00111, "and", and>;
390 def OR_3r : F3R<0b01000, "or", or>;
393 def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),
394 (ins GRRegs:$addr, GRRegs:$offset),
395 "ldw $dst, $addr[$offset]", []>;
397 def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst),
398 (ins GRRegs:$addr, i32imm:$offset),
399 "ldw $dst, $addr[$offset]", []>;
401 def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),
402 (ins GRRegs:$addr, GRRegs:$offset),
403 "ld16s $dst, $addr[$offset]", []>;
405 def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst),
406 (ins GRRegs:$addr, GRRegs:$offset),
407 "ld8u $dst, $addr[$offset]", []>;
411 def STW_l3r : _FL3R<0b000001100, (outs),
412 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
413 "stw $val, $addr[$offset]", []>;
415 def STW_2rus : _F2RUS<0b00000, (outs),
416 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
417 "stw $val, $addr[$offset]", []>;
420 defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
421 defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
423 // The first operand is treated as an immediate since it refers to a register
424 // number in another thread.
425 def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c),
426 "set t[$c]:r$a, $b", []>;
428 // Three operand long
429 def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),
430 (ins GRRegs:$addr, GRRegs:$offset),
431 "ldaw $dst, $addr[$offset]",
433 (ldawf GRRegs:$addr, GRRegs:$offset))]>;
435 let neverHasSideEffects = 1 in
436 def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst),
437 (ins GRRegs:$addr, i32imm:$offset),
438 "ldaw $dst, $addr[$offset]", []>;
440 def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst),
441 (ins GRRegs:$addr, GRRegs:$offset),
442 "ldaw $dst, $addr[-$offset]",
444 (ldawb GRRegs:$addr, GRRegs:$offset))]>;
446 let neverHasSideEffects = 1 in
447 def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst),
448 (ins GRRegs:$addr, i32imm:$offset),
449 "ldaw $dst, $addr[-$offset]", []>;
451 def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst),
452 (ins GRRegs:$addr, GRRegs:$offset),
453 "lda16 $dst, $addr[$offset]",
455 (lda16f GRRegs:$addr, GRRegs:$offset))]>;
457 def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst),
458 (ins GRRegs:$addr, GRRegs:$offset),
459 "lda16 $dst, $addr[-$offset]",
461 (lda16b GRRegs:$addr, GRRegs:$offset))]>;
463 def MUL_l3r : FL3R<0b001111100, "mul", mul>;
464 // Instructions which may trap are marked as side effecting.
465 let hasSideEffects = 1 in {
466 def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>;
467 def DIVU_l3r : FL3R<0b010011100, "divu", udiv>;
468 def REMS_l3r : FL3R<0b110001100, "rems", srem>;
469 def REMU_l3r : FL3R<0b110011100, "remu", urem>;
471 def XOR_l3r : FL3R<0b000011100, "xor", xor>;
472 defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>;
474 let Constraints = "$src1 = $dst" in
475 def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst),
476 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
477 "crc32 $dst, $src2, $src3",
479 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
483 def ST16_l3r : _FL3R<0b100001100, (outs),
484 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
485 "st16 $val, $addr[$offset]", []>;
487 def ST8_l3r : _FL3R<0b100011100, (outs),
488 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
489 "st8 $val, $addr[$offset]", []>;
492 def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a),
493 (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c",
496 def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs),
497 (ins GRRegs:$a, GRRegs:$b, i32imm:$c),
498 "outpw res[$b], $a, $c", []>;
501 let Constraints = "$e = $a,$f = $b" in {
502 def MACCU_l4r : _FL4RSrcDstSrcDst<
503 0b000001, (outs GRRegs:$a, GRRegs:$b),
504 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>;
506 def MACCS_l4r : _FL4RSrcDstSrcDst<
507 0b000010, (outs GRRegs:$a, GRRegs:$b),
508 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>;
511 let Constraints = "$e = $b" in
512 def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b),
513 (ins GRRegs:$e, GRRegs:$c, GRRegs:$d),
514 "crc8 $b, $a, $c, $d", []>;
518 def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2),
519 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
520 "ladd $dst2, $dst1, $src1, $src2, $src3",
523 def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2),
524 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
525 "lsub $dst2, $dst1, $src1, $src2, $src3", []>;
527 def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2),
528 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
529 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
533 def LMUL_l6r : _FL6R<
534 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2),
535 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
536 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
540 //let Uses = [DP] in ...
541 let neverHasSideEffects = 1, isReMaterializable = 1 in
542 def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b),
543 "ldaw $a, dp[$b]", []>;
545 let isReMaterializable = 1 in
546 def LDAWDP_lru6: _FLRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b),
548 [(set RRegs:$a, (dprelwrapper tglobaladdr:$b))]>;
551 def LDWDP_ru6: _FRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b),
552 "ldw $a, dp[$b]", []>;
554 def LDWDP_lru6: _FLRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b),
556 [(set RRegs:$a, (load (dprelwrapper tglobaladdr:$b)))]>;
559 def STWDP_ru6 : _FRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b),
560 "stw $a, dp[$b]", []>;
562 def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b),
564 [(store RRegs:$a, (dprelwrapper tglobaladdr:$b))]>;
566 //let Uses = [CP] in ..
567 let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in {
568 def LDWCP_ru6 : _FRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b),
569 "ldw $a, cp[$b]", []>;
570 def LDWCP_lru6: _FLRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b),
572 [(set RRegs:$a, (load (cprelwrapper tglobaladdr:$b)))]>;
577 def STWSP_ru6 : _FRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b),
579 [(XCoreStwsp RRegs:$a, immU6:$b)]>;
581 def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b),
583 [(XCoreStwsp RRegs:$a, immU16:$b)]>;
587 def LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),
589 [(set RRegs:$a, (XCoreLdwsp immU6:$b))]>;
591 def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),
593 [(set RRegs:$a, (XCoreLdwsp immU16:$b))]>;
596 let neverHasSideEffects = 1 in {
597 def LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
598 "ldaw $a, sp[$b]", []>;
600 def LDAWSP_lru6 : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
601 "ldaw $a, sp[$b]", []>;
605 let isReMaterializable = 1 in {
606 def LDC_ru6 : _FRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b),
607 "ldc $a, $b", [(set RRegs:$a, immU6:$b)]>;
609 def LDC_lru6 : _FLRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b),
610 "ldc $a, $b", [(set RRegs:$a, immU16:$b)]>;
613 def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
615 [(int_xcore_setc GRRegs:$a, immU6:$b)]>;
617 def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
619 [(int_xcore_setc GRRegs:$a, immU16:$b)]>;
621 // Operand register - U6
622 let isBranch = 1, isTerminator = 1 in {
623 defm BRFT: FRU6_LRU6_branch<0b011100, "bt">;
624 defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">;
625 defm BRFF: FRU6_LRU6_branch<0b011110, "bf">;
626 defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">;
630 let Defs = [SP], Uses = [SP] in {
631 let neverHasSideEffects = 1 in
632 defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">;
635 defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">;
637 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
638 defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>;
642 let neverHasSideEffects = 1 in
643 defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">;
645 let Uses = [R11], isCall=1 in
646 defm BLAT : FU6_LU6_np<0b0111001101, "blat">;
648 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
649 def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>;
651 def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>;
653 def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
655 def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
658 //let Uses = [CP] in ...
659 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
660 def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]",
663 let Defs = [R11], isReMaterializable = 1 in
664 def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]",
665 [(set R11, (cprelwrapper tglobaladdr:$a))]>;
668 defm GETSR : FU6_LU6_np<0b0111111100, "getsr r11,">;
670 defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>;
672 defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>;
674 // setsr may cause a branch if it is used to enable events. clrsr may
675 // branch if it is executed while events are enabled.
676 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
677 isCodeGenOnly = 1 in {
678 defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">;
679 defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">;
682 defm KCALL : FU6_LU6_np<0b0111001111, "kcall">;
684 let Uses = [SP], Defs = [SP], mayStore = 1 in
685 defm KENTSP : FU6_LU6_np<0b0111101110, "kentsp">;
687 let Uses = [SP], Defs = [SP], mayLoad = 1 in
688 defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">;
692 let Defs = [R11], isReMaterializable = 1 in {
693 let neverHasSideEffects = 1 in
694 def LDAPF_u10 : _FU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", []>;
696 def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a",
697 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
699 let neverHasSideEffects = 1 in
700 def LDAPB_u10 : _FU10<0b110111, (outs), (ins pcrel_imm_neg:$a), "ldap r11, $a",
703 let neverHasSideEffects = 1 in
704 def LDAPB_lu10 : _FLU10<0b110111, (outs), (ins pcrel_imm_neg:$a),
706 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
708 let isCodeGenOnly = 1 in
709 def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a",
710 [(set R11, (pcrelwrapper tblockaddress:$a))]>;
714 // All calls clobber the link register and the non-callee-saved registers:
715 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
716 def BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>;
718 def BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>;
720 def BLRF_u10 : _FU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a",
723 def BLRF_lu10 : _FLU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a",
724 [(XCoreBranchLink tglobaladdr:$a)]>;
726 def BLRB_u10 : _FU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>;
728 def BLRB_lu10 : _FLU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>;
731 let Defs = [R11], mayLoad = 1, isReMaterializable = 1,
732 neverHasSideEffects = 1 in {
733 def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>;
735 def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]",
740 def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),
741 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;
743 def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),
744 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
746 let Constraints = "$src1 = $dst" in {
748 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
750 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
754 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
756 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
759 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
761 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
765 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
767 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
770 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
771 "andnot $dst, $src2",
772 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
775 let isReMaterializable = 1, neverHasSideEffects = 1 in
776 def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size),
777 "mkmsk $dst, $size", []>;
779 def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),
781 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
783 def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type),
785 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
787 def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r),
788 "getts $dst, res[$r]",
789 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
791 def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val),
792 "setpt res[$r], $val",
793 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
795 def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),
796 "outct res[$r], $val",
797 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
799 def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val),
800 "outct res[$r], $val",
801 [(int_xcore_outct GRRegs:$r, immUs:$val)]>;
803 def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val),
804 "outt res[$r], $val",
805 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
807 def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val),
809 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
811 let Constraints = "$src = $dst" in
813 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
814 "outshr res[$r], $src",
815 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
817 def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r),
818 "inct $dst, res[$r]",
819 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
821 def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r),
823 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
825 def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r),
827 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;
829 let Constraints = "$src = $dst" in
831 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
832 "inshr $dst, res[$r]",
833 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
835 def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),
836 "chkct res[$r], $val",
837 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
839 def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val),
840 "chkct res[$r], $val",
841 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
843 def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src),
844 "testct $dst, res[$src]",
845 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>;
847 def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src),
848 "testwct $dst, res[$src]",
849 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>;
851 def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val),
852 "setd res[$r], $val",
853 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
855 def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
856 "setpsc res[$src1], $src2",
857 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
859 def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r),
860 "getst $dst, res[$r]",
861 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;
863 def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t),
864 "init t[$t]:sp, $src",
865 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;
867 def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t),
868 "init t[$t]:pc, $src",
869 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;
871 def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t),
872 "init t[$t]:cp, $src",
873 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;
875 def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t),
876 "init t[$t]:dp, $src",
877 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
879 def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src),
880 "peek $dst, res[$src]",
881 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;
883 def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src),
884 "endin $dst, res[$src]",
885 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
887 def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b),
888 "eef $a, res[$b]", []>;
890 def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b),
891 "eet $a, res[$b]", []>;
893 def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b),
894 "tsetmr r$a, $b", []>;
897 def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),
899 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
901 def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src),
902 "byterev $dst, $src",
903 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
905 def CLZ_l2r : _FL2R<0b0000111000, (outs GRRegs:$dst), (ins GRRegs:$src),
907 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
909 def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src),
910 "getd $dst, res[$src]", []>;
912 def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src),
913 "getn $dst, res[$src]", []>;
915 def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val),
916 "setc res[$r], $val",
917 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;
919 def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val),
920 "settw res[$r], $val",
921 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;
923 def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src),
924 "get $dst, ps[$src]",
925 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>;
927 def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
928 "set ps[$src1], $src2",
929 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;
931 def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t),
932 "init t[$t]:lr, $src",
933 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>;
935 def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2),
936 "setclk res[$src1], $src2",
937 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;
939 def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
940 "setn res[$src1], $src2", []>;
942 def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
943 "setrdy res[$src1], $src2",
944 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
946 def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src),
947 "testlcl $dst, res[$src]", []>;
950 def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
952 [(int_xcore_msync GRRegs:$a)]>;
953 def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a),
955 [(int_xcore_mjoin GRRegs:$a)]>;
957 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
958 def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a),
960 [(brind GRRegs:$a)]>;
962 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
963 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
965 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;
967 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
968 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
970 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
972 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
973 def BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>;
975 let Defs=[SP], neverHasSideEffects=1 in
976 def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>;
978 let neverHasSideEffects=1 in
979 def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>;
981 let neverHasSideEffects=1 in
982 def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>;
984 let hasCtrlDep = 1 in
985 def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a),
989 let hasCtrlDep = 1 in
990 def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a),
995 // All calls clobber the link register and the non-callee-saved registers:
996 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
997 def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a),
999 [(XCoreBranchLink GRRegs:$a)]>;
1002 def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a),
1004 [(int_xcore_syncr GRRegs:$a)]>;
1006 def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a),
1008 [(int_xcore_freer GRRegs:$a)]>;
1011 def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a),
1012 "setv res[$a], r11",
1013 [(int_xcore_setv GRRegs:$a, R11)]>;
1015 def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),
1016 "setev res[$a], r11",
1017 [(int_xcore_setev GRRegs:$a, R11)]>;
1020 def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>;
1022 def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]",
1023 [(int_xcore_edu GRRegs:$a)]>;
1025 def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
1027 [(int_xcore_eeu GRRegs:$a)]>;
1029 def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>;
1031 def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>;
1033 def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>;
1035 def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>;
1037 def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]",
1038 [(int_xcore_clrpt GRRegs:$a)]>;
1040 // Zero operand short
1042 def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
1044 def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>;
1046 let Defs = [SP], Uses = [SP] in
1047 def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>;
1050 def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>;
1052 def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>;
1054 def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>;
1056 let Defs = [R11] in {
1057 def GETID_0R : _F0R<0b0001001110, (outs), (ins),
1059 [(set R11, (int_xcore_getid))]>;
1061 def GETED_0R : _F0R<0b0000111110, (outs), (ins),
1063 [(set R11, (int_xcore_geted))]>;
1065 def GETET_0R : _F0R<0b0000111111, (outs), (ins),
1067 [(set R11, (int_xcore_getet))]>;
1069 def GETKEP_0R : _F0R<0b0001001111, (outs), (ins),
1070 "get r11, kep", []>;
1072 def GETKSP_0R : _F0R<0b0001011100, (outs), (ins),
1073 "get r11, ksp", []>;
1077 def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>;
1079 let Uses = [SP], mayLoad = 1 in {
1080 def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>;
1082 def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>;
1084 def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>;
1086 def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>;
1090 def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>;
1092 def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),
1094 [(int_xcore_ssync)]>;
1096 let Uses = [SP], mayStore = 1 in {
1097 def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>;
1099 def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>;
1101 def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>;
1103 def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>;
1106 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
1107 hasSideEffects = 1 in
1108 def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),
1110 [(brind (int_xcore_waitevent))]>;
1112 //===----------------------------------------------------------------------===//
1113 // Non-Instruction Patterns
1114 //===----------------------------------------------------------------------===//
1116 def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>;
1119 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
1120 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
1121 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
1124 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1125 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1126 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1128 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1129 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1130 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1132 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
1133 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
1134 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
1135 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1136 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
1139 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1140 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1141 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1142 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1143 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1144 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1147 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
1148 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1149 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
1150 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1152 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
1153 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1154 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
1155 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1157 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
1158 (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1159 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
1160 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
1161 def : Pat<(store GRRegs:$val, GRRegs:$addr),
1162 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
1165 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
1168 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
1174 // unconditional branch
1175 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
1177 // direct match equal/notequal zero brcond
1178 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
1179 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
1180 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
1181 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
1183 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1184 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1185 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1186 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1187 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1188 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1189 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1190 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1191 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1192 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1193 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
1194 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
1196 // generic brcond pattern
1197 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
1204 // direct match equal/notequal zero select
1205 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1206 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1208 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1209 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1211 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1212 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1213 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1214 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1215 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1216 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1217 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1218 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1219 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1220 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1221 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
1222 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
1225 /// setcc patterns, only matched when none of the above brcond
1229 // setcc 2 register operands
1230 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
1231 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1232 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
1233 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1235 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1236 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
1237 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
1238 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
1240 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
1241 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1242 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
1243 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1245 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
1246 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
1247 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
1248 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
1250 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
1251 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1253 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
1254 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
1256 // setcc reg/imm operands
1257 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
1258 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
1259 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
1260 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
1263 def : Pat<(add GRRegs:$addr, immUs4:$offset),
1264 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1266 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
1267 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1269 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
1270 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
1272 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1273 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
1274 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
1276 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
1277 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
1283 def : Pat<(mul GRRegs:$src, 3),
1284 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
1286 def : Pat<(mul GRRegs:$src, 5),
1287 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
1289 def : Pat<(mul GRRegs:$src, -3),
1290 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
1292 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
1293 def : Pat<(sra GRRegs:$src, 31),
1294 (ASHR_l2rus GRRegs:$src, 32)>;
1296 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1297 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1299 // setge X, 0 is canonicalized to setgt X, -1
1300 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1301 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1303 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1304 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
1306 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1307 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
1309 def : Pat<(setgt GRRegs:$lhs, -1),
1310 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
1312 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
1313 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;
1315 def : Pat<(load (cprelwrapper tconstpool:$b)),
1316 (LDWCP_lru6 tconstpool:$b)>;
1318 def : Pat<(cprelwrapper tconstpool:$b),
1319 (LDAWCP_lu6 tconstpool:$b)>;