1 //===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the XCore instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
35 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
36 [SDNPHasChain, SDNPOptInFlag]>;
38 def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
41 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,
44 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,
47 def SDT_XCoreAddress : SDTypeProfile<1, 1,
48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
53 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
56 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
59 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
60 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
63 // These are target-independent nodes, but have target-specific formats.
64 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
65 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
68 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
69 [SDNPHasChain, SDNPOutFlag]>;
70 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
71 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
73 //===----------------------------------------------------------------------===//
74 // Instruction Pattern Stuff
75 //===----------------------------------------------------------------------===//
77 def div4_xform : SDNodeXForm<imm, [{
78 // Transformation function: imm/4
79 assert(N->getZExtValue() % 4 == 0);
80 return getI32Imm(N->getZExtValue()/4);
83 def msksize_xform : SDNodeXForm<imm, [{
84 // Transformation function: get the size of a mask
85 assert(isMask_32(N->getZExtValue()));
86 // look for the first non-zero bit
87 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue()));
90 def neg_xform : SDNodeXForm<imm, [{
91 // Transformation function: -imm
92 uint32_t value = N->getZExtValue();
93 return getI32Imm(-value);
96 def bpwsub_xform : SDNodeXForm<imm, [{
97 // Transformation function: 32-imm
98 uint32_t value = N->getZExtValue();
99 return getI32Imm(32-value);
102 def div4neg_xform : SDNodeXForm<imm, [{
103 // Transformation function: -imm/4
104 uint32_t value = N->getZExtValue();
105 assert(-value % 4 == 0);
106 return getI32Imm(-value/4);
109 def immUs4Neg : PatLeaf<(imm), [{
110 uint32_t value = (uint32_t)N->getZExtValue();
111 return (-value)%4 == 0 && (-value)/4 <= 11;
114 def immUs4 : PatLeaf<(imm), [{
115 uint32_t value = (uint32_t)N->getZExtValue();
116 return value%4 == 0 && value/4 <= 11;
119 def immUsNeg : PatLeaf<(imm), [{
120 return -((uint32_t)N->getZExtValue()) <= 11;
123 def immUs : PatLeaf<(imm), [{
124 return (uint32_t)N->getZExtValue() <= 11;
127 def immU6 : PatLeaf<(imm), [{
128 return (uint32_t)N->getZExtValue() < (1 << 6);
131 def immU10 : PatLeaf<(imm), [{
132 return (uint32_t)N->getZExtValue() < (1 << 10);
135 def immU16 : PatLeaf<(imm), [{
136 return (uint32_t)N->getZExtValue() < (1 << 16);
139 def immU20 : PatLeaf<(imm), [{
140 return (uint32_t)N->getZExtValue() < (1 << 20);
143 def immMskBitp : PatLeaf<(imm), [{
144 uint32_t value = (uint32_t)N->getZExtValue();
145 if (!isMask_32(value)) {
148 int msksize = 32 - CountLeadingZeros_32(value);
149 return (msksize >= 1 && msksize <= 8)
155 def immBitp : PatLeaf<(imm), [{
156 uint32_t value = (uint32_t)N->getZExtValue();
157 return (value >= 1 && value <= 8)
163 def immBpwSubBitp : PatLeaf<(imm), [{
164 uint32_t value = (uint32_t)N->getZExtValue();
165 return (value >= 24 && value <= 31)
171 def lda16f : PatFrag<(ops node:$addr, node:$offset),
172 (add node:$addr, (shl node:$offset, 1))>;
173 def lda16b : PatFrag<(ops node:$addr, node:$offset),
174 (sub node:$addr, (shl node:$offset, 1))>;
175 def ldawf : PatFrag<(ops node:$addr, node:$offset),
176 (add node:$addr, (shl node:$offset, 2))>;
177 def ldawb : PatFrag<(ops node:$addr, node:$offset),
178 (sub node:$addr, (shl node:$offset, 2))>;
180 // Instruction operand types
181 def calltarget : Operand<i32>;
182 def brtarget : Operand<OtherVT>;
183 def pclabel : Operand<i32>;
186 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
187 def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper],
189 def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper],
193 def MEMii : Operand<i32> {
194 let PrintMethod = "printMemOperand";
195 let MIOperandInfo = (ops i32imm, i32imm);
199 def InlineJT : Operand<i32> {
200 let PrintMethod = "printInlineJT";
203 def InlineJT32 : Operand<i32> {
204 let PrintMethod = "printInlineJT32";
207 //===----------------------------------------------------------------------===//
208 // Instruction Class Templates
209 //===----------------------------------------------------------------------===//
211 // Three operand short
213 multiclass F3R_2RUS<string OpcStr, SDNode OpNode> {
215 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
216 !strconcat(OpcStr, " $dst, $b, $c"),
217 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
219 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
220 !strconcat(OpcStr, " $dst, $b, $c"),
221 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
224 multiclass F3R_2RUS_np<string OpcStr> {
226 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
227 !strconcat(OpcStr, " $dst, $b, $c"),
230 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
231 !strconcat(OpcStr, " $dst, $b, $c"),
235 multiclass F3R_2RBITP<string OpcStr, SDNode OpNode> {
237 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
238 !strconcat(OpcStr, " $dst, $b, $c"),
239 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
241 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
242 !strconcat(OpcStr, " $dst, $b, $c"),
243 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
246 class F3R<string OpcStr, SDNode OpNode> : _F3R<
247 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
248 !strconcat(OpcStr, " $dst, $b, $c"),
249 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
251 class F3R_np<string OpcStr> : _F3R<
252 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
253 !strconcat(OpcStr, " $dst, $b, $c"),
255 // Three operand long
257 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
258 multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> {
260 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
261 !strconcat(OpcStr, " $dst, $b, $c"),
262 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
263 def _l2rus : _FL2RUS<
264 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
265 !strconcat(OpcStr, " $dst, $b, $c"),
266 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
269 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
270 multiclass FL3R_L2RBITP<string OpcStr, SDNode OpNode> {
272 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
273 !strconcat(OpcStr, " $dst, $b, $c"),
274 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
275 def _l2rus : _FL2RUS<
276 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
277 !strconcat(OpcStr, " $dst, $b, $c"),
278 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
281 class FL3R<string OpcStr, SDNode OpNode> : _FL3R<
282 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
283 !strconcat(OpcStr, " $dst, $b, $c"),
284 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
287 // Operand register - U6
288 multiclass FRU6_LRU6_branch<string OpcStr> {
290 (outs), (ins GRRegs:$cond, brtarget:$dest),
291 !strconcat(OpcStr, " $cond, $dest"),
294 (outs), (ins GRRegs:$cond, brtarget:$dest),
295 !strconcat(OpcStr, " $cond, $dest"),
299 multiclass FRU6_LRU6_cp<string OpcStr> {
301 (outs GRRegs:$dst), (ins i32imm:$a),
302 !strconcat(OpcStr, " $dst, cp[$a]"),
305 (outs GRRegs:$dst), (ins i32imm:$a),
306 !strconcat(OpcStr, " $dst, cp[$a]"),
311 multiclass FU6_LU6<string OpcStr, SDNode OpNode> {
313 (outs), (ins i32imm:$b),
314 !strconcat(OpcStr, " $b"),
315 [(OpNode immU6:$b)]>;
317 (outs), (ins i32imm:$b),
318 !strconcat(OpcStr, " $b"),
319 [(OpNode immU16:$b)]>;
322 multiclass FU6_LU6_np<string OpcStr> {
324 (outs), (ins i32imm:$b),
325 !strconcat(OpcStr, " $b"),
328 (outs), (ins i32imm:$b),
329 !strconcat(OpcStr, " $b"),
334 multiclass FU10_LU10_np<string OpcStr> {
336 (outs), (ins i32imm:$b),
337 !strconcat(OpcStr, " $b"),
340 (outs), (ins i32imm:$b),
341 !strconcat(OpcStr, " $b"),
347 class F2R_np<string OpcStr> : _F2R<
348 (outs GRRegs:$dst), (ins GRRegs:$b),
349 !strconcat(OpcStr, " $dst, $b"),
354 //===----------------------------------------------------------------------===//
355 // Pseudo Instructions
356 //===----------------------------------------------------------------------===//
358 let Defs = [SP], Uses = [SP] in {
359 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
360 "${:comment} ADJCALLSTACKDOWN $amt",
361 [(callseq_start timm:$amt)]>;
362 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
363 "${:comment} ADJCALLSTACKUP $amt1",
364 [(callseq_end timm:$amt1, timm:$amt2)]>;
367 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
368 "${:comment} LDWFI $dst, $addr",
369 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
371 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
372 "${:comment} LDAWFI $dst, $addr",
373 [(set GRRegs:$dst, ADDRspii:$addr)]>;
375 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
376 "${:comment} STWFI $src, $addr",
377 [(store GRRegs:$src, ADDRspii:$addr)]>;
379 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
380 // instruction selection into a branch sequence.
381 let usesCustomInserter = 1 in {
382 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
383 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
384 "${:comment} SELECT_CC PSEUDO!",
386 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
389 //===----------------------------------------------------------------------===//
391 //===----------------------------------------------------------------------===//
393 // Three operand short
394 defm ADD : F3R_2RUS<"add", add>;
395 defm SUB : F3R_2RUS<"sub", sub>;
396 let neverHasSideEffects = 1 in {
397 defm EQ : F3R_2RUS_np<"eq">;
398 def LSS_3r : F3R_np<"lss">;
399 def LSU_3r : F3R_np<"lsu">;
401 def AND_3r : F3R<"and", and>;
402 def OR_3r : F3R<"or", or>;
405 def LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
406 "ldw $dst, $addr[$offset]",
409 def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset),
410 "ldw $dst, $addr[$offset]",
413 def LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
414 "ld16s $dst, $addr[$offset]",
417 def LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
418 "ld8u $dst, $addr[$offset]",
423 def STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
424 "stw $val, $addr[$offset]",
427 def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
428 "stw $val, $addr[$offset]",
432 defm SHL : F3R_2RBITP<"shl", shl>;
433 defm SHR : F3R_2RBITP<"shr", srl>;
436 // Three operand long
437 def LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
438 "ldaw $dst, $addr[$offset]",
439 [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>;
441 let neverHasSideEffects = 1 in
442 def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst),
443 (ins GRRegs:$addr, i32imm:$offset),
444 "ldaw $dst, $addr[$offset]",
447 def LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
448 "ldaw $dst, $addr[-$offset]",
449 [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>;
451 let neverHasSideEffects = 1 in
452 def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst),
453 (ins GRRegs:$addr, i32imm:$offset),
454 "ldaw $dst, $addr[-$offset]",
457 def LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
458 "lda16 $dst, $addr[$offset]",
459 [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>;
461 def LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
462 "lda16 $dst, $addr[-$offset]",
463 [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>;
465 def MUL_l3r : FL3R<"mul", mul>;
466 // Instructions which may trap are marked as side effecting.
467 let hasSideEffects = 1 in {
468 def DIVS_l3r : FL3R<"divs", sdiv>;
469 def DIVU_l3r : FL3R<"divu", udiv>;
470 def REMS_l3r : FL3R<"rems", srem>;
471 def REMU_l3r : FL3R<"remu", urem>;
473 def XOR_l3r : FL3R<"xor", xor>;
474 defm ASHR : FL3R_L2RBITP<"ashr", sra>;
475 // TODO crc32, crc8, inpw, outpw
477 def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
478 "st16 $val, $addr[$offset]",
481 def ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
482 "st8 $val, $addr[$offset]",
487 let Constraints = "$src1 = $dst1,$src2 = $dst2" in {
488 def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
489 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
491 "maccu $dst1, $dst2, $src3, $src4",
494 def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
495 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
497 "maccs $dst1, $dst2, $src3, $src4",
503 def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
504 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
505 "ladd $dst1, $dst2, $src1, $src2, $src3",
508 def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
509 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
510 "lsub $dst1, $dst2, $src1, $src2, $src3",
513 def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
514 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
515 "ldiv $dst1, $dst2, $src1, $src2, $src3",
520 def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
521 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
523 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
528 //let Uses = [DP] in ...
529 let neverHasSideEffects = 1, isReMaterializable = 1 in
530 def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
534 let isReMaterializable = 1 in
535 def LDAWDP_lru6: _FLRU6<
536 (outs GRRegs:$dst), (ins MEMii:$a),
538 [(set GRRegs:$dst, ADDRdpii:$a)]>;
541 def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
545 def LDWDP_lru6: _FLRU6<
546 (outs GRRegs:$dst), (ins MEMii:$a),
548 [(set GRRegs:$dst, (load ADDRdpii:$a))]>;
551 def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
552 "stw $val, dp[$addr]",
555 def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
556 "stw $val, dp[$addr]",
557 [(store GRRegs:$val, ADDRdpii:$addr)]>;
559 //let Uses = [CP] in ..
560 let mayLoad = 1, isReMaterializable = 1 in
561 defm LDWCP : FRU6_LRU6_cp<"ldw">;
565 def STWSP_ru6 : _FRU6<
566 (outs), (ins GRRegs:$val, i32imm:$index),
567 "stw $val, sp[$index]",
568 [(XCoreStwsp GRRegs:$val, immU6:$index)]>;
570 def STWSP_lru6 : _FLRU6<
571 (outs), (ins GRRegs:$val, i32imm:$index),
572 "stw $val, sp[$index]",
573 [(XCoreStwsp GRRegs:$val, immU16:$index)]>;
577 def LDWSP_ru6 : _FRU6<
578 (outs GRRegs:$dst), (ins i32imm:$b),
582 def LDWSP_lru6 : _FLRU6<
583 (outs GRRegs:$dst), (ins i32imm:$b),
588 let neverHasSideEffects = 1 in {
589 def LDAWSP_ru6 : _FRU6<
590 (outs GRRegs:$dst), (ins i32imm:$b),
594 def LDAWSP_lru6 : _FLRU6<
595 (outs GRRegs:$dst), (ins i32imm:$b),
599 def LDAWSP_ru6_RRegs : _FRU6<
600 (outs RRegs:$dst), (ins i32imm:$b),
604 def LDAWSP_lru6_RRegs : _FLRU6<
605 (outs RRegs:$dst), (ins i32imm:$b),
611 let isReMaterializable = 1 in {
613 (outs GRRegs:$dst), (ins i32imm:$b),
615 [(set GRRegs:$dst, immU6:$b)]>;
617 def LDC_lru6 : _FLRU6<
618 (outs GRRegs:$dst), (ins i32imm:$b),
620 [(set GRRegs:$dst, immU16:$b)]>;
623 // Operand register - U6
625 let isBranch = 1, isTerminator = 1 in {
626 defm BRFT: FRU6_LRU6_branch<"bt">;
627 defm BRBT: FRU6_LRU6_branch<"bt">;
628 defm BRFF: FRU6_LRU6_branch<"bf">;
629 defm BRBF: FRU6_LRU6_branch<"bf">;
633 let Defs = [SP], Uses = [SP] in {
634 let neverHasSideEffects = 1 in
635 defm EXTSP : FU6_LU6_np<"extsp">;
637 defm ENTSP : FU6_LU6_np<"entsp">;
639 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
640 defm RETSP : FU6_LU6<"retsp", XCoreRetsp>;
644 // TODO extdp, kentsp, krestsp, blat, setsr
645 // clrsr, getsr, kalli
646 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
649 (ins brtarget:$target),
653 def BRBU_lu6 : _FLU6<
655 (ins brtarget:$target),
661 (ins brtarget:$target),
665 def BRFU_lu6 : _FLU6<
667 (ins brtarget:$target),
672 //let Uses = [CP] in ...
673 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
674 def LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a),
678 let Defs = [R11], isReMaterializable = 1 in
679 def LDAWCP_lu6: _FLRU6<
680 (outs), (ins MEMii:$a),
682 [(set R11, ADDRcpii:$a)]>;
685 // TODO ldwcpl, blacp
687 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
688 def LDAP_u10 : _FU10<
694 let Defs = [R11], isReMaterializable = 1 in
695 def LDAP_lu10 : _FLU10<
699 [(set R11, (pcrelwrapper tglobaladdr:$addr))]>;
701 let Defs = [R11], isReMaterializable = 1 in
702 def LDAP_lu10_ba : _FLU10<(outs),
705 [(set R11, (pcrelwrapper tblockaddress:$addr))]>;
708 // All calls clobber the link register and the non-callee-saved registers:
709 Defs = [R0, R1, R2, R3, R11, LR] in {
712 (ins calltarget:$target, variable_ops),
714 [(XCoreBranchLink immU10:$target)]>;
716 def BL_lu10 : _FLU10<
718 (ins calltarget:$target, variable_ops),
720 [(XCoreBranchLink immU20:$target)]>;
725 def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
727 [(set GRRegs:$dst, (not GRRegs:$b))]>;
729 def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
731 [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
733 // TODO setd, eet, eef, getts, setpt, outct, inct, chkct, outt, intt, out,
734 // in, outshr, inshr, testct, testwct, tinitpc, tinitdp, tinitsp, tinitcp,
735 // tsetmr, sext (reg), zext (reg)
736 let isTwoAddress = 1 in {
737 let neverHasSideEffects = 1 in
738 def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
742 let neverHasSideEffects = 1 in
743 def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
747 def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
748 "andnot $dst, $src2",
749 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
752 let isReMaterializable = 1, neverHasSideEffects = 1 in
753 def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size),
757 def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size),
759 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>;
762 // TODO settw, setclk, setrdy, setpsc, endin, peek,
763 // getd, testlcl, tinitlr, getps, setps
764 def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
766 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
768 def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
769 "byterev $dst, $src",
770 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
772 def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
774 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
777 // TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp
778 // setdp, setcp, setv, setev, kcall
780 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
781 def BAU_1r : _F1R<(outs), (ins GRRegs:$addr),
783 [(brind GRRegs:$addr)]>;
785 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
786 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
788 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;
790 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
791 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
793 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
795 let Defs=[SP], neverHasSideEffects=1 in
796 def SETSP_1r : _F1R<(outs), (ins GRRegs:$src),
800 let hasCtrlDep = 1 in
801 def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src),
805 let hasCtrlDep = 1 in
806 def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src),
811 // All calls clobber the link register and the non-callee-saved registers:
812 Defs = [R0, R1, R2, R3, R11, LR] in {
813 def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops),
815 [(XCoreBranchLink GRRegs:$addr)]>;
818 // Zero operand short
819 // TODO waiteu, clre, ssync, freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
820 // stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret,
824 def GETID_0R : _F0R<(outs), (ins),
826 [(set R11, (int_xcore_getid))]>;
828 //===----------------------------------------------------------------------===//
829 // Non-Instruction Patterns
830 //===----------------------------------------------------------------------===//
832 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
833 def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
836 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
837 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
838 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
841 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
842 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
843 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
845 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
846 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
847 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
849 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
850 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
851 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
852 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
853 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
856 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
857 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
858 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
859 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
860 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
861 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
864 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
865 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
866 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
867 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
869 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
870 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
871 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
872 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
874 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
875 (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
876 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
877 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
878 def : Pat<(store GRRegs:$val, GRRegs:$addr),
879 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
882 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
885 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
891 // unconditional branch
892 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
894 // direct match equal/notequal zero brcond
895 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
896 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
897 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
898 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
900 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
901 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
902 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
903 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
904 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
905 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
906 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
907 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
908 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
909 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
910 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
911 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
913 // generic brcond pattern
914 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
921 // direct match equal/notequal zero select
922 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
923 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
925 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
926 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
928 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
929 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
930 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
931 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
932 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
933 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
934 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
935 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
936 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
937 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
938 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
939 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
942 /// setcc patterns, only matched when none of the above brcond
946 // setcc 2 register operands
947 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
948 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
949 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
950 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
952 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
953 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
954 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
955 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
957 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
958 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
959 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
960 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
962 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
963 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
964 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
965 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
967 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
968 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
970 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
971 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
973 // setcc reg/imm operands
974 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
975 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
976 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
977 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
980 def : Pat<(add GRRegs:$addr, immUs4:$offset),
981 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
983 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
984 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
986 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
987 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
989 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
990 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
991 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
993 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
994 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
1000 def : Pat<(mul GRRegs:$src, 3),
1001 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
1003 def : Pat<(mul GRRegs:$src, 5),
1004 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
1006 def : Pat<(mul GRRegs:$src, -3),
1007 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
1009 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
1010 def : Pat<(sra GRRegs:$src, 31),
1011 (ASHR_l2rus GRRegs:$src, 32)>;
1013 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1014 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1016 // setge X, 0 is canonicalized to setgt X, -1
1017 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1018 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1020 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1021 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
1023 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1024 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
1026 def : Pat<(setgt GRRegs:$lhs, -1),
1027 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
1029 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
1030 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;