1 //===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the XCore instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
34 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTNone,
35 [SDNPHasChain, SDNPOptInFlag]>;
37 def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
38 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
40 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,
43 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,
46 def SDT_XCoreAddress : SDTypeProfile<1, 1,
47 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
49 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
52 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
55 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
58 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
59 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
62 // These are target-independent nodes, but have target-specific formats.
63 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
64 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
67 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
68 [SDNPHasChain, SDNPOutFlag]>;
69 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
70 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
72 //===----------------------------------------------------------------------===//
73 // Instruction Pattern Stuff
74 //===----------------------------------------------------------------------===//
76 def div4_xform : SDNodeXForm<imm, [{
77 // Transformation function: imm/4
78 assert(N->getZExtValue() % 4 == 0);
79 return getI32Imm(N->getZExtValue()/4);
82 def msksize_xform : SDNodeXForm<imm, [{
83 // Transformation function: get the size of a mask
84 assert(isMask_32(N->getZExtValue()));
85 // look for the first non-zero bit
86 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue()));
89 def neg_xform : SDNodeXForm<imm, [{
90 // Transformation function: -imm
91 uint32_t value = N->getZExtValue();
92 return getI32Imm(-value);
95 def bpwsub_xform : SDNodeXForm<imm, [{
96 // Transformation function: 32-imm
97 uint32_t value = N->getZExtValue();
98 return getI32Imm(32-value);
101 def div4neg_xform : SDNodeXForm<imm, [{
102 // Transformation function: -imm/4
103 uint32_t value = N->getZExtValue();
104 assert(-value % 4 == 0);
105 return getI32Imm(-value/4);
108 def immUs4Neg : PatLeaf<(imm), [{
109 uint32_t value = (uint32_t)N->getZExtValue();
110 return (-value)%4 == 0 && (-value)/4 <= 11;
113 def immUs4 : PatLeaf<(imm), [{
114 uint32_t value = (uint32_t)N->getZExtValue();
115 return value%4 == 0 && value/4 <= 11;
118 def immUsNeg : PatLeaf<(imm), [{
119 return -((uint32_t)N->getZExtValue()) <= 11;
122 def immUs : PatLeaf<(imm), [{
123 return (uint32_t)N->getZExtValue() <= 11;
126 def immU6 : PatLeaf<(imm), [{
127 return (uint32_t)N->getZExtValue() < (1 << 6);
130 def immU10 : PatLeaf<(imm), [{
131 return (uint32_t)N->getZExtValue() < (1 << 10);
134 def immU16 : PatLeaf<(imm), [{
135 return (uint32_t)N->getZExtValue() < (1 << 16);
138 def immU20 : PatLeaf<(imm), [{
139 return (uint32_t)N->getZExtValue() < (1 << 20);
142 def immMskBitp : PatLeaf<(imm), [{
143 uint32_t value = (uint32_t)N->getZExtValue();
144 if (!isMask_32(value)) {
147 int msksize = 32 - CountLeadingZeros_32(value);
148 return (msksize >= 1 && msksize <= 8)
154 def immBitp : PatLeaf<(imm), [{
155 uint32_t value = (uint32_t)N->getZExtValue();
156 return (value >= 1 && value <= 8)
162 def immBpwSubBitp : PatLeaf<(imm), [{
163 uint32_t value = (uint32_t)N->getZExtValue();
164 return (value >= 24 && value <= 31)
170 def lda16f : PatFrag<(ops node:$addr, node:$offset),
171 (add node:$addr, (shl node:$offset, 1))>;
172 def lda16b : PatFrag<(ops node:$addr, node:$offset),
173 (sub node:$addr, (shl node:$offset, 1))>;
174 def ldawf : PatFrag<(ops node:$addr, node:$offset),
175 (add node:$addr, (shl node:$offset, 2))>;
176 def ldawb : PatFrag<(ops node:$addr, node:$offset),
177 (sub node:$addr, (shl node:$offset, 2))>;
179 // Instruction operand types
180 def calltarget : Operand<i32>;
181 def brtarget : Operand<OtherVT>;
182 def pclabel : Operand<i32>;
185 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
186 def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper],
188 def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper],
192 def MEMii : Operand<i32> {
193 let PrintMethod = "printMemOperand";
194 let MIOperandInfo = (ops i32imm, i32imm);
198 def InlineJT : Operand<i32> {
199 let PrintMethod = "printInlineJT";
202 def InlineJT32 : Operand<i32> {
203 let PrintMethod = "printInlineJT32";
206 //===----------------------------------------------------------------------===//
207 // Instruction Class Templates
208 //===----------------------------------------------------------------------===//
210 // Three operand short
212 multiclass F3R_2RUS<string OpcStr, SDNode OpNode> {
214 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
215 !strconcat(OpcStr, " $dst, $b, $c"),
216 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
218 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
219 !strconcat(OpcStr, " $dst, $b, $c"),
220 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
223 multiclass F3R_2RUS_np<string OpcStr> {
225 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
226 !strconcat(OpcStr, " $dst, $b, $c"),
229 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
230 !strconcat(OpcStr, " $dst, $b, $c"),
234 multiclass F3R_2RBITP<string OpcStr, SDNode OpNode> {
236 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
237 !strconcat(OpcStr, " $dst, $b, $c"),
238 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
240 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
241 !strconcat(OpcStr, " $dst, $b, $c"),
242 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
245 class F3R<string OpcStr, SDNode OpNode> : _F3R<
246 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
247 !strconcat(OpcStr, " $dst, $b, $c"),
248 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
250 class F3R_np<string OpcStr> : _F3R<
251 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
252 !strconcat(OpcStr, " $dst, $b, $c"),
254 // Three operand long
256 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
257 multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> {
259 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
260 !strconcat(OpcStr, " $dst, $b, $c"),
261 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
262 def _l2rus : _FL2RUS<
263 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
264 !strconcat(OpcStr, " $dst, $b, $c"),
265 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
268 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
269 multiclass FL3R_L2RBITP<string OpcStr, SDNode OpNode> {
271 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
272 !strconcat(OpcStr, " $dst, $b, $c"),
273 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
274 def _l2rus : _FL2RUS<
275 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
276 !strconcat(OpcStr, " $dst, $b, $c"),
277 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
280 class FL3R<string OpcStr, SDNode OpNode> : _FL3R<
281 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
282 !strconcat(OpcStr, " $dst, $b, $c"),
283 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
286 // Operand register - U6
287 multiclass FRU6_LRU6_branch<string OpcStr> {
289 (outs), (ins GRRegs:$cond, brtarget:$dest),
290 !strconcat(OpcStr, " $cond, $dest"),
293 (outs), (ins GRRegs:$cond, brtarget:$dest),
294 !strconcat(OpcStr, " $cond, $dest"),
298 multiclass FRU6_LRU6_cp<string OpcStr> {
300 (outs GRRegs:$dst), (ins i32imm:$a),
301 !strconcat(OpcStr, " $dst, cp[$a]"),
304 (outs GRRegs:$dst), (ins i32imm:$a),
305 !strconcat(OpcStr, " $dst, cp[$a]"),
310 multiclass FU6_LU6<string OpcStr, SDNode OpNode> {
312 (outs), (ins i32imm:$b),
313 !strconcat(OpcStr, " $b"),
314 [(OpNode immU6:$b)]>;
316 (outs), (ins i32imm:$b),
317 !strconcat(OpcStr, " $b"),
318 [(OpNode immU16:$b)]>;
321 multiclass FU6_LU6_np<string OpcStr> {
323 (outs), (ins i32imm:$b),
324 !strconcat(OpcStr, " $b"),
327 (outs), (ins i32imm:$b),
328 !strconcat(OpcStr, " $b"),
333 multiclass FU10_LU10_np<string OpcStr> {
335 (outs), (ins i32imm:$b),
336 !strconcat(OpcStr, " $b"),
339 (outs), (ins i32imm:$b),
340 !strconcat(OpcStr, " $b"),
346 class F2R_np<string OpcStr> : _F2R<
347 (outs GRRegs:$dst), (ins GRRegs:$b),
348 !strconcat(OpcStr, " $dst, $b"),
353 //===----------------------------------------------------------------------===//
354 // Pseudo Instructions
355 //===----------------------------------------------------------------------===//
357 let Defs = [SP], Uses = [SP] in {
358 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
359 "${:comment} ADJCALLSTACKDOWN $amt",
360 [(callseq_start timm:$amt)]>;
361 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
362 "${:comment} ADJCALLSTACKUP $amt1",
363 [(callseq_end timm:$amt1, timm:$amt2)]>;
366 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
367 "${:comment} LDWFI $dst, $addr",
368 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
370 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
371 "${:comment} LDAWFI $dst, $addr",
372 [(set GRRegs:$dst, ADDRspii:$addr)]>;
374 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
375 "${:comment} STWFI $src, $addr",
376 [(store GRRegs:$src, ADDRspii:$addr)]>;
378 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
379 // instruction selection into a branch sequence.
380 let usesCustomInserter = 1 in {
381 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
382 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
383 "${:comment} SELECT_CC PSEUDO!",
385 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
388 //===----------------------------------------------------------------------===//
390 //===----------------------------------------------------------------------===//
392 // Three operand short
393 defm ADD : F3R_2RUS<"add", add>;
394 defm SUB : F3R_2RUS<"sub", sub>;
395 let neverHasSideEffects = 1 in {
396 defm EQ : F3R_2RUS_np<"eq">;
397 def LSS_3r : F3R_np<"lss">;
398 def LSU_3r : F3R_np<"lsu">;
400 def AND_3r : F3R<"and", and>;
401 def OR_3r : F3R<"or", or>;
404 def LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
405 "ldw $dst, $addr[$offset]",
408 def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset),
409 "ldw $dst, $addr[$offset]",
412 def LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
413 "ld16s $dst, $addr[$offset]",
416 def LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
417 "ld8u $dst, $addr[$offset]",
422 def STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
423 "stw $val, $addr[$offset]",
426 def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
427 "stw $val, $addr[$offset]",
431 defm SHL : F3R_2RBITP<"shl", shl>;
432 defm SHR : F3R_2RBITP<"shr", srl>;
435 // Three operand long
436 def LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
437 "ldaw $dst, $addr[$offset]",
438 [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>;
440 let neverHasSideEffects = 1 in
441 def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst),
442 (ins GRRegs:$addr, i32imm:$offset),
443 "ldaw $dst, $addr[$offset]",
446 def LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
447 "ldaw $dst, $addr[-$offset]",
448 [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>;
450 let neverHasSideEffects = 1 in
451 def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst),
452 (ins GRRegs:$addr, i32imm:$offset),
453 "ldaw $dst, $addr[-$offset]",
456 def LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
457 "lda16 $dst, $addr[$offset]",
458 [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>;
460 def LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
461 "lda16 $dst, $addr[-$offset]",
462 [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>;
464 def MUL_l3r : FL3R<"mul", mul>;
465 // Instructions which may trap are marked as side effecting.
466 let hasSideEffects = 1 in {
467 def DIVS_l3r : FL3R<"divs", sdiv>;
468 def DIVU_l3r : FL3R<"divu", udiv>;
469 def REMS_l3r : FL3R<"rems", srem>;
470 def REMU_l3r : FL3R<"remu", urem>;
472 def XOR_l3r : FL3R<"xor", xor>;
473 defm ASHR : FL3R_L2RBITP<"ashr", sra>;
474 // TODO crc32, crc8, inpw, outpw
476 def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
477 "st16 $val, $addr[$offset]",
480 def ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
481 "st8 $val, $addr[$offset]",
486 let Constraints = "$src1 = $dst1,$src2 = $dst2" in {
487 def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
488 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
490 "maccu $dst1, $dst2, $src3, $src4",
493 def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
494 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
496 "maccs $dst1, $dst2, $src3, $src4",
502 def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
503 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
504 "ladd $dst1, $dst2, $src1, $src2, $src3",
507 def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
508 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
509 "lsub $dst1, $dst2, $src1, $src2, $src3",
512 def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
513 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
514 "ldiv $dst1, $dst2, $src1, $src2, $src3",
519 def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
520 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
522 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
527 //let Uses = [DP] in ...
528 let neverHasSideEffects = 1, isReMaterializable = 1 in
529 def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
533 let isReMaterializable = 1 in
534 def LDAWDP_lru6: _FLRU6<
535 (outs GRRegs:$dst), (ins MEMii:$a),
537 [(set GRRegs:$dst, ADDRdpii:$a)]>;
540 def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
544 def LDWDP_lru6: _FLRU6<
545 (outs GRRegs:$dst), (ins MEMii:$a),
547 [(set GRRegs:$dst, (load ADDRdpii:$a))]>;
550 def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
551 "stw $val, dp[$addr]",
554 def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
555 "stw $val, dp[$addr]",
556 [(store GRRegs:$val, ADDRdpii:$addr)]>;
558 //let Uses = [CP] in ..
559 let mayLoad = 1, isReMaterializable = 1 in
560 defm LDWCP : FRU6_LRU6_cp<"ldw">;
564 def STWSP_ru6 : _FRU6<
565 (outs), (ins GRRegs:$val, i32imm:$index),
566 "stw $val, sp[$index]",
567 [(XCoreStwsp GRRegs:$val, immU6:$index)]>;
569 def STWSP_lru6 : _FLRU6<
570 (outs), (ins GRRegs:$val, i32imm:$index),
571 "stw $val, sp[$index]",
572 [(XCoreStwsp GRRegs:$val, immU16:$index)]>;
576 def LDWSP_ru6 : _FRU6<
577 (outs GRRegs:$dst), (ins i32imm:$b),
581 def LDWSP_lru6 : _FLRU6<
582 (outs GRRegs:$dst), (ins i32imm:$b),
587 let neverHasSideEffects = 1 in {
588 def LDAWSP_ru6 : _FRU6<
589 (outs GRRegs:$dst), (ins i32imm:$b),
593 def LDAWSP_lru6 : _FLRU6<
594 (outs GRRegs:$dst), (ins i32imm:$b),
598 def LDAWSP_ru6_RRegs : _FRU6<
599 (outs RRegs:$dst), (ins i32imm:$b),
603 def LDAWSP_lru6_RRegs : _FLRU6<
604 (outs RRegs:$dst), (ins i32imm:$b),
610 let isReMaterializable = 1 in {
612 (outs GRRegs:$dst), (ins i32imm:$b),
614 [(set GRRegs:$dst, immU6:$b)]>;
616 def LDC_lru6 : _FLRU6<
617 (outs GRRegs:$dst), (ins i32imm:$b),
619 [(set GRRegs:$dst, immU16:$b)]>;
622 // Operand register - U6
624 let isBranch = 1, isTerminator = 1 in {
625 defm BRFT: FRU6_LRU6_branch<"bt">;
626 defm BRBT: FRU6_LRU6_branch<"bt">;
627 defm BRFF: FRU6_LRU6_branch<"bf">;
628 defm BRBF: FRU6_LRU6_branch<"bf">;
632 let Defs = [SP], Uses = [SP] in {
633 let neverHasSideEffects = 1 in
634 defm EXTSP : FU6_LU6_np<"extsp">;
636 defm ENTSP : FU6_LU6_np<"entsp">;
638 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
639 defm RETSP : FU6_LU6<"retsp", XCoreRetsp>;
643 // TODO extdp, kentsp, krestsp, blat, setsr
644 // clrsr, getsr, kalli
645 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
648 (ins brtarget:$target),
652 def BRBU_lu6 : _FLU6<
654 (ins brtarget:$target),
660 (ins brtarget:$target),
664 def BRFU_lu6 : _FLU6<
666 (ins brtarget:$target),
671 //let Uses = [CP] in ...
672 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
673 def LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a),
677 let Defs = [R11], isReMaterializable = 1 in
678 def LDAWCP_lu6: _FLRU6<
679 (outs), (ins MEMii:$a),
681 [(set R11, ADDRcpii:$a)]>;
684 // TODO ldwcpl, blacp
686 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
687 def LDAP_u10 : _FU10<
693 let Defs = [R11], isReMaterializable = 1 in
694 def LDAP_lu10 : _FLU10<
698 [(set R11, (pcrelwrapper tglobaladdr:$addr))]>;
700 let Defs = [R11], isReMaterializable = 1 in
701 def LDAP_lu10_ba : _FLU10<(outs),
704 [(set R11, (pcrelwrapper tblockaddress:$addr))]>;
706 let isCall=1, isBarrier = 1,
707 // All calls clobber the link register and the non-callee-saved registers:
708 Defs = [R0, R1, R2, R3, R11, LR] in {
711 (ins calltarget:$target, variable_ops),
713 [(XCoreBranchLink immU10:$target)]>;
715 def BL_lu10 : _FLU10<
717 (ins calltarget:$target, variable_ops),
719 [(XCoreBranchLink immU20:$target)]>;
724 def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
726 [(set GRRegs:$dst, (not GRRegs:$b))]>;
728 def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
730 [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
732 // TODO setd, eet, eef, getts, setpt, outct, inct, chkct, outt, intt, out,
733 // in, outshr, inshr, testct, testwct, tinitpc, tinitdp, tinitsp, tinitcp,
734 // tsetmr, sext (reg), zext (reg)
735 let isTwoAddress = 1 in {
736 let neverHasSideEffects = 1 in
737 def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
741 let neverHasSideEffects = 1 in
742 def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
746 def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
747 "andnot $dst, $src2",
748 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
751 let isReMaterializable = 1, neverHasSideEffects = 1 in
752 def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size),
756 def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size),
758 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>;
761 // TODO settw, setclk, setrdy, setpsc, endin, peek,
762 // getd, testlcl, tinitlr, getps, setps
763 def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
765 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
767 def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
768 "byterev $dst, $src",
769 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
771 def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
773 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
776 // TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp
777 // setdp, setcp, setv, setev, kcall
779 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
780 def BAU_1r : _F1R<(outs), (ins GRRegs:$addr),
782 [(brind GRRegs:$addr)]>;
784 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
785 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
787 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;
789 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
790 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
792 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
794 let Defs=[SP], neverHasSideEffects=1 in
795 def SETSP_1r : _F1R<(outs), (ins GRRegs:$src),
799 let hasCtrlDep = 1 in
800 def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src),
804 let hasCtrlDep = 1 in
805 def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src),
810 // All calls clobber the link register and the non-callee-saved registers:
811 Defs = [R0, R1, R2, R3, R11, LR] in {
812 def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops),
814 [(XCoreBranchLink GRRegs:$addr)]>;
817 // Zero operand short
818 // TODO waiteu, clre, ssync, freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
819 // stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret,
823 def GETID_0R : _F0R<(outs), (ins),
825 [(set R11, (int_xcore_getid))]>;
827 //===----------------------------------------------------------------------===//
828 // Non-Instruction Patterns
829 //===----------------------------------------------------------------------===//
831 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
832 def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
835 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
836 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
837 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
840 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
841 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
842 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
844 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
845 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
846 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
848 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
849 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
850 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
851 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
852 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
855 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
856 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
857 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
858 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
859 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
860 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
863 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
864 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
865 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
866 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
868 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
869 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
870 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
871 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
873 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
874 (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
875 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
876 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
877 def : Pat<(store GRRegs:$val, GRRegs:$addr),
878 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
881 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
884 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
890 // unconditional branch
891 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
893 // direct match equal/notequal zero brcond
894 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
895 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
896 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
897 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
899 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
900 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
901 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
902 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
903 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
904 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
905 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
906 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
907 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
908 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
909 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
910 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
912 // generic brcond pattern
913 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
920 // direct match equal/notequal zero select
921 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
922 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
924 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
925 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
927 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
928 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
929 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
930 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
931 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
932 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
933 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
934 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
935 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
936 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
937 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
938 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
941 /// setcc patterns, only matched when none of the above brcond
945 // setcc 2 register operands
946 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
947 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
948 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
949 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
951 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
952 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
953 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
954 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
956 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
957 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
958 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
959 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
961 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
962 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
963 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
964 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
966 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
967 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
969 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
970 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
972 // setcc reg/imm operands
973 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
974 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
975 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
976 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
979 def : Pat<(add GRRegs:$addr, immUs4:$offset),
980 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
982 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
983 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
985 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
986 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
988 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
989 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
990 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
992 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
993 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
999 def : Pat<(mul GRRegs:$src, 3),
1000 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
1002 def : Pat<(mul GRRegs:$src, 5),
1003 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
1005 def : Pat<(mul GRRegs:$src, -3),
1006 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
1008 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
1009 def : Pat<(sra GRRegs:$src, 31),
1010 (ASHR_l2rus GRRegs:$src, 32)>;
1012 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1013 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1015 // setge X, 0 is canonicalized to setgt X, -1
1016 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1017 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1019 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1020 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
1022 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1023 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
1025 def : Pat<(setgt GRRegs:$lhs, -1),
1026 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
1028 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
1029 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;