1 //===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the XCore instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
35 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>;
38 def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
41 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,
44 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,
47 def SDT_XCoreAddress : SDTypeProfile<1, 1,
48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
53 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
56 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
59 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
60 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
61 [SDNPHasChain, SDNPMayStore]>;
63 // These are target-independent nodes, but have target-specific formats.
64 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
65 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
68 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
69 [SDNPHasChain, SDNPOutGlue]>;
70 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
71 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
73 def SDT_XCoreMEMBARRIER : SDTypeProfile<0, 0, []>;
75 def XCoreMemBarrier : SDNode<"XCoreISD::MEMBARRIER", SDT_XCoreMEMBARRIER,
78 //===----------------------------------------------------------------------===//
79 // Instruction Pattern Stuff
80 //===----------------------------------------------------------------------===//
82 def div4_xform : SDNodeXForm<imm, [{
83 // Transformation function: imm/4
84 assert(N->getZExtValue() % 4 == 0);
85 return getI32Imm(N->getZExtValue()/4);
88 def msksize_xform : SDNodeXForm<imm, [{
89 // Transformation function: get the size of a mask
90 assert(isMask_32(N->getZExtValue()));
91 // look for the first non-zero bit
92 return getI32Imm(32 - countLeadingZeros((uint32_t)N->getZExtValue()));
95 def neg_xform : SDNodeXForm<imm, [{
96 // Transformation function: -imm
97 uint32_t value = N->getZExtValue();
98 return getI32Imm(-value);
101 def bpwsub_xform : SDNodeXForm<imm, [{
102 // Transformation function: 32-imm
103 uint32_t value = N->getZExtValue();
104 return getI32Imm(32-value);
107 def div4neg_xform : SDNodeXForm<imm, [{
108 // Transformation function: -imm/4
109 uint32_t value = N->getZExtValue();
110 assert(-value % 4 == 0);
111 return getI32Imm(-value/4);
114 def immUs4Neg : PatLeaf<(imm), [{
115 uint32_t value = (uint32_t)N->getZExtValue();
116 return (-value)%4 == 0 && (-value)/4 <= 11;
119 def immUs4 : PatLeaf<(imm), [{
120 uint32_t value = (uint32_t)N->getZExtValue();
121 return value%4 == 0 && value/4 <= 11;
124 def immUsNeg : PatLeaf<(imm), [{
125 return -((uint32_t)N->getZExtValue()) <= 11;
128 def immUs : PatLeaf<(imm), [{
129 return (uint32_t)N->getZExtValue() <= 11;
132 def immU6 : PatLeaf<(imm), [{
133 return (uint32_t)N->getZExtValue() < (1 << 6);
136 def immU10 : PatLeaf<(imm), [{
137 return (uint32_t)N->getZExtValue() < (1 << 10);
140 def immU16 : PatLeaf<(imm), [{
141 return (uint32_t)N->getZExtValue() < (1 << 16);
144 def immU20 : PatLeaf<(imm), [{
145 return (uint32_t)N->getZExtValue() < (1 << 20);
148 def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;
150 def immBitp : PatLeaf<(imm), [{
151 uint32_t value = (uint32_t)N->getZExtValue();
152 return (value >= 1 && value <= 8)
158 def immBpwSubBitp : PatLeaf<(imm), [{
159 uint32_t value = (uint32_t)N->getZExtValue();
160 return (value >= 24 && value <= 31)
166 def lda16f : PatFrag<(ops node:$addr, node:$offset),
167 (add node:$addr, (shl node:$offset, 1))>;
168 def lda16b : PatFrag<(ops node:$addr, node:$offset),
169 (sub node:$addr, (shl node:$offset, 1))>;
170 def ldawf : PatFrag<(ops node:$addr, node:$offset),
171 (add node:$addr, (shl node:$offset, 2))>;
172 def ldawb : PatFrag<(ops node:$addr, node:$offset),
173 (sub node:$addr, (shl node:$offset, 2))>;
175 // Instruction operand types
176 def pcrel_imm : Operand<i32>;
177 def pcrel_imm_neg : Operand<i32> {
178 let DecoderMethod = "DecodeNegImmOperand";
180 def brtarget : Operand<OtherVT>;
181 def brtarget_neg : Operand<OtherVT> {
182 let DecoderMethod = "DecodeNegImmOperand";
186 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
189 def MEMii : Operand<i32> {
190 let MIOperandInfo = (ops i32imm, i32imm);
194 def InlineJT : Operand<i32> {
195 let PrintMethod = "printInlineJT";
198 def InlineJT32 : Operand<i32> {
199 let PrintMethod = "printInlineJT32";
202 //===----------------------------------------------------------------------===//
203 // Instruction Class Templates
204 //===----------------------------------------------------------------------===//
206 // Three operand short
208 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
209 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
210 !strconcat(OpcStr, " $dst, $b, $c"),
211 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
212 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
213 !strconcat(OpcStr, " $dst, $b, $c"),
214 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
217 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
218 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
219 !strconcat(OpcStr, " $dst, $b, $c"), []>;
220 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
221 !strconcat(OpcStr, " $dst, $b, $c"), []>;
224 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
226 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
227 !strconcat(OpcStr, " $dst, $b, $c"),
228 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
229 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
230 !strconcat(OpcStr, " $dst, $b, $c"),
231 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
234 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
235 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
236 !strconcat(OpcStr, " $dst, $b, $c"),
237 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
239 class F3R_np<bits<5> opc, string OpcStr> :
240 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
241 !strconcat(OpcStr, " $dst, $b, $c"), []>;
242 // Three operand long
244 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
245 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
247 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
248 !strconcat(OpcStr, " $dst, $b, $c"),
249 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
250 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
251 !strconcat(OpcStr, " $dst, $b, $c"),
252 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
255 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
256 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
258 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
259 !strconcat(OpcStr, " $dst, $b, $c"),
260 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
261 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
262 !strconcat(OpcStr, " $dst, $b, $c"),
263 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
266 class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
267 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
268 !strconcat(OpcStr, " $dst, $b, $c"),
269 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
272 // Operand register - U6
273 multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> {
274 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
275 !strconcat(OpcStr, " $a, $b"), []>;
276 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
277 !strconcat(OpcStr, " $a, $b"), []>;
280 multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> {
281 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b),
282 !strconcat(OpcStr, " $a, $b"), []>;
283 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b),
284 !strconcat(OpcStr, " $a, $b"), []>;
289 multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> {
290 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
291 [(OpNode immU6:$a)]>;
292 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
293 [(OpNode immU16:$a)]>;
296 multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> {
297 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
299 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
303 multiclass FU6_LU6_np<bits<10> opc, string OpcStr> {
304 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
305 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
310 class F2R_np<bits<6> opc, string OpcStr> :
311 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),
312 !strconcat(OpcStr, " $dst, $b"), []>;
316 //===----------------------------------------------------------------------===//
317 // Pseudo Instructions
318 //===----------------------------------------------------------------------===//
320 let Defs = [SP], Uses = [SP] in {
321 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
322 "# ADJCALLSTACKDOWN $amt",
323 [(callseq_start timm:$amt)]>;
324 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
325 "# ADJCALLSTACKUP $amt1",
326 [(callseq_end timm:$amt1, timm:$amt2)]>;
329 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
330 "# LDWFI $dst, $addr",
331 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
333 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
334 "# LDAWFI $dst, $addr",
335 [(set GRRegs:$dst, ADDRspii:$addr)]>;
337 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
338 "# STWFI $src, $addr",
339 [(store GRRegs:$src, ADDRspii:$addr)]>;
341 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
342 // instruction selection into a branch sequence.
343 let usesCustomInserter = 1 in {
344 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
345 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
346 "# SELECT_CC PSEUDO!",
348 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
351 let hasSideEffects = 1 in
352 def Int_MemBarrier : PseudoInstXCore<(outs), (ins), "#MEMBARRIER",
353 [(XCoreMemBarrier)]>;
355 //===----------------------------------------------------------------------===//
357 //===----------------------------------------------------------------------===//
359 // Three operand short
360 defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
361 defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;
362 let neverHasSideEffects = 1 in {
363 defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">;
364 def LSS_3r : F3R_np<0b11000, "lss">;
365 def LSU_3r : F3R_np<0b11001, "lsu">;
367 def AND_3r : F3R<0b00111, "and", and>;
368 def OR_3r : F3R<0b01000, "or", or>;
371 def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),
372 (ins GRRegs:$addr, GRRegs:$offset),
373 "ldw $dst, $addr[$offset]", []>;
375 def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst),
376 (ins GRRegs:$addr, i32imm:$offset),
377 "ldw $dst, $addr[$offset]", []>;
379 def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),
380 (ins GRRegs:$addr, GRRegs:$offset),
381 "ld16s $dst, $addr[$offset]", []>;
383 def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst),
384 (ins GRRegs:$addr, GRRegs:$offset),
385 "ld8u $dst, $addr[$offset]", []>;
389 def STW_l3r : _FL3R<0b000001100, (outs),
390 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
391 "stw $val, $addr[$offset]", []>;
393 def STW_2rus : _F2RUS<0b0000, (outs),
394 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
395 "stw $val, $addr[$offset]", []>;
398 defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
399 defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
401 // The first operand is treated as an immediate since it refers to a register
402 // number in another thread.
403 def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c),
404 "set t[$c]:r$a, $b", []>;
406 // Three operand long
407 def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),
408 (ins GRRegs:$addr, GRRegs:$offset),
409 "ldaw $dst, $addr[$offset]",
411 (ldawf GRRegs:$addr, GRRegs:$offset))]>;
413 let neverHasSideEffects = 1 in
414 def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst),
415 (ins GRRegs:$addr, i32imm:$offset),
416 "ldaw $dst, $addr[$offset]", []>;
418 def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst),
419 (ins GRRegs:$addr, GRRegs:$offset),
420 "ldaw $dst, $addr[-$offset]",
422 (ldawb GRRegs:$addr, GRRegs:$offset))]>;
424 let neverHasSideEffects = 1 in
425 def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst),
426 (ins GRRegs:$addr, i32imm:$offset),
427 "ldaw $dst, $addr[-$offset]", []>;
429 def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst),
430 (ins GRRegs:$addr, GRRegs:$offset),
431 "lda16 $dst, $addr[$offset]",
433 (lda16f GRRegs:$addr, GRRegs:$offset))]>;
435 def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst),
436 (ins GRRegs:$addr, GRRegs:$offset),
437 "lda16 $dst, $addr[-$offset]",
439 (lda16b GRRegs:$addr, GRRegs:$offset))]>;
441 def MUL_l3r : FL3R<0b001111100, "mul", mul>;
442 // Instructions which may trap are marked as side effecting.
443 let hasSideEffects = 1 in {
444 def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>;
445 def DIVU_l3r : FL3R<0b010011100, "divu", udiv>;
446 def REMS_l3r : FL3R<0b110001100, "rems", srem>;
447 def REMU_l3r : FL3R<0b110011100, "remu", urem>;
449 def XOR_l3r : FL3R<0b000011100, "xor", xor>;
450 defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>;
452 let Constraints = "$src1 = $dst" in
453 def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst),
454 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
455 "crc32 $dst, $src2, $src3",
457 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
461 def ST16_l3r : _FL3R<0b100001100, (outs),
462 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
463 "st16 $val, $addr[$offset]", []>;
465 def ST8_l3r : _FL3R<0b100011100, (outs),
466 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
467 "st8 $val, $addr[$offset]", []>;
470 def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a),
471 (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c",
474 def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs),
475 (ins GRRegs:$a, GRRegs:$b, i32imm:$c),
476 "outpw res[$b], $a, $c", []>;
479 let Constraints = "$e = $a,$f = $b" in {
480 def MACCU_l4r : _FL4RSrcDstSrcDst<
481 0b000001, (outs GRRegs:$a, GRRegs:$b),
482 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>;
484 def MACCS_l4r : _FL4RSrcDstSrcDst<
485 0b000010, (outs GRRegs:$a, GRRegs:$b),
486 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>;
489 let Constraints = "$e = $b" in
490 def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b),
491 (ins GRRegs:$e, GRRegs:$c, GRRegs:$d),
492 "crc8 $b, $a, $c, $d", []>;
496 def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2),
497 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
498 "ladd $dst2, $dst1, $src1, $src2, $src3",
501 def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2),
502 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
503 "lsub $dst2, $dst1, $src1, $src2, $src3", []>;
505 def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2),
506 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
507 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
511 def LMUL_l6r : _FL6R<
512 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2),
513 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
514 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
518 //let Uses = [DP] in ...
519 let neverHasSideEffects = 1, isReMaterializable = 1 in
520 def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b),
521 "ldaw $a, dp[$b]", []>;
523 let isReMaterializable = 1 in
524 def LDAWDP_lru6: _FLRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b),
526 [(set RRegs:$a, (dprelwrapper tglobaladdr:$b))]>;
529 def LDWDP_ru6: _FRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b),
530 "ldw $a, dp[$b]", []>;
532 def LDWDP_lru6: _FLRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b),
534 [(set RRegs:$a, (load (dprelwrapper tglobaladdr:$b)))]>;
537 def STWDP_ru6 : _FRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b),
538 "stw $a, dp[$b]", []>;
540 def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b),
542 [(store RRegs:$a, (dprelwrapper tglobaladdr:$b))]>;
544 //let Uses = [CP] in ..
545 let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in {
546 def LDWCP_ru6 : _FRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b),
547 "ldw $a, cp[$b]", []>;
548 def LDWCP_lru6: _FLRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b),
550 [(set RRegs:$a, (load (cprelwrapper tglobaladdr:$b)))]>;
555 def STWSP_ru6 : _FRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b),
557 [(XCoreStwsp RRegs:$a, immU6:$b)]>;
559 def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b),
561 [(XCoreStwsp RRegs:$a, immU16:$b)]>;
565 def LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),
566 "ldw $a, sp[$b]", []>;
568 def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),
569 "ldw $a, sp[$b]", []>;
572 let neverHasSideEffects = 1 in {
573 def LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
574 "ldaw $a, sp[$b]", []>;
576 def LDAWSP_lru6 : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
577 "ldaw $a, sp[$b]", []>;
581 let isReMaterializable = 1 in {
582 def LDC_ru6 : _FRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b),
583 "ldc $a, $b", [(set RRegs:$a, immU6:$b)]>;
585 def LDC_lru6 : _FLRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b),
586 "ldc $a, $b", [(set RRegs:$a, immU16:$b)]>;
589 def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
591 [(int_xcore_setc GRRegs:$a, immU6:$b)]>;
593 def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
595 [(int_xcore_setc GRRegs:$a, immU16:$b)]>;
597 // Operand register - U6
598 let isBranch = 1, isTerminator = 1 in {
599 defm BRFT: FRU6_LRU6_branch<0b011100, "bt">;
600 defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">;
601 defm BRFF: FRU6_LRU6_branch<0b011110, "bf">;
602 defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">;
606 let Defs = [SP], Uses = [SP] in {
607 let neverHasSideEffects = 1 in
608 defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">;
611 defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">;
613 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
614 defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>;
618 let neverHasSideEffects = 1 in
619 defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">;
621 let Uses = [R11], isCall=1 in
622 defm BLAT : FU6_LU6_np<0b0111001101, "blat">;
624 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
625 def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>;
627 def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>;
629 def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
631 def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
634 //let Uses = [CP] in ...
635 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
636 def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]",
639 let Defs = [R11], isReMaterializable = 1 in
640 def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]",
641 [(set R11, (cprelwrapper tglobaladdr:$a))]>;
644 defm GETSR : FU6_LU6_np<0b0111111100, "getsr r11,">;
646 defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>;
648 defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>;
650 // setsr may cause a branch if it is used to enable events. clrsr may
651 // branch if it is executed while events are enabled.
652 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
653 isCodeGenOnly = 1 in {
654 defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">;
655 defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">;
658 defm KCALL : FU6_LU6_np<0b0111001111, "kcall">;
660 let Uses = [SP], Defs = [SP], mayStore = 1 in
661 defm KENTSP : FU6_LU6_np<0b0111101110, "kentsp">;
663 let Uses = [SP], Defs = [SP], mayLoad = 1 in
664 defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">;
668 let Defs = [R11], isReMaterializable = 1 in {
669 let neverHasSideEffects = 1 in
670 def LDAPF_u10 : _FU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", []>;
672 def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a",
673 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
675 let neverHasSideEffects = 1 in
676 def LDAPB_u10 : _FU10<0b110111, (outs), (ins pcrel_imm_neg:$a), "ldap r11, $a",
679 let neverHasSideEffects = 1 in
680 def LDAPB_lu10 : _FLU10<0b110111, (outs), (ins pcrel_imm_neg:$a),
682 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
684 let isCodeGenOnly = 1 in
685 def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a",
686 [(set R11, (pcrelwrapper tblockaddress:$a))]>;
690 // All calls clobber the link register and the non-callee-saved registers:
691 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
692 def BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>;
694 def BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>;
696 def BLRF_u10 : _FU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a",
697 [(XCoreBranchLink immU10:$a)]>;
699 def BLRF_lu10 : _FLU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a",
700 [(XCoreBranchLink immU20:$a)]>;
702 def BLRB_u10 : _FU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>;
704 def BLRB_lu10 : _FLU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>;
707 let Defs = [R11], mayLoad = 1, isReMaterializable = 1,
708 neverHasSideEffects = 1 in {
709 def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>;
711 def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]",
716 def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),
717 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;
719 def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),
720 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
722 let Constraints = "$src1 = $dst" in {
724 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
726 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
730 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
732 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
735 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
737 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
741 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
743 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
746 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
747 "andnot $dst, $src2",
748 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
751 let isReMaterializable = 1, neverHasSideEffects = 1 in
752 def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size),
753 "mkmsk $dst, $size", []>;
755 def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),
757 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
759 def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type),
761 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
763 def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r),
764 "getts $dst, res[$r]",
765 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
767 def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val),
768 "setpt res[$r], $val",
769 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
771 def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),
772 "outct res[$r], $val",
773 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
775 def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val),
776 "outct res[$r], $val",
777 [(int_xcore_outct GRRegs:$r, immUs:$val)]>;
779 def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val),
780 "outt res[$r], $val",
781 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
783 def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val),
785 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
787 let Constraints = "$src = $dst" in
789 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
790 "outshr res[$r], $src",
791 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
793 def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r),
794 "inct $dst, res[$r]",
795 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
797 def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r),
799 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
801 def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r),
803 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;
805 let Constraints = "$src = $dst" in
807 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
808 "inshr $dst, res[$r]",
809 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
811 def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),
812 "chkct res[$r], $val",
813 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
815 def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val),
816 "chkct res[$r], $val",
817 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
819 def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src),
820 "testct $dst, res[$src]",
821 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>;
823 def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src),
824 "testwct $dst, res[$src]",
825 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>;
827 def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val),
828 "setd res[$r], $val",
829 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
831 def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
832 "setpsc res[$src1], $src2",
833 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
835 def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r),
836 "getst $dst, res[$r]",
837 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;
839 def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t),
840 "init t[$t]:sp, $src",
841 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;
843 def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t),
844 "init t[$t]:pc, $src",
845 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;
847 def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t),
848 "init t[$t]:cp, $src",
849 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;
851 def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t),
852 "init t[$t]:dp, $src",
853 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
855 def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src),
856 "peek $dst, res[$src]",
857 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;
859 def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src),
860 "endin $dst, res[$src]",
861 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
863 def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b),
864 "eef $a, res[$b]", []>;
866 def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b),
867 "eet $a, res[$b]", []>;
869 def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b),
870 "tsetmr r$a, $b", []>;
873 def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),
875 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
877 def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src),
878 "byterev $dst, $src",
879 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
881 def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src),
883 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
885 def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src),
886 "getd $dst, res[$src]", []>;
888 def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src),
889 "getn $dst, res[$src]", []>;
891 def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val),
892 "setc res[$r], $val",
893 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;
895 def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val),
896 "settw res[$r], $val",
897 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;
899 def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src),
900 "get $dst, ps[$src]",
901 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>;
903 def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
904 "set ps[$src1], $src2",
905 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;
907 def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t),
908 "init t[$t]:lr, $src",
909 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>;
911 def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2),
912 "setclk res[$src1], $src2",
913 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;
915 def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
916 "setn res[$src1], $src2", []>;
918 def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
919 "setrdy res[$src1], $src2",
920 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
922 def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src),
923 "testlcl $dst, res[$src]", []>;
926 def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
928 [(int_xcore_msync GRRegs:$a)]>;
929 def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a),
931 [(int_xcore_mjoin GRRegs:$a)]>;
933 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
934 def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a),
936 [(brind GRRegs:$a)]>;
938 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
939 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
941 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;
943 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
944 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
946 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
948 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
949 def BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>;
951 let Defs=[SP], neverHasSideEffects=1 in
952 def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>;
954 let neverHasSideEffects=1 in
955 def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>;
957 let neverHasSideEffects=1 in
958 def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>;
960 let hasCtrlDep = 1 in
961 def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a),
965 let hasCtrlDep = 1 in
966 def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a),
971 // All calls clobber the link register and the non-callee-saved registers:
972 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
973 def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a),
975 [(XCoreBranchLink GRRegs:$a)]>;
978 def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a),
980 [(int_xcore_syncr GRRegs:$a)]>;
982 def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a),
984 [(int_xcore_freer GRRegs:$a)]>;
987 def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a),
989 [(int_xcore_setv GRRegs:$a, R11)]>;
991 def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),
992 "setev res[$a], r11",
993 [(int_xcore_setev GRRegs:$a, R11)]>;
996 def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>;
998 def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", []>;
1000 def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
1002 [(int_xcore_eeu GRRegs:$a)]>;
1004 def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>;
1006 def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>;
1008 def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>;
1010 def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>;
1012 def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", []>;
1014 // Zero operand short
1016 def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
1018 def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>;
1020 let Defs = [SP], Uses = [SP] in
1021 def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>;
1024 def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>;
1026 def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>;
1028 def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>;
1030 let Defs = [R11] in {
1031 def GETID_0R : _F0R<0b0001001110, (outs), (ins),
1033 [(set R11, (int_xcore_getid))]>;
1035 def GETED_0R : _F0R<0b0000111110, (outs), (ins),
1037 [(set R11, (int_xcore_geted))]>;
1039 def GETET_0R : _F0R<0b0000111111, (outs), (ins),
1041 [(set R11, (int_xcore_getet))]>;
1043 def GETKEP_0R : _F0R<0b0001001111, (outs), (ins),
1044 "get r11, kep", []>;
1046 def GETKSP_0R : _F0R<0b0001011100, (outs), (ins),
1047 "get r11, ksp", []>;
1051 def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>;
1053 let Uses = [SP], mayLoad = 1 in {
1054 def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>;
1056 def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>;
1058 def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>;
1060 def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>;
1064 def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>;
1066 def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),
1068 [(int_xcore_ssync)]>;
1070 let Uses = [SP], mayStore = 1 in {
1071 def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>;
1073 def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>;
1075 def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>;
1077 def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>;
1080 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
1081 hasSideEffects = 1 in
1082 def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),
1084 [(brind (int_xcore_waitevent))]>;
1086 //===----------------------------------------------------------------------===//
1087 // Non-Instruction Patterns
1088 //===----------------------------------------------------------------------===//
1090 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BLRF_lu10 tglobaladdr:$addr)>;
1091 def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>;
1094 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
1095 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
1096 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
1099 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1100 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1101 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1103 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1104 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1105 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1107 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
1108 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
1109 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
1110 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1111 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
1114 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1115 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1116 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1117 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1118 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1119 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1122 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
1123 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1124 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
1125 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1127 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
1128 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1129 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
1130 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1132 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
1133 (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1134 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
1135 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
1136 def : Pat<(store GRRegs:$val, GRRegs:$addr),
1137 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
1140 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
1143 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
1149 // unconditional branch
1150 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
1152 // direct match equal/notequal zero brcond
1153 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
1154 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
1155 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
1156 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
1158 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1159 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1160 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1161 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1162 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1163 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1164 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1165 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1166 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1167 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1168 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
1169 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
1171 // generic brcond pattern
1172 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
1179 // direct match equal/notequal zero select
1180 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1181 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1183 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1184 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1186 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1187 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1188 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1189 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1190 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1191 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1192 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1193 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1194 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1195 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1196 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
1197 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
1200 /// setcc patterns, only matched when none of the above brcond
1204 // setcc 2 register operands
1205 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
1206 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1207 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
1208 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1210 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1211 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
1212 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
1213 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
1215 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
1216 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1217 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
1218 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1220 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
1221 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
1222 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
1223 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
1225 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
1226 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1228 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
1229 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
1231 // setcc reg/imm operands
1232 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
1233 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
1234 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
1235 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
1238 def : Pat<(add GRRegs:$addr, immUs4:$offset),
1239 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1241 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
1242 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1244 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
1245 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
1247 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1248 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
1249 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
1251 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
1252 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
1258 def : Pat<(mul GRRegs:$src, 3),
1259 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
1261 def : Pat<(mul GRRegs:$src, 5),
1262 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
1264 def : Pat<(mul GRRegs:$src, -3),
1265 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
1267 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
1268 def : Pat<(sra GRRegs:$src, 31),
1269 (ASHR_l2rus GRRegs:$src, 32)>;
1271 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1272 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1274 // setge X, 0 is canonicalized to setgt X, -1
1275 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1276 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1278 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1279 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
1281 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1282 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
1284 def : Pat<(setgt GRRegs:$lhs, -1),
1285 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
1287 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
1288 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;
1290 def : Pat<(load (cprelwrapper tconstpool:$b)),
1291 (LDWCP_lru6 tconstpool:$b)>;
1293 def : Pat<(cprelwrapper tconstpool:$b),
1294 (LDAWCP_lu6 tconstpool:$b)>;