1 //===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the XCore instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
34 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTNone,
35 [SDNPHasChain, SDNPOptInFlag]>;
37 def SDT_XCoreAddress : SDTypeProfile<1, 1,
38 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
40 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
43 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
46 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
49 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
50 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
53 // These are target-independent nodes, but have target-specific formats.
54 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
55 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
58 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
59 [SDNPHasChain, SDNPOutFlag]>;
60 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
61 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
63 //===----------------------------------------------------------------------===//
64 // Instruction Pattern Stuff
65 //===----------------------------------------------------------------------===//
67 def div4_xform : SDNodeXForm<imm, [{
68 // Transformation function: imm/4
69 assert(N->getZExtValue() % 4 == 0);
70 return getI32Imm(N->getZExtValue()/4);
73 def msksize_xform : SDNodeXForm<imm, [{
74 // Transformation function: get the size of a mask
75 assert(isMask_32(N->getZExtValue()));
76 // look for the first non-zero bit
77 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue()));
80 def neg_xform : SDNodeXForm<imm, [{
81 // Transformation function: -imm
82 uint32_t value = N->getZExtValue();
83 return getI32Imm(-value);
86 def bpwsub_xform : SDNodeXForm<imm, [{
87 // Transformation function: 32-imm
88 uint32_t value = N->getZExtValue();
89 return getI32Imm(32-value);
92 def div4neg_xform : SDNodeXForm<imm, [{
93 // Transformation function: -imm/4
94 uint32_t value = N->getZExtValue();
95 assert(-value % 4 == 0);
96 return getI32Imm(-value/4);
99 def immUs4Neg : PatLeaf<(imm), [{
100 uint32_t value = (uint32_t)N->getZExtValue();
101 return (-value)%4 == 0 && (-value)/4 <= 11;
104 def immUs4 : PatLeaf<(imm), [{
105 uint32_t value = (uint32_t)N->getZExtValue();
106 return value%4 == 0 && value/4 <= 11;
109 def immUsNeg : PatLeaf<(imm), [{
110 return -((uint32_t)N->getZExtValue()) <= 11;
113 def immUs : PatLeaf<(imm), [{
114 return (uint32_t)N->getZExtValue() <= 11;
117 def immU6 : PatLeaf<(imm), [{
118 return (uint32_t)N->getZExtValue() < (1 << 6);
121 def immU10 : PatLeaf<(imm), [{
122 return (uint32_t)N->getZExtValue() < (1 << 10);
125 def immU16 : PatLeaf<(imm), [{
126 return (uint32_t)N->getZExtValue() < (1 << 16);
129 def immU20 : PatLeaf<(imm), [{
130 return (uint32_t)N->getZExtValue() < (1 << 20);
133 def immMskBitp : PatLeaf<(imm), [{
134 uint32_t value = (uint32_t)N->getZExtValue();
135 if (!isMask_32(value)) {
138 int msksize = 32 - CountLeadingZeros_32(value);
139 return (msksize >= 1 && msksize <= 8)
145 def immBitp : PatLeaf<(imm), [{
146 uint32_t value = (uint32_t)N->getZExtValue();
147 return (value >= 1 && value <= 8)
153 def immBpwSubBitp : PatLeaf<(imm), [{
154 uint32_t value = (uint32_t)N->getZExtValue();
155 return (value >= 24 && value <= 31)
161 def lda16f : PatFrag<(ops node:$addr, node:$offset),
162 (add node:$addr, (shl node:$offset, 1))>;
163 def lda16b : PatFrag<(ops node:$addr, node:$offset),
164 (sub node:$addr, (shl node:$offset, 1))>;
165 def ldawf : PatFrag<(ops node:$addr, node:$offset),
166 (add node:$addr, (shl node:$offset, 2))>;
167 def ldawb : PatFrag<(ops node:$addr, node:$offset),
168 (sub node:$addr, (shl node:$offset, 2))>;
170 // Instruction operand types
171 def calltarget : Operand<i32>;
172 def brtarget : Operand<OtherVT>;
173 def pclabel : Operand<i32>;
176 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
177 def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper],
179 def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper],
183 def MEMii : Operand<i32> {
184 let PrintMethod = "printMemOperand";
185 let MIOperandInfo = (ops i32imm, i32imm);
188 //===----------------------------------------------------------------------===//
189 // Instruction Class Templates
190 //===----------------------------------------------------------------------===//
192 // Three operand short
194 multiclass F3R_2RUS<string OpcStr, SDNode OpNode> {
196 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
197 !strconcat(OpcStr, " $dst, $b, $c"),
198 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
200 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
201 !strconcat(OpcStr, " $dst, $b, $c"),
202 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
205 multiclass F3R_2RUS_np<string OpcStr> {
207 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
208 !strconcat(OpcStr, " $dst, $b, $c"),
211 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
212 !strconcat(OpcStr, " $dst, $b, $c"),
216 multiclass F3R_2RBITP<string OpcStr, SDNode OpNode> {
218 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
219 !strconcat(OpcStr, " $dst, $b, $c"),
220 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
222 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
223 !strconcat(OpcStr, " $dst, $b, $c"),
224 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
227 class F3R<string OpcStr, SDNode OpNode> : _F3R<
228 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
229 !strconcat(OpcStr, " $dst, $b, $c"),
230 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
232 class F3R_np<string OpcStr> : _F3R<
233 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
234 !strconcat(OpcStr, " $dst, $b, $c"),
236 // Three operand long
238 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
239 multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> {
241 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
242 !strconcat(OpcStr, " $dst, $b, $c"),
243 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
244 def _l2rus : _FL2RUS<
245 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
246 !strconcat(OpcStr, " $dst, $b, $c"),
247 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
250 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
251 multiclass FL3R_L2RBITP<string OpcStr, SDNode OpNode> {
253 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
254 !strconcat(OpcStr, " $dst, $b, $c"),
255 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
256 def _l2rus : _FL2RUS<
257 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
258 !strconcat(OpcStr, " $dst, $b, $c"),
259 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
262 class FL3R<string OpcStr, SDNode OpNode> : _FL3R<
263 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
264 !strconcat(OpcStr, " $dst, $b, $c"),
265 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
268 // Operand register - U6
269 multiclass FRU6_LRU6_branch<string OpcStr> {
271 (outs), (ins GRRegs:$cond, brtarget:$dest),
272 !strconcat(OpcStr, " $cond, $dest"),
275 (outs), (ins GRRegs:$cond, brtarget:$dest),
276 !strconcat(OpcStr, " $cond, $dest"),
280 multiclass FRU6_LRU6_cp<string OpcStr> {
282 (outs GRRegs:$dst), (ins i32imm:$a),
283 !strconcat(OpcStr, " $dst, cp[$a]"),
286 (outs GRRegs:$dst), (ins i32imm:$a),
287 !strconcat(OpcStr, " $dst, cp[$a]"),
292 multiclass FU6_LU6<string OpcStr, SDNode OpNode> {
294 (outs), (ins i32imm:$b),
295 !strconcat(OpcStr, " $b"),
296 [(OpNode immU6:$b)]>;
298 (outs), (ins i32imm:$b),
299 !strconcat(OpcStr, " $b"),
300 [(OpNode immU16:$b)]>;
303 multiclass FU6_LU6_np<string OpcStr> {
305 (outs), (ins i32imm:$b),
306 !strconcat(OpcStr, " $b"),
309 (outs), (ins i32imm:$b),
310 !strconcat(OpcStr, " $b"),
315 multiclass FU10_LU10_np<string OpcStr> {
317 (outs), (ins i32imm:$b),
318 !strconcat(OpcStr, " $b"),
321 (outs), (ins i32imm:$b),
322 !strconcat(OpcStr, " $b"),
328 class F2R_np<string OpcStr> : _F2R<
329 (outs GRRegs:$dst), (ins GRRegs:$b),
330 !strconcat(OpcStr, " $dst, $b"),
335 //===----------------------------------------------------------------------===//
336 // Pseudo Instructions
337 //===----------------------------------------------------------------------===//
339 let Defs = [SP], Uses = [SP] in {
340 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
341 "${:comment} ADJCALLSTACKDOWN $amt",
342 [(callseq_start timm:$amt)]>;
343 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
344 "${:comment} ADJCALLSTACKUP $amt1",
345 [(callseq_end timm:$amt1, timm:$amt2)]>;
348 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
349 "${:comment} LDWFI $dst, $addr",
350 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
352 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
353 "${:comment} LDAWFI $dst, $addr",
354 [(set GRRegs:$dst, ADDRspii:$addr)]>;
356 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
357 "${:comment} STWFI $src, $addr",
358 [(store GRRegs:$src, ADDRspii:$addr)]>;
360 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
361 // scheduler into a branch sequence.
362 let usesCustomDAGSchedInserter = 1 in {
363 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
364 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
365 "${:comment} SELECT_CC PSEUDO!",
367 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
370 //===----------------------------------------------------------------------===//
372 //===----------------------------------------------------------------------===//
374 // Three operand short
375 defm ADD : F3R_2RUS<"add", add>;
376 defm SUB : F3R_2RUS<"sub", sub>;
377 let neverHasSideEffects = 1 in {
378 defm EQ : F3R_2RUS_np<"eq">;
379 def LSS_3r : F3R_np<"lss">;
380 def LSU_3r : F3R_np<"lsu">;
382 def AND_3r : F3R<"and", and>;
383 def OR_3r : F3R<"or", or>;
386 def LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
387 "ldw $dst, $addr[$offset]",
390 def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset),
391 "ldw $dst, $addr[$offset]",
394 def LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
395 "ld16s $dst, $addr[$offset]",
398 def LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
399 "ld8u $dst, $addr[$offset]",
404 def STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
405 "stw $val, $addr[$offset]",
408 def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
409 "stw $val, $addr[$offset]",
413 defm SHL : F3R_2RBITP<"shl", shl>;
414 defm SHR : F3R_2RBITP<"shr", srl>;
417 // Three operand long
418 def LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
419 "ldaw $dst, $addr[$offset]",
420 [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>;
422 let neverHasSideEffects = 1 in
423 def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst),
424 (ins GRRegs:$addr, i32imm:$offset),
425 "ldaw $dst, $addr[$offset]",
428 def LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
429 "ldaw $dst, $addr[-$offset]",
430 [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>;
432 let neverHasSideEffects = 1 in
433 def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst),
434 (ins GRRegs:$addr, i32imm:$offset),
435 "ldaw $dst, $addr[-$offset]",
438 def LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
439 "lda16 $dst, $addr[$offset]",
440 [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>;
442 def LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
443 "lda16 $dst, $addr[-$offset]",
444 [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>;
446 def MUL_l3r : FL3R<"mul", mul>;
447 // Instructions which may trap are marked as side effecting.
448 let hasSideEffects = 1 in {
449 def DIVS_l3r : FL3R<"divs", sdiv>;
450 def DIVU_l3r : FL3R<"divu", udiv>;
451 def REMS_l3r : FL3R<"rems", srem>;
452 def REMU_l3r : FL3R<"remu", urem>;
454 def XOR_l3r : FL3R<"xor", xor>;
455 defm ASHR : FL3R_L2RBITP<"ashr", sra>;
456 // TODO crc32, crc8, inpw, outpw
458 def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
459 "st16 $val, $addr[$offset]",
462 def ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
463 "st8 $val, $addr[$offset]",
468 let Constraints = "$src1 = $dst1,$src2 = $dst2" in {
469 def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
470 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
472 "maccu $dst1, $dst2, $src3, $src4",
475 def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
476 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
478 "maccs $dst1, $dst2, $src3, $src4",
484 def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
485 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
486 "ladd $dst1, $dst2, $src1, $src2, $src3",
489 def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
490 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
491 "lsub $dst1, $dst2, $src1, $src2, $src3",
494 def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
495 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
496 "ldiv $dst1, $dst2, $src1, $src2, $src3",
501 def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
502 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
504 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
509 //let Uses = [DP] in ...
510 let neverHasSideEffects = 1, isReMaterializable = 1 in
511 def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
515 let isReMaterializable = 1 in
516 def LDAWDP_lru6: _FLRU6<
517 (outs GRRegs:$dst), (ins MEMii:$a),
519 [(set GRRegs:$dst, ADDRdpii:$a)]>;
522 def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
526 def LDWDP_lru6: _FLRU6<
527 (outs GRRegs:$dst), (ins MEMii:$a),
529 [(set GRRegs:$dst, (load ADDRdpii:$a))]>;
532 def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
533 "stw $val, dp[$addr]",
536 def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
537 "stw $val, dp[$addr]",
538 [(store GRRegs:$val, ADDRdpii:$addr)]>;
540 //let Uses = [CP] in ..
541 let mayLoad = 1, isReMaterializable = 1 in
542 defm LDWCP : FRU6_LRU6_cp<"ldw">;
546 def STWSP_ru6 : _FRU6<
547 (outs), (ins GRRegs:$val, i32imm:$index),
548 "stw $val, sp[$index]",
549 [(XCoreStwsp GRRegs:$val, immU6:$index)]>;
551 def STWSP_lru6 : _FLRU6<
552 (outs), (ins GRRegs:$val, i32imm:$index),
553 "stw $val, sp[$index]",
554 [(XCoreStwsp GRRegs:$val, immU16:$index)]>;
558 def LDWSP_ru6 : _FRU6<
559 (outs GRRegs:$dst), (ins i32imm:$b),
563 def LDWSP_lru6 : _FLRU6<
564 (outs GRRegs:$dst), (ins i32imm:$b),
569 let neverHasSideEffects = 1 in {
570 def LDAWSP_ru6 : _FRU6<
571 (outs GRRegs:$dst), (ins i32imm:$b),
575 def LDAWSP_lru6 : _FLRU6<
576 (outs GRRegs:$dst), (ins i32imm:$b),
580 def LDAWSP_ru6_RRegs : _FRU6<
581 (outs RRegs:$dst), (ins i32imm:$b),
585 def LDAWSP_lru6_RRegs : _FLRU6<
586 (outs RRegs:$dst), (ins i32imm:$b),
592 let isReMaterializable = 1 in {
594 (outs GRRegs:$dst), (ins i32imm:$b),
596 [(set GRRegs:$dst, immU6:$b)]>;
598 def LDC_lru6 : _FLRU6<
599 (outs GRRegs:$dst), (ins i32imm:$b),
601 [(set GRRegs:$dst, immU16:$b)]>;
604 // Operand register - U6
606 let isBranch = 1, isTerminator = 1 in {
607 defm BRFT: FRU6_LRU6_branch<"bt">;
608 defm BRBT: FRU6_LRU6_branch<"bt">;
609 defm BRFF: FRU6_LRU6_branch<"bf">;
610 defm BRBF: FRU6_LRU6_branch<"bf">;
614 let Defs = [SP], Uses = [SP] in {
615 let neverHasSideEffects = 1 in
616 defm EXTSP : FU6_LU6_np<"extsp">;
618 defm ENTSP : FU6_LU6_np<"entsp">;
620 let isReturn = 1, isTerminator = 1, mayLoad = 1 in {
621 defm RETSP : FU6_LU6<"retsp", XCoreRetsp>;
625 // TODO extdp, kentsp, krestsp, blat, setsr
626 // clrsr, getsr, kalli
627 let isBranch = 1, isTerminator = 1 in {
630 (ins brtarget:$target),
634 def BRBU_lu6 : _FLU6<
636 (ins brtarget:$target),
642 (ins brtarget:$target),
646 def BRFU_lu6 : _FLU6<
648 (ins brtarget:$target),
653 //let Uses = [CP] in ...
654 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
655 def LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a),
659 let Defs = [R11], isReMaterializable = 1 in
660 def LDAWCP_lu6: _FLRU6<
661 (outs), (ins MEMii:$a),
663 [(set R11, ADDRcpii:$a)]>;
666 // TODO ldwcpl, blacp
668 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
669 def LDAP_u10 : _FU10<
675 let Defs = [R11], isReMaterializable = 1 in
676 def LDAP_lu10 : _FLU10<
680 [(set R11, (pcrelwrapper tglobaladdr:$addr))]>;
683 // All calls clobber the the link register and the non-callee-saved registers:
684 Defs = [R0, R1, R2, R3, R11, LR] in {
687 (ins calltarget:$target, variable_ops),
689 [(XCoreBranchLink immU10:$target)]>;
691 def BL_lu10 : _FLU10<
693 (ins calltarget:$target, variable_ops),
695 [(XCoreBranchLink immU20:$target)]>;
700 def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
702 [(set GRRegs:$dst, (not GRRegs:$b))]>;
704 def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
706 [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
708 // TODO setd, eet, eef, getts, setpt, outct, inct, chkct, outt, intt, out,
709 // in, outshr, inshr, testct, testwct, tinitpc, tinitdp, tinitsp, tinitcp,
710 // tsetmr, sext (reg), zext (reg)
711 let isTwoAddress = 1 in {
712 let neverHasSideEffects = 1 in
713 def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
717 let neverHasSideEffects = 1 in
718 def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
722 def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
723 "andnot $dst, $src2",
724 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
727 let isReMaterializable = 1, neverHasSideEffects = 1 in
728 def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size),
732 def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size),
734 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>;
737 // TODO settw, setclk, setrdy, setpsc, endin, peek,
738 // getd, testlcl, tinitlr, getps, setps
739 def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
741 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
743 def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
744 "byterev $dst, $src",
745 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
747 def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
749 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
752 // TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp
753 // bru, setdp, setcp, setv, setev, kcall
755 let isBranch=1, isIndirectBranch=1, isTerminator=1 in
756 def BAU_1r : _F1R<(outs), (ins GRRegs:$addr),
758 [(brind GRRegs:$addr)]>;
760 let Defs=[SP], neverHasSideEffects=1 in
761 def SETSP_1r : _F1R<(outs), (ins GRRegs:$src),
765 let isBarrier = 1, hasCtrlDep = 1 in
766 def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src),
770 let isBarrier = 1, hasCtrlDep = 1 in
771 def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src),
776 // All calls clobber the the link register and the non-callee-saved registers:
777 Defs = [R0, R1, R2, R3, R11, LR] in {
778 def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops),
780 [(XCoreBranchLink GRRegs:$addr)]>;
783 // Zero operand short
784 // TODO waiteu, clre, ssync, freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
785 // stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret,
789 def GETID_0R : _F0R<(outs), (ins),
791 [(set R11, (int_xcore_getid))]>;
793 //===----------------------------------------------------------------------===//
794 // Non-Instruction Patterns
795 //===----------------------------------------------------------------------===//
797 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
798 def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
801 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
802 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
803 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
806 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
807 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
808 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
810 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
811 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
812 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
814 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
815 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
816 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
817 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
818 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
821 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
822 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
823 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
824 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
825 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
826 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
829 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
830 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
831 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
832 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
834 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
835 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
836 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
837 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
839 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
840 (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
841 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
842 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
843 def : Pat<(store GRRegs:$val, GRRegs:$addr),
844 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
847 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
850 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
856 // unconditional branch
857 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
859 // direct match equal/notequal zero brcond
860 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
861 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
862 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
863 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
865 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
866 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
867 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
868 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
869 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
870 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
871 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
872 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
873 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
874 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
875 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
876 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
878 // generic brcond pattern
879 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
886 // direct match equal/notequal zero select
887 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
888 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
890 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
891 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
893 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
894 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
895 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
896 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
897 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
898 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
899 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
900 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
901 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
902 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
903 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
904 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
907 /// setcc patterns, only matched when none of the above brcond
911 // setcc 2 register operands
912 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
913 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
914 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
915 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
917 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
918 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
919 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
920 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
922 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
923 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
924 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
925 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
927 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
928 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
929 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
930 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
932 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
933 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
935 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
936 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
938 // setcc reg/imm operands
939 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
940 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
941 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
942 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
945 def : Pat<(add GRRegs:$addr, immUs4:$offset),
946 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
948 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
949 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
951 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
952 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
954 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
955 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
956 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
958 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
959 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
965 def : Pat<(mul GRRegs:$src, 3),
966 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
968 def : Pat<(mul GRRegs:$src, 5),
969 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
971 def : Pat<(mul GRRegs:$src, -3),
972 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
974 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
975 def : Pat<(sra GRRegs:$src, 31),
976 (ASHR_l2rus GRRegs:$src, 32)>;
978 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
979 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
981 // setge X, 0 is canonicalized to setgt X, -1
982 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
983 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
985 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
986 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
988 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
989 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
991 def : Pat<(setgt GRRegs:$lhs, -1),
992 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
994 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
995 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;