1 //===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the XCore instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
35 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
36 [SDNPHasChain, SDNPOptInGlue]>;
38 def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
41 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,
44 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,
47 def SDT_XCoreAddress : SDTypeProfile<1, 1,
48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
53 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
56 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
59 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
60 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
63 // These are target-independent nodes, but have target-specific formats.
64 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
65 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
68 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
69 [SDNPHasChain, SDNPOutGlue]>;
70 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
71 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
73 //===----------------------------------------------------------------------===//
74 // Instruction Pattern Stuff
75 //===----------------------------------------------------------------------===//
77 def div4_xform : SDNodeXForm<imm, [{
78 // Transformation function: imm/4
79 assert(N->getZExtValue() % 4 == 0);
80 return getI32Imm(N->getZExtValue()/4);
83 def msksize_xform : SDNodeXForm<imm, [{
84 // Transformation function: get the size of a mask
85 assert(isMask_32(N->getZExtValue()));
86 // look for the first non-zero bit
87 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue()));
90 def neg_xform : SDNodeXForm<imm, [{
91 // Transformation function: -imm
92 uint32_t value = N->getZExtValue();
93 return getI32Imm(-value);
96 def bpwsub_xform : SDNodeXForm<imm, [{
97 // Transformation function: 32-imm
98 uint32_t value = N->getZExtValue();
99 return getI32Imm(32-value);
102 def div4neg_xform : SDNodeXForm<imm, [{
103 // Transformation function: -imm/4
104 uint32_t value = N->getZExtValue();
105 assert(-value % 4 == 0);
106 return getI32Imm(-value/4);
109 def immUs4Neg : PatLeaf<(imm), [{
110 uint32_t value = (uint32_t)N->getZExtValue();
111 return (-value)%4 == 0 && (-value)/4 <= 11;
114 def immUs4 : PatLeaf<(imm), [{
115 uint32_t value = (uint32_t)N->getZExtValue();
116 return value%4 == 0 && value/4 <= 11;
119 def immUsNeg : PatLeaf<(imm), [{
120 return -((uint32_t)N->getZExtValue()) <= 11;
123 def immUs : PatLeaf<(imm), [{
124 return (uint32_t)N->getZExtValue() <= 11;
127 def immU6 : PatLeaf<(imm), [{
128 return (uint32_t)N->getZExtValue() < (1 << 6);
131 def immU10 : PatLeaf<(imm), [{
132 return (uint32_t)N->getZExtValue() < (1 << 10);
135 def immU16 : PatLeaf<(imm), [{
136 return (uint32_t)N->getZExtValue() < (1 << 16);
139 def immU20 : PatLeaf<(imm), [{
140 return (uint32_t)N->getZExtValue() < (1 << 20);
143 def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;
145 def immBitp : PatLeaf<(imm), [{
146 uint32_t value = (uint32_t)N->getZExtValue();
147 return (value >= 1 && value <= 8)
153 def immBpwSubBitp : PatLeaf<(imm), [{
154 uint32_t value = (uint32_t)N->getZExtValue();
155 return (value >= 24 && value <= 31)
161 def lda16f : PatFrag<(ops node:$addr, node:$offset),
162 (add node:$addr, (shl node:$offset, 1))>;
163 def lda16b : PatFrag<(ops node:$addr, node:$offset),
164 (sub node:$addr, (shl node:$offset, 1))>;
165 def ldawf : PatFrag<(ops node:$addr, node:$offset),
166 (add node:$addr, (shl node:$offset, 2))>;
167 def ldawb : PatFrag<(ops node:$addr, node:$offset),
168 (sub node:$addr, (shl node:$offset, 2))>;
170 // Instruction operand types
171 def calltarget : Operand<i32>;
172 def brtarget : Operand<OtherVT>;
173 def pclabel : Operand<i32>;
176 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
177 def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper],
179 def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper],
183 def MEMii : Operand<i32> {
184 let PrintMethod = "printMemOperand";
185 let MIOperandInfo = (ops i32imm, i32imm);
189 def InlineJT : Operand<i32> {
190 let PrintMethod = "printInlineJT";
193 def InlineJT32 : Operand<i32> {
194 let PrintMethod = "printInlineJT32";
197 //===----------------------------------------------------------------------===//
198 // Instruction Class Templates
199 //===----------------------------------------------------------------------===//
201 // Three operand short
203 multiclass F3R_2RUS<string OpcStr, SDNode OpNode> {
205 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
206 !strconcat(OpcStr, " $dst, $b, $c"),
207 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
209 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
210 !strconcat(OpcStr, " $dst, $b, $c"),
211 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
214 multiclass F3R_2RUS_np<string OpcStr> {
216 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
217 !strconcat(OpcStr, " $dst, $b, $c"),
220 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
221 !strconcat(OpcStr, " $dst, $b, $c"),
225 multiclass F3R_2RBITP<string OpcStr, SDNode OpNode> {
227 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
228 !strconcat(OpcStr, " $dst, $b, $c"),
229 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
231 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
232 !strconcat(OpcStr, " $dst, $b, $c"),
233 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
236 class F3R<string OpcStr, SDNode OpNode> : _F3R<
237 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
238 !strconcat(OpcStr, " $dst, $b, $c"),
239 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
241 class F3R_np<string OpcStr> : _F3R<
242 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
243 !strconcat(OpcStr, " $dst, $b, $c"),
245 // Three operand long
247 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
248 multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> {
250 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
251 !strconcat(OpcStr, " $dst, $b, $c"),
252 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
253 def _l2rus : _FL2RUS<
254 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
255 !strconcat(OpcStr, " $dst, $b, $c"),
256 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
259 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
260 multiclass FL3R_L2RBITP<string OpcStr, SDNode OpNode> {
262 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
263 !strconcat(OpcStr, " $dst, $b, $c"),
264 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
265 def _l2rus : _FL2RUS<
266 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
267 !strconcat(OpcStr, " $dst, $b, $c"),
268 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
271 class FL3R<string OpcStr, SDNode OpNode> : _FL3R<
272 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
273 !strconcat(OpcStr, " $dst, $b, $c"),
274 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
277 // Operand register - U6
278 multiclass FRU6_LRU6_branch<string OpcStr> {
280 (outs), (ins GRRegs:$cond, brtarget:$dest),
281 !strconcat(OpcStr, " $cond, $dest"),
284 (outs), (ins GRRegs:$cond, brtarget:$dest),
285 !strconcat(OpcStr, " $cond, $dest"),
289 multiclass FRU6_LRU6_cp<string OpcStr> {
291 (outs GRRegs:$dst), (ins i32imm:$a),
292 !strconcat(OpcStr, " $dst, cp[$a]"),
295 (outs GRRegs:$dst), (ins i32imm:$a),
296 !strconcat(OpcStr, " $dst, cp[$a]"),
301 multiclass FU6_LU6<string OpcStr, SDNode OpNode> {
303 (outs), (ins i32imm:$b),
304 !strconcat(OpcStr, " $b"),
305 [(OpNode immU6:$b)]>;
307 (outs), (ins i32imm:$b),
308 !strconcat(OpcStr, " $b"),
309 [(OpNode immU16:$b)]>;
312 multiclass FU6_LU6_np<string OpcStr> {
314 (outs), (ins i32imm:$b),
315 !strconcat(OpcStr, " $b"),
318 (outs), (ins i32imm:$b),
319 !strconcat(OpcStr, " $b"),
324 multiclass FU10_LU10_np<string OpcStr> {
326 (outs), (ins i32imm:$b),
327 !strconcat(OpcStr, " $b"),
330 (outs), (ins i32imm:$b),
331 !strconcat(OpcStr, " $b"),
337 class F2R_np<string OpcStr> : _F2R<
338 (outs GRRegs:$dst), (ins GRRegs:$b),
339 !strconcat(OpcStr, " $dst, $b"),
344 //===----------------------------------------------------------------------===//
345 // Pseudo Instructions
346 //===----------------------------------------------------------------------===//
348 let Defs = [SP], Uses = [SP] in {
349 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
350 "${:comment} ADJCALLSTACKDOWN $amt",
351 [(callseq_start timm:$amt)]>;
352 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
353 "${:comment} ADJCALLSTACKUP $amt1",
354 [(callseq_end timm:$amt1, timm:$amt2)]>;
357 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
358 "${:comment} LDWFI $dst, $addr",
359 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
361 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
362 "${:comment} LDAWFI $dst, $addr",
363 [(set GRRegs:$dst, ADDRspii:$addr)]>;
365 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
366 "${:comment} STWFI $src, $addr",
367 [(store GRRegs:$src, ADDRspii:$addr)]>;
369 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
370 // instruction selection into a branch sequence.
371 let usesCustomInserter = 1 in {
372 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
373 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
374 "${:comment} SELECT_CC PSEUDO!",
376 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
379 //===----------------------------------------------------------------------===//
381 //===----------------------------------------------------------------------===//
383 // Three operand short
384 defm ADD : F3R_2RUS<"add", add>;
385 defm SUB : F3R_2RUS<"sub", sub>;
386 let neverHasSideEffects = 1 in {
387 defm EQ : F3R_2RUS_np<"eq">;
388 def LSS_3r : F3R_np<"lss">;
389 def LSU_3r : F3R_np<"lsu">;
391 def AND_3r : F3R<"and", and>;
392 def OR_3r : F3R<"or", or>;
395 def LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
396 "ldw $dst, $addr[$offset]",
399 def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset),
400 "ldw $dst, $addr[$offset]",
403 def LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
404 "ld16s $dst, $addr[$offset]",
407 def LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
408 "ld8u $dst, $addr[$offset]",
413 def STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
414 "stw $val, $addr[$offset]",
417 def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
418 "stw $val, $addr[$offset]",
422 defm SHL : F3R_2RBITP<"shl", shl>;
423 defm SHR : F3R_2RBITP<"shr", srl>;
426 // Three operand long
427 def LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
428 "ldaw $dst, $addr[$offset]",
429 [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>;
431 let neverHasSideEffects = 1 in
432 def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst),
433 (ins GRRegs:$addr, i32imm:$offset),
434 "ldaw $dst, $addr[$offset]",
437 def LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
438 "ldaw $dst, $addr[-$offset]",
439 [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>;
441 let neverHasSideEffects = 1 in
442 def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst),
443 (ins GRRegs:$addr, i32imm:$offset),
444 "ldaw $dst, $addr[-$offset]",
447 def LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
448 "lda16 $dst, $addr[$offset]",
449 [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>;
451 def LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
452 "lda16 $dst, $addr[-$offset]",
453 [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>;
455 def MUL_l3r : FL3R<"mul", mul>;
456 // Instructions which may trap are marked as side effecting.
457 let hasSideEffects = 1 in {
458 def DIVS_l3r : FL3R<"divs", sdiv>;
459 def DIVU_l3r : FL3R<"divu", udiv>;
460 def REMS_l3r : FL3R<"rems", srem>;
461 def REMU_l3r : FL3R<"remu", urem>;
463 def XOR_l3r : FL3R<"xor", xor>;
464 defm ASHR : FL3R_L2RBITP<"ashr", sra>;
465 // TODO crc32, crc8, inpw, outpw
467 def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
468 "st16 $val, $addr[$offset]",
471 def ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
472 "st8 $val, $addr[$offset]",
477 let Constraints = "$src1 = $dst1,$src2 = $dst2" in {
478 def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
479 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
481 "maccu $dst1, $dst2, $src3, $src4",
484 def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
485 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
487 "maccs $dst1, $dst2, $src3, $src4",
493 def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
494 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
495 "ladd $dst1, $dst2, $src1, $src2, $src3",
498 def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
499 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
500 "lsub $dst1, $dst2, $src1, $src2, $src3",
503 def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
504 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
505 "ldiv $dst1, $dst2, $src1, $src2, $src3",
510 def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
511 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
513 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
518 //let Uses = [DP] in ...
519 let neverHasSideEffects = 1, isReMaterializable = 1 in
520 def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
524 let isReMaterializable = 1 in
525 def LDAWDP_lru6: _FLRU6<
526 (outs GRRegs:$dst), (ins MEMii:$a),
528 [(set GRRegs:$dst, ADDRdpii:$a)]>;
531 def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
535 def LDWDP_lru6: _FLRU6<
536 (outs GRRegs:$dst), (ins MEMii:$a),
538 [(set GRRegs:$dst, (load ADDRdpii:$a))]>;
541 def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
542 "stw $val, dp[$addr]",
545 def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
546 "stw $val, dp[$addr]",
547 [(store GRRegs:$val, ADDRdpii:$addr)]>;
549 //let Uses = [CP] in ..
550 let mayLoad = 1, isReMaterializable = 1 in
551 defm LDWCP : FRU6_LRU6_cp<"ldw">;
555 def STWSP_ru6 : _FRU6<
556 (outs), (ins GRRegs:$val, i32imm:$index),
557 "stw $val, sp[$index]",
558 [(XCoreStwsp GRRegs:$val, immU6:$index)]>;
560 def STWSP_lru6 : _FLRU6<
561 (outs), (ins GRRegs:$val, i32imm:$index),
562 "stw $val, sp[$index]",
563 [(XCoreStwsp GRRegs:$val, immU16:$index)]>;
567 def LDWSP_ru6 : _FRU6<
568 (outs GRRegs:$dst), (ins i32imm:$b),
572 def LDWSP_lru6 : _FLRU6<
573 (outs GRRegs:$dst), (ins i32imm:$b),
578 let neverHasSideEffects = 1 in {
579 def LDAWSP_ru6 : _FRU6<
580 (outs GRRegs:$dst), (ins i32imm:$b),
584 def LDAWSP_lru6 : _FLRU6<
585 (outs GRRegs:$dst), (ins i32imm:$b),
589 def LDAWSP_ru6_RRegs : _FRU6<
590 (outs RRegs:$dst), (ins i32imm:$b),
594 def LDAWSP_lru6_RRegs : _FLRU6<
595 (outs RRegs:$dst), (ins i32imm:$b),
601 let isReMaterializable = 1 in {
603 (outs GRRegs:$dst), (ins i32imm:$b),
605 [(set GRRegs:$dst, immU6:$b)]>;
607 def LDC_lru6 : _FLRU6<
608 (outs GRRegs:$dst), (ins i32imm:$b),
610 [(set GRRegs:$dst, immU16:$b)]>;
613 def SETC_ru6 : _FRU6<(outs), (ins GRRegs:$r, i32imm:$val),
614 "setc res[$r], $val",
615 [(int_xcore_setc GRRegs:$r, immU6:$val)]>;
617 def SETC_lru6 : _FLRU6<(outs), (ins GRRegs:$r, i32imm:$val),
618 "setc res[$r], $val",
619 [(int_xcore_setc GRRegs:$r, immU16:$val)]>;
621 // Operand register - U6
622 let isBranch = 1, isTerminator = 1 in {
623 defm BRFT: FRU6_LRU6_branch<"bt">;
624 defm BRBT: FRU6_LRU6_branch<"bt">;
625 defm BRFF: FRU6_LRU6_branch<"bf">;
626 defm BRBF: FRU6_LRU6_branch<"bf">;
630 let Defs = [SP], Uses = [SP] in {
631 let neverHasSideEffects = 1 in
632 defm EXTSP : FU6_LU6_np<"extsp">;
634 defm ENTSP : FU6_LU6_np<"entsp">;
636 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
637 defm RETSP : FU6_LU6<"retsp", XCoreRetsp>;
641 // TODO extdp, kentsp, krestsp, blat, setsr
642 // clrsr, getsr, kalli
643 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
646 (ins brtarget:$target),
650 def BRBU_lu6 : _FLU6<
652 (ins brtarget:$target),
658 (ins brtarget:$target),
662 def BRFU_lu6 : _FLU6<
664 (ins brtarget:$target),
669 //let Uses = [CP] in ...
670 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
671 def LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a),
675 let Defs = [R11], isReMaterializable = 1 in
676 def LDAWCP_lu6: _FLRU6<
677 (outs), (ins MEMii:$a),
679 [(set R11, ADDRcpii:$a)]>;
682 // TODO ldwcpl, blacp
684 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
685 def LDAP_u10 : _FU10<
691 let Defs = [R11], isReMaterializable = 1 in
692 def LDAP_lu10 : _FLU10<
696 [(set R11, (pcrelwrapper tglobaladdr:$addr))]>;
698 let Defs = [R11], isReMaterializable = 1 in
699 def LDAP_lu10_ba : _FLU10<(outs),
702 [(set R11, (pcrelwrapper tblockaddress:$addr))]>;
705 // All calls clobber the link register and the non-callee-saved registers:
706 Defs = [R0, R1, R2, R3, R11, LR] in {
709 (ins calltarget:$target, variable_ops),
711 [(XCoreBranchLink immU10:$target)]>;
713 def BL_lu10 : _FLU10<
715 (ins calltarget:$target, variable_ops),
717 [(XCoreBranchLink immU20:$target)]>;
722 def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
724 [(set GRRegs:$dst, (not GRRegs:$b))]>;
726 def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
728 [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
730 // TODO setd, eet, eef, testwct, tinitpc, tinitdp,
731 // tinitsp, tinitcp, tsetmr, sext (reg), zext (reg)
732 let Constraints = "$src1 = $dst" in {
733 let neverHasSideEffects = 1 in
734 def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
738 let neverHasSideEffects = 1 in
739 def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
743 def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
744 "andnot $dst, $src2",
745 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
748 let isReMaterializable = 1, neverHasSideEffects = 1 in
749 def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size),
753 def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size),
755 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>;
757 def GETR_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$type),
759 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
761 def GETTS_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
762 "getts $dst, res[$r]",
763 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
765 def SETPT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
766 "setpt res[$r], $val",
767 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
769 def OUTCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
770 "outct res[$r], $val",
771 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
773 def OUTCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val),
774 "outct res[$r], $val",
775 [(int_xcore_outct GRRegs:$r, immUs:$val)]>;
777 def OUTT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
778 "outt res[$r], $val",
779 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
781 def OUT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
783 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
785 let Constraints = "$src = $dst" in
786 def OUTSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src),
787 "outshr res[$r], $src",
788 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
790 def INCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
791 "inct $dst, res[$r]",
792 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
794 def INT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
796 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
798 def IN_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
800 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;
802 let Constraints = "$src = $dst" in
803 def INSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src),
804 "inshr $dst, res[$r]",
805 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
807 def CHKCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
808 "chkct res[$r], $val",
809 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
811 def CHKCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val),
812 "chkct res[$r], $val",
813 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
815 def SETD_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
816 "setd res[$r], $val",
817 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
820 // TODO setclk, setrdy, setpsc, endin, peek,
821 // getd, testlcl, tinitlr, getps, setps
822 def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
824 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
826 def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
827 "byterev $dst, $src",
828 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
830 def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
832 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
834 def SETC_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val),
835 "setc res[$r], $val",
836 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;
838 def SETTW_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val),
839 "settw res[$r], $val",
840 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;
843 // TODO edu, eeu, waitet, waitef, tstart, msync, mjoin, clrtp
844 // setdp, setcp, setev, kcall
846 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
847 def BAU_1r : _F1R<(outs), (ins GRRegs:$addr),
849 [(brind GRRegs:$addr)]>;
851 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
852 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
854 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;
856 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
857 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
859 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
861 let Defs=[SP], neverHasSideEffects=1 in
862 def SETSP_1r : _F1R<(outs), (ins GRRegs:$src),
866 let hasCtrlDep = 1 in
867 def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src),
871 let hasCtrlDep = 1 in
872 def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src),
877 // All calls clobber the link register and the non-callee-saved registers:
878 Defs = [R0, R1, R2, R3, R11, LR] in {
879 def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops),
881 [(XCoreBranchLink GRRegs:$addr)]>;
884 def SYNCR_1r : _F1R<(outs), (ins GRRegs:$r),
886 [(int_xcore_syncr GRRegs:$r)]>;
888 def FREER_1r : _F1R<(outs), (ins GRRegs:$r),
890 [(int_xcore_freer GRRegs:$r)]>;
893 def SETV_1r : _F1R<(outs), (ins GRRegs:$r),
895 [(int_xcore_setv GRRegs:$r, R11)]>;
897 // Zero operand short
898 // TODO ssync, freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
899 // stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret,
902 def CLRE_0R : _F0R<(outs), (ins), "clre", [(int_xcore_clre)]>;
905 def GETID_0R : _F0R<(outs), (ins),
907 [(set R11, (int_xcore_getid))]>;
909 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
910 hasSideEffects = 1 in
911 def WAITEU_0R : _F0R<(outs), (ins),
913 [(brind (int_xcore_waitevent))]>;
915 //===----------------------------------------------------------------------===//
916 // Non-Instruction Patterns
917 //===----------------------------------------------------------------------===//
919 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
920 def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
923 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
924 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
925 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
928 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
929 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
930 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
932 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
933 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
934 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
936 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
937 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
938 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
939 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
940 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
943 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
944 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
945 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
946 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
947 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
948 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
951 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
952 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
953 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
954 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
956 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
957 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
958 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
959 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
961 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
962 (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
963 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
964 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
965 def : Pat<(store GRRegs:$val, GRRegs:$addr),
966 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
969 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
972 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
978 // unconditional branch
979 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
981 // direct match equal/notequal zero brcond
982 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
983 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
984 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
985 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
987 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
988 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
989 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
990 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
991 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
992 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
993 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
994 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
995 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
996 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
997 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
998 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
1000 // generic brcond pattern
1001 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
1008 // direct match equal/notequal zero select
1009 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1010 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1012 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1013 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1015 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1016 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1017 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1018 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1019 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1020 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1021 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1022 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1023 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1024 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1025 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
1026 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
1029 /// setcc patterns, only matched when none of the above brcond
1033 // setcc 2 register operands
1034 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
1035 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1036 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
1037 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1039 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1040 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
1041 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
1042 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
1044 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
1045 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1046 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
1047 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1049 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
1050 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
1051 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
1052 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
1054 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
1055 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1057 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
1058 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
1060 // setcc reg/imm operands
1061 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
1062 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
1063 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
1064 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
1067 def : Pat<(add GRRegs:$addr, immUs4:$offset),
1068 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1070 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
1071 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1073 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
1074 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
1076 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1077 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
1078 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
1080 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
1081 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
1087 def : Pat<(mul GRRegs:$src, 3),
1088 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
1090 def : Pat<(mul GRRegs:$src, 5),
1091 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
1093 def : Pat<(mul GRRegs:$src, -3),
1094 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
1096 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
1097 def : Pat<(sra GRRegs:$src, 31),
1098 (ASHR_l2rus GRRegs:$src, 32)>;
1100 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1101 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1103 // setge X, 0 is canonicalized to setgt X, -1
1104 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1105 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1107 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1108 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
1110 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1111 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
1113 def : Pat<(setgt GRRegs:$lhs, -1),
1114 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
1116 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
1117 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;