1 //===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the XCore instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
35 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad]>;
38 def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
41 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,
44 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,
47 def SDT_XCoreAddress : SDTypeProfile<1, 1,
48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
53 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
56 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
59 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
60 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
61 [SDNPHasChain, SDNPMayStore]>;
63 // These are target-independent nodes, but have target-specific formats.
64 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
65 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
68 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
69 [SDNPHasChain, SDNPOutGlue]>;
70 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
71 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
73 //===----------------------------------------------------------------------===//
74 // Instruction Pattern Stuff
75 //===----------------------------------------------------------------------===//
77 def div4_xform : SDNodeXForm<imm, [{
78 // Transformation function: imm/4
79 assert(N->getZExtValue() % 4 == 0);
80 return getI32Imm(N->getZExtValue()/4);
83 def msksize_xform : SDNodeXForm<imm, [{
84 // Transformation function: get the size of a mask
85 assert(isMask_32(N->getZExtValue()));
86 // look for the first non-zero bit
87 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue()));
90 def neg_xform : SDNodeXForm<imm, [{
91 // Transformation function: -imm
92 uint32_t value = N->getZExtValue();
93 return getI32Imm(-value);
96 def bpwsub_xform : SDNodeXForm<imm, [{
97 // Transformation function: 32-imm
98 uint32_t value = N->getZExtValue();
99 return getI32Imm(32-value);
102 def div4neg_xform : SDNodeXForm<imm, [{
103 // Transformation function: -imm/4
104 uint32_t value = N->getZExtValue();
105 assert(-value % 4 == 0);
106 return getI32Imm(-value/4);
109 def immUs4Neg : PatLeaf<(imm), [{
110 uint32_t value = (uint32_t)N->getZExtValue();
111 return (-value)%4 == 0 && (-value)/4 <= 11;
114 def immUs4 : PatLeaf<(imm), [{
115 uint32_t value = (uint32_t)N->getZExtValue();
116 return value%4 == 0 && value/4 <= 11;
119 def immUsNeg : PatLeaf<(imm), [{
120 return -((uint32_t)N->getZExtValue()) <= 11;
123 def immUs : PatLeaf<(imm), [{
124 return (uint32_t)N->getZExtValue() <= 11;
127 def immU6 : PatLeaf<(imm), [{
128 return (uint32_t)N->getZExtValue() < (1 << 6);
131 def immU10 : PatLeaf<(imm), [{
132 return (uint32_t)N->getZExtValue() < (1 << 10);
135 def immU16 : PatLeaf<(imm), [{
136 return (uint32_t)N->getZExtValue() < (1 << 16);
139 def immU20 : PatLeaf<(imm), [{
140 return (uint32_t)N->getZExtValue() < (1 << 20);
143 def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;
145 def immBitp : PatLeaf<(imm), [{
146 uint32_t value = (uint32_t)N->getZExtValue();
147 return (value >= 1 && value <= 8)
153 def immBpwSubBitp : PatLeaf<(imm), [{
154 uint32_t value = (uint32_t)N->getZExtValue();
155 return (value >= 24 && value <= 31)
161 def lda16f : PatFrag<(ops node:$addr, node:$offset),
162 (add node:$addr, (shl node:$offset, 1))>;
163 def lda16b : PatFrag<(ops node:$addr, node:$offset),
164 (sub node:$addr, (shl node:$offset, 1))>;
165 def ldawf : PatFrag<(ops node:$addr, node:$offset),
166 (add node:$addr, (shl node:$offset, 2))>;
167 def ldawb : PatFrag<(ops node:$addr, node:$offset),
168 (sub node:$addr, (shl node:$offset, 2))>;
170 // Instruction operand types
171 def calltarget : Operand<i32>;
172 def brtarget : Operand<OtherVT>;
173 def pclabel : Operand<i32>;
176 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
177 def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper],
179 def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper],
183 def MEMii : Operand<i32> {
184 let PrintMethod = "printMemOperand";
185 let MIOperandInfo = (ops i32imm, i32imm);
189 def InlineJT : Operand<i32> {
190 let PrintMethod = "printInlineJT";
193 def InlineJT32 : Operand<i32> {
194 let PrintMethod = "printInlineJT32";
197 //===----------------------------------------------------------------------===//
198 // Instruction Class Templates
199 //===----------------------------------------------------------------------===//
201 // Three operand short
203 multiclass F3R_2RUS<string OpcStr, SDNode OpNode> {
205 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
206 !strconcat(OpcStr, " $dst, $b, $c"),
207 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
209 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
210 !strconcat(OpcStr, " $dst, $b, $c"),
211 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
214 multiclass F3R_2RUS_np<string OpcStr> {
216 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
217 !strconcat(OpcStr, " $dst, $b, $c"),
220 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
221 !strconcat(OpcStr, " $dst, $b, $c"),
225 multiclass F3R_2RBITP<string OpcStr, SDNode OpNode> {
227 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
228 !strconcat(OpcStr, " $dst, $b, $c"),
229 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
231 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
232 !strconcat(OpcStr, " $dst, $b, $c"),
233 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
236 class F3R<string OpcStr, SDNode OpNode> : _F3R<
237 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
238 !strconcat(OpcStr, " $dst, $b, $c"),
239 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
241 class F3R_np<string OpcStr> : _F3R<
242 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
243 !strconcat(OpcStr, " $dst, $b, $c"),
245 // Three operand long
247 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
248 multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> {
250 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
251 !strconcat(OpcStr, " $dst, $b, $c"),
252 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
253 def _l2rus : _FL2RUS<
254 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
255 !strconcat(OpcStr, " $dst, $b, $c"),
256 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
259 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
260 multiclass FL3R_L2RBITP<string OpcStr, SDNode OpNode> {
262 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
263 !strconcat(OpcStr, " $dst, $b, $c"),
264 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
265 def _l2rus : _FL2RUS<
266 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
267 !strconcat(OpcStr, " $dst, $b, $c"),
268 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
271 class FL3R<string OpcStr, SDNode OpNode> : _FL3R<
272 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
273 !strconcat(OpcStr, " $dst, $b, $c"),
274 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
277 // Operand register - U6
278 multiclass FRU6_LRU6_branch<string OpcStr> {
280 (outs), (ins GRRegs:$cond, brtarget:$dest),
281 !strconcat(OpcStr, " $cond, $dest"),
284 (outs), (ins GRRegs:$cond, brtarget:$dest),
285 !strconcat(OpcStr, " $cond, $dest"),
289 multiclass FRU6_LRU6_cp<string OpcStr> {
291 (outs GRRegs:$dst), (ins i32imm:$a),
292 !strconcat(OpcStr, " $dst, cp[$a]"),
295 (outs GRRegs:$dst), (ins i32imm:$a),
296 !strconcat(OpcStr, " $dst, cp[$a]"),
301 multiclass FU6_LU6<string OpcStr, SDNode OpNode> {
303 (outs), (ins i32imm:$b),
304 !strconcat(OpcStr, " $b"),
305 [(OpNode immU6:$b)]>;
307 (outs), (ins i32imm:$b),
308 !strconcat(OpcStr, " $b"),
309 [(OpNode immU16:$b)]>;
311 multiclass FU6_LU6_int<string OpcStr, Intrinsic Int> {
313 (outs), (ins i32imm:$b),
314 !strconcat(OpcStr, " $b"),
317 (outs), (ins i32imm:$b),
318 !strconcat(OpcStr, " $b"),
322 multiclass FU6_LU6_np<string OpcStr> {
324 (outs), (ins i32imm:$b),
325 !strconcat(OpcStr, " $b"),
328 (outs), (ins i32imm:$b),
329 !strconcat(OpcStr, " $b"),
334 multiclass FU10_LU10_np<string OpcStr> {
336 (outs), (ins i32imm:$b),
337 !strconcat(OpcStr, " $b"),
340 (outs), (ins i32imm:$b),
341 !strconcat(OpcStr, " $b"),
347 class F2R_np<bits<6> opc, string OpcStr> :
348 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),
349 !strconcat(OpcStr, " $dst, $b"), []>;
353 //===----------------------------------------------------------------------===//
354 // Pseudo Instructions
355 //===----------------------------------------------------------------------===//
357 let Defs = [SP], Uses = [SP] in {
358 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
359 "# ADJCALLSTACKDOWN $amt",
360 [(callseq_start timm:$amt)]>;
361 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
362 "# ADJCALLSTACKUP $amt1",
363 [(callseq_end timm:$amt1, timm:$amt2)]>;
366 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
367 "# LDWFI $dst, $addr",
368 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
370 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
371 "# LDAWFI $dst, $addr",
372 [(set GRRegs:$dst, ADDRspii:$addr)]>;
374 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
375 "# STWFI $src, $addr",
376 [(store GRRegs:$src, ADDRspii:$addr)]>;
378 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
379 // instruction selection into a branch sequence.
380 let usesCustomInserter = 1 in {
381 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
382 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
383 "# SELECT_CC PSEUDO!",
385 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
388 //===----------------------------------------------------------------------===//
390 //===----------------------------------------------------------------------===//
392 // Three operand short
393 defm ADD : F3R_2RUS<"add", add>;
394 defm SUB : F3R_2RUS<"sub", sub>;
395 let neverHasSideEffects = 1 in {
396 defm EQ : F3R_2RUS_np<"eq">;
397 def LSS_3r : F3R_np<"lss">;
398 def LSU_3r : F3R_np<"lsu">;
400 def AND_3r : F3R<"and", and>;
401 def OR_3r : F3R<"or", or>;
404 def LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
405 "ldw $dst, $addr[$offset]",
408 def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset),
409 "ldw $dst, $addr[$offset]",
412 def LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
413 "ld16s $dst, $addr[$offset]",
416 def LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
417 "ld8u $dst, $addr[$offset]",
422 def STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
423 "stw $val, $addr[$offset]",
426 def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
427 "stw $val, $addr[$offset]",
431 defm SHL : F3R_2RBITP<"shl", shl>;
432 defm SHR : F3R_2RBITP<"shr", srl>;
435 // Three operand long
436 def LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
437 "ldaw $dst, $addr[$offset]",
438 [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>;
440 let neverHasSideEffects = 1 in
441 def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst),
442 (ins GRRegs:$addr, i32imm:$offset),
443 "ldaw $dst, $addr[$offset]",
446 def LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
447 "ldaw $dst, $addr[-$offset]",
448 [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>;
450 let neverHasSideEffects = 1 in
451 def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst),
452 (ins GRRegs:$addr, i32imm:$offset),
453 "ldaw $dst, $addr[-$offset]",
456 def LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
457 "lda16 $dst, $addr[$offset]",
458 [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>;
460 def LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
461 "lda16 $dst, $addr[-$offset]",
462 [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>;
464 def MUL_l3r : FL3R<"mul", mul>;
465 // Instructions which may trap are marked as side effecting.
466 let hasSideEffects = 1 in {
467 def DIVS_l3r : FL3R<"divs", sdiv>;
468 def DIVU_l3r : FL3R<"divu", udiv>;
469 def REMS_l3r : FL3R<"rems", srem>;
470 def REMU_l3r : FL3R<"remu", urem>;
472 def XOR_l3r : FL3R<"xor", xor>;
473 defm ASHR : FL3R_L2RBITP<"ashr", sra>;
475 let Constraints = "$src1 = $dst" in
476 def CRC_l3r : _FL3R<(outs GRRegs:$dst),
477 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
478 "crc32 $dst, $src2, $src3",
480 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
485 def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
486 "st16 $val, $addr[$offset]",
489 def ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
490 "st8 $val, $addr[$offset]",
495 let Constraints = "$src1 = $dst1,$src2 = $dst2" in {
496 def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
497 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
499 "maccu $dst1, $dst2, $src3, $src4",
502 def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
503 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
505 "maccs $dst1, $dst2, $src3, $src4",
509 let Constraints = "$src1 = $dst1" in
510 def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
511 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
512 "crc8 $dst1, $dst2, $src2, $src3",
517 def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
518 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
519 "ladd $dst1, $dst2, $src1, $src2, $src3",
522 def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
523 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
524 "lsub $dst1, $dst2, $src1, $src2, $src3",
527 def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
528 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
529 "ldiv $dst1, $dst2, $src1, $src2, $src3",
534 def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
535 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
537 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
542 //let Uses = [DP] in ...
543 let neverHasSideEffects = 1, isReMaterializable = 1 in
544 def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
548 let isReMaterializable = 1 in
549 def LDAWDP_lru6: _FLRU6<
550 (outs GRRegs:$dst), (ins MEMii:$a),
552 [(set GRRegs:$dst, ADDRdpii:$a)]>;
555 def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
559 def LDWDP_lru6: _FLRU6<
560 (outs GRRegs:$dst), (ins MEMii:$a),
562 [(set GRRegs:$dst, (load ADDRdpii:$a))]>;
565 def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
566 "stw $val, dp[$addr]",
569 def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
570 "stw $val, dp[$addr]",
571 [(store GRRegs:$val, ADDRdpii:$addr)]>;
573 //let Uses = [CP] in ..
574 let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in
575 defm LDWCP : FRU6_LRU6_cp<"ldw">;
579 def STWSP_ru6 : _FRU6<
580 (outs), (ins GRRegs:$val, i32imm:$index),
581 "stw $val, sp[$index]",
582 [(XCoreStwsp GRRegs:$val, immU6:$index)]>;
584 def STWSP_lru6 : _FLRU6<
585 (outs), (ins GRRegs:$val, i32imm:$index),
586 "stw $val, sp[$index]",
587 [(XCoreStwsp GRRegs:$val, immU16:$index)]>;
591 def LDWSP_ru6 : _FRU6<
592 (outs GRRegs:$dst), (ins i32imm:$b),
596 def LDWSP_lru6 : _FLRU6<
597 (outs GRRegs:$dst), (ins i32imm:$b),
602 let neverHasSideEffects = 1 in {
603 def LDAWSP_ru6 : _FRU6<
604 (outs GRRegs:$dst), (ins i32imm:$b),
608 def LDAWSP_lru6 : _FLRU6<
609 (outs GRRegs:$dst), (ins i32imm:$b),
613 def LDAWSP_ru6_RRegs : _FRU6<
614 (outs RRegs:$dst), (ins i32imm:$b),
618 def LDAWSP_lru6_RRegs : _FLRU6<
619 (outs RRegs:$dst), (ins i32imm:$b),
625 let isReMaterializable = 1 in {
627 (outs GRRegs:$dst), (ins i32imm:$b),
629 [(set GRRegs:$dst, immU6:$b)]>;
631 def LDC_lru6 : _FLRU6<
632 (outs GRRegs:$dst), (ins i32imm:$b),
634 [(set GRRegs:$dst, immU16:$b)]>;
637 def SETC_ru6 : _FRU6<(outs), (ins GRRegs:$r, i32imm:$val),
638 "setc res[$r], $val",
639 [(int_xcore_setc GRRegs:$r, immU6:$val)]>;
641 def SETC_lru6 : _FLRU6<(outs), (ins GRRegs:$r, i32imm:$val),
642 "setc res[$r], $val",
643 [(int_xcore_setc GRRegs:$r, immU16:$val)]>;
645 // Operand register - U6
646 let isBranch = 1, isTerminator = 1 in {
647 defm BRFT: FRU6_LRU6_branch<"bt">;
648 defm BRBT: FRU6_LRU6_branch<"bt">;
649 defm BRFF: FRU6_LRU6_branch<"bf">;
650 defm BRBF: FRU6_LRU6_branch<"bf">;
654 let Defs = [SP], Uses = [SP] in {
655 let neverHasSideEffects = 1 in
656 defm EXTSP : FU6_LU6_np<"extsp">;
658 defm ENTSP : FU6_LU6_np<"entsp">;
660 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
661 defm RETSP : FU6_LU6<"retsp", XCoreRetsp>;
665 // TODO extdp, kentsp, krestsp, blat
667 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
670 (ins brtarget:$target),
674 def BRBU_lu6 : _FLU6<
676 (ins brtarget:$target),
682 (ins brtarget:$target),
686 def BRFU_lu6 : _FLU6<
688 (ins brtarget:$target),
693 //let Uses = [CP] in ...
694 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
695 def LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a),
699 let Defs = [R11], isReMaterializable = 1 in
700 def LDAWCP_lu6: _FLRU6<
701 (outs), (ins MEMii:$a),
703 [(set R11, ADDRcpii:$a)]>;
705 defm SETSR : FU6_LU6_int<"setsr", int_xcore_setsr>;
707 defm CLRSR : FU6_LU6_int<"clrsr", int_xcore_clrsr>;
709 // setsr may cause a branch if it is used to enable events. clrsr may
710 // branch if it is executed while events are enabled.
711 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in {
712 defm SETSR_branch : FU6_LU6_np<"setsr">;
713 defm CLRSR_branch : FU6_LU6_np<"clrsr">;
717 // TODO ldwcpl, blacp
719 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
720 def LDAP_u10 : _FU10<
726 let Defs = [R11], isReMaterializable = 1 in
727 def LDAP_lu10 : _FLU10<
731 [(set R11, (pcrelwrapper tglobaladdr:$addr))]>;
733 let Defs = [R11], isReMaterializable = 1 in
734 def LDAP_lu10_ba : _FLU10<(outs),
737 [(set R11, (pcrelwrapper tblockaddress:$addr))]>;
740 // All calls clobber the link register and the non-callee-saved registers:
741 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
743 (outs), (ins calltarget:$target),
745 [(XCoreBranchLink immU10:$target)]>;
747 def BL_lu10 : _FLU10<
748 (outs), (ins calltarget:$target),
750 [(XCoreBranchLink immU20:$target)]>;
754 // TODO eet, eef, tsetmr
755 def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),
756 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;
758 def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),
759 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
761 let Constraints = "$src1 = $dst" in {
762 def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
764 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
768 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
770 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
772 def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
774 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
778 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
780 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
783 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
784 "andnot $dst, $src2",
785 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
788 let isReMaterializable = 1, neverHasSideEffects = 1 in
789 def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size),
793 def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),
795 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
797 def GETR_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$type),
799 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
801 def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r),
802 "getts $dst, res[$r]",
803 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
805 def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val),
806 "setpt res[$r], $val",
807 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
809 def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),
810 "outct res[$r], $val",
811 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
813 def OUTCT_rus : _F2RUS<(outs), (ins GRRegs:$r, i32imm:$val),
814 "outct res[$r], $val",
815 [(int_xcore_outct GRRegs:$r, immUs:$val)]>;
817 def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val),
818 "outt res[$r], $val",
819 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
821 def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val),
823 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
825 let Constraints = "$src = $dst" in
827 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
828 "outshr res[$r], $src",
829 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
831 def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r),
832 "inct $dst, res[$r]",
833 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
835 def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r),
837 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
839 def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r),
841 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;
843 let Constraints = "$src = $dst" in
845 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
846 "inshr $dst, res[$r]",
847 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
849 def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),
850 "chkct res[$r], $val",
851 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
853 def CHKCT_rus : _F2RUS<(outs), (ins GRRegs:$r, i32imm:$val),
854 "chkct res[$r], $val",
855 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
857 def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src),
858 "testct $dst, res[$src]",
859 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>;
861 def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src),
862 "testwct $dst, res[$src]",
863 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>;
865 def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val),
866 "setd res[$r], $val",
867 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
869 def SETPSC_l2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
870 "setpsc res[$src1], $src2",
871 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
873 def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r),
874 "getst $dst, res[$r]",
875 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;
877 def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t),
878 "init t[$t]:sp, $src",
879 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;
881 def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t),
882 "init t[$t]:pc, $src",
883 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;
885 def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t),
886 "init t[$t]:cp, $src",
887 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;
889 def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t),
890 "init t[$t]:dp, $src",
891 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
895 def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
897 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
899 def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
900 "byterev $dst, $src",
901 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
903 def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
905 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
907 def SETC_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val),
908 "setc res[$r], $val",
909 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;
911 def SETTW_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val),
912 "settw res[$r], $val",
913 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;
915 def GETPS_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
916 "get $dst, ps[$src]",
917 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>;
919 def SETPS_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
920 "set ps[$src1], $src2",
921 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;
923 def INITLR_l2r : _FL2R<(outs), (ins GRRegs:$t, GRRegs:$src),
924 "init t[$t]:lr, $src",
925 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>;
927 def SETCLK_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
928 "setclk res[$src1], $src2",
929 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;
931 def SETRDY_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
932 "setrdy res[$src1], $src2",
933 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
935 def PEEK_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
936 "peek $dst, res[$src]",
937 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;
939 def ENDIN_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
940 "endin $dst, res[$src]",
941 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
944 // TODO edu, eeu, waitet, waitef, tstart, clrtp
945 // setdp, setcp, setev, kcall
947 def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
949 [(int_xcore_msync GRRegs:$a)]>;
950 def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a),
952 [(int_xcore_mjoin GRRegs:$a)]>;
954 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
955 def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a),
957 [(brind GRRegs:$a)]>;
959 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
960 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
962 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;
964 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
965 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
967 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
969 let Defs=[SP], neverHasSideEffects=1 in
970 def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a),
974 let hasCtrlDep = 1 in
975 def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a),
979 let hasCtrlDep = 1 in
980 def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a),
985 // All calls clobber the link register and the non-callee-saved registers:
986 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
987 def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a),
989 [(XCoreBranchLink GRRegs:$a)]>;
992 def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a),
994 [(int_xcore_syncr GRRegs:$a)]>;
996 def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a),
998 [(int_xcore_freer GRRegs:$a)]>;
1001 def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a),
1002 "setv res[$a], r11",
1003 [(int_xcore_setv GRRegs:$a, R11)]>;
1005 def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),
1006 "setev res[$a], r11",
1007 [(int_xcore_setev GRRegs:$a, R11)]>;
1010 def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
1012 [(int_xcore_eeu GRRegs:$a)]>;
1014 // Zero operand short
1015 // TODO freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
1016 // stet, getkep, getksp, setkep, getid, kret, dcall, dret,
1019 def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
1021 let Defs = [R11] in {
1022 def GETID_0R : _F0R<0b0001001110, (outs), (ins),
1024 [(set R11, (int_xcore_getid))]>;
1026 def GETED_0R : _F0R<0b0000111110, (outs), (ins),
1028 [(set R11, (int_xcore_geted))]>;
1030 def GETET_0R : _F0R<0b0000111111, (outs), (ins),
1032 [(set R11, (int_xcore_getet))]>;
1035 def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),
1037 [(int_xcore_ssync)]>;
1039 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
1040 hasSideEffects = 1 in
1041 def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),
1043 [(brind (int_xcore_waitevent))]>;
1045 //===----------------------------------------------------------------------===//
1046 // Non-Instruction Patterns
1047 //===----------------------------------------------------------------------===//
1049 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
1050 def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
1053 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
1054 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
1055 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
1058 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1059 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1060 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1062 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1063 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1064 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1066 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
1067 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
1068 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
1069 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1070 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
1073 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1074 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1075 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1076 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1077 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1078 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1081 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
1082 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1083 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
1084 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1086 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
1087 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1088 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
1089 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1091 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
1092 (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1093 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
1094 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
1095 def : Pat<(store GRRegs:$val, GRRegs:$addr),
1096 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
1099 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
1102 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
1108 // unconditional branch
1109 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
1111 // direct match equal/notequal zero brcond
1112 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
1113 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
1114 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
1115 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
1117 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1118 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1119 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1120 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1121 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1122 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1123 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1124 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1125 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1126 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1127 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
1128 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
1130 // generic brcond pattern
1131 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
1138 // direct match equal/notequal zero select
1139 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1140 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1142 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1143 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1145 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1146 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1147 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1148 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1149 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1150 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1151 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1152 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1153 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1154 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1155 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
1156 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
1159 /// setcc patterns, only matched when none of the above brcond
1163 // setcc 2 register operands
1164 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
1165 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1166 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
1167 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1169 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1170 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
1171 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
1172 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
1174 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
1175 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1176 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
1177 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1179 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
1180 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
1181 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
1182 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
1184 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
1185 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1187 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
1188 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
1190 // setcc reg/imm operands
1191 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
1192 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
1193 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
1194 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
1197 def : Pat<(add GRRegs:$addr, immUs4:$offset),
1198 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1200 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
1201 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1203 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
1204 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
1206 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1207 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
1208 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
1210 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
1211 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
1217 def : Pat<(mul GRRegs:$src, 3),
1218 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
1220 def : Pat<(mul GRRegs:$src, 5),
1221 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
1223 def : Pat<(mul GRRegs:$src, -3),
1224 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
1226 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
1227 def : Pat<(sra GRRegs:$src, 31),
1228 (ASHR_l2rus GRRegs:$src, 32)>;
1230 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1231 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1233 // setge X, 0 is canonicalized to setgt X, -1
1234 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1235 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1237 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1238 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
1240 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1241 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
1243 def : Pat<(setgt GRRegs:$lhs, -1),
1244 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
1246 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
1247 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;