1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Type.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
39 : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
44 static inline bool isImmUs(unsigned val) {
48 static inline bool isImmU6(unsigned val) {
49 return val < (1 << 6);
52 static inline bool isImmU16(unsigned val) {
53 return val < (1 << 16);
56 static const unsigned XCore_ArgRegs[] = {
57 XCore::R0, XCore::R1, XCore::R2, XCore::R3
60 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
65 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
67 return array_lengthof(XCore_ArgRegs);
70 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
71 return MF.getMMI().hasDebugInfo() || !MF.getFunction()->doesNotThrow() ||
72 UnwindTablesMandatory;
75 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
77 static const unsigned CalleeSavedRegs[] = {
78 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
79 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
82 return CalleeSavedRegs;
85 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
86 BitVector Reserved(getNumRegs());
87 Reserved.set(XCore::CP);
88 Reserved.set(XCore::DP);
89 Reserved.set(XCore::SP);
90 Reserved.set(XCore::LR);
92 Reserved.set(XCore::R10);
98 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
99 // TODO can we estimate stack size?
103 bool XCoreRegisterInfo::hasFP(const MachineFunction &MF) const {
104 return DisableFramePointerElim(MF) || MF.getFrameInfo()->hasVarSizedObjects();
107 // This function eliminates ADJCALLSTACKDOWN,
108 // ADJCALLSTACKUP pseudo instructions
109 void XCoreRegisterInfo::
110 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator I) const {
112 if (!hasReservedCallFrame(MF)) {
113 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
114 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
115 MachineInstr *Old = I;
116 uint64_t Amount = Old->getOperand(0).getImm();
118 // We need to keep the stack aligned properly. To do this, we round the
119 // amount of space needed for the outgoing arguments up to the next
120 // alignment boundary.
121 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
122 Amount = (Amount+Align-1)/Align*Align;
124 assert(Amount%4 == 0);
127 bool isU6 = isImmU6(Amount);
129 if (!isU6 && !isImmU16(Amount)) {
130 // FIX could emit multiple instructions in this case.
132 errs() << "eliminateCallFramePseudoInstr size too big: "
139 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
140 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
141 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
144 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
145 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
146 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
150 // Replace the pseudo instruction with a new instruction...
159 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
160 int SPAdj, FrameIndexValue *Value,
161 RegScavenger *RS) const {
162 assert(SPAdj == 0 && "Unexpected");
163 MachineInstr &MI = *II;
164 DebugLoc dl = MI.getDebugLoc();
167 while (!MI.getOperand(i).isFI()) {
169 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
172 MachineOperand &FrameOp = MI.getOperand(i);
173 int FrameIndex = FrameOp.getIndex();
175 MachineFunction &MF = *MI.getParent()->getParent();
176 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
177 int StackSize = MF.getFrameInfo()->getStackSize();
180 DEBUG(errs() << "\nFunction : "
181 << MF.getFunction()->getName() << "\n");
182 DEBUG(errs() << "<--------->\n");
183 DEBUG(MI.print(errs()));
184 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
185 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
186 DEBUG(errs() << "StackSize : " << StackSize << "\n");
191 // fold constant into offset.
192 Offset += MI.getOperand(i + 1).getImm();
193 MI.getOperand(i + 1).ChangeToImmediate(0);
195 assert(Offset%4 == 0 && "Misaligned stack offset");
197 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
203 unsigned Reg = MI.getOperand(0).getReg();
204 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
206 assert(XCore::GRRegsRegisterClass->contains(Reg) &&
207 "Unexpected register operand");
209 MachineBasicBlock &MBB = *MI.getParent();
212 bool isUs = isImmUs(Offset);
213 unsigned FramePtr = XCore::R10;
217 report_fatal_error("eliminateFrameIndex Frame size too big: " +
219 unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
221 loadConstant(MBB, II, ScratchReg, Offset, dl);
222 switch (MI.getOpcode()) {
224 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
226 .addReg(ScratchReg, RegState::Kill);
229 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
230 .addReg(Reg, getKillRegState(isKill))
232 .addReg(ScratchReg, RegState::Kill);
235 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
237 .addReg(ScratchReg, RegState::Kill);
240 llvm_unreachable("Unexpected Opcode");
243 switch (MI.getOpcode()) {
245 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
250 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
251 .addReg(Reg, getKillRegState(isKill))
256 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
261 llvm_unreachable("Unexpected Opcode");
265 bool isU6 = isImmU6(Offset);
266 if (!isU6 && !isImmU16(Offset))
267 report_fatal_error("eliminateFrameIndex Frame size too big: " +
270 switch (MI.getOpcode()) {
273 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
274 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
278 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
279 BuildMI(MBB, II, dl, TII.get(NewOpcode))
280 .addReg(Reg, getKillRegState(isKill))
284 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
285 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
289 llvm_unreachable("Unexpected Opcode");
292 // Erase old instruction.
298 XCoreRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
299 RegScavenger *RS) const {
300 MachineFrameInfo *MFI = MF.getFrameInfo();
301 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
302 const TargetRegisterClass *RC = XCore::GRRegsRegisterClass;
303 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
305 MF.getRegInfo().setPhysRegUnused(XCore::LR);
307 bool isVarArg = MF.getFunction()->isVarArg();
310 // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
311 FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true);
313 FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(),
316 XFI->setUsesLR(FrameIdx);
317 XFI->setLRSpillSlot(FrameIdx);
319 if (requiresRegisterScavenging(MF)) {
320 // Reserve a slot close to SP or frame pointer.
321 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
326 // A callee save register is used to hold the FP.
327 // This needs saving / restoring in the epilogue / prologue.
328 XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(),
334 void XCoreRegisterInfo::
335 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
339 void XCoreRegisterInfo::
340 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
341 unsigned DstReg, int64_t Value, DebugLoc dl) const {
342 // TODO use mkmsk if possible.
343 if (!isImmU16(Value)) {
344 // TODO use constant pool.
345 report_fatal_error("loadConstant value too big " + Twine(Value));
347 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
348 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
351 void XCoreRegisterInfo::
352 storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
353 unsigned SrcReg, int Offset, DebugLoc dl) const {
354 assert(Offset%4 == 0 && "Misaligned stack offset");
356 bool isU6 = isImmU6(Offset);
357 if (!isU6 && !isImmU16(Offset))
358 report_fatal_error("storeToStack offset too big " + Twine(Offset));
359 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
360 BuildMI(MBB, I, dl, TII.get(Opcode))
365 void XCoreRegisterInfo::
366 loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
367 unsigned DstReg, int Offset, DebugLoc dl) const {
368 assert(Offset%4 == 0 && "Misaligned stack offset");
370 bool isU6 = isImmU6(Offset);
371 if (!isU6 && !isImmU16(Offset))
372 report_fatal_error("loadFromStack offset too big " + Twine(Offset));
373 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
374 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
378 void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const {
379 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
380 MachineBasicBlock::iterator MBBI = MBB.begin();
381 MachineFrameInfo *MFI = MF.getFrameInfo();
382 MachineModuleInfo *MMI = &MF.getMMI();
383 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
384 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
388 // Work out frame sizes.
389 int FrameSize = MFI->getStackSize();
391 assert(FrameSize%4 == 0 && "Misaligned frame size");
395 bool isU6 = isImmU6(FrameSize);
397 if (!isU6 && !isImmU16(FrameSize)) {
398 // FIXME could emit multiple instructions.
399 report_fatal_error("emitPrologue Frame size too big: " + Twine(FrameSize));
401 bool emitFrameMoves = needsFrameMoves(MF);
403 // Do we need to allocate space on the stack?
405 bool saveLR = XFI->getUsesLR();
406 bool LRSavedOnEntry = false;
408 if (saveLR && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0)) {
409 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
410 MBB.addLiveIn(XCore::LR);
412 LRSavedOnEntry = true;
414 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
416 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
418 if (emitFrameMoves) {
419 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
421 // Show update of SP.
422 MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
423 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
425 MachineLocation SPDst(MachineLocation::VirtualFP);
426 MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize * 4);
427 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
429 if (LRSavedOnEntry) {
430 MachineLocation CSDst(MachineLocation::VirtualFP, 0);
431 MachineLocation CSSrc(XCore::LR);
432 Moves.push_back(MachineMove(FrameLabel, CSDst, CSSrc));
436 int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
437 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl);
438 MBB.addLiveIn(XCore::LR);
440 if (emitFrameMoves) {
441 MCSymbol *SaveLRLabel = MMI->getContext().CreateTempSymbol();
442 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel);
443 MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset);
444 MachineLocation CSSrc(XCore::LR);
445 MMI->getFrameMoves().push_back(MachineMove(SaveLRLabel, CSDst, CSSrc));
451 // Save R10 to the stack.
452 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
453 storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl);
454 // R10 is live-in. It is killed at the spill.
455 MBB.addLiveIn(XCore::R10);
456 if (emitFrameMoves) {
457 MCSymbol *SaveR10Label = MMI->getContext().CreateTempSymbol();
458 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveR10Label);
459 MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset);
460 MachineLocation CSSrc(XCore::R10);
461 MMI->getFrameMoves().push_back(MachineMove(SaveR10Label, CSDst, CSSrc));
463 // Set the FP from the SP.
464 unsigned FramePtr = XCore::R10;
465 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
467 if (emitFrameMoves) {
468 // Show FP is now valid.
469 MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
470 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
471 MachineLocation SPDst(FramePtr);
472 MachineLocation SPSrc(MachineLocation::VirtualFP);
473 MMI->getFrameMoves().push_back(MachineMove(FrameLabel, SPDst, SPSrc));
477 if (emitFrameMoves) {
478 // Frame moves for callee saved.
479 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
480 std::vector<std::pair<MCSymbol*, CalleeSavedInfo> >&SpillLabels =
481 XFI->getSpillLabels();
482 for (unsigned I = 0, E = SpillLabels.size(); I != E; ++I) {
483 MCSymbol *SpillLabel = SpillLabels[I].first;
484 CalleeSavedInfo &CSI = SpillLabels[I].second;
485 int Offset = MFI->getObjectOffset(CSI.getFrameIdx());
486 unsigned Reg = CSI.getReg();
487 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
488 MachineLocation CSSrc(Reg);
489 Moves.push_back(MachineMove(SpillLabel, CSDst, CSSrc));
494 void XCoreRegisterInfo::emitEpilogue(MachineFunction &MF,
495 MachineBasicBlock &MBB) const {
496 MachineFrameInfo *MFI = MF.getFrameInfo();
497 MachineBasicBlock::iterator MBBI = prior(MBB.end());
498 DebugLoc dl = MBBI->getDebugLoc();
503 // Restore the stack pointer.
504 unsigned FramePtr = XCore::R10;
505 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
509 // Work out frame sizes.
510 int FrameSize = MFI->getStackSize();
512 assert(FrameSize%4 == 0 && "Misaligned frame size");
516 bool isU6 = isImmU6(FrameSize);
518 if (!isU6 && !isImmU16(FrameSize)) {
519 // FIXME could emit multiple instructions.
520 report_fatal_error("emitEpilogue Frame size too big: " + Twine(FrameSize));
524 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
528 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
529 FPSpillOffset += FrameSize*4;
530 loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl);
532 bool restoreLR = XFI->getUsesLR();
533 if (restoreLR && MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0) {
534 int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
535 LRSpillOffset += FrameSize*4;
536 loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl);
540 // Fold prologue into return instruction
541 assert(MBBI->getOpcode() == XCore::RETSP_u6
542 || MBBI->getOpcode() == XCore::RETSP_lu6);
543 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
544 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
547 int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
548 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize);
553 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
554 return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
557 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
560 return FP ? XCore::R10 : XCore::SP;
563 unsigned XCoreRegisterInfo::getRARegister() const {
567 void XCoreRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
569 // Initial state of the frame pointer is SP.
570 MachineLocation Dst(MachineLocation::VirtualFP);
571 MachineLocation Src(XCore::SP, 0);
572 Moves.push_back(MachineMove(0, Dst, Src));
575 #include "XCoreGenRegisterInfo.inc"