1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Type.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
39 : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
44 static inline bool isImmUs(unsigned val) {
48 static inline bool isImmU6(unsigned val) {
49 return val < (1 << 6);
52 static inline bool isImmU16(unsigned val) {
53 return val < (1 << 16);
56 static const unsigned XCore_ArgRegs[] = {
57 XCore::R0, XCore::R1, XCore::R2, XCore::R3
60 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
65 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
67 return array_lengthof(XCore_ArgRegs);
70 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF)
72 const MachineFrameInfo *MFI = MF.getFrameInfo();
73 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
74 return (MMI && MMI->hasDebugInfo()) ||
75 !MF.getFunction()->doesNotThrow() ||
76 UnwindTablesMandatory;
79 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
81 static const unsigned CalleeSavedRegs[] = {
82 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
83 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
86 return CalleeSavedRegs;
89 const TargetRegisterClass* const*
90 XCoreRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
91 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
92 XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
93 XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
94 XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
95 XCore::GRRegsRegisterClass, XCore::RRegsRegisterClass,
98 return CalleeSavedRegClasses;
101 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
102 BitVector Reserved(getNumRegs());
103 Reserved.set(XCore::CP);
104 Reserved.set(XCore::DP);
105 Reserved.set(XCore::SP);
106 Reserved.set(XCore::LR);
108 Reserved.set(XCore::R10);
114 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
115 // TODO can we estimate stack size?
119 bool XCoreRegisterInfo::hasFP(const MachineFunction &MF) const {
120 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
123 // This function eliminates ADJCALLSTACKDOWN,
124 // ADJCALLSTACKUP pseudo instructions
125 void XCoreRegisterInfo::
126 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
127 MachineBasicBlock::iterator I) const {
128 if (!hasReservedCallFrame(MF)) {
129 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
130 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
131 MachineInstr *Old = I;
132 uint64_t Amount = Old->getOperand(0).getImm();
134 // We need to keep the stack aligned properly. To do this, we round the
135 // amount of space needed for the outgoing arguments up to the next
136 // alignment boundary.
137 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
138 Amount = (Amount+Align-1)/Align*Align;
140 assert(Amount%4 == 0);
143 bool isU6 = isImmU6(Amount);
145 if (!isU6 && !isImmU16(Amount)) {
146 // FIX could emit multiple instructions in this case.
148 errs() << "eliminateCallFramePseudoInstr size too big: "
155 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
156 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
157 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
160 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
161 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
162 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
166 // Replace the pseudo instruction with a new instruction...
175 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
176 int SPAdj, int *Value,
177 RegScavenger *RS) const {
178 assert(SPAdj == 0 && "Unexpected");
179 MachineInstr &MI = *II;
180 DebugLoc dl = MI.getDebugLoc();
183 while (!MI.getOperand(i).isFI()) {
185 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
188 MachineOperand &FrameOp = MI.getOperand(i);
189 int FrameIndex = FrameOp.getIndex();
191 MachineFunction &MF = *MI.getParent()->getParent();
192 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
193 int StackSize = MF.getFrameInfo()->getStackSize();
196 DEBUG(errs() << "\nFunction : "
197 << MF.getFunction()->getName() << "\n");
198 DEBUG(errs() << "<--------->\n");
199 DEBUG(MI.print(errs()));
200 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
201 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
202 DEBUG(errs() << "StackSize : " << StackSize << "\n");
207 // fold constant into offset.
208 Offset += MI.getOperand(i + 1).getImm();
209 MI.getOperand(i + 1).ChangeToImmediate(0);
211 assert(Offset%4 == 0 && "Misaligned stack offset");
213 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
219 unsigned Reg = MI.getOperand(0).getReg();
220 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
222 assert(XCore::GRRegsRegisterClass->contains(Reg) &&
223 "Unexpected register operand");
225 MachineBasicBlock &MBB = *MI.getParent();
228 bool isUs = isImmUs(Offset);
229 unsigned FramePtr = XCore::R10;
234 raw_string_ostream Msg(msg);
235 Msg << "eliminateFrameIndex Frame size too big: " << Offset;
236 llvm_report_error(Msg.str());
238 unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
240 loadConstant(MBB, II, ScratchReg, Offset, dl);
241 switch (MI.getOpcode()) {
243 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
245 .addReg(ScratchReg, RegState::Kill);
248 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
249 .addReg(Reg, getKillRegState(isKill))
251 .addReg(ScratchReg, RegState::Kill);
254 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
256 .addReg(ScratchReg, RegState::Kill);
259 llvm_unreachable("Unexpected Opcode");
262 switch (MI.getOpcode()) {
264 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
269 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
270 .addReg(Reg, getKillRegState(isKill))
275 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
280 llvm_unreachable("Unexpected Opcode");
284 bool isU6 = isImmU6(Offset);
285 if (!isU6 && !isImmU16(Offset)) {
287 raw_string_ostream Msg(msg);
288 Msg << "eliminateFrameIndex Frame size too big: " << Offset;
289 llvm_report_error(Msg.str());
292 switch (MI.getOpcode()) {
295 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
296 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
300 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
301 BuildMI(MBB, II, dl, TII.get(NewOpcode))
302 .addReg(Reg, getKillRegState(isKill))
306 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
307 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
311 llvm_unreachable("Unexpected Opcode");
314 // Erase old instruction.
320 XCoreRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
321 RegScavenger *RS) const {
322 MachineFrameInfo *MFI = MF.getFrameInfo();
323 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
324 const TargetRegisterClass *RC = XCore::GRRegsRegisterClass;
325 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
327 MF.getRegInfo().setPhysRegUnused(XCore::LR);
329 bool isVarArg = MF.getFunction()->isVarArg();
332 // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
333 FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0);
335 FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
337 XFI->setUsesLR(FrameIdx);
338 XFI->setLRSpillSlot(FrameIdx);
340 if (requiresRegisterScavenging(MF)) {
341 // Reserve a slot close to SP or frame pointer.
342 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
343 RC->getAlignment()));
346 // A callee save register is used to hold the FP.
347 // This needs saving / restoring in the epilogue / prologue.
348 XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(),
349 RC->getAlignment()));
353 void XCoreRegisterInfo::
354 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
358 void XCoreRegisterInfo::
359 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
360 unsigned DstReg, int64_t Value, DebugLoc dl) const {
361 // TODO use mkmsk if possible.
362 if (!isImmU16(Value)) {
363 // TODO use constant pool.
365 raw_string_ostream Msg(msg);
366 Msg << "loadConstant value too big " << Value;
367 llvm_report_error(Msg.str());
369 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
370 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
373 void XCoreRegisterInfo::
374 storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
375 unsigned SrcReg, int Offset, DebugLoc dl) const {
376 assert(Offset%4 == 0 && "Misaligned stack offset");
378 bool isU6 = isImmU6(Offset);
379 if (!isU6 && !isImmU16(Offset)) {
381 raw_string_ostream Msg(msg);
382 Msg << "storeToStack offset too big " << Offset;
383 llvm_report_error(Msg.str());
385 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
386 BuildMI(MBB, I, dl, TII.get(Opcode))
391 void XCoreRegisterInfo::
392 loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
393 unsigned DstReg, int Offset, DebugLoc dl) const {
394 assert(Offset%4 == 0 && "Misaligned stack offset");
396 bool isU6 = isImmU6(Offset);
397 if (!isU6 && !isImmU16(Offset)) {
399 raw_string_ostream Msg(msg);
400 Msg << "loadFromStack offset too big " << Offset;
401 llvm_report_error(Msg.str());
403 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
404 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
408 void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const {
409 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
410 MachineBasicBlock::iterator MBBI = MBB.begin();
411 MachineFrameInfo *MFI = MF.getFrameInfo();
412 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
413 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
414 DebugLoc dl = (MBBI != MBB.end() ?
415 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
419 // Work out frame sizes.
420 int FrameSize = MFI->getStackSize();
422 assert(FrameSize%4 == 0 && "Misaligned frame size");
426 bool isU6 = isImmU6(FrameSize);
428 if (!isU6 && !isImmU16(FrameSize)) {
429 // FIXME could emit multiple instructions.
431 raw_string_ostream Msg(msg);
432 Msg << "emitPrologue Frame size too big: " << FrameSize;
433 llvm_report_error(Msg.str());
435 bool emitFrameMoves = needsFrameMoves(MF);
437 // Do we need to allocate space on the stack?
439 bool saveLR = XFI->getUsesLR();
440 bool LRSavedOnEntry = false;
442 if (saveLR && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0)) {
443 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
444 MBB.addLiveIn(XCore::LR);
446 LRSavedOnEntry = true;
448 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
450 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
452 if (emitFrameMoves) {
453 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
455 // Show update of SP.
456 unsigned FrameLabelId = MMI->NextLabelID();
457 BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId);
459 MachineLocation SPDst(MachineLocation::VirtualFP);
460 MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize * 4);
461 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
463 if (LRSavedOnEntry) {
464 MachineLocation CSDst(MachineLocation::VirtualFP, 0);
465 MachineLocation CSSrc(XCore::LR);
466 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
470 int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
471 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl);
472 MBB.addLiveIn(XCore::LR);
474 if (emitFrameMoves) {
475 unsigned SaveLRLabelId = MMI->NextLabelID();
476 BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(SaveLRLabelId);
477 MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset);
478 MachineLocation CSSrc(XCore::LR);
479 MMI->getFrameMoves().push_back(MachineMove(SaveLRLabelId,
486 // Save R10 to the stack.
487 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
488 storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl);
489 // R10 is live-in. It is killed at the spill.
490 MBB.addLiveIn(XCore::R10);
491 if (emitFrameMoves) {
492 unsigned SaveR10LabelId = MMI->NextLabelID();
493 BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(SaveR10LabelId);
494 MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset);
495 MachineLocation CSSrc(XCore::R10);
496 MMI->getFrameMoves().push_back(MachineMove(SaveR10LabelId,
499 // Set the FP from the SP.
500 unsigned FramePtr = XCore::R10;
501 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
503 if (emitFrameMoves) {
504 // Show FP is now valid.
505 unsigned FrameLabelId = MMI->NextLabelID();
506 BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId);
507 MachineLocation SPDst(FramePtr);
508 MachineLocation SPSrc(MachineLocation::VirtualFP);
509 MMI->getFrameMoves().push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
513 if (emitFrameMoves) {
514 // Frame moves for callee saved.
515 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
516 std::vector<std::pair<unsigned, CalleeSavedInfo> >&SpillLabels =
517 XFI->getSpillLabels();
518 for (unsigned I = 0, E = SpillLabels.size(); I != E; ++I) {
519 unsigned SpillLabel = SpillLabels[I].first;
520 CalleeSavedInfo &CSI = SpillLabels[I].second;
521 int Offset = MFI->getObjectOffset(CSI.getFrameIdx());
522 unsigned Reg = CSI.getReg();
523 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
524 MachineLocation CSSrc(Reg);
525 Moves.push_back(MachineMove(SpillLabel, CSDst, CSSrc));
530 void XCoreRegisterInfo::emitEpilogue(MachineFunction &MF,
531 MachineBasicBlock &MBB) const {
532 MachineFrameInfo *MFI = MF.getFrameInfo();
533 MachineBasicBlock::iterator MBBI = prior(MBB.end());
534 DebugLoc dl = MBBI->getDebugLoc();
539 // Restore the stack pointer.
540 unsigned FramePtr = XCore::R10;
541 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
545 // Work out frame sizes.
546 int FrameSize = MFI->getStackSize();
548 assert(FrameSize%4 == 0 && "Misaligned frame size");
552 bool isU6 = isImmU6(FrameSize);
554 if (!isU6 && !isImmU16(FrameSize)) {
555 // FIXME could emit multiple instructions.
557 raw_string_ostream Msg(msg);
558 Msg << "emitEpilogue Frame size too big: " << FrameSize;
559 llvm_report_error(Msg.str());
563 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
567 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
568 FPSpillOffset += FrameSize*4;
569 loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl);
571 bool restoreLR = XFI->getUsesLR();
572 if (restoreLR && MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0) {
573 int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
574 LRSpillOffset += FrameSize*4;
575 loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl);
579 // Fold prologue into return instruction
580 assert(MBBI->getOpcode() == XCore::RETSP_u6
581 || MBBI->getOpcode() == XCore::RETSP_lu6);
582 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
583 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
586 int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
587 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize);
592 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
593 return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
596 unsigned XCoreRegisterInfo::getFrameRegister(MachineFunction &MF) const {
599 return FP ? XCore::R10 : XCore::SP;
602 unsigned XCoreRegisterInfo::getRARegister() const {
606 void XCoreRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
608 // Initial state of the frame pointer is SP.
609 MachineLocation Dst(MachineLocation::VirtualFP);
610 MachineLocation Src(XCore::SP, 0);
611 Moves.push_back(MachineMove(0, Dst, Src));
614 #include "XCoreGenRegisterInfo.inc"