1 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
16 #include "XCoreInstrInfo.h"
17 #include "XCoreMachineFunctionInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Type.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetOptions.h"
36 #define GET_REGINFO_TARGET_DESC
37 #include "XCoreGenRegisterInfo.inc"
41 XCoreRegisterInfo::XCoreRegisterInfo()
42 : XCoreGenRegisterInfo(XCore::LR) {
46 static inline bool isImmUs(unsigned val) {
50 static inline bool isImmU6(unsigned val) {
51 return val < (1 << 6);
54 static inline bool isImmU16(unsigned val) {
55 return val < (1 << 16);
59 static void InsertFPImmInst(MachineBasicBlock::iterator II,
60 const XCoreInstrInfo &TII,
61 unsigned Reg, unsigned FrameReg, int Offset ) {
62 MachineInstr &MI = *II;
63 MachineBasicBlock &MBB = *MI.getParent();
64 DebugLoc dl = MI.getDebugLoc();
66 switch (MI.getOpcode()) {
68 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
73 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
74 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
79 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
84 llvm_unreachable("Unexpected Opcode");
88 static void InsertFPConstInst(MachineBasicBlock::iterator II,
89 const XCoreInstrInfo &TII,
90 unsigned Reg, unsigned FrameReg,
91 int Offset, RegScavenger *RS ) {
92 assert(RS && "requiresRegisterScavenging failed");
93 MachineInstr &MI = *II;
94 MachineBasicBlock &MBB = *MI.getParent();
95 DebugLoc dl = MI.getDebugLoc();
97 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
98 RS->setUsed(ScratchOffset);
99 TII.loadImmediate(MBB, II, ScratchOffset, Offset);
101 switch (MI.getOpcode()) {
103 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
105 .addReg(ScratchOffset, RegState::Kill);
108 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
109 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
111 .addReg(ScratchOffset, RegState::Kill);
114 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
116 .addReg(ScratchOffset, RegState::Kill);
119 llvm_unreachable("Unexpected Opcode");
123 static void InsertSPImmInst(MachineBasicBlock::iterator II,
124 const XCoreInstrInfo &TII,
125 unsigned Reg, int Offset) {
126 MachineInstr &MI = *II;
127 MachineBasicBlock &MBB = *MI.getParent();
128 DebugLoc dl = MI.getDebugLoc();
129 bool isU6 = isImmU6(Offset);
130 switch (MI.getOpcode()) {
133 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
134 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
138 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
139 BuildMI(MBB, II, dl, TII.get(NewOpcode))
140 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
144 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
145 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
149 llvm_unreachable("Unexpected Opcode");
153 static void InsertSPConstInst(MachineBasicBlock::iterator II,
154 const XCoreInstrInfo &TII,
155 unsigned Reg, int Offset, RegScavenger *RS ) {
156 assert(RS && "requiresRegisterScavenging failed");
157 MachineInstr &MI = *II;
158 MachineBasicBlock &MBB = *MI.getParent();
159 DebugLoc dl = MI.getDebugLoc();
160 unsigned OpCode = MI.getOpcode();
162 unsigned ScratchBase;
163 if (OpCode==XCore::STWFI) {
164 ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
165 RS->setUsed(ScratchBase);
168 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0);
169 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
170 RS->setUsed(ScratchOffset);
171 TII.loadImmediate(MBB, II, ScratchOffset, Offset);
175 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
176 .addReg(ScratchBase, RegState::Kill)
177 .addReg(ScratchOffset, RegState::Kill);
180 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
181 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
182 .addReg(ScratchBase, RegState::Kill)
183 .addReg(ScratchOffset, RegState::Kill);
186 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
187 .addReg(ScratchBase, RegState::Kill)
188 .addReg(ScratchOffset, RegState::Kill);
191 llvm_unreachable("Unexpected Opcode");
195 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
196 return MF.getMMI().hasDebugInfo() ||
197 MF.getFunction()->needsUnwindTableEntry();
200 const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
202 // The callee saved registers LR & FP are explicitly handled during
203 // emitPrologue & emitEpilogue and releated functions.
204 static const uint16_t CalleeSavedRegs[] = {
205 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
206 XCore::R8, XCore::R9, XCore::R10,
209 static const uint16_t CalleeSavedRegsFP[] = {
210 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
211 XCore::R8, XCore::R9,
214 const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering();
216 return CalleeSavedRegsFP;
217 return CalleeSavedRegs;
220 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
221 BitVector Reserved(getNumRegs());
222 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
224 Reserved.set(XCore::CP);
225 Reserved.set(XCore::DP);
226 Reserved.set(XCore::SP);
227 Reserved.set(XCore::LR);
228 if (TFI->hasFP(MF)) {
229 Reserved.set(XCore::R10);
235 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
240 XCoreRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
245 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
250 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
251 int SPAdj, unsigned FIOperandNum,
252 RegScavenger *RS) const {
253 assert(SPAdj == 0 && "Unexpected");
254 MachineInstr &MI = *II;
255 MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
256 int FrameIndex = FrameOp.getIndex();
258 MachineFunction &MF = *MI.getParent()->getParent();
259 const XCoreInstrInfo &TII =
260 *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
262 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
263 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
264 int StackSize = MF.getFrameInfo()->getStackSize();
267 DEBUG(errs() << "\nFunction : "
268 << MF.getName() << "\n");
269 DEBUG(errs() << "<--------->\n");
270 DEBUG(MI.print(errs()));
271 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
272 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
273 DEBUG(errs() << "StackSize : " << StackSize << "\n");
278 unsigned FrameReg = getFrameRegister(MF);
280 // Special handling of DBG_VALUE instructions.
281 if (MI.isDebugValue()) {
282 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
283 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
287 // fold constant into offset.
288 Offset += MI.getOperand(FIOperandNum + 1).getImm();
289 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
291 assert(Offset%4 == 0 && "Misaligned stack offset");
292 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
295 unsigned Reg = MI.getOperand(0).getReg();
296 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
298 if (TFI->hasFP(MF)) {
300 InsertFPImmInst(II, TII, Reg, FrameReg, Offset);
302 InsertFPConstInst(II, TII, Reg, FrameReg, Offset, RS);
304 if (isImmU16(Offset))
305 InsertSPImmInst(II, TII, Reg, Offset);
307 InsertSPConstInst(II, TII, Reg, Offset, RS);
309 // Erase old instruction.
310 MachineBasicBlock &MBB = *MI.getParent();
315 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
316 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
318 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;