1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Type.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
39 : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
44 static inline bool isImmUs(unsigned val) {
48 static inline bool isImmU6(unsigned val) {
49 return val < (1 << 6);
52 static inline bool isImmU16(unsigned val) {
53 return val < (1 << 16);
56 static const unsigned XCore_ArgRegs[] = {
57 XCore::R0, XCore::R1, XCore::R2, XCore::R3
60 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
65 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
67 return array_lengthof(XCore_ArgRegs);
70 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
71 return MF.getMMI().hasDebugInfo() || !MF.getFunction()->doesNotThrow() ||
72 UnwindTablesMandatory;
75 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
77 static const unsigned CalleeSavedRegs[] = {
78 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
79 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
82 return CalleeSavedRegs;
85 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
86 BitVector Reserved(getNumRegs());
87 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
89 Reserved.set(XCore::CP);
90 Reserved.set(XCore::DP);
91 Reserved.set(XCore::SP);
92 Reserved.set(XCore::LR);
94 Reserved.set(XCore::R10);
100 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
101 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
103 // TODO can we estimate stack size?
104 return TFI->hasFP(MF);
107 // This function eliminates ADJCALLSTACKDOWN,
108 // ADJCALLSTACKUP pseudo instructions
109 void XCoreRegisterInfo::
110 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator I) const {
112 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
114 if (!TFI->hasReservedCallFrame(MF)) {
115 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
116 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
117 MachineInstr *Old = I;
118 uint64_t Amount = Old->getOperand(0).getImm();
120 // We need to keep the stack aligned properly. To do this, we round the
121 // amount of space needed for the outgoing arguments up to the next
122 // alignment boundary.
123 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
124 Amount = (Amount+Align-1)/Align*Align;
126 assert(Amount%4 == 0);
129 bool isU6 = isImmU6(Amount);
131 if (!isU6 && !isImmU16(Amount)) {
132 // FIX could emit multiple instructions in this case.
134 errs() << "eliminateCallFramePseudoInstr size too big: "
141 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
142 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
143 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
146 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
147 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
148 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
152 // Replace the pseudo instruction with a new instruction...
161 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
162 int SPAdj, RegScavenger *RS) const {
163 assert(SPAdj == 0 && "Unexpected");
164 MachineInstr &MI = *II;
165 DebugLoc dl = MI.getDebugLoc();
168 while (!MI.getOperand(i).isFI()) {
170 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
173 MachineOperand &FrameOp = MI.getOperand(i);
174 int FrameIndex = FrameOp.getIndex();
176 MachineFunction &MF = *MI.getParent()->getParent();
177 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
178 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
179 int StackSize = MF.getFrameInfo()->getStackSize();
182 DEBUG(errs() << "\nFunction : "
183 << MF.getFunction()->getName() << "\n");
184 DEBUG(errs() << "<--------->\n");
185 DEBUG(MI.print(errs()));
186 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
187 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
188 DEBUG(errs() << "StackSize : " << StackSize << "\n");
193 // fold constant into offset.
194 Offset += MI.getOperand(i + 1).getImm();
195 MI.getOperand(i + 1).ChangeToImmediate(0);
197 assert(Offset%4 == 0 && "Misaligned stack offset");
199 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
203 bool FP = TFI->hasFP(MF);
205 unsigned Reg = MI.getOperand(0).getReg();
206 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
208 assert(XCore::GRRegsRegisterClass->contains(Reg) &&
209 "Unexpected register operand");
211 MachineBasicBlock &MBB = *MI.getParent();
214 bool isUs = isImmUs(Offset);
215 unsigned FramePtr = XCore::R10;
219 report_fatal_error("eliminateFrameIndex Frame size too big: " +
221 unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
223 loadConstant(MBB, II, ScratchReg, Offset, dl);
224 switch (MI.getOpcode()) {
226 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
228 .addReg(ScratchReg, RegState::Kill);
231 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
232 .addReg(Reg, getKillRegState(isKill))
234 .addReg(ScratchReg, RegState::Kill);
237 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
239 .addReg(ScratchReg, RegState::Kill);
242 llvm_unreachable("Unexpected Opcode");
245 switch (MI.getOpcode()) {
247 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
252 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
253 .addReg(Reg, getKillRegState(isKill))
258 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
263 llvm_unreachable("Unexpected Opcode");
267 bool isU6 = isImmU6(Offset);
268 if (!isU6 && !isImmU16(Offset))
269 report_fatal_error("eliminateFrameIndex Frame size too big: " +
272 switch (MI.getOpcode()) {
275 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
276 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
280 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
281 BuildMI(MBB, II, dl, TII.get(NewOpcode))
282 .addReg(Reg, getKillRegState(isKill))
286 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
287 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
291 llvm_unreachable("Unexpected Opcode");
294 // Erase old instruction.
299 XCoreRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
300 RegScavenger *RS) const {
301 MachineFrameInfo *MFI = MF.getFrameInfo();
302 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
303 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
304 const TargetRegisterClass *RC = XCore::GRRegsRegisterClass;
305 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
307 MF.getRegInfo().setPhysRegUnused(XCore::LR);
309 bool isVarArg = MF.getFunction()->isVarArg();
312 // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
313 FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true);
315 FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(),
318 XFI->setUsesLR(FrameIdx);
319 XFI->setLRSpillSlot(FrameIdx);
321 if (requiresRegisterScavenging(MF)) {
322 // Reserve a slot close to SP or frame pointer.
323 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
327 if (TFI->hasFP(MF)) {
328 // A callee save register is used to hold the FP.
329 // This needs saving / restoring in the epilogue / prologue.
330 XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(),
336 void XCoreRegisterInfo::
337 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
341 void XCoreRegisterInfo::
342 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
343 unsigned DstReg, int64_t Value, DebugLoc dl) const {
344 // TODO use mkmsk if possible.
345 if (!isImmU16(Value)) {
346 // TODO use constant pool.
347 report_fatal_error("loadConstant value too big " + Twine(Value));
349 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
350 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
353 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
354 return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
357 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
358 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
360 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
363 unsigned XCoreRegisterInfo::getRARegister() const {
367 void XCoreRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
369 // Initial state of the frame pointer is SP.
370 MachineLocation Dst(MachineLocation::VirtualFP);
371 MachineLocation Src(XCore::SP, 0);
372 Moves.push_back(MachineMove(0, Dst, Src));
375 #include "XCoreGenRegisterInfo.inc"