1 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
16 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
38 #define GET_REGINFO_TARGET_DESC
39 #include "XCoreGenRegisterInfo.inc"
43 XCoreRegisterInfo::XCoreRegisterInfo()
44 : XCoreGenRegisterInfo(XCore::LR) {
48 static inline bool isImmUs(unsigned val) {
52 static inline bool isImmU6(unsigned val) {
53 return val < (1 << 6);
56 static inline bool isImmU16(unsigned val) {
57 return val < (1 << 16);
60 static void loadConstant(MachineBasicBlock::iterator II,
61 const TargetInstrInfo &TII,
62 unsigned DstReg, int64_t Value) {
63 MachineInstr &MI = *II;
64 MachineBasicBlock &MBB = *MI.getParent();
65 DebugLoc dl = MI.getDebugLoc();
67 if (isMask_32(Value)) {
68 int N = Log2_32(Value) + 1;
69 BuildMI(MBB, II, dl, TII.get(XCore::MKMSK_rus), DstReg).addImm(N);
70 } else if (isImmU16(Value)) {
71 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
72 BuildMI(MBB, II, dl, TII.get(Opcode), DstReg).addImm(Value);
74 MachineConstantPool *ConstantPool = MBB.getParent()->getConstantPool();
75 const Constant *C = ConstantInt::get(
76 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Value);
77 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
78 BuildMI(MBB, II, dl, TII.get(XCore::LDWCP_lru6), DstReg)
79 .addConstantPoolIndex(Idx);
83 static void InsertFPImmInst(MachineBasicBlock::iterator II,
84 const TargetInstrInfo &TII,
85 unsigned Reg, unsigned FrameReg, int Offset ) {
86 MachineInstr &MI = *II;
87 MachineBasicBlock &MBB = *MI.getParent();
88 DebugLoc dl = MI.getDebugLoc();
90 switch (MI.getOpcode()) {
92 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
97 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
98 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
103 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
108 llvm_unreachable("Unexpected Opcode");
112 static void InsertFPConstInst(MachineBasicBlock::iterator II,
113 const TargetInstrInfo &TII,
114 unsigned Reg, unsigned FrameReg,
115 int Offset, RegScavenger *RS ) {
116 assert(RS && "requiresRegisterScavenging failed");
117 MachineInstr &MI = *II;
118 MachineBasicBlock &MBB = *MI.getParent();
119 DebugLoc dl = MI.getDebugLoc();
121 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
122 RS->setUsed(ScratchOffset);
123 loadConstant(II, TII, ScratchOffset, Offset);
125 switch (MI.getOpcode()) {
127 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
129 .addReg(ScratchOffset, RegState::Kill);
132 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
133 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
135 .addReg(ScratchOffset, RegState::Kill);
138 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
140 .addReg(ScratchOffset, RegState::Kill);
143 llvm_unreachable("Unexpected Opcode");
147 static void InsertSPImmInst(MachineBasicBlock::iterator II,
148 const TargetInstrInfo &TII,
149 unsigned Reg, int Offset) {
150 MachineInstr &MI = *II;
151 MachineBasicBlock &MBB = *MI.getParent();
152 DebugLoc dl = MI.getDebugLoc();
153 bool isU6 = isImmU6(Offset);
154 switch (MI.getOpcode()) {
157 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
158 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
162 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
163 BuildMI(MBB, II, dl, TII.get(NewOpcode))
164 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
168 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
169 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
173 llvm_unreachable("Unexpected Opcode");
177 static void InsertSPConstInst(MachineBasicBlock::iterator II,
178 const TargetInstrInfo &TII,
179 unsigned Reg, int Offset, RegScavenger *RS ) {
180 assert(RS && "requiresRegisterScavenging failed");
181 MachineInstr &MI = *II;
182 MachineBasicBlock &MBB = *MI.getParent();
183 DebugLoc dl = MI.getDebugLoc();
184 unsigned OpCode = MI.getOpcode();
186 unsigned ScratchBase;
187 if (OpCode==XCore::STWFI) {
188 ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
189 RS->setUsed(ScratchBase);
192 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0);
193 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
194 RS->setUsed(ScratchOffset);
195 loadConstant(II, TII, ScratchOffset, Offset);
199 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
200 .addReg(ScratchBase, RegState::Kill)
201 .addReg(ScratchOffset, RegState::Kill);
204 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
205 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
206 .addReg(ScratchBase, RegState::Kill)
207 .addReg(ScratchOffset, RegState::Kill);
210 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
211 .addReg(ScratchBase, RegState::Kill)
212 .addReg(ScratchOffset, RegState::Kill);
215 llvm_unreachable("Unexpected Opcode");
219 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
220 return MF.getMMI().hasDebugInfo() ||
221 MF.getFunction()->needsUnwindTableEntry();
224 const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
226 static const uint16_t CalleeSavedRegs[] = {
227 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
228 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
231 return CalleeSavedRegs;
234 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
235 BitVector Reserved(getNumRegs());
236 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
238 Reserved.set(XCore::CP);
239 Reserved.set(XCore::DP);
240 Reserved.set(XCore::SP);
241 Reserved.set(XCore::LR);
242 if (TFI->hasFP(MF)) {
243 Reserved.set(XCore::R10);
249 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
254 XCoreRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
259 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
264 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
265 int SPAdj, unsigned FIOperandNum,
266 RegScavenger *RS) const {
267 assert(SPAdj == 0 && "Unexpected");
268 MachineInstr &MI = *II;
269 MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
270 int FrameIndex = FrameOp.getIndex();
272 MachineFunction &MF = *MI.getParent()->getParent();
273 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
274 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
275 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
276 int StackSize = MF.getFrameInfo()->getStackSize();
279 DEBUG(errs() << "\nFunction : "
280 << MF.getName() << "\n");
281 DEBUG(errs() << "<--------->\n");
282 DEBUG(MI.print(errs()));
283 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
284 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
285 DEBUG(errs() << "StackSize : " << StackSize << "\n");
290 unsigned FrameReg = getFrameRegister(MF);
292 // Special handling of DBG_VALUE instructions.
293 if (MI.isDebugValue()) {
294 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
295 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
299 // fold constant into offset.
300 Offset += MI.getOperand(FIOperandNum + 1).getImm();
301 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
303 assert(Offset%4 == 0 && "Misaligned stack offset");
304 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
307 unsigned Reg = MI.getOperand(0).getReg();
308 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
310 if (TFI->hasFP(MF)) {
312 InsertFPImmInst(II, TII, Reg, FrameReg, Offset);
314 InsertFPConstInst(II, TII, Reg, FrameReg, Offset, RS);
316 if (isImmU16(Offset))
317 InsertSPImmInst(II, TII, Reg, Offset);
319 InsertSPConstInst(II, TII, Reg, Offset, RS);
321 // Erase old instruction.
322 MachineBasicBlock &MBB = *MI.getParent();
327 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
328 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
330 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;