1 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/Type.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/Target/TargetFrameLowering.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/STLExtras.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
35 #define GET_REGINFO_TARGET_DESC
36 #include "XCoreGenRegisterInfo.inc"
40 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
45 static inline bool isImmUs(unsigned val) {
49 static inline bool isImmU6(unsigned val) {
50 return val < (1 << 6);
53 static inline bool isImmU16(unsigned val) {
54 return val < (1 << 16);
57 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
58 return MF.getMMI().hasDebugInfo() ||
59 MF.getFunction()->needsUnwindTableEntry();
62 const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
64 static const uint16_t CalleeSavedRegs[] = {
65 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
66 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
69 return CalleeSavedRegs;
72 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
73 BitVector Reserved(getNumRegs());
74 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
76 Reserved.set(XCore::CP);
77 Reserved.set(XCore::DP);
78 Reserved.set(XCore::SP);
79 Reserved.set(XCore::LR);
81 Reserved.set(XCore::R10);
87 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
88 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
90 // TODO can we estimate stack size?
91 return TFI->hasFP(MF);
95 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
99 // This function eliminates ADJCALLSTACKDOWN,
100 // ADJCALLSTACKUP pseudo instructions
101 void XCoreRegisterInfo::
102 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator I) const {
104 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
106 if (!TFI->hasReservedCallFrame(MF)) {
107 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
108 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
109 MachineInstr *Old = I;
110 uint64_t Amount = Old->getOperand(0).getImm();
112 // We need to keep the stack aligned properly. To do this, we round the
113 // amount of space needed for the outgoing arguments up to the next
114 // alignment boundary.
115 unsigned Align = TFI->getStackAlignment();
116 Amount = (Amount+Align-1)/Align*Align;
118 assert(Amount%4 == 0);
121 bool isU6 = isImmU6(Amount);
122 if (!isU6 && !isImmU16(Amount)) {
123 // FIX could emit multiple instructions in this case.
125 errs() << "eliminateCallFramePseudoInstr size too big: "
132 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
133 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
134 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
137 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
138 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
139 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
143 // Replace the pseudo instruction with a new instruction...
152 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
153 int SPAdj, RegScavenger *RS) const {
154 assert(SPAdj == 0 && "Unexpected");
155 MachineInstr &MI = *II;
156 DebugLoc dl = MI.getDebugLoc();
159 while (!MI.getOperand(i).isFI()) {
161 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
164 MachineOperand &FrameOp = MI.getOperand(i);
165 int FrameIndex = FrameOp.getIndex();
167 MachineFunction &MF = *MI.getParent()->getParent();
168 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
169 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
170 int StackSize = MF.getFrameInfo()->getStackSize();
173 DEBUG(errs() << "\nFunction : "
174 << MF.getFunction()->getName() << "\n");
175 DEBUG(errs() << "<--------->\n");
176 DEBUG(MI.print(errs()));
177 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
178 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
179 DEBUG(errs() << "StackSize : " << StackSize << "\n");
184 unsigned FrameReg = getFrameRegister(MF);
186 // Special handling of DBG_VALUE instructions.
187 if (MI.isDebugValue()) {
188 MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/);
189 MI.getOperand(i+1).ChangeToImmediate(Offset);
193 // fold constant into offset.
194 Offset += MI.getOperand(i + 1).getImm();
195 MI.getOperand(i + 1).ChangeToImmediate(0);
197 assert(Offset%4 == 0 && "Misaligned stack offset");
199 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
203 bool FP = TFI->hasFP(MF);
205 unsigned Reg = MI.getOperand(0).getReg();
206 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
208 assert(XCore::GRRegsRegisterClass->contains(Reg) &&
209 "Unexpected register operand");
211 MachineBasicBlock &MBB = *MI.getParent();
214 bool isUs = isImmUs(Offset);
218 report_fatal_error("eliminateFrameIndex Frame size too big: " +
220 unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
222 loadConstant(MBB, II, ScratchReg, Offset, dl);
223 switch (MI.getOpcode()) {
225 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
227 .addReg(ScratchReg, RegState::Kill);
230 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
231 .addReg(Reg, getKillRegState(isKill))
233 .addReg(ScratchReg, RegState::Kill);
236 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
238 .addReg(ScratchReg, RegState::Kill);
241 llvm_unreachable("Unexpected Opcode");
244 switch (MI.getOpcode()) {
246 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
251 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
252 .addReg(Reg, getKillRegState(isKill))
257 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
262 llvm_unreachable("Unexpected Opcode");
266 bool isU6 = isImmU6(Offset);
267 if (!isU6 && !isImmU16(Offset))
268 report_fatal_error("eliminateFrameIndex Frame size too big: " +
271 switch (MI.getOpcode()) {
274 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
275 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
279 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
280 BuildMI(MBB, II, dl, TII.get(NewOpcode))
281 .addReg(Reg, getKillRegState(isKill))
285 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
286 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
290 llvm_unreachable("Unexpected Opcode");
293 // Erase old instruction.
297 void XCoreRegisterInfo::
298 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
299 unsigned DstReg, int64_t Value, DebugLoc dl) const {
300 // TODO use mkmsk if possible.
301 if (!isImmU16(Value)) {
302 // TODO use constant pool.
303 report_fatal_error("loadConstant value too big " + Twine(Value));
305 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
306 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
309 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
310 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
312 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;