1 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
16 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
38 #define GET_REGINFO_TARGET_DESC
39 #include "XCoreGenRegisterInfo.inc"
43 XCoreRegisterInfo::XCoreRegisterInfo()
44 : XCoreGenRegisterInfo(XCore::LR) {
48 static inline bool isImmUs(unsigned val) {
52 static inline bool isImmU6(unsigned val) {
53 return val < (1 << 6);
56 static inline bool isImmU16(unsigned val) {
57 return val < (1 << 16);
60 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
61 return MF.getMMI().hasDebugInfo() ||
62 MF.getFunction()->needsUnwindTableEntry();
65 const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
67 static const uint16_t CalleeSavedRegs[] = {
68 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
69 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
72 return CalleeSavedRegs;
75 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
76 BitVector Reserved(getNumRegs());
77 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
79 Reserved.set(XCore::CP);
80 Reserved.set(XCore::DP);
81 Reserved.set(XCore::SP);
82 Reserved.set(XCore::LR);
84 Reserved.set(XCore::R10);
90 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
91 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
93 // TODO can we estimate stack size?
94 return TFI->hasFP(MF);
98 XCoreRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
99 return requiresRegisterScavenging(MF);
103 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
108 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
109 int SPAdj, unsigned FIOperandNum,
110 RegScavenger *RS) const {
111 assert(SPAdj == 0 && "Unexpected");
112 MachineInstr &MI = *II;
113 DebugLoc dl = MI.getDebugLoc();
114 MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
115 int FrameIndex = FrameOp.getIndex();
117 MachineFunction &MF = *MI.getParent()->getParent();
118 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
119 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
120 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
121 int StackSize = MF.getFrameInfo()->getStackSize();
124 DEBUG(errs() << "\nFunction : "
125 << MF.getName() << "\n");
126 DEBUG(errs() << "<--------->\n");
127 DEBUG(MI.print(errs()));
128 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
129 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
130 DEBUG(errs() << "StackSize : " << StackSize << "\n");
135 unsigned FrameReg = getFrameRegister(MF);
137 // Special handling of DBG_VALUE instructions.
138 if (MI.isDebugValue()) {
139 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
140 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
144 // fold constant into offset.
145 Offset += MI.getOperand(FIOperandNum + 1).getImm();
146 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
148 assert(Offset%4 == 0 && "Misaligned stack offset");
150 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
154 bool FP = TFI->hasFP(MF);
156 unsigned Reg = MI.getOperand(0).getReg();
157 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
159 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
161 MachineBasicBlock &MBB = *MI.getParent();
164 bool isUs = isImmUs(Offset);
168 report_fatal_error("eliminateFrameIndex Frame size too big: " +
170 unsigned ScratchReg = RS->scavengeRegister(&XCore::GRRegsRegClass, II,
172 loadConstant(MBB, II, ScratchReg, Offset, dl);
173 switch (MI.getOpcode()) {
175 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
177 .addReg(ScratchReg, RegState::Kill);
180 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
181 .addReg(Reg, getKillRegState(isKill))
183 .addReg(ScratchReg, RegState::Kill);
186 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
188 .addReg(ScratchReg, RegState::Kill);
191 llvm_unreachable("Unexpected Opcode");
194 switch (MI.getOpcode()) {
196 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
201 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
202 .addReg(Reg, getKillRegState(isKill))
207 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
212 llvm_unreachable("Unexpected Opcode");
216 bool isU6 = isImmU6(Offset);
217 if (!isU6 && !isImmU16(Offset))
218 report_fatal_error("eliminateFrameIndex Frame size too big: " +
221 switch (MI.getOpcode()) {
224 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
225 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
229 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
230 BuildMI(MBB, II, dl, TII.get(NewOpcode))
231 .addReg(Reg, getKillRegState(isKill))
235 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
236 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
240 llvm_unreachable("Unexpected Opcode");
243 // Erase old instruction.
247 void XCoreRegisterInfo::
248 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
249 unsigned DstReg, int64_t Value, DebugLoc dl) const {
250 const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo();
251 if (isMask_32(Value)) {
252 int N = Log2_32(Value) + 1;
253 BuildMI(MBB, I, dl, TII.get(XCore::MKMSK_rus), DstReg).addImm(N);
254 } else if (isImmU16(Value)) {
255 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
256 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
259 MachineConstantPool *ConstantPool = MBB.getParent()->getConstantPool();
260 const Constant *C = ConstantInt::get(
261 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Value);
262 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
263 BuildMI(MBB, I, dl, TII.get(XCore::LDWCP_lru6), DstReg)
264 .addConstantPoolIndex(Idx);
268 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
269 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
271 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;