1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Type.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
39 : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
44 static inline bool isImmUs(unsigned val) {
48 static inline bool isImmU6(unsigned val) {
49 return val < (1 << 6);
52 static inline bool isImmU16(unsigned val) {
53 return val < (1 << 16);
56 static const unsigned XCore_ArgRegs[] = {
57 XCore::R0, XCore::R1, XCore::R2, XCore::R3
60 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
65 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
67 return array_lengthof(XCore_ArgRegs);
70 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
71 return MF.getMMI().hasDebugInfo() || !MF.getFunction()->doesNotThrow() ||
72 UnwindTablesMandatory;
75 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
77 static const unsigned CalleeSavedRegs[] = {
78 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
79 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
82 return CalleeSavedRegs;
85 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
86 BitVector Reserved(getNumRegs());
87 Reserved.set(XCore::CP);
88 Reserved.set(XCore::DP);
89 Reserved.set(XCore::SP);
90 Reserved.set(XCore::LR);
92 Reserved.set(XCore::R10);
98 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
99 // TODO can we estimate stack size?
103 bool XCoreRegisterInfo::hasFP(const MachineFunction &MF) const {
104 return DisableFramePointerElim(MF) || MF.getFrameInfo()->hasVarSizedObjects();
107 // This function eliminates ADJCALLSTACKDOWN,
108 // ADJCALLSTACKUP pseudo instructions
109 void XCoreRegisterInfo::
110 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator I) const {
112 if (!hasReservedCallFrame(MF)) {
113 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
114 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
115 MachineInstr *Old = I;
116 uint64_t Amount = Old->getOperand(0).getImm();
118 // We need to keep the stack aligned properly. To do this, we round the
119 // amount of space needed for the outgoing arguments up to the next
120 // alignment boundary.
121 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
122 Amount = (Amount+Align-1)/Align*Align;
124 assert(Amount%4 == 0);
127 bool isU6 = isImmU6(Amount);
129 if (!isU6 && !isImmU16(Amount)) {
130 // FIX could emit multiple instructions in this case.
132 errs() << "eliminateCallFramePseudoInstr size too big: "
139 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
140 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
141 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
144 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
145 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
146 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
150 // Replace the pseudo instruction with a new instruction...
159 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
160 int SPAdj, RegScavenger *RS) const {
161 assert(SPAdj == 0 && "Unexpected");
162 MachineInstr &MI = *II;
163 DebugLoc dl = MI.getDebugLoc();
166 while (!MI.getOperand(i).isFI()) {
168 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
171 MachineOperand &FrameOp = MI.getOperand(i);
172 int FrameIndex = FrameOp.getIndex();
174 MachineFunction &MF = *MI.getParent()->getParent();
175 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
176 int StackSize = MF.getFrameInfo()->getStackSize();
179 DEBUG(errs() << "\nFunction : "
180 << MF.getFunction()->getName() << "\n");
181 DEBUG(errs() << "<--------->\n");
182 DEBUG(MI.print(errs()));
183 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
184 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
185 DEBUG(errs() << "StackSize : " << StackSize << "\n");
190 // fold constant into offset.
191 Offset += MI.getOperand(i + 1).getImm();
192 MI.getOperand(i + 1).ChangeToImmediate(0);
194 assert(Offset%4 == 0 && "Misaligned stack offset");
196 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
202 unsigned Reg = MI.getOperand(0).getReg();
203 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
205 assert(XCore::GRRegsRegisterClass->contains(Reg) &&
206 "Unexpected register operand");
208 MachineBasicBlock &MBB = *MI.getParent();
211 bool isUs = isImmUs(Offset);
212 unsigned FramePtr = XCore::R10;
216 report_fatal_error("eliminateFrameIndex Frame size too big: " +
218 unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
220 loadConstant(MBB, II, ScratchReg, Offset, dl);
221 switch (MI.getOpcode()) {
223 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
225 .addReg(ScratchReg, RegState::Kill);
228 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
229 .addReg(Reg, getKillRegState(isKill))
231 .addReg(ScratchReg, RegState::Kill);
234 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
236 .addReg(ScratchReg, RegState::Kill);
239 llvm_unreachable("Unexpected Opcode");
242 switch (MI.getOpcode()) {
244 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
249 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
250 .addReg(Reg, getKillRegState(isKill))
255 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
260 llvm_unreachable("Unexpected Opcode");
264 bool isU6 = isImmU6(Offset);
265 if (!isU6 && !isImmU16(Offset))
266 report_fatal_error("eliminateFrameIndex Frame size too big: " +
269 switch (MI.getOpcode()) {
272 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
273 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
277 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
278 BuildMI(MBB, II, dl, TII.get(NewOpcode))
279 .addReg(Reg, getKillRegState(isKill))
283 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
284 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
288 llvm_unreachable("Unexpected Opcode");
291 // Erase old instruction.
296 XCoreRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
297 RegScavenger *RS) const {
298 MachineFrameInfo *MFI = MF.getFrameInfo();
299 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
300 const TargetRegisterClass *RC = XCore::GRRegsRegisterClass;
301 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
303 MF.getRegInfo().setPhysRegUnused(XCore::LR);
305 bool isVarArg = MF.getFunction()->isVarArg();
308 // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
309 FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true);
311 FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(),
314 XFI->setUsesLR(FrameIdx);
315 XFI->setLRSpillSlot(FrameIdx);
317 if (requiresRegisterScavenging(MF)) {
318 // Reserve a slot close to SP or frame pointer.
319 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
324 // A callee save register is used to hold the FP.
325 // This needs saving / restoring in the epilogue / prologue.
326 XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(),
332 void XCoreRegisterInfo::
333 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
337 void XCoreRegisterInfo::
338 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
339 unsigned DstReg, int64_t Value, DebugLoc dl) const {
340 // TODO use mkmsk if possible.
341 if (!isImmU16(Value)) {
342 // TODO use constant pool.
343 report_fatal_error("loadConstant value too big " + Twine(Value));
345 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
346 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
349 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
350 return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
353 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
356 return FP ? XCore::R10 : XCore::SP;
359 unsigned XCoreRegisterInfo::getRARegister() const {
363 void XCoreRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
365 // Initial state of the frame pointer is SP.
366 MachineLocation Dst(MachineLocation::VirtualFP);
367 MachineLocation Src(XCore::SP, 0);
368 Moves.push_back(MachineMove(0, Dst, Src));
371 #include "XCoreGenRegisterInfo.inc"