1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetFrameLowering.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Type.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
36 #define GET_REGINFO_MC_DESC
37 #define GET_REGINFO_TARGET_DESC
38 #include "XCoreGenRegisterInfo.inc"
42 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
43 : XCoreGenRegisterInfo(), TII(tii) {
47 static inline bool isImmUs(unsigned val) {
51 static inline bool isImmU6(unsigned val) {
52 return val < (1 << 6);
55 static inline bool isImmU16(unsigned val) {
56 return val < (1 << 16);
59 static const unsigned XCore_ArgRegs[] = {
60 XCore::R0, XCore::R1, XCore::R2, XCore::R3
63 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
68 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
70 return array_lengthof(XCore_ArgRegs);
73 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
74 return MF.getMMI().hasDebugInfo() ||
75 MF.getFunction()->needsUnwindTableEntry();
78 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
80 static const unsigned CalleeSavedRegs[] = {
81 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
82 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
85 return CalleeSavedRegs;
88 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
89 BitVector Reserved(getNumRegs());
90 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
92 Reserved.set(XCore::CP);
93 Reserved.set(XCore::DP);
94 Reserved.set(XCore::SP);
95 Reserved.set(XCore::LR);
97 Reserved.set(XCore::R10);
103 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
104 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
106 // TODO can we estimate stack size?
107 return TFI->hasFP(MF);
111 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
115 // This function eliminates ADJCALLSTACKDOWN,
116 // ADJCALLSTACKUP pseudo instructions
117 void XCoreRegisterInfo::
118 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
119 MachineBasicBlock::iterator I) const {
120 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
122 if (!TFI->hasReservedCallFrame(MF)) {
123 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
124 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
125 MachineInstr *Old = I;
126 uint64_t Amount = Old->getOperand(0).getImm();
128 // We need to keep the stack aligned properly. To do this, we round the
129 // amount of space needed for the outgoing arguments up to the next
130 // alignment boundary.
131 unsigned Align = TFI->getStackAlignment();
132 Amount = (Amount+Align-1)/Align*Align;
134 assert(Amount%4 == 0);
137 bool isU6 = isImmU6(Amount);
138 if (!isU6 && !isImmU16(Amount)) {
139 // FIX could emit multiple instructions in this case.
141 errs() << "eliminateCallFramePseudoInstr size too big: "
148 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
149 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
150 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
153 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
154 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
155 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
159 // Replace the pseudo instruction with a new instruction...
168 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
169 int SPAdj, RegScavenger *RS) const {
170 assert(SPAdj == 0 && "Unexpected");
171 MachineInstr &MI = *II;
172 DebugLoc dl = MI.getDebugLoc();
175 while (!MI.getOperand(i).isFI()) {
177 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
180 MachineOperand &FrameOp = MI.getOperand(i);
181 int FrameIndex = FrameOp.getIndex();
183 MachineFunction &MF = *MI.getParent()->getParent();
184 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
185 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
186 int StackSize = MF.getFrameInfo()->getStackSize();
189 DEBUG(errs() << "\nFunction : "
190 << MF.getFunction()->getName() << "\n");
191 DEBUG(errs() << "<--------->\n");
192 DEBUG(MI.print(errs()));
193 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
194 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
195 DEBUG(errs() << "StackSize : " << StackSize << "\n");
200 // fold constant into offset.
201 Offset += MI.getOperand(i + 1).getImm();
202 MI.getOperand(i + 1).ChangeToImmediate(0);
204 assert(Offset%4 == 0 && "Misaligned stack offset");
206 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
210 bool FP = TFI->hasFP(MF);
212 unsigned Reg = MI.getOperand(0).getReg();
213 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
215 assert(XCore::GRRegsRegisterClass->contains(Reg) &&
216 "Unexpected register operand");
218 MachineBasicBlock &MBB = *MI.getParent();
221 bool isUs = isImmUs(Offset);
222 unsigned FramePtr = XCore::R10;
226 report_fatal_error("eliminateFrameIndex Frame size too big: " +
228 unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
230 loadConstant(MBB, II, ScratchReg, Offset, dl);
231 switch (MI.getOpcode()) {
233 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
235 .addReg(ScratchReg, RegState::Kill);
238 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
239 .addReg(Reg, getKillRegState(isKill))
241 .addReg(ScratchReg, RegState::Kill);
244 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
246 .addReg(ScratchReg, RegState::Kill);
249 llvm_unreachable("Unexpected Opcode");
252 switch (MI.getOpcode()) {
254 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
259 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
260 .addReg(Reg, getKillRegState(isKill))
265 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
270 llvm_unreachable("Unexpected Opcode");
274 bool isU6 = isImmU6(Offset);
275 if (!isU6 && !isImmU16(Offset))
276 report_fatal_error("eliminateFrameIndex Frame size too big: " +
279 switch (MI.getOpcode()) {
282 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
283 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
287 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
288 BuildMI(MBB, II, dl, TII.get(NewOpcode))
289 .addReg(Reg, getKillRegState(isKill))
293 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
294 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
298 llvm_unreachable("Unexpected Opcode");
301 // Erase old instruction.
305 void XCoreRegisterInfo::
306 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
307 unsigned DstReg, int64_t Value, DebugLoc dl) const {
308 // TODO use mkmsk if possible.
309 if (!isImmU16(Value)) {
310 // TODO use constant pool.
311 report_fatal_error("loadConstant value too big " + Twine(Value));
313 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
314 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
317 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
318 return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
321 int XCoreRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
322 return XCoreGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
325 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
326 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
328 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
331 unsigned XCoreRegisterInfo::getRARegister() const {