1 //===- InstCombineSimplifyDemanded.cpp ------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains logic for simplifying instructions based on information
11 // about how they are used.
13 //===----------------------------------------------------------------------===//
16 #include "InstCombine.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/IntrinsicInst.h"
23 /// ShrinkDemandedConstant - Check to see if the specified operand of the
24 /// specified instruction is a constant integer. If so, check to see if there
25 /// are any bits set in the constant that are not demanded. If so, shrink the
26 /// constant and return true.
27 static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo,
29 assert(I && "No instruction?");
30 assert(OpNo < I->getNumOperands() && "Operand index too large");
32 // If the operand is not a constant integer, nothing to do.
33 ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo));
34 if (!OpC) return false;
36 // If there are no bits set that aren't demanded, nothing to do.
37 Demanded = Demanded.zextOrTrunc(OpC->getValue().getBitWidth());
38 if ((~Demanded & OpC->getValue()) == 0)
41 // This instruction is producing bits that are not demanded. Shrink the RHS.
42 Demanded &= OpC->getValue();
43 I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded));
49 /// SimplifyDemandedInstructionBits - Inst is an integer instruction that
50 /// SimplifyDemandedBits knows about. See if the instruction has any
51 /// properties that allow us to simplify its operands.
52 bool InstCombiner::SimplifyDemandedInstructionBits(Instruction &Inst) {
53 unsigned BitWidth = Inst.getType()->getScalarSizeInBits();
54 APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
55 APInt DemandedMask(APInt::getAllOnesValue(BitWidth));
57 Value *V = SimplifyDemandedUseBits(&Inst, DemandedMask,
58 KnownZero, KnownOne, 0);
59 if (V == 0) return false;
60 if (V == &Inst) return true;
61 ReplaceInstUsesWith(Inst, V);
65 /// SimplifyDemandedBits - This form of SimplifyDemandedBits simplifies the
66 /// specified instruction operand if possible, updating it in place. It returns
67 /// true if it made any change and false otherwise.
68 bool InstCombiner::SimplifyDemandedBits(Use &U, APInt DemandedMask,
69 APInt &KnownZero, APInt &KnownOne,
71 Value *NewVal = SimplifyDemandedUseBits(U.get(), DemandedMask,
72 KnownZero, KnownOne, Depth);
73 if (NewVal == 0) return false;
79 /// SimplifyDemandedUseBits - This function attempts to replace V with a simpler
80 /// value based on the demanded bits. When this function is called, it is known
81 /// that only the bits set in DemandedMask of the result of V are ever used
82 /// downstream. Consequently, depending on the mask and V, it may be possible
83 /// to replace V with a constant or one of its operands. In such cases, this
84 /// function does the replacement and returns true. In all other cases, it
85 /// returns false after analyzing the expression and setting KnownOne and known
86 /// to be one in the expression. KnownZero contains all the bits that are known
87 /// to be zero in the expression. These are provided to potentially allow the
88 /// caller (which might recursively be SimplifyDemandedBits itself) to simplify
89 /// the expression. KnownOne and KnownZero always follow the invariant that
90 /// KnownOne & KnownZero == 0. That is, a bit can't be both 1 and 0. Note that
91 /// the bits in KnownOne and KnownZero may only be accurate for those bits set
92 /// in DemandedMask. Note also that the bitwidth of V, DemandedMask, KnownZero
93 /// and KnownOne must all be the same.
95 /// This returns null if it did not change anything and it permits no
96 /// simplification. This returns V itself if it did some simplification of V's
97 /// operands based on the information about what bits are demanded. This returns
98 /// some other non-null value if it found out that V is equal to another value
99 /// in the context where the specified bits are demanded, but not for all users.
100 Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
101 APInt &KnownZero, APInt &KnownOne,
103 assert(V != 0 && "Null pointer of Value???");
104 assert(Depth <= 6 && "Limit Search Depth");
105 uint32_t BitWidth = DemandedMask.getBitWidth();
106 Type *VTy = V->getType();
107 assert((TD || !VTy->isPointerTy()) &&
108 "SimplifyDemandedBits needs to know bit widths!");
109 assert((!TD || TD->getTypeSizeInBits(VTy->getScalarType()) == BitWidth) &&
110 (!VTy->isIntOrIntVectorTy() ||
111 VTy->getScalarSizeInBits() == BitWidth) &&
112 KnownZero.getBitWidth() == BitWidth &&
113 KnownOne.getBitWidth() == BitWidth &&
114 "Value *V, DemandedMask, KnownZero and KnownOne "
115 "must have same BitWidth");
116 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
117 // We know all of the bits for a constant!
118 KnownOne = CI->getValue() & DemandedMask;
119 KnownZero = ~KnownOne & DemandedMask;
122 if (isa<ConstantPointerNull>(V)) {
123 // We know all of the bits for a constant!
124 KnownOne.clearAllBits();
125 KnownZero = DemandedMask;
129 KnownZero.clearAllBits();
130 KnownOne.clearAllBits();
131 if (DemandedMask == 0) { // Not demanding any bits from V.
132 if (isa<UndefValue>(V))
134 return UndefValue::get(VTy);
137 if (Depth == 6) // Limit search depth.
140 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
141 APInt RHSKnownZero(BitWidth, 0), RHSKnownOne(BitWidth, 0);
143 Instruction *I = dyn_cast<Instruction>(V);
145 ComputeMaskedBits(V, DemandedMask, KnownZero, KnownOne, Depth);
146 return 0; // Only analyze instructions.
149 // If there are multiple uses of this value and we aren't at the root, then
150 // we can't do any simplifications of the operands, because DemandedMask
151 // only reflects the bits demanded by *one* of the users.
152 if (Depth != 0 && !I->hasOneUse()) {
153 // Despite the fact that we can't simplify this instruction in all User's
154 // context, we can at least compute the knownzero/knownone bits, and we can
155 // do simplifications that apply to *just* the one user if we know that
156 // this instruction has a simpler value in that context.
157 if (I->getOpcode() == Instruction::And) {
158 // If either the LHS or the RHS are Zero, the result is zero.
159 ComputeMaskedBits(I->getOperand(1), DemandedMask,
160 RHSKnownZero, RHSKnownOne, Depth+1);
161 ComputeMaskedBits(I->getOperand(0), DemandedMask & ~RHSKnownZero,
162 LHSKnownZero, LHSKnownOne, Depth+1);
164 // If all of the demanded bits are known 1 on one side, return the other.
165 // These bits cannot contribute to the result of the 'and' in this
167 if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) ==
168 (DemandedMask & ~LHSKnownZero))
169 return I->getOperand(0);
170 if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) ==
171 (DemandedMask & ~RHSKnownZero))
172 return I->getOperand(1);
174 // If all of the demanded bits in the inputs are known zeros, return zero.
175 if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask)
176 return Constant::getNullValue(VTy);
178 } else if (I->getOpcode() == Instruction::Or) {
179 // We can simplify (X|Y) -> X or Y in the user's context if we know that
180 // only bits from X or Y are demanded.
182 // If either the LHS or the RHS are One, the result is One.
183 ComputeMaskedBits(I->getOperand(1), DemandedMask,
184 RHSKnownZero, RHSKnownOne, Depth+1);
185 ComputeMaskedBits(I->getOperand(0), DemandedMask & ~RHSKnownOne,
186 LHSKnownZero, LHSKnownOne, Depth+1);
188 // If all of the demanded bits are known zero on one side, return the
189 // other. These bits cannot contribute to the result of the 'or' in this
191 if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) ==
192 (DemandedMask & ~LHSKnownOne))
193 return I->getOperand(0);
194 if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) ==
195 (DemandedMask & ~RHSKnownOne))
196 return I->getOperand(1);
198 // If all of the potentially set bits on one side are known to be set on
199 // the other side, just use the 'other' side.
200 if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) ==
201 (DemandedMask & (~RHSKnownZero)))
202 return I->getOperand(0);
203 if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) ==
204 (DemandedMask & (~LHSKnownZero)))
205 return I->getOperand(1);
208 // Compute the KnownZero/KnownOne bits to simplify things downstream.
209 ComputeMaskedBits(I, DemandedMask, KnownZero, KnownOne, Depth);
213 // If this is the root being simplified, allow it to have multiple uses,
214 // just set the DemandedMask to all bits so that we can try to simplify the
215 // operands. This allows visitTruncInst (for example) to simplify the
216 // operand of a trunc without duplicating all the logic below.
217 if (Depth == 0 && !V->hasOneUse())
218 DemandedMask = APInt::getAllOnesValue(BitWidth);
220 switch (I->getOpcode()) {
222 ComputeMaskedBits(I, DemandedMask, KnownZero, KnownOne, Depth);
224 case Instruction::And:
225 // If either the LHS or the RHS are Zero, the result is zero.
226 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask,
227 RHSKnownZero, RHSKnownOne, Depth+1) ||
228 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask & ~RHSKnownZero,
229 LHSKnownZero, LHSKnownOne, Depth+1))
231 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?");
232 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?");
234 // If all of the demanded bits are known 1 on one side, return the other.
235 // These bits cannot contribute to the result of the 'and'.
236 if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) ==
237 (DemandedMask & ~LHSKnownZero))
238 return I->getOperand(0);
239 if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) ==
240 (DemandedMask & ~RHSKnownZero))
241 return I->getOperand(1);
243 // If all of the demanded bits in the inputs are known zeros, return zero.
244 if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask)
245 return Constant::getNullValue(VTy);
247 // If the RHS is a constant, see if we can simplify it.
248 if (ShrinkDemandedConstant(I, 1, DemandedMask & ~LHSKnownZero))
251 // Output known-1 bits are only known if set in both the LHS & RHS.
252 KnownOne = RHSKnownOne & LHSKnownOne;
253 // Output known-0 are known to be clear if zero in either the LHS | RHS.
254 KnownZero = RHSKnownZero | LHSKnownZero;
256 case Instruction::Or:
257 // If either the LHS or the RHS are One, the result is One.
258 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask,
259 RHSKnownZero, RHSKnownOne, Depth+1) ||
260 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask & ~RHSKnownOne,
261 LHSKnownZero, LHSKnownOne, Depth+1))
263 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?");
264 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?");
266 // If all of the demanded bits are known zero on one side, return the other.
267 // These bits cannot contribute to the result of the 'or'.
268 if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) ==
269 (DemandedMask & ~LHSKnownOne))
270 return I->getOperand(0);
271 if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) ==
272 (DemandedMask & ~RHSKnownOne))
273 return I->getOperand(1);
275 // If all of the potentially set bits on one side are known to be set on
276 // the other side, just use the 'other' side.
277 if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) ==
278 (DemandedMask & (~RHSKnownZero)))
279 return I->getOperand(0);
280 if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) ==
281 (DemandedMask & (~LHSKnownZero)))
282 return I->getOperand(1);
284 // If the RHS is a constant, see if we can simplify it.
285 if (ShrinkDemandedConstant(I, 1, DemandedMask))
288 // Output known-0 bits are only known if clear in both the LHS & RHS.
289 KnownZero = RHSKnownZero & LHSKnownZero;
290 // Output known-1 are known to be set if set in either the LHS | RHS.
291 KnownOne = RHSKnownOne | LHSKnownOne;
293 case Instruction::Xor: {
294 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask,
295 RHSKnownZero, RHSKnownOne, Depth+1) ||
296 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask,
297 LHSKnownZero, LHSKnownOne, Depth+1))
299 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?");
300 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?");
302 // If all of the demanded bits are known zero on one side, return the other.
303 // These bits cannot contribute to the result of the 'xor'.
304 if ((DemandedMask & RHSKnownZero) == DemandedMask)
305 return I->getOperand(0);
306 if ((DemandedMask & LHSKnownZero) == DemandedMask)
307 return I->getOperand(1);
309 // If all of the demanded bits are known to be zero on one side or the
310 // other, turn this into an *inclusive* or.
311 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
312 if ((DemandedMask & ~RHSKnownZero & ~LHSKnownZero) == 0) {
314 BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1),
316 return InsertNewInstWith(Or, *I);
319 // If all of the demanded bits on one side are known, and all of the set
320 // bits on that side are also known to be set on the other side, turn this
321 // into an AND, as we know the bits will be cleared.
322 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
323 if ((DemandedMask & (RHSKnownZero|RHSKnownOne)) == DemandedMask) {
325 if ((RHSKnownOne & LHSKnownOne) == RHSKnownOne) {
326 Constant *AndC = Constant::getIntegerValue(VTy,
327 ~RHSKnownOne & DemandedMask);
328 Instruction *And = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
329 return InsertNewInstWith(And, *I);
333 // If the RHS is a constant, see if we can simplify it.
334 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
335 if (ShrinkDemandedConstant(I, 1, DemandedMask))
338 // If our LHS is an 'and' and if it has one use, and if any of the bits we
339 // are flipping are known to be set, then the xor is just resetting those
340 // bits to zero. We can just knock out bits from the 'and' and the 'xor',
341 // simplifying both of them.
342 if (Instruction *LHSInst = dyn_cast<Instruction>(I->getOperand(0)))
343 if (LHSInst->getOpcode() == Instruction::And && LHSInst->hasOneUse() &&
344 isa<ConstantInt>(I->getOperand(1)) &&
345 isa<ConstantInt>(LHSInst->getOperand(1)) &&
346 (LHSKnownOne & RHSKnownOne & DemandedMask) != 0) {
347 ConstantInt *AndRHS = cast<ConstantInt>(LHSInst->getOperand(1));
348 ConstantInt *XorRHS = cast<ConstantInt>(I->getOperand(1));
349 APInt NewMask = ~(LHSKnownOne & RHSKnownOne & DemandedMask);
352 ConstantInt::get(I->getType(), NewMask & AndRHS->getValue());
353 Instruction *NewAnd = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
354 InsertNewInstWith(NewAnd, *I);
357 ConstantInt::get(I->getType(), NewMask & XorRHS->getValue());
358 Instruction *NewXor = BinaryOperator::CreateXor(NewAnd, XorC);
359 return InsertNewInstWith(NewXor, *I);
362 // Output known-0 bits are known if clear or set in both the LHS & RHS.
363 KnownZero= (RHSKnownZero & LHSKnownZero) | (RHSKnownOne & LHSKnownOne);
364 // Output known-1 are known to be set if set in only one of the LHS, RHS.
365 KnownOne = (RHSKnownZero & LHSKnownOne) | (RHSKnownOne & LHSKnownZero);
368 case Instruction::Select:
369 if (SimplifyDemandedBits(I->getOperandUse(2), DemandedMask,
370 RHSKnownZero, RHSKnownOne, Depth+1) ||
371 SimplifyDemandedBits(I->getOperandUse(1), DemandedMask,
372 LHSKnownZero, LHSKnownOne, Depth+1))
374 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?");
375 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?");
377 // If the operands are constants, see if we can simplify them.
378 if (ShrinkDemandedConstant(I, 1, DemandedMask) ||
379 ShrinkDemandedConstant(I, 2, DemandedMask))
382 // Only known if known in both the LHS and RHS.
383 KnownOne = RHSKnownOne & LHSKnownOne;
384 KnownZero = RHSKnownZero & LHSKnownZero;
386 case Instruction::Trunc: {
387 unsigned truncBf = I->getOperand(0)->getType()->getScalarSizeInBits();
388 DemandedMask = DemandedMask.zext(truncBf);
389 KnownZero = KnownZero.zext(truncBf);
390 KnownOne = KnownOne.zext(truncBf);
391 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask,
392 KnownZero, KnownOne, Depth+1))
394 DemandedMask = DemandedMask.trunc(BitWidth);
395 KnownZero = KnownZero.trunc(BitWidth);
396 KnownOne = KnownOne.trunc(BitWidth);
397 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
400 case Instruction::BitCast:
401 if (!I->getOperand(0)->getType()->isIntOrIntVectorTy())
402 return 0; // vector->int or fp->int?
404 if (VectorType *DstVTy = dyn_cast<VectorType>(I->getType())) {
405 if (VectorType *SrcVTy =
406 dyn_cast<VectorType>(I->getOperand(0)->getType())) {
407 if (DstVTy->getNumElements() != SrcVTy->getNumElements())
408 // Don't touch a bitcast between vectors of different element counts.
411 // Don't touch a scalar-to-vector bitcast.
413 } else if (I->getOperand(0)->getType()->isVectorTy())
414 // Don't touch a vector-to-scalar bitcast.
417 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask,
418 KnownZero, KnownOne, Depth+1))
420 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
422 case Instruction::ZExt: {
423 // Compute the bits in the result that are not present in the input.
424 unsigned SrcBitWidth =I->getOperand(0)->getType()->getScalarSizeInBits();
426 DemandedMask = DemandedMask.trunc(SrcBitWidth);
427 KnownZero = KnownZero.trunc(SrcBitWidth);
428 KnownOne = KnownOne.trunc(SrcBitWidth);
429 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask,
430 KnownZero, KnownOne, Depth+1))
432 DemandedMask = DemandedMask.zext(BitWidth);
433 KnownZero = KnownZero.zext(BitWidth);
434 KnownOne = KnownOne.zext(BitWidth);
435 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
436 // The top bits are known to be zero.
437 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth);
440 case Instruction::SExt: {
441 // Compute the bits in the result that are not present in the input.
442 unsigned SrcBitWidth =I->getOperand(0)->getType()->getScalarSizeInBits();
444 APInt InputDemandedBits = DemandedMask &
445 APInt::getLowBitsSet(BitWidth, SrcBitWidth);
447 APInt NewBits(APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth));
448 // If any of the sign extended bits are demanded, we know that the sign
450 if ((NewBits & DemandedMask) != 0)
451 InputDemandedBits.setBit(SrcBitWidth-1);
453 InputDemandedBits = InputDemandedBits.trunc(SrcBitWidth);
454 KnownZero = KnownZero.trunc(SrcBitWidth);
455 KnownOne = KnownOne.trunc(SrcBitWidth);
456 if (SimplifyDemandedBits(I->getOperandUse(0), InputDemandedBits,
457 KnownZero, KnownOne, Depth+1))
459 InputDemandedBits = InputDemandedBits.zext(BitWidth);
460 KnownZero = KnownZero.zext(BitWidth);
461 KnownOne = KnownOne.zext(BitWidth);
462 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
464 // If the sign bit of the input is known set or clear, then we know the
465 // top bits of the result.
467 // If the input sign bit is known zero, or if the NewBits are not demanded
468 // convert this into a zero extension.
469 if (KnownZero[SrcBitWidth-1] || (NewBits & ~DemandedMask) == NewBits) {
470 // Convert to ZExt cast
471 CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName());
472 return InsertNewInstWith(NewCast, *I);
473 } else if (KnownOne[SrcBitWidth-1]) { // Input sign bit known set
478 case Instruction::Add: {
479 // Figure out what the input bits are. If the top bits of the and result
480 // are not demanded, then the add doesn't demand them from its input
482 unsigned NLZ = DemandedMask.countLeadingZeros();
484 // If there is a constant on the RHS, there are a variety of xformations
486 if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) {
487 // If null, this should be simplified elsewhere. Some of the xforms here
488 // won't work if the RHS is zero.
492 // If the top bit of the output is demanded, demand everything from the
493 // input. Otherwise, we demand all the input bits except NLZ top bits.
494 APInt InDemandedBits(APInt::getLowBitsSet(BitWidth, BitWidth - NLZ));
496 // Find information about known zero/one bits in the input.
497 if (SimplifyDemandedBits(I->getOperandUse(0), InDemandedBits,
498 LHSKnownZero, LHSKnownOne, Depth+1))
501 // If the RHS of the add has bits set that can't affect the input, reduce
503 if (ShrinkDemandedConstant(I, 1, InDemandedBits))
506 // Avoid excess work.
507 if (LHSKnownZero == 0 && LHSKnownOne == 0)
510 // Turn it into OR if input bits are zero.
511 if ((LHSKnownZero & RHS->getValue()) == RHS->getValue()) {
513 BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1),
515 return InsertNewInstWith(Or, *I);
518 // We can say something about the output known-zero and known-one bits,
519 // depending on potential carries from the input constant and the
520 // unknowns. For example if the LHS is known to have at most the 0x0F0F0
521 // bits set and the RHS constant is 0x01001, then we know we have a known
522 // one mask of 0x00001 and a known zero mask of 0xE0F0E.
524 // To compute this, we first compute the potential carry bits. These are
525 // the bits which may be modified. I'm not aware of a better way to do
527 const APInt &RHSVal = RHS->getValue();
528 APInt CarryBits((~LHSKnownZero + RHSVal) ^ (~LHSKnownZero ^ RHSVal));
530 // Now that we know which bits have carries, compute the known-1/0 sets.
532 // Bits are known one if they are known zero in one operand and one in the
533 // other, and there is no input carry.
534 KnownOne = ((LHSKnownZero & RHSVal) |
535 (LHSKnownOne & ~RHSVal)) & ~CarryBits;
537 // Bits are known zero if they are known zero in both operands and there
538 // is no input carry.
539 KnownZero = LHSKnownZero & ~RHSVal & ~CarryBits;
541 // If the high-bits of this ADD are not demanded, then it does not demand
542 // the high bits of its LHS or RHS.
543 if (DemandedMask[BitWidth-1] == 0) {
544 // Right fill the mask of bits for this ADD to demand the most
545 // significant bit and all those below it.
546 APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ));
547 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedFromOps,
548 LHSKnownZero, LHSKnownOne, Depth+1) ||
549 SimplifyDemandedBits(I->getOperandUse(1), DemandedFromOps,
550 LHSKnownZero, LHSKnownOne, Depth+1))
556 case Instruction::Sub:
557 // If the high-bits of this SUB are not demanded, then it does not demand
558 // the high bits of its LHS or RHS.
559 if (DemandedMask[BitWidth-1] == 0) {
560 // Right fill the mask of bits for this SUB to demand the most
561 // significant bit and all those below it.
562 uint32_t NLZ = DemandedMask.countLeadingZeros();
563 APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ));
564 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedFromOps,
565 LHSKnownZero, LHSKnownOne, Depth+1) ||
566 SimplifyDemandedBits(I->getOperandUse(1), DemandedFromOps,
567 LHSKnownZero, LHSKnownOne, Depth+1))
571 // Otherwise just hand the sub off to ComputeMaskedBits to fill in
572 // the known zeros and ones.
573 ComputeMaskedBits(V, DemandedMask, KnownZero, KnownOne, Depth);
575 // Turn this into a xor if LHS is 2^n-1 and the remaining bits are known
577 if (ConstantInt *C0 = dyn_cast<ConstantInt>(I->getOperand(0))) {
578 APInt I0 = C0->getValue();
579 if ((I0 + 1).isPowerOf2() && (I0 | KnownZero).isAllOnesValue()) {
580 Instruction *Xor = BinaryOperator::CreateXor(I->getOperand(1), C0);
581 return InsertNewInstWith(Xor, *I);
585 case Instruction::Shl:
586 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
587 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
588 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
590 // If the shift is NUW/NSW, then it does demand the high bits.
591 ShlOperator *IOp = cast<ShlOperator>(I);
592 if (IOp->hasNoSignedWrap())
593 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
594 else if (IOp->hasNoUnsignedWrap())
595 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
597 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn,
598 KnownZero, KnownOne, Depth+1))
600 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
601 KnownZero <<= ShiftAmt;
602 KnownOne <<= ShiftAmt;
603 // low bits known zero.
605 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
608 case Instruction::LShr:
609 // For a logical shift right
610 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
611 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
613 // Unsigned shift right.
614 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
616 // If the shift is exact, then it does demand the low bits (and knows that
618 if (cast<LShrOperator>(I)->isExact())
619 DemandedMaskIn |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
621 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn,
622 KnownZero, KnownOne, Depth+1))
624 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
625 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
626 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt);
628 // Compute the new bits that are at the top now.
629 APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt));
630 KnownZero |= HighBits; // high bits known zero.
634 case Instruction::AShr:
635 // If this is an arithmetic shift right and only the low-bit is set, we can
636 // always convert this into a logical shr, even if the shift amount is
637 // variable. The low bit of the shift cannot be an input sign bit unless
638 // the shift amount is >= the size of the datatype, which is undefined.
639 if (DemandedMask == 1) {
640 // Perform the logical shift right.
641 Instruction *NewVal = BinaryOperator::CreateLShr(
642 I->getOperand(0), I->getOperand(1), I->getName());
643 return InsertNewInstWith(NewVal, *I);
646 // If the sign bit is the only bit demanded by this ashr, then there is no
647 // need to do it, the shift doesn't change the high bit.
648 if (DemandedMask.isSignBit())
649 return I->getOperand(0);
651 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
652 uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
654 // Signed shift right.
655 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
656 // If any of the "high bits" are demanded, we should set the sign bit as
658 if (DemandedMask.countLeadingZeros() <= ShiftAmt)
659 DemandedMaskIn.setBit(BitWidth-1);
661 // If the shift is exact, then it does demand the low bits (and knows that
663 if (cast<AShrOperator>(I)->isExact())
664 DemandedMaskIn |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
666 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn,
667 KnownZero, KnownOne, Depth+1))
669 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
670 // Compute the new bits that are at the top now.
671 APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt));
672 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
673 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt);
675 // Handle the sign bits.
676 APInt SignBit(APInt::getSignBit(BitWidth));
677 // Adjust to where it is now in the mask.
678 SignBit = APIntOps::lshr(SignBit, ShiftAmt);
680 // If the input sign bit is known to be zero, or if none of the top bits
681 // are demanded, turn this into an unsigned shift right.
682 if (BitWidth <= ShiftAmt || KnownZero[BitWidth-ShiftAmt-1] ||
683 (HighBits & ~DemandedMask) == HighBits) {
684 // Perform the logical shift right.
685 BinaryOperator *NewVal = BinaryOperator::CreateLShr(I->getOperand(0),
687 NewVal->setIsExact(cast<BinaryOperator>(I)->isExact());
688 return InsertNewInstWith(NewVal, *I);
689 } else if ((KnownOne & SignBit) != 0) { // New bits are known one.
690 KnownOne |= HighBits;
694 case Instruction::SRem:
695 if (ConstantInt *Rem = dyn_cast<ConstantInt>(I->getOperand(1))) {
696 // X % -1 demands all the bits because we don't want to introduce
697 // INT_MIN % -1 (== undef) by accident.
698 if (Rem->isAllOnesValue())
700 APInt RA = Rem->getValue().abs();
701 if (RA.isPowerOf2()) {
702 if (DemandedMask.ult(RA)) // srem won't affect demanded bits
703 return I->getOperand(0);
705 APInt LowBits = RA - 1;
706 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth);
707 if (SimplifyDemandedBits(I->getOperandUse(0), Mask2,
708 LHSKnownZero, LHSKnownOne, Depth+1))
711 // The low bits of LHS are unchanged by the srem.
712 KnownZero = LHSKnownZero & LowBits;
713 KnownOne = LHSKnownOne & LowBits;
715 // If LHS is non-negative or has all low bits zero, then the upper bits
717 if (LHSKnownZero[BitWidth-1] || ((LHSKnownZero & LowBits) == LowBits))
718 KnownZero |= ~LowBits;
720 // If LHS is negative and not all low bits are zero, then the upper bits
722 if (LHSKnownOne[BitWidth-1] && ((LHSKnownOne & LowBits) != 0))
723 KnownOne |= ~LowBits;
725 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
729 // The sign bit is the LHS's sign bit, except when the result of the
730 // remainder is zero.
731 if (DemandedMask.isNegative() && KnownZero.isNonNegative()) {
732 APInt Mask2 = APInt::getSignBit(BitWidth);
733 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
734 ComputeMaskedBits(I->getOperand(0), Mask2, LHSKnownZero, LHSKnownOne,
736 // If it's known zero, our sign bit is also zero.
737 if (LHSKnownZero.isNegative())
738 KnownZero |= LHSKnownZero;
741 case Instruction::URem: {
742 APInt KnownZero2(BitWidth, 0), KnownOne2(BitWidth, 0);
743 APInt AllOnes = APInt::getAllOnesValue(BitWidth);
744 if (SimplifyDemandedBits(I->getOperandUse(0), AllOnes,
745 KnownZero2, KnownOne2, Depth+1) ||
746 SimplifyDemandedBits(I->getOperandUse(1), AllOnes,
747 KnownZero2, KnownOne2, Depth+1))
750 unsigned Leaders = KnownZero2.countLeadingOnes();
751 Leaders = std::max(Leaders,
752 KnownZero2.countLeadingOnes());
753 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & DemandedMask;
756 case Instruction::Call:
757 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
758 switch (II->getIntrinsicID()) {
760 case Intrinsic::bswap: {
761 // If the only bits demanded come from one byte of the bswap result,
762 // just shift the input byte into position to eliminate the bswap.
763 unsigned NLZ = DemandedMask.countLeadingZeros();
764 unsigned NTZ = DemandedMask.countTrailingZeros();
766 // Round NTZ down to the next byte. If we have 11 trailing zeros, then
767 // we need all the bits down to bit 8. Likewise, round NLZ. If we
768 // have 14 leading zeros, round to 8.
771 // If we need exactly one byte, we can do this transformation.
772 if (BitWidth-NLZ-NTZ == 8) {
773 unsigned ResultBit = NTZ;
774 unsigned InputBit = BitWidth-NTZ-8;
776 // Replace this with either a left or right shift to get the byte into
779 if (InputBit > ResultBit)
780 NewVal = BinaryOperator::CreateLShr(II->getArgOperand(0),
781 ConstantInt::get(I->getType(), InputBit-ResultBit));
783 NewVal = BinaryOperator::CreateShl(II->getArgOperand(0),
784 ConstantInt::get(I->getType(), ResultBit-InputBit));
786 return InsertNewInstWith(NewVal, *I);
789 // TODO: Could compute known zero/one bits based on the input.
792 case Intrinsic::x86_sse42_crc32_64_8:
793 case Intrinsic::x86_sse42_crc32_64_64:
794 KnownZero = APInt::getHighBitsSet(64, 32);
798 ComputeMaskedBits(V, DemandedMask, KnownZero, KnownOne, Depth);
802 // If the client is only demanding bits that we know, return the known
804 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
805 return Constant::getIntegerValue(VTy, KnownOne);
810 /// SimplifyDemandedVectorElts - The specified value produces a vector with
811 /// any number of elements. DemandedElts contains the set of elements that are
812 /// actually used by the caller. This method analyzes which elements of the
813 /// operand are undef and returns that information in UndefElts.
815 /// If the information about demanded elements can be used to simplify the
816 /// operation, the operation is simplified, then the resultant value is
817 /// returned. This returns null if no change was made.
818 Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
821 unsigned VWidth = cast<VectorType>(V->getType())->getNumElements();
822 APInt EltMask(APInt::getAllOnesValue(VWidth));
823 assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!");
825 if (isa<UndefValue>(V)) {
826 // If the entire vector is undefined, just return this info.
831 if (DemandedElts == 0) { // If nothing is demanded, provide undef.
833 return UndefValue::get(V->getType());
838 // Handle ConstantAggregateZero, ConstantVector, ConstantDataSequential.
839 if (Constant *C = dyn_cast<Constant>(V)) {
840 // Check if this is identity. If so, return 0 since we are not simplifying
842 if (DemandedElts.isAllOnesValue())
845 Type *EltTy = cast<VectorType>(V->getType())->getElementType();
846 Constant *Undef = UndefValue::get(EltTy);
848 SmallVector<Constant*, 16> Elts;
849 for (unsigned i = 0; i != VWidth; ++i) {
850 if (!DemandedElts[i]) { // If not demanded, set to undef.
851 Elts.push_back(Undef);
856 Constant *Elt = C->getAggregateElement(i);
857 if (Elt == 0) return 0;
859 if (isa<UndefValue>(Elt)) { // Already undef.
860 Elts.push_back(Undef);
862 } else { // Otherwise, defined.
867 // If we changed the constant, return it.
868 Constant *NewCV = ConstantVector::get(Elts);
869 return NewCV != C ? NewCV : 0;
872 // Limit search depth.
876 // If multiple users are using the root value, proceed with
877 // simplification conservatively assuming that all elements
879 if (!V->hasOneUse()) {
880 // Quit if we find multiple users of a non-root value though.
881 // They'll be handled when it's their turn to be visited by
882 // the main instcombine process.
884 // TODO: Just compute the UndefElts information recursively.
887 // Conservatively assume that all elements are needed.
888 DemandedElts = EltMask;
891 Instruction *I = dyn_cast<Instruction>(V);
892 if (!I) return 0; // Only analyze instructions.
894 bool MadeChange = false;
895 APInt UndefElts2(VWidth, 0);
897 switch (I->getOpcode()) {
900 case Instruction::InsertElement: {
901 // If this is a variable index, we don't know which element it overwrites.
902 // demand exactly the same input as we produce.
903 ConstantInt *Idx = dyn_cast<ConstantInt>(I->getOperand(2));
905 // Note that we can't propagate undef elt info, because we don't know
906 // which elt is getting updated.
907 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts,
908 UndefElts2, Depth+1);
909 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
913 // If this is inserting an element that isn't demanded, remove this
915 unsigned IdxNo = Idx->getZExtValue();
916 if (IdxNo >= VWidth || !DemandedElts[IdxNo]) {
918 return I->getOperand(0);
921 // Otherwise, the element inserted overwrites whatever was there, so the
922 // input demanded set is simpler than the output set.
923 APInt DemandedElts2 = DemandedElts;
924 DemandedElts2.clearBit(IdxNo);
925 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts2,
927 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
929 // The inserted element is defined.
930 UndefElts.clearBit(IdxNo);
933 case Instruction::ShuffleVector: {
934 ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
936 cast<VectorType>(Shuffle->getOperand(0)->getType())->getNumElements();
937 APInt LeftDemanded(LHSVWidth, 0), RightDemanded(LHSVWidth, 0);
938 for (unsigned i = 0; i < VWidth; i++) {
939 if (DemandedElts[i]) {
940 unsigned MaskVal = Shuffle->getMaskValue(i);
941 if (MaskVal != -1u) {
942 assert(MaskVal < LHSVWidth * 2 &&
943 "shufflevector mask index out of range!");
944 if (MaskVal < LHSVWidth)
945 LeftDemanded.setBit(MaskVal);
947 RightDemanded.setBit(MaskVal - LHSVWidth);
952 APInt UndefElts4(LHSVWidth, 0);
953 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), LeftDemanded,
954 UndefElts4, Depth+1);
955 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
957 APInt UndefElts3(LHSVWidth, 0);
958 TmpV = SimplifyDemandedVectorElts(I->getOperand(1), RightDemanded,
959 UndefElts3, Depth+1);
960 if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; }
962 bool NewUndefElts = false;
963 for (unsigned i = 0; i < VWidth; i++) {
964 unsigned MaskVal = Shuffle->getMaskValue(i);
965 if (MaskVal == -1u) {
967 } else if (!DemandedElts[i]) {
970 } else if (MaskVal < LHSVWidth) {
971 if (UndefElts4[MaskVal]) {
976 if (UndefElts3[MaskVal - LHSVWidth]) {
984 // Add additional discovered undefs.
985 std::vector<Constant*> Elts;
986 for (unsigned i = 0; i < VWidth; ++i) {
988 Elts.push_back(UndefValue::get(Type::getInt32Ty(I->getContext())));
990 Elts.push_back(ConstantInt::get(Type::getInt32Ty(I->getContext()),
991 Shuffle->getMaskValue(i)));
993 I->setOperand(2, ConstantVector::get(Elts));
998 case Instruction::BitCast: {
999 // Vector->vector casts only.
1000 VectorType *VTy = dyn_cast<VectorType>(I->getOperand(0)->getType());
1002 unsigned InVWidth = VTy->getNumElements();
1003 APInt InputDemandedElts(InVWidth, 0);
1006 if (VWidth == InVWidth) {
1007 // If we are converting from <4 x i32> -> <4 x f32>, we demand the same
1008 // elements as are demanded of us.
1010 InputDemandedElts = DemandedElts;
1011 } else if (VWidth > InVWidth) {
1015 // If there are more elements in the result than there are in the source,
1016 // then an input element is live if any of the corresponding output
1017 // elements are live.
1018 Ratio = VWidth/InVWidth;
1019 for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
1020 if (DemandedElts[OutIdx])
1021 InputDemandedElts.setBit(OutIdx/Ratio);
1027 // If there are more elements in the source than there are in the result,
1028 // then an input element is live if the corresponding output element is
1030 Ratio = InVWidth/VWidth;
1031 for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
1032 if (DemandedElts[InIdx/Ratio])
1033 InputDemandedElts.setBit(InIdx);
1036 // div/rem demand all inputs, because they don't want divide by zero.
1037 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), InputDemandedElts,
1038 UndefElts2, Depth+1);
1040 I->setOperand(0, TmpV);
1044 UndefElts = UndefElts2;
1045 if (VWidth > InVWidth) {
1046 llvm_unreachable("Unimp");
1047 // If there are more elements in the result than there are in the source,
1048 // then an output element is undef if the corresponding input element is
1050 for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1051 if (UndefElts2[OutIdx/Ratio])
1052 UndefElts.setBit(OutIdx);
1053 } else if (VWidth < InVWidth) {
1054 llvm_unreachable("Unimp");
1055 // If there are more elements in the source than there are in the result,
1056 // then a result element is undef if all of the corresponding input
1057 // elements are undef.
1058 UndefElts = ~0ULL >> (64-VWidth); // Start out all undef.
1059 for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
1060 if (!UndefElts2[InIdx]) // Not undef?
1061 UndefElts.clearBit(InIdx/Ratio); // Clear undef bit.
1065 case Instruction::And:
1066 case Instruction::Or:
1067 case Instruction::Xor:
1068 case Instruction::Add:
1069 case Instruction::Sub:
1070 case Instruction::Mul:
1071 // div/rem demand all inputs, because they don't want divide by zero.
1072 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts,
1073 UndefElts, Depth+1);
1074 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
1075 TmpV = SimplifyDemandedVectorElts(I->getOperand(1), DemandedElts,
1076 UndefElts2, Depth+1);
1077 if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; }
1079 // Output elements are undefined if both are undefined. Consider things
1080 // like undef&0. The result is known zero, not undef.
1081 UndefElts &= UndefElts2;
1084 case Instruction::Call: {
1085 IntrinsicInst *II = dyn_cast<IntrinsicInst>(I);
1087 switch (II->getIntrinsicID()) {
1090 // Binary vector operations that work column-wise. A dest element is a
1091 // function of the corresponding input elements from the two inputs.
1092 case Intrinsic::x86_sse_sub_ss:
1093 case Intrinsic::x86_sse_mul_ss:
1094 case Intrinsic::x86_sse_min_ss:
1095 case Intrinsic::x86_sse_max_ss:
1096 case Intrinsic::x86_sse2_sub_sd:
1097 case Intrinsic::x86_sse2_mul_sd:
1098 case Intrinsic::x86_sse2_min_sd:
1099 case Intrinsic::x86_sse2_max_sd:
1100 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
1101 UndefElts, Depth+1);
1102 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1103 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts,
1104 UndefElts2, Depth+1);
1105 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
1107 // If only the low elt is demanded and this is a scalarizable intrinsic,
1108 // scalarize it now.
1109 if (DemandedElts == 1) {
1110 switch (II->getIntrinsicID()) {
1112 case Intrinsic::x86_sse_sub_ss:
1113 case Intrinsic::x86_sse_mul_ss:
1114 case Intrinsic::x86_sse2_sub_sd:
1115 case Intrinsic::x86_sse2_mul_sd:
1116 // TODO: Lower MIN/MAX/ABS/etc
1117 Value *LHS = II->getArgOperand(0);
1118 Value *RHS = II->getArgOperand(1);
1119 // Extract the element as scalars.
1120 LHS = InsertNewInstWith(ExtractElementInst::Create(LHS,
1121 ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U)), *II);
1122 RHS = InsertNewInstWith(ExtractElementInst::Create(RHS,
1123 ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U)), *II);
1125 switch (II->getIntrinsicID()) {
1126 default: llvm_unreachable("Case stmts out of sync!");
1127 case Intrinsic::x86_sse_sub_ss:
1128 case Intrinsic::x86_sse2_sub_sd:
1129 TmpV = InsertNewInstWith(BinaryOperator::CreateFSub(LHS, RHS,
1130 II->getName()), *II);
1132 case Intrinsic::x86_sse_mul_ss:
1133 case Intrinsic::x86_sse2_mul_sd:
1134 TmpV = InsertNewInstWith(BinaryOperator::CreateFMul(LHS, RHS,
1135 II->getName()), *II);
1140 InsertElementInst::Create(
1141 UndefValue::get(II->getType()), TmpV,
1142 ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U, false),
1144 InsertNewInstWith(New, *II);
1149 // Output elements are undefined if both are undefined. Consider things
1150 // like undef&0. The result is known zero, not undef.
1151 UndefElts &= UndefElts2;
1157 return MadeChange ? I : 0;