package/boot/uboot-layerscape/patches/0013-armv8-fsl-layerscape-Add-support-of-QorIQ-LS1012A-So.patch

   1 From 53ffd67d944fa23037e7f97e583fae300d4367f7 Mon Sep 17 00:00:00 2001
   2 From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
   3 Date: Sat, 23 Apr 2016 15:23:52 +0530
   4 Subject: [PATCH 13/93] armv8: fsl-layerscape: Add support of QorIQ LS1012A
   5  SoC
   6
   7 [context adjustment]
   8
   9 The QorIQ LS1012A processor, optimized for battery-backed or
  10 USB-powered, integrates a single ARM Cortex-A53 core with a hardware
  11 packet forwarding engine and high-speed interfaces to deliver
  12 line-rate networking performance.
  13
  14 This patch add support of LS1012A SoC along with
  15  - Update platform & DDR clock read logic as per SVR
  16  - Define MMDC controller register set.
  17  - Update LUT base address for PCIe
  18  - Avoid L3 platform cache compilation
  19  - Update USB address, errata
  20  - SerDes table
  21
  22 Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
  23 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
  24 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
  25 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
  26 Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
  27 ---
  28  arch/arm/cpu/armv8/fsl-layerscape/Makefile         |    4 ++
  29  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c |   24 +++++--
  30  arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S       |    2 +
  31  arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c |   74 ++++++++++++++++++++
  32  arch/arm/cpu/armv8/fsl-layerscape/soc.c            |    6 +-
  33  arch/arm/include/asm/arch-fsl-layerscape/config.h  |   32 +++++++++
  34  arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |    1 +
  35  .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |    1 +
  36  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |    4 ++
  37  arch/arm/include/asm/arch-fsl-layerscape/soc.h     |    1 +
  38  include/fsl_mmdc.h                                 |   53 ++++++++++++++
  39  include/linux/usb/xhci-fsl.h                       |    4 ++
  40  12 files changed, 199 insertions(+), 7 deletions(-)
  41  create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
  42  create mode 100644 include/fsl_mmdc.h
  43
  44 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
  45 index 27bfeb1..03f73d1 100644
  46 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
  47 +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
  48 @@ -33,3 +33,7 @@ endif
  49  ifneq ($(CONFIG_LS1043A),)
  50  obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
  51  endif
  52 +
  53 +ifneq ($(CONFIG_LS1012A),)
  54 +obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
  55 +endif
  56 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
  57 index 078b087..63e5bed 100644
  58 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
  59 +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
  60 @@ -33,6 +33,7 @@ void get_sys_info(struct sys_info *sys_info)
  61  #endif
  62         struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
  63         unsigned int cpu;
  64 +       unsigned int svr, ver;
  65         const u8 core_cplx_pll[8] = {
  66                 [0] = 0,        /* CC1 PPL / 1 */
  67                 [1] = 0,        /* CC1 PPL / 2 */
  68 @@ -59,12 +60,20 @@ void get_sys_info(struct sys_info *sys_info)
  69         sys_info->freq_ddrbus = sysclk;
  70  #endif
  71
  72 -       sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
  73 -                       FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
  74 -                       FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
  75 -       sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
  76 -                       FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
  77 -                       FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
  78 +       svr = gur_in32(&gur->svr);
  79 +       ver = SVR_SOC_VER(svr);
  80 +       if (ver == SVR_LS1012) {
  81 +               sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
  82 +                               FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
  83 +                               FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
  84 +       } else {
  85 +               sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
  86 +                               FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
  87 +                               FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
  88 +               sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
  89 +                               FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
  90 +                               FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
  91 +       }
  92
  93         for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
  94                 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
  95 @@ -83,6 +92,9 @@ void get_sys_info(struct sys_info *sys_info)
  96                         freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  97         }
  98
  99 +       if (ver == SVR_LS1012)
 100 +               sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
 101 +
 102  #define HWA_CGA_M1_CLK_SEL     0xe0000000
 103  #define HWA_CGA_M1_CLK_SHIFT   29
 104  #ifdef CONFIG_SYS_DPAA_FMAN
 105 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
 106 index 5f5bfb9..b40834a 100644
 107 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
 108 +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
 109 @@ -184,6 +184,7 @@ ENTRY(lowlevel_init)
 110         ret
 111  ENDPROC(lowlevel_init)
 112
 113 +#ifdef CONFIG_FSL_LSCH3
 114  hnf_pstate_poll:
 115         /* x0 has the desired status, return 0 for success, 1 for timeout
 116          * clobber x1, x2, x3, x4, x6, x7
 117 @@ -261,6 +262,7 @@ ENTRY(__asm_flush_l3_cache)
 118         mov     lr, x29
 119         ret
 120  ENDPROC(__asm_flush_l3_cache)
 121 +#endif
 122
 123  #ifdef CONFIG_MP
 124         /* Keep literals not used by the secondary boot code outside it */
 125 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
 126 new file mode 100644
 127 index 0000000..ff0903c
 128 --- /dev/null
 129 +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
 130 @@ -0,0 +1,74 @@
 131 +/*
 132 + * Copyright 2016 Freescale Semiconductor, Inc.
 133 + *
 134 + * SPDX-License-Identifier:    GPL-2.0+
 135 + */
 136 +
 137 +#include <common.h>
 138 +#include <asm/arch/fsl_serdes.h>
 139 +#include <asm/arch/immap_lsch2.h>
 140 +
 141 +struct serdes_config {
 142 +       u32 protocol;
 143 +       u8 lanes[SRDS_MAX_LANES];
 144 +};
 145 +
 146 +static struct serdes_config serdes1_cfg_tbl[] = {
 147 +       {0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} },
 148 +       {0x0008, {NONE, NONE, NONE, SATA1} },
 149 +       {0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} },
 150 +       {0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
 151 +       {0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} },
 152 +       {0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
 153 +       {0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
 154 +       {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
 155 +       {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
 156 +       {}
 157 +};
 158 +
 159 +static struct serdes_config *serdes_cfg_tbl[] = {
 160 +       serdes1_cfg_tbl,
 161 +};
 162 +
 163 +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
 164 +{
 165 +       struct serdes_config *ptr;
 166 +
 167 +       if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
 168 +               return 0;
 169 +
 170 +       ptr = serdes_cfg_tbl[serdes];
 171 +       while (ptr->protocol) {
 172 +               if (ptr->protocol == cfg)
 173 +                       return ptr->lanes[lane];
 174 +               ptr++;
 175 +       }
 176 +
 177 +       return 0;
 178 +}
 179 +
 180 +int is_serdes_prtcl_valid(int serdes, u32 prtcl)
 181 +{
 182 +       int i;
 183 +       struct serdes_config *ptr;
 184 +
 185 +       if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
 186 +               return 0;
 187 +
 188 +       ptr = serdes_cfg_tbl[serdes];
 189 +       while (ptr->protocol) {
 190 +               if (ptr->protocol == prtcl)
 191 +                       break;
 192 +               ptr++;
 193 +       }
 194 +
 195 +       if (!ptr->protocol)
 196 +               return 0;
 197 +
 198 +       for (i = 0; i < SRDS_MAX_LANES; i++) {
 199 +               if (ptr->lanes[i] != NONE)
 200 +                       return 1;
 201 +       }
 202 +
 203 +       return 0;
 204 +}
 205 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
 206 index 23f0c88..ec561a7 100644
 207 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
 208 +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
 209 @@ -12,8 +12,10 @@
 210  #include <asm/io.h>
 211  #include <asm/global_data.h>
 212  #include <asm/arch-fsl-layerscape/config.h>
 213 +#ifdef CONFIG_SYS_FSL_DDR
 214  #include <fsl_ddr_sdram.h>
 215  #include <fsl_ddr.h>
 216 +#endif
 217  #ifdef CONFIG_CHAIN_OF_TRUST
 218  #include <fsl_validate.h>
 219  #endif
 220 @@ -46,14 +48,16 @@ static void erratum_a009008(void)
 221  static void erratum_a009798(void)
 222  {
 223  #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
 224 -#if defined(CONFIG_LS1043A)
 225 +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
 226         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
 227         u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
 228         scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
 229 +#if defined(CONFIG_LS1043A)
 230         val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
 231         scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
 232         val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
 233         scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
 234 +#endif
 235  #elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
 236         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
 237         u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
 238 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
 239 index f876c56..6ea4e8e 100644
 240 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
 241 +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
 242 @@ -14,8 +14,11 @@
 243  #else
 244  #define CONFIG_SYS_FSL_DDRC_ARM_GEN3   /* Enable Freescale ARM DDR3 driver */
 245  #endif
 246 +
 247 +#ifndef CONFIG_LS1012A
 248  #define CONFIG_SYS_FSL_DDR             /* Freescale DDR driver */
 249  #define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_5_0
 250 +#endif
 251
 252  /*
 253   * Reserve secure memory
 254 @@ -205,6 +208,35 @@
 255  #define CONFIG_SYS_FSL_ERRATUM_A008997
 256  #define CONFIG_SYS_FSL_ERRATUM_A009007
 257  #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 258 +#elif defined(CONFIG_LS1012A)
 259 +#define CONFIG_MAX_CPUS                         1
 260 +#define CONFIG_SYS_CACHELINE_SIZE              64
 261 +#define CONFIG_NUM_DDR_CONTROLLERS             1
 262 +#define CONFIG_SYS_CCSRBAR_DEFAULT             0x01000000
 263 +#define CONFIG_SYS_FSL_SEC_COMPAT              5
 264 +#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
 265 +
 266 +#define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */
 267 +#define CONFIG_SYS_FSL_OCRAM_SIZE              0x200000 /* 2 MiB */
 268 +
 269 +#define GICD_BASE              0x01401000
 270 +#define GICC_BASE              0x01402000
 271 +
 272 +#define CONFIG_SYS_FSL_CCSR_GUR_BE
 273 +#define CONFIG_SYS_FSL_CCSR_SCFG_BE
 274 +#define CONFIG_SYS_FSL_ESDHC_BE
 275 +#define CONFIG_SYS_FSL_WDOG_BE
 276 +#define CONFIG_SYS_FSL_DSPI_BE
 277 +#define CONFIG_SYS_FSL_QSPI_BE
 278 +#define CONFIG_SYS_FSL_PEX_LUT_BE
 279 +
 280 +#define SRDS_MAX_LANES         4
 281 +#define CONFIG_SYS_FSL_SRDS_1
 282 +#define CONFIG_SYS_FSL_PCIE_COMPAT             "fsl,qoriq-pcie-v2.4"
 283 +#define CONFIG_SYS_FSL_SEC_BE
 284 +
 285 +#define CONFIG_SYS_FSL_ERRATUM_A009798
 286 +
 287  #else
 288  #error SoC not defined
 289  #endif
 290 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
 291 index a7522da..e4ff990 100644
 292 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
 293 +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
 294 @@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = {
 295         CPU_TYPE_ENTRY(LS1043, LS1043, 4),
 296         CPU_TYPE_ENTRY(LS1023, LS1023, 2),
 297         CPU_TYPE_ENTRY(LS2040, LS2040, 4),
 298 +       CPU_TYPE_ENTRY(LS1012, LS1012, 1),
 299  };
 300
 301  #ifndef CONFIG_SYS_DCACHE_OFF
 302 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
 303 index 7096dac..4a3f4f3 100644
 304 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
 305 +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
 306 @@ -134,6 +134,7 @@ enum srds_prtcl {
 307         SGMII_2500_FM2_DTSEC6,
 308         SGMII_2500_FM2_DTSEC9,
 309         SGMII_2500_FM2_DTSEC10,
 310 +       TX_CLK,
 311         SERDES_PRCTL_COUNT
 312  };
 313
 314 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
 315 index 2852f9c..5b026f8 100644
 316 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
 317 +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
 318 @@ -62,7 +62,11 @@
 319  #define CONFIG_SYS_PCIE2_PHYS_ADDR             0x4800000000ULL
 320  #define CONFIG_SYS_PCIE3_PHYS_ADDR             0x5000000000ULL
 321  /* LUT registers */
 322 +#ifdef CONFIG_LS1012A
 323 +#define PCIE_LUT_BASE                          0xC0000
 324 +#else
 325  #define PCIE_LUT_BASE                          0x10000
 326 +#endif
 327  #define PCIE_LUT_LCTRL0                                0x7F8
 328  #define PCIE_LUT_DBG                           0x7FC
 329
 330 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
 331 index 56989e1..0822b49 100644
 332 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
 333 +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
 334 @@ -41,6 +41,7 @@ struct cpu_type {
 335         { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
 336
 337  #define SVR_WO_E               0xFFFFFE
 338 +#define SVR_LS1012             0x870400
 339  #define SVR_LS1043             0x879200
 340  #define SVR_LS1023             0x879208
 341  #define SVR_LS2045             0x870120
 342 diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
 343 new file mode 100644
 344 index 0000000..3df822e
 345 --- /dev/null
 346 +++ b/include/fsl_mmdc.h
 347 @@ -0,0 +1,53 @@
 348 +/*
 349 + * Copyright 2015 Freescale Semiconductor, Inc.
 350 + *
 351 + * SPDX-License-Identifier:    GPL-2.0+
 352 + */
 353 +
 354 +#ifndef FSL_MMDC_H
 355 +#define FSL_MMDC_H
 356 +
 357 +/* MMDC Registers */
 358 +struct mmdc_p_regs {
 359 +       u32 mdctl;
 360 +       u32 mdpdc;
 361 +       u32 mdotc;
 362 +       u32 mdcfg0;
 363 +       u32 mdcfg1;
 364 +       u32 mdcfg2;
 365 +       u32 mdmisc;
 366 +       u32 mdscr;
 367 +       u32 mdref;
 368 +       u32 res1[2];
 369 +       u32 mdrwd;
 370 +       u32 mdor;
 371 +       u32 mdmrr;
 372 +       u32 mdcfg3lp;
 373 +       u32 mdmr4;
 374 +       u32 mdasp;
 375 +       u32 res3[239];
 376 +       u32 maarcr;
 377 +       u32 mapsr;
 378 +       u32 res4[254];
 379 +       u32 mpzqhwctrl;
 380 +       u32 res5[2];
 381 +       u32 mpwldectrl0;
 382 +       u32 mpwldectrl1;
 383 +       u32 res6;
 384 +       u32 mpodtctrl;
 385 +       u32 mprddqby0dl;
 386 +       u32 mprddqby1dl;
 387 +       u32 mprddqby2dl;
 388 +       u32 mprddqby3dl;
 389 +       u32 res7[4];
 390 +       u32 mpdgctrl0;
 391 +       u32 mpdgctrl1;
 392 +       u32 res8;
 393 +       u32 mprddlctl;
 394 +       u32 res9;
 395 +       u32 mpwrdlctl;
 396 +       u32 res10[25];
 397 +       u32 mpmur0;
 398 +};
 399 +
 400 +#endif /* FSL_MMDC_H */
 401 diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
 402 index 4966608..72a5d5b 100644
 403 --- a/include/linux/usb/xhci-fsl.h
 404 +++ b/include/linux/usb/xhci-fsl.h
 405 @@ -66,6 +66,10 @@ struct fsl_xhci {
 406  #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
 407  #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
 408  #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
 409 +#elif defined(CONFIG_LS1012A)
 410 +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
 411 +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
 412 +#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
 413  #endif
 414
 415  #define FSL_USB_XHCI_ADDR      {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
 416 --
 417 1.7.9.5
 418