package/kernel/mac80211/patches/621-rt2x00-add-support-for-mt7620.patch

   1 From: Roman Yeryomin <roman@advem.lv>
   2 Date: Tue, 1 Jul 2014 10:26:18 +0000
   3 Subject: [PATCH] mac80211: rt2x00: add support for mt7620
   4
   5 Support for MT7620 was added to OpenWrt in r41441 and heavily reworked
   6 since in order to match the Kernel's code quality standards.
   7
   8 Signed-off-by: Roman Yeryomin <roman@advem.lv>
   9 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  10 ---
  11
  12 --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
  13 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
  14 @@ -81,6 +81,7 @@
  15  #define RF5372                         0x5372
  16  #define RF5390                         0x5390
  17  #define RF5392                         0x5392
  18 +#define RF7620                         0x7620
  19
  20  /*
  21   * Chipset revisions.
  22 @@ -641,6 +642,14 @@
  23  #define RF_CSR_CFG_BUSY                        FIELD32(0x00020000)
  24
  25  /*
  26 + * mt7620 RF registers (reversed order)
  27 + */
  28 +#define RF_CSR_CFG_DATA_MT7620         FIELD32(0x0000ff00)
  29 +#define RF_CSR_CFG_REGNUM_MT7620       FIELD32(0x03ff0000)
  30 +#define RF_CSR_CFG_WRITE_MT7620                FIELD32(0x00000010)
  31 +#define RF_CSR_CFG_BUSY_MT7620         FIELD32(0x00000001)
  32 +
  33 +/*
  34   * EFUSE_CSR: RT30x0 EEPROM
  35   */
  36  #define EFUSE_CTRL                     0x0580
  37 @@ -1024,6 +1033,11 @@
  38  #define AUTOWAKEUP_CFG_AUTOWAKE                FIELD32(0x00008000)
  39
  40  /*
  41 + * mt7620
  42 + */
  43 +#define MIMO_PS_CFG                    0x1210
  44 +
  45 +/*
  46   * EDCA_AC0_CFG:
  47   */
  48  #define EDCA_AC0_CFG                   0x1300
  49 @@ -1203,6 +1217,8 @@
  50  #define TX_PIN_CFG_RFTR_POL            FIELD32(0x00020000)
  51  #define TX_PIN_CFG_TRSW_EN             FIELD32(0x00040000)
  52  #define TX_PIN_CFG_TRSW_POL            FIELD32(0x00080000)
  53 +#define TX_PIN_CFG_RFRX_EN             FIELD32(0x00100000) /* mt7620 */
  54 +#define TX_PIN_CFG_RFRX_POL            FIELD32(0x00200000) /* mt7620 */
  55  #define TX_PIN_CFG_PA_PE_A2_EN         FIELD32(0x01000000)
  56  #define TX_PIN_CFG_PA_PE_G2_EN         FIELD32(0x02000000)
  57  #define TX_PIN_CFG_PA_PE_A2_POL                FIELD32(0x04000000)
  58 @@ -1549,6 +1565,17 @@
  59  #define TX_PWR_CFG_4_EXT_STBC4_CH2     FIELD32(0x0000000f)
  60  #define TX_PWR_CFG_4_EXT_STBC6_CH2     FIELD32(0x00000f00)
  61
  62 +/* mt7620 */
  63 +#define TX0_RF_GAIN_CORRECT            0x13a0
  64 +#define TX1_RF_GAIN_CORRECT            0x13a4
  65 +#define TX0_RF_GAIN_ATTEN              0x13a8
  66 +#define TX1_RF_GAIN_ATTEN              0x13ac
  67 +#define TX_ALG_CFG_0                   0x13b0
  68 +#define TX_ALG_CFG_1                   0x13b4
  69 +#define TX0_BB_GAIN_ATTEN              0x13c0
  70 +#define TX1_BB_GAIN_ATTEN              0x13c4
  71 +#define TX_ALC_VGA3                    0x13c8
  72 +
  73  /* TX_PWR_CFG_7 */
  74  #define TX_PWR_CFG_7                   0x13d4
  75  #define TX_PWR_CFG_7_OFDM54_CH0                FIELD32(0x0000000f)
  76 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  77 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  78 @@ -60,6 +60,9 @@
  79         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  80  #define WAIT_FOR_RFCSR(__dev, __reg) \
  81         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  82 +#define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
  83 +       rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
  84 +                           (__reg))
  85  #define WAIT_FOR_RF(__dev, __reg) \
  86         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  87  #define WAIT_FOR_MCU(__dev, __reg) \
  88 @@ -151,19 +154,56 @@ static void rt2800_rfcsr_write(struct rt
  89          * Wait until the RFCSR becomes available, afterwards we
  90          * can safely write the new data into the register.
  91          */
  92 -       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  93 -               reg = 0;
  94 -               rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
  95 -               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  96 -               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
  97 -               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  98 +       switch (rt2x00dev->chip.rf) {
  99 +       case RF7620:
 100 +               if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
 101 +                       reg = 0;
 102 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
 103 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
 104 +                                          word);
 105 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
 106 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
 107 +
 108 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 109 +               }
 110 +               break;
 111 +
 112 +       default:
 113 +               if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 114 +                       reg = 0;
 115 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 116 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 117 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 118 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 119
 120 -               rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 121 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 122 +               }
 123 +               break;
 124         }
 125
 126         mutex_unlock(&rt2x00dev->csr_mutex);
 127  }
 128
 129 +static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
 130 +                                   const unsigned int reg, const u8 value)
 131 +{
 132 +       rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
 133 +}
 134 +
 135 +static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
 136 +                                      const unsigned int reg, const u8 value)
 137 +{
 138 +       rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
 139 +       rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
 140 +}
 141 +
 142 +static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
 143 +                                    const unsigned int reg, const u8 value)
 144 +{
 145 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
 146 +       rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
 147 +}
 148 +
 149  static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 150                               const unsigned int word, u8 *value)
 151  {
 152 @@ -179,22 +219,48 @@ static void rt2800_rfcsr_read(struct rt2
 153          * doesn't become available in time, reg will be 0xffffffff
 154          * which means we return 0xff to the caller.
 155          */
 156 -       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 157 -               reg = 0;
 158 -               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159 -               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 160 -               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161 +       switch (rt2x00dev->chip.rf) {
 162 +       case RF7620:
 163 +               if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
 164 +                       reg = 0;
 165 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
 166 +                                          word);
 167 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
 168 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
 169
 170 -               rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 171 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 172
 173 -               WAIT_FOR_RFCSR(rt2x00dev, &reg);
 174 -       }
 175 +                       WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
 176 +               }
 177 +
 178 +               *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
 179 +               break;
 180 +
 181 +       default:
 182 +               if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 183 +                       reg = 0;
 184 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 185 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 186 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 187
 188 -       *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 189 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190 +
 191 +                       WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192 +               }
 193 +
 194 +               *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195 +               break;
 196 +       }
 197
 198         mutex_unlock(&rt2x00dev->csr_mutex);
 199  }
 200
 201 +static void rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
 202 +                                  const unsigned int reg, u8 *value)
 203 +{
 204 +       rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)), value);
 205 +}
 206 +
 207  static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 208                             const unsigned int word, const u32 value)
 209  {
 210 @@ -526,6 +592,16 @@ void rt2800_get_txwi_rxwi_size(struct rt
 211                 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
 212                 break;
 213
 214 +       case RT5390:
 215 +               if (rt2x00dev->chip.rf == RF7620) {
 216 +                       *txwi_size = TXWI_DESC_SIZE_5WORDS;
 217 +                       *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 218 +               } else {
 219 +                       *txwi_size = TXWI_DESC_SIZE_4WORDS;
 220 +                       *rxwi_size = RXWI_DESC_SIZE_4WORDS;
 221 +               }
 222 +               break;
 223 +
 224         case RT5592:
 225                 *txwi_size = TXWI_DESC_SIZE_5WORDS;
 226                 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 227 @@ -3258,6 +3334,296 @@ static void rt2800_config_channel_rf55xx
 228         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
 229  }
 230
 231 +static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
 232 +                                        struct ieee80211_conf *conf,
 233 +                                        struct rf_channel *rf,
 234 +                                        struct channel_info *info)
 235 +{
 236 +       struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 237 +       u32 mac_sys_ctrl, mac_status;
 238 +       u16 eeprom, target_power;
 239 +       u32 tx_pin = 0x00150F0F;
 240 +       u8 txrx_agc_fc;
 241 +       u8 rfcsr;
 242 +       u32 reg;
 243 +       u8 bbp;
 244 +       int i;
 245 +
 246 +       /* Frequeny plan setting */
 247 +       /* Rdiv setting (stored in rf->rf1)
 248 +        * R13[1:0]
 249 +        */
 250 +       rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
 251 +       rfcsr = rfcsr & (~0x03);
 252 +       if (rt2800_clk_is_20mhz(rt2x00dev))
 253 +               rfcsr |= (rf->rf1 & 0x03);
 254 +
 255 +       rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
 256 +
 257 +       /* N setting (stored in rf->rf2)
 258 +        * R21[0], R20[7:0]
 259 +        */
 260 +       rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
 261 +       rfcsr = (rf->rf2 & 0x00ff);
 262 +       rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
 263 +
 264 +       rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
 265 +       rfcsr = rfcsr & (~0x01);
 266 +       rfcsr |= ((rf->rf2 & 0x0100) >> 8);
 267 +       rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
 268 +
 269 +       /* K setting (stored in rf->rf3[0:7])
 270 +        * R16[3:0] (RF PLL freq selection)
 271 +        */
 272 +       rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
 273 +       rfcsr = rfcsr & (~0x0f);
 274 +       rfcsr |= (rf->rf3 & 0x0f);
 275 +       rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
 276 +
 277 +       /* D setting (stored in rf->rf3[8:15])
 278 +        * R22[2:0] (D=15, R22[2:0]=<111>)
 279 +        */
 280 +       rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
 281 +       rfcsr = rfcsr & (~0x07);
 282 +       rfcsr |= ((rf->rf3 >> 8) & 0x07);
 283 +       rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
 284 +
 285 +       /* Ksd setting (stored in rf->rf4)
 286 +        * Ksd: R19<1:0>,R18<7:0>,R17<7:0>
 287 +        */
 288 +       rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
 289 +       rfcsr = (rf->rf4 & 0x000000ff);
 290 +       rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
 291 +
 292 +       rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
 293 +       rfcsr = ((rf->rf4 & 0x0000ff00) >> 8);
 294 +       rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
 295 +
 296 +       rt2800_rfcsr_read(rt2x00dev, 19, &rfcsr);
 297 +       rfcsr = rfcsr & (~0x03);
 298 +       rfcsr |= ((rf->rf4 & 0x00030000) >> 16);
 299 +       rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
 300 +
 301 +       /* Default: XO=20MHz , SDM mode */
 302 +       rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
 303 +       rfcsr = rfcsr & (~0xE0);
 304 +       rfcsr |= 0x80;
 305 +       rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
 306 +
 307 +       rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
 308 +       rfcsr |= 0x80;
 309 +       rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
 310 +
 311 +       rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
 312 +       if (rt2x00dev->default_ant.tx_chain_num == 1)
 313 +               rfcsr &= (~0x2);
 314 +       else
 315 +               rfcsr |= 0x2;
 316 +       rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 317 +
 318 +       rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
 319 +       if (rt2x00dev->default_ant.tx_chain_num == 1)
 320 +               rfcsr &= (~0x20);
 321 +       else
 322 +               rfcsr |= 0x20;
 323 +       if (rt2x00dev->default_ant.rx_chain_num == 1)
 324 +               rfcsr &= (~0x02);
 325 +       else
 326 +               rfcsr |= 0x02;
 327 +       rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
 328 +
 329 +       rt2800_rfcsr_read(rt2x00dev, 42, &rfcsr);
 330 +       if (rt2x00dev->default_ant.tx_chain_num == 1)
 331 +               rfcsr &= (~0x40);
 332 +       else
 333 +               rfcsr |= 0x40;
 334 +       rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
 335 +
 336 +       /* RF for DC Cal BW */
 337 +       if (conf_is_ht40(conf)) {
 338 +               rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
 339 +               rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
 340 +               rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
 341 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
 342 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
 343 +       } else {
 344 +               rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
 345 +               rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
 346 +               rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
 347 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
 348 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
 349 +       }
 350 +
 351 +       if (conf_is_ht40(conf)) {
 352 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
 353 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
 354 +       } else {
 355 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
 356 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
 357 +       }
 358 +
 359 +       rt2800_rfcsr_read(rt2x00dev, 28, &rfcsr);
 360 +       if (conf_is_ht40(conf) && (rf->channel == 11))
 361 +               rfcsr |= 0x4;
 362 +       else
 363 +               rfcsr &= (~0x4);
 364 +       rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
 365 +
 366 +       /*if (bScan == FALSE)*/
 367 +       if (conf_is_ht40(conf)) {
 368 +               txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
 369 +                                               RFCSR24_TX_AGC_FC);
 370 +       } else {
 371 +               txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
 372 +                                               RFCSR24_TX_AGC_FC);
 373 +       }
 374 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rfcsr);
 375 +       rfcsr &= (~0x3F);
 376 +       rfcsr |= txrx_agc_fc;
 377 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
 378 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rfcsr);
 379 +       rfcsr &= (~0x3F);
 380 +       rfcsr |= txrx_agc_fc;
 381 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
 382 +       rt2800_rfcsr_read_bank(rt2x00dev, 7, 6, &rfcsr);
 383 +       rfcsr &= (~0x3F);
 384 +       rfcsr |= txrx_agc_fc;
 385 +       rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
 386 +       rt2800_rfcsr_read_bank(rt2x00dev, 7, 7, &rfcsr);
 387 +       rfcsr &= (~0x3F);
 388 +       rfcsr |= txrx_agc_fc;
 389 +       rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
 390 +
 391 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rfcsr);
 392 +       rfcsr &= (~0x3F);
 393 +       rfcsr |= txrx_agc_fc;
 394 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
 395 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rfcsr);
 396 +       rfcsr &= (~0x3F);
 397 +       rfcsr |= txrx_agc_fc;
 398 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
 399 +       rt2800_rfcsr_read_bank(rt2x00dev, 7, 58, &rfcsr);
 400 +       rfcsr &= (~0x3F);
 401 +       rfcsr |= txrx_agc_fc;
 402 +       rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
 403 +       rt2800_rfcsr_read_bank(rt2x00dev, 7, 59, &rfcsr);
 404 +       rfcsr &= (~0x3F);
 405 +       rfcsr |= txrx_agc_fc;
 406 +       rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
 407 +
 408 +       rt2800_register_read(rt2x00dev, TX_ALG_CFG_0, &reg);
 409 +       reg = reg & (~0x3F3F);
 410 +       reg |= info->default_power1;
 411 +       reg |= (info->default_power2 << 8);
 412 +       reg |= (0x2F << 16);
 413 +       reg |= (0x2F << 24);
 414 +
 415 +       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
 416 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
 417 +               /* init base power by e2p target power */
 418 +               rt2800_eeprom_read(rt2x00dev, 0xD0, &target_power);
 419 +               target_power &= 0x3F;
 420 +               reg = reg & (~0x3F3F);
 421 +               reg |= target_power;
 422 +               reg |= (target_power << 8);
 423 +       }
 424 +       rt2800_register_write(rt2x00dev, TX_ALG_CFG_0, reg);
 425 +
 426 +       rt2800_register_read(rt2x00dev, TX_ALG_CFG_1, &reg);
 427 +       reg = reg & (~0x3F);
 428 +       rt2800_register_write(rt2x00dev, TX_ALG_CFG_1, reg);
 429 +
 430 +       /*if (bScan == FALSE)*/
 431 +       /* Save MAC SYS CTRL registers */
 432 +       rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &mac_sys_ctrl);
 433 +       /* Disable Tx/Rx */
 434 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
 435 +       /* Check MAC Tx/Rx idle */
 436 +       for (i = 0; i < 10000; i++) {
 437 +               rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &mac_status);
 438 +               if (mac_status & 0x3)
 439 +                       usleep_range(50, 200);
 440 +               else
 441 +                       break;
 442 +       }
 443 +
 444 +       if (i == 10000)
 445 +               rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
 446 +
 447 +       if (rf->channel > 10) {
 448 +               rt2800_bbp_read(rt2x00dev, 30, &bbp);
 449 +               bbp = 0x40;
 450 +               rt2800_bbp_write(rt2x00dev, 30, bbp);
 451 +               rt2800_rfcsr_write(rt2x00dev, 39, 0);
 452 +               if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
 453 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
 454 +               else
 455 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
 456 +       } else {
 457 +               rt2800_bbp_read(rt2x00dev, 30, &bbp);
 458 +               bbp = 0x1f;
 459 +               rt2800_bbp_write(rt2x00dev, 30, bbp);
 460 +               rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
 461 +               if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
 462 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
 463 +               else
 464 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
 465 +       }
 466 +
 467 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
 468 +
 469 +       rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
 470 +       rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
 471 +
 472 +       /* vcocal_en (initiate VCO calibration (reset after completion)) */
 473 +       rt2800_rfcsr_read(rt2x00dev, 4, &rfcsr);
 474 +       rfcsr = ((rfcsr & ~0x80) | 0x80);
 475 +       rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
 476 +       usleep_range(2000, 3000);
 477 +
 478 +       rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 479 +
 480 +       if (rt2x00dev->default_ant.tx_chain_num == 1) {
 481 +               rt2800_bbp_write(rt2x00dev, 91, 0x07);
 482 +               rt2800_bbp_write(rt2x00dev, 95, 0x1A);
 483 +               rt2800_bbp_write(rt2x00dev, 195, 128);
 484 +               rt2800_bbp_write(rt2x00dev, 196, 0xA0);
 485 +               rt2800_bbp_write(rt2x00dev, 195, 170);
 486 +               rt2800_bbp_write(rt2x00dev, 196, 0x12);
 487 +               rt2800_bbp_write(rt2x00dev, 195, 171);
 488 +               rt2800_bbp_write(rt2x00dev, 196, 0x10);
 489 +       } else {
 490 +               rt2800_bbp_write(rt2x00dev, 91, 0x06);
 491 +               rt2800_bbp_write(rt2x00dev, 95, 0x9A);
 492 +               rt2800_bbp_write(rt2x00dev, 195, 128);
 493 +               rt2800_bbp_write(rt2x00dev, 196, 0xE0);
 494 +               rt2800_bbp_write(rt2x00dev, 195, 170);
 495 +               rt2800_bbp_write(rt2x00dev, 196, 0x30);
 496 +               rt2800_bbp_write(rt2x00dev, 195, 171);
 497 +               rt2800_bbp_write(rt2x00dev, 196, 0x30);
 498 +       }
 499 +
 500 +       if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 501 +               rt2800_bbp_write(rt2x00dev, 75, 0x60);
 502 +               rt2800_bbp_write(rt2x00dev, 76, 0x44);
 503 +               rt2800_bbp_write(rt2x00dev, 79, 0x1C);
 504 +               rt2800_bbp_write(rt2x00dev, 80, 0x0C);
 505 +               rt2800_bbp_write(rt2x00dev, 82, 0xB6);
 506 +
 507 +               if (!conf_is_ht40(conf)) {
 508 +                       rt2800_bbp_write(rt2x00dev, 195, 141);
 509 +                       rt2800_bbp_write(rt2x00dev, 196, 0x1A);
 510 +               }
 511 +       }
 512 +
 513 +       /* On 11A, We should delay and wait RF/BBP to be stable
 514 +        * and the appropriate time should be 1000 micro seconds
 515 +        * 2005/06/05 - On 11G, we also need this delay time.
 516 +        * Otherwise it's difficult to pass the WHQL.
 517 +        */
 518 +       usleep_range(1000, 1500);
 519 +}
 520 +
 521  static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
 522                                            const unsigned int word,
 523                                            const u8 value)
 524 @@ -3414,7 +3780,7 @@ static void rt2800_config_channel(struct
 525                                   struct channel_info *info)
 526  {
 527         u32 reg;
 528 -       unsigned int tx_pin;
 529 +       u32 tx_pin;
 530         u8 bbp, rfcsr;
 531
 532         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
 533 @@ -3468,6 +3834,9 @@ static void rt2800_config_channel(struct
 534         case RF5592:
 535                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
 536                 break;
 537 +       case RF7620:
 538 +               rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
 539 +               break;
 540         default:
 541                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
 542         }
 543 @@ -3574,7 +3943,7 @@ static void rt2800_config_channel(struct
 544                 else if (rt2x00_rt(rt2x00dev, RT3593) ||
 545                          rt2x00_rt(rt2x00dev, RT3883))
 546                         rt2800_bbp_write(rt2x00dev, 82, 0x82);
 547 -               else
 548 +               else if (rt2x00dev->chip.rf != RF7620)
 549                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 550
 551                 if (rt2x00_rt(rt2x00dev, RT3593) ||
 552 @@ -3596,7 +3965,7 @@ static void rt2800_config_channel(struct
 553         if (rt2x00_rt(rt2x00dev, RT3572))
 554                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
 555
 556 -       tx_pin = 0;
 557 +       rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
 558
 559         switch (rt2x00dev->default_ant.tx_chain_num) {
 560         case 3:
 561 @@ -3645,6 +4014,7 @@ static void rt2800_config_channel(struct
 562
 563         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 564         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 565 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */
 566
 567         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 568
 569 @@ -3720,7 +4090,8 @@ static void rt2800_config_channel(struct
 570                 usleep_range(1000, 1500);
 571         }
 572
 573 -       if (rt2x00_rt(rt2x00dev, RT5592)) {
 574 +       if (rt2x00_rt(rt2x00dev, RT5592) ||
 575 +           (rt2x00_rt(rt2x00dev, RT5390) && rt2x00_rf(rt2x00dev, RF7620))) {
 576                 rt2800_bbp_write(rt2x00dev, 195, 141);
 577                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
 578
 579 @@ -4662,6 +5033,15 @@ void rt2800_vco_calibration(struct rt2x0
 580                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
 581                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
 582                 break;
 583 +       case RF7620:
 584 +               rt2800_rfcsr_read(rt2x00dev, 4, &rfcsr);
 585 +               /* vcocal_en (initiate VCO calibration (reset after completion))
 586 +                * It should be at the end of RF configuration.
 587 +                */
 588 +               rfcsr = ((rfcsr & ~0x80) | 0x80);
 589 +               rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
 590 +               usleep_range(2000, 3000);
 591 +               break;
 592         default:
 593                 WARN_ONCE(1, "Not supported RF chipet %x for VCO recalibration",
 594                           rt2x00dev->chip.rf);
 595 @@ -5037,6 +5417,24 @@ static int rt2800_init_registers(struct
 596                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
 597                 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
 598                 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
 599 +       } else if (rt2x00_rf(rt2x00dev, RF7620)) {
 600 +               rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
 601 +               rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
 602 +               rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
 603 +               rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002);
 604 +               rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F);
 605 +               rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x06060606);
 606 +               rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
 607 +               rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
 608 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
 609 +               rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
 610 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
 611 +                                     0x3630363A);
 612 +               rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
 613 +                                     0x3630363A);
 614 +               rt2800_register_read(rt2x00dev, TX_ALG_CFG_1, &reg);
 615 +               reg = reg & (~0x80000000);
 616 +               rt2800_register_write(rt2x00dev, TX_ALG_CFG_1, reg);
 617         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
 618                    rt2x00_rt(rt2x00dev, RT5392)) {
 619                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
 620 @@ -6075,6 +6473,225 @@ static void rt2800_init_bbp_5592(struct
 621                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
 622  }
 623
 624 +static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
 625 +                                 const u8 reg, const u8 value)
 626 +{
 627 +       rt2800_bbp_write(rt2x00dev, 195, reg);
 628 +       rt2800_bbp_write(rt2x00dev, 196, value);
 629 +}
 630 +
 631 +static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
 632 +                                 const u8 reg, const u8 value)
 633 +{
 634 +       rt2800_bbp_write(rt2x00dev, 158, reg);
 635 +       rt2800_bbp_write(rt2x00dev, 159, value);
 636 +}
 637 +
 638 +static void rt2800_init_bbp_7620(struct rt2x00_dev *rt2x00dev)
 639 +{
 640 +       u8 bbp;
 641 +
 642 +       /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
 643 +       rt2800_bbp_read(rt2x00dev, 105, &bbp);
 644 +       rt2x00_set_field8(&bbp, BBP105_MLD,
 645 +                         rt2x00dev->default_ant.rx_chain_num == 2);
 646 +       rt2800_bbp_write(rt2x00dev, 105, bbp);
 647 +
 648 +       /* Avoid data loss and CRC errors */
 649 +       /* MAC interface control (MAC_IF_80M, 1: 80 MHz) */
 650 +       rt2800_bbp4_mac_if_ctrl(rt2x00dev);
 651 +
 652 +       /* Fix I/Q swap issue */
 653 +       rt2800_bbp_read(rt2x00dev, 1, &bbp);
 654 +       bbp |= 0x04;
 655 +       rt2800_bbp_write(rt2x00dev, 1, bbp);
 656 +
 657 +       /* BBP for G band */
 658 +       rt2800_bbp_write(rt2x00dev, 3, 0x08);
 659 +       rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
 660 +       rt2800_bbp_write(rt2x00dev, 6, 0x08);
 661 +       rt2800_bbp_write(rt2x00dev, 14, 0x09);
 662 +       rt2800_bbp_write(rt2x00dev, 15, 0xFF);
 663 +       rt2800_bbp_write(rt2x00dev, 16, 0x01);
 664 +       rt2800_bbp_write(rt2x00dev, 20, 0x06);
 665 +       rt2800_bbp_write(rt2x00dev, 21, 0x00);
 666 +       rt2800_bbp_write(rt2x00dev, 22, 0x00);
 667 +       rt2800_bbp_write(rt2x00dev, 27, 0x00);
 668 +       rt2800_bbp_write(rt2x00dev, 28, 0x00);
 669 +       rt2800_bbp_write(rt2x00dev, 30, 0x00);
 670 +       rt2800_bbp_write(rt2x00dev, 31, 0x48);
 671 +       rt2800_bbp_write(rt2x00dev, 47, 0x40);
 672 +       rt2800_bbp_write(rt2x00dev, 62, 0x00);
 673 +       rt2800_bbp_write(rt2x00dev, 63, 0x00);
 674 +       rt2800_bbp_write(rt2x00dev, 64, 0x00);
 675 +       rt2800_bbp_write(rt2x00dev, 65, 0x2C);
 676 +       rt2800_bbp_write(rt2x00dev, 66, 0x1C);
 677 +       rt2800_bbp_write(rt2x00dev, 67, 0x20);
 678 +       rt2800_bbp_write(rt2x00dev, 68, 0xDD);
 679 +       rt2800_bbp_write(rt2x00dev, 69, 0x10);
 680 +       rt2800_bbp_write(rt2x00dev, 70, 0x05);
 681 +       rt2800_bbp_write(rt2x00dev, 73, 0x18);
 682 +       rt2800_bbp_write(rt2x00dev, 74, 0x0F);
 683 +       rt2800_bbp_write(rt2x00dev, 75, 0x60);
 684 +       rt2800_bbp_write(rt2x00dev, 76, 0x44);
 685 +       rt2800_bbp_write(rt2x00dev, 77, 0x59);
 686 +       rt2800_bbp_write(rt2x00dev, 78, 0x1E);
 687 +       rt2800_bbp_write(rt2x00dev, 79, 0x1C);
 688 +       rt2800_bbp_write(rt2x00dev, 80, 0x0C);
 689 +       rt2800_bbp_write(rt2x00dev, 81, 0x3A);
 690 +       rt2800_bbp_write(rt2x00dev, 82, 0xB6);
 691 +       rt2800_bbp_write(rt2x00dev, 83, 0x9A);
 692 +       rt2800_bbp_write(rt2x00dev, 84, 0x9A);
 693 +       rt2800_bbp_write(rt2x00dev, 86, 0x38);
 694 +       rt2800_bbp_write(rt2x00dev, 88, 0x90);
 695 +       rt2800_bbp_write(rt2x00dev, 91, 0x04);
 696 +       rt2800_bbp_write(rt2x00dev, 92, 0x02);
 697 +       rt2800_bbp_write(rt2x00dev, 95, 0x9A);
 698 +       rt2800_bbp_write(rt2x00dev, 96, 0x00);
 699 +       rt2800_bbp_write(rt2x00dev, 103, 0xC0);
 700 +       rt2800_bbp_write(rt2x00dev, 104, 0x92);
 701 +       /* FIXME BBP105 owerwrite */
 702 +       rt2800_bbp_write(rt2x00dev, 105, 0x3C);
 703 +       rt2800_bbp_write(rt2x00dev, 106, 0x12);
 704 +       rt2800_bbp_write(rt2x00dev, 109, 0x00);
 705 +       rt2800_bbp_write(rt2x00dev, 134, 0x10);
 706 +       rt2800_bbp_write(rt2x00dev, 135, 0xA6);
 707 +       rt2800_bbp_write(rt2x00dev, 137, 0x04);
 708 +       rt2800_bbp_write(rt2x00dev, 142, 0x30);
 709 +       rt2800_bbp_write(rt2x00dev, 143, 0xF7);
 710 +       rt2800_bbp_write(rt2x00dev, 160, 0xEC);
 711 +       rt2800_bbp_write(rt2x00dev, 161, 0xC4);
 712 +       rt2800_bbp_write(rt2x00dev, 162, 0x77);
 713 +       rt2800_bbp_write(rt2x00dev, 163, 0xF9);
 714 +       rt2800_bbp_write(rt2x00dev, 164, 0x00);
 715 +       rt2800_bbp_write(rt2x00dev, 165, 0x00);
 716 +       rt2800_bbp_write(rt2x00dev, 186, 0x00);
 717 +       rt2800_bbp_write(rt2x00dev, 187, 0x00);
 718 +       rt2800_bbp_write(rt2x00dev, 188, 0x00);
 719 +       rt2800_bbp_write(rt2x00dev, 186, 0x00);
 720 +       rt2800_bbp_write(rt2x00dev, 187, 0x01);
 721 +       rt2800_bbp_write(rt2x00dev, 188, 0x00);
 722 +       rt2800_bbp_write(rt2x00dev, 189, 0x00);
 723 +
 724 +       rt2800_bbp_write(rt2x00dev, 91, 0x06);
 725 +       rt2800_bbp_write(rt2x00dev, 92, 0x04);
 726 +       rt2800_bbp_write(rt2x00dev, 93, 0x54);
 727 +       rt2800_bbp_write(rt2x00dev, 99, 0x50);
 728 +       rt2800_bbp_write(rt2x00dev, 148, 0x84);
 729 +       rt2800_bbp_write(rt2x00dev, 167, 0x80);
 730 +       rt2800_bbp_write(rt2x00dev, 178, 0xFF);
 731 +       rt2800_bbp_write(rt2x00dev, 106, 0x13);
 732 +
 733 +       /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
 734 +       rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
 735 +       rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); /* ? see above */
 736 +       rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
 737 +       rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
 738 +       rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
 739 +       rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
 740 +       rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
 741 +       rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
 742 +       rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
 743 +       rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
 744 +       rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
 745 +       rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
 746 +       rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
 747 +       rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
 748 +       rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
 749 +       rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
 750 +       rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
 751 +       rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
 752 +       rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
 753 +       rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
 754 +       rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
 755 +       rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
 756 +       rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
 757 +       rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
 758 +       rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
 759 +       rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
 760 +       rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
 761 +       rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
 762 +       rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
 763 +       rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
 764 +       rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
 765 +       rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
 766 +       rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
 767 +       rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
 768 +       rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
 769 +       rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
 770 +       rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
 771 +       rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
 772 +       rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
 773 +       rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
 774 +       rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
 775 +       rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
 776 +       rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
 777 +       rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
 778 +       rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
 779 +       rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
 780 +       rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
 781 +       rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
 782 +       rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
 783 +       rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
 784 +       rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
 785 +       rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
 786 +       rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
 787 +       rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
 788 +       rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
 789 +       rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
 790 +       rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
 791 +       rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
 792 +       rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
 793 +       rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
 794 +       rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
 795 +       rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
 796 +       rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
 797 +       rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
 798 +       rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
 799 +       rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
 800 +       rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
 801 +       rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
 802 +       rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
 803 +       rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
 804 +       rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
 805 +       rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
 806 +       rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
 807 +       rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
 808 +       rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
 809 +       rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
 810 +       rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
 811 +       rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
 812 +       rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
 813 +       rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
 814 +       rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
 815 +       rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
 816 +       rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
 817 +
 818 +       /* BBP for G band DCOC function */
 819 +       rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
 820 +       rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
 821 +       rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
 822 +       rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
 823 +       rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
 824 +       rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
 825 +       rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
 826 +       rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
 827 +       rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
 828 +       rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
 829 +       rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
 830 +       rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
 831 +       rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
 832 +       rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
 833 +       rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
 834 +       rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
 835 +       rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
 836 +       rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
 837 +       rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
 838 +       rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
 839 +
 840 +       rt2800_bbp4_mac_if_ctrl(rt2x00dev);
 841 +}
 842 +
 843  static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
 844  {
 845         unsigned int i;
 846 @@ -6117,7 +6734,10 @@ static void rt2800_init_bbp(struct rt2x0
 847                 return;
 848         case RT5390:
 849         case RT5392:
 850 -               rt2800_init_bbp_53xx(rt2x00dev);
 851 +               if (rt2x00dev->chip.rf == RF7620)
 852 +                       rt2800_init_bbp_7620(rt2x00dev);
 853 +               else
 854 +                       rt2800_init_bbp_53xx(rt2x00dev);
 855                 break;
 856         case RT5592:
 857                 rt2800_init_bbp_5592(rt2x00dev);
 858 @@ -7331,6 +7951,277 @@ static void rt2800_init_rfcsr_5592(struc
 859         rt2800_led_open_drain_enable(rt2x00dev);
 860  }
 861
 862 +static void rt2800_init_rfcsr_7620(struct rt2x00_dev *rt2x00dev)
 863 +{
 864 +       u8 rfvalue;
 865 +       u16 freq;
 866 +
 867 +       /* Initialize RF central register to default value */
 868 +       rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
 869 +       rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
 870 +       rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
 871 +       rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
 872 +       rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
 873 +       rt2800_rfcsr_write(rt2x00dev, 5, 0x40); /* Read only */
 874 +       rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
 875 +       rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
 876 +       rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
 877 +       rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
 878 +       rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
 879 +       rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
 880 +       /* rt2800_rfcsr_write(rt2x00dev, 12, 0x43); *//* EEPROM */
 881 +       rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
 882 +       rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
 883 +       rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
 884 +       rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
 885 +       rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
 886 +       rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
 887 +       rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
 888 +       rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
 889 +       rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
 890 +       rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
 891 +       rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
 892 +       rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
 893 +       rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
 894 +       rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
 895 +       rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
 896 +       rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
 897 +       rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
 898 +       rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
 899 +       rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
 900 +       rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
 901 +       rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
 902 +       rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
 903 +       rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
 904 +       rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
 905 +       rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
 906 +       rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
 907 +       rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
 908 +       rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
 909 +       rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
 910 +       rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
 911 +       rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
 912 +
 913 +       rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
 914 +       if (rt2800_clk_is_20mhz(rt2x00dev))
 915 +               rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
 916 +       else
 917 +               rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
 918 +       rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
 919 +       rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
 920 +       rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
 921 +       rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
 922 +       rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
 923 +       rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
 924 +       rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
 925 +       rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
 926 +       rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
 927 +       rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
 928 +       rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
 929 +       rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
 930 +       rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
 931 +       rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
 932 +       rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
 933 +       rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
 934 +
 935 +       rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
 936 +       rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
 937 +       rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
 938 +
 939 +       /* use rt2800_adjust_freq_offset ? */
 940 +       rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &freq);
 941 +       rfvalue = freq & 0xff;
 942 +       rt2800_rfcsr_write(rt2x00dev, 12, rfvalue);
 943 +
 944 +       /* Initialize RF channel register to default value */
 945 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
 946 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
 947 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
 948 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
 949 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
 950 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
 951 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
 952 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
 953 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
 954 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
 955 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
 956 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
 957 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
 958 +       /* rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); */ /* fails */
 959 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
 960 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
 961 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
 962 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
 963 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
 964 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
 965 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
 966 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
 967 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
 968 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
 969 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
 970 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
 971 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
 972 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
 973 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
 974 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
 975 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
 976 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
 977 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
 978 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
 979 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
 980 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
 981 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
 982 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
 983 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
 984 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
 985 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
 986 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
 987 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
 988 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
 989 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
 990 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
 991 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
 992 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
 993 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
 994 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
 995 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
 996 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
 997 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
 998 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
 999 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
1000 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
1001 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
1002 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
1003 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
1004 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
1005 +
1006 +       rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
1007 +
1008 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
1009 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
1010 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
1011 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
1012 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
1013 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
1014 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
1015 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
1016 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
1017 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
1018 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
1019 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
1020 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
1021 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
1022 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
1023 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
1024 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
1025 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
1026 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x69);
1027 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
1028 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x20);
1029 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
1030 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
1031 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
1032 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
1033 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
1034 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
1035 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
1036 +
1037 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
1038 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
1039 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
1040 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
1041 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
1042 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
1043 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
1044 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
1045 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
1046 +
1047 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
1048 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
1049 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
1050 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
1051 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
1052 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
1053 +
1054 +       /* Initialize RF channel register for DRQFN */
1055 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
1056 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
1057 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
1058 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
1059 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
1060 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
1061 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
1062 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
1063 +
1064 +       /* Initialize RF DC calibration register to default value */
1065 +       rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
1066 +       rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
1067 +       rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
1068 +       rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
1069 +       rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
1070 +       rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
1071 +       rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
1072 +       rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
1073 +       rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
1074 +       rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
1075 +       rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
1076 +       rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
1077 +       rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
1078 +       rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
1079 +       rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
1080 +       rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
1081 +       rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
1082 +       rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
1083 +       rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
1084 +       rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
1085 +       rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
1086 +       rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
1087 +       rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
1088 +       rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
1089 +       rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
1090 +       rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
1091 +       rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
1092 +       rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
1093 +       rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
1094 +       rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
1095 +       rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
1096 +       rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
1097 +       rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
1098 +       rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
1099 +       rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
1100 +       rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
1101 +       rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
1102 +       rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
1103 +       rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
1104 +       rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
1105 +       rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
1106 +       rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
1107 +       rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
1108 +       rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
1109 +       rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
1110 +       rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
1111 +       rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
1112 +       rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
1113 +       rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
1114 +       rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
1115 +       rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
1116 +       rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
1117 +       rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
1118 +       rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
1119 +       rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
1120 +       rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
1121 +       rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
1122 +       rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
1123 +       rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
1124 +
1125 +       rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
1126 +       rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
1127 +       rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
1128 +
1129 +       rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
1130 +       rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
1131 +}
1132 +
1133  static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1134  {
1135         if (rt2800_is_305x_soc(rt2x00dev)) {
1136 @@ -7366,7 +8257,10 @@ static void rt2800_init_rfcsr(struct rt2
1137                 rt2800_init_rfcsr_5350(rt2x00dev);
1138                 break;
1139         case RT5390:
1140 -               rt2800_init_rfcsr_5390(rt2x00dev);
1141 +               if (rt2x00dev->chip.rf == RF7620)
1142 +                       rt2800_init_rfcsr_7620(rt2x00dev);
1143 +               else
1144 +                       rt2800_init_rfcsr_5390(rt2x00dev);
1145                 break;
1146         case RT5392:
1147                 rt2800_init_rfcsr_5392(rt2x00dev);
1148 @@ -7780,6 +8674,7 @@ static int rt2800_init_eeprom(struct rt2
1149         case RF5390:
1150         case RF5392:
1151         case RF5592:
1152 +       case RF7620:
1153                 break;
1154         default:
1155                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
1156 @@ -8258,6 +9153,24 @@ static const struct rf_channel rf_vals_5
1157         {196, 83, 0, 12, 1},
1158  };
1159
1160 +static const struct rf_channel rf_vals_7620[] = {
1161 +       /* Channel, Rdiv, N, K | (D >> 8), Ksd */
1162 +       {1, 3, 0x50, 0 | (0 >> 8), 0x19999},
1163 +       {2, 3, 0x50, 0 | (0 >> 8), 0x24444},
1164 +       {3, 3, 0x50, 0 | (0 >> 8), 0x2EEEE},
1165 +       {4, 3, 0x50, 0 | (0 >> 8), 0x39999},
1166 +       {5, 3, 0x51, 0 | (0 >> 8), 0x04444},
1167 +       {6, 3, 0x51, 0 | (0 >> 8), 0x0EEEE},
1168 +       {7, 3, 0x51, 0 | (0 >> 8), 0x19999},
1169 +       {8, 3, 0x51, 0 | (0 >> 8), 0x24444},
1170 +       {9, 3, 0x51, 0 | (0 >> 8), 0x2EEEE},
1171 +       {10, 3, 0x51, 0 | (0 >> 8), 0x39999},
1172 +       {11, 3, 0x52, 0 | (0 >> 8), 0x04444},
1173 +       {12, 3, 0x52, 0 | (0 >> 8), 0x0EEEE},
1174 +       {13, 3, 0x52, 0 | (0 >> 8), 0x19999},
1175 +       {14, 3, 0x52, 0 | (0 >> 8), 0x33333},
1176 +};
1177 +
1178  static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1179  {
1180         struct hw_mode_spec *spec = &rt2x00dev->spec;
1181 @@ -8361,6 +9274,11 @@ static int rt2800_probe_hw_mode(struct r
1182                         spec->channels = rf_vals_3x;
1183                 break;
1184
1185 +       case RF7620:
1186 +               spec->num_channels = ARRAY_SIZE(rf_vals_7620);
1187 +               spec->channels = rf_vals_7620;
1188 +               break;
1189 +
1190         case RF3052:
1191         case RF3053:
1192                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
1193 @@ -8498,6 +9416,7 @@ static int rt2800_probe_hw_mode(struct r
1194         case RF5390:
1195         case RF5392:
1196         case RF5592:
1197 +       case RF7620:
1198                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
1199                 break;
1200         }