package/kernel/mac80211/patches/621-rt2x00-add-support-for-mt7620.patch

   1 From: Roman Yeryomin <roman@advem.lv>
   2 Date: Tue, 1 Jul 2014 10:26:18 +0000
   3 Subject: [PATCH] mac80211: rt2x00: add support for mt7620
   4
   5 Support for MT7620 was added to OpenWrt in r41441 and heavily reworked
   6 since in order to match the Kernel's code quality standards.
   7
   8 Signed-off-by: Roman Yeryomin <roman@advem.lv>
   9 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  10 ---
  11
  12 --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
  13 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
  14 @@ -81,6 +81,7 @@
  15  #define RF5372                         0x5372
  16  #define RF5390                         0x5390
  17  #define RF5392                         0x5392
  18 +#define RF7620                         0x7620
  19
  20  /*
  21   * Chipset revisions.
  22 @@ -641,6 +642,14 @@
  23  #define RF_CSR_CFG_BUSY                        FIELD32(0x00020000)
  24
  25  /*
  26 + * MT7620 RF registers (reversed order)
  27 + */
  28 +#define RF_CSR_CFG_DATA_MT7620         FIELD32(0x0000ff00)
  29 +#define RF_CSR_CFG_REGNUM_MT7620       FIELD32(0x03ff0000)
  30 +#define RF_CSR_CFG_WRITE_MT7620                FIELD32(0x00000010)
  31 +#define RF_CSR_CFG_BUSY_MT7620         FIELD32(0x00000001)
  32 +
  33 +/*
  34   * EFUSE_CSR: RT30x0 EEPROM
  35   */
  36  #define EFUSE_CTRL                     0x0580
  37 @@ -1024,6 +1033,16 @@
  38  #define AUTOWAKEUP_CFG_AUTOWAKE                FIELD32(0x00008000)
  39
  40  /*
  41 + * MIMO_PS_CFG: MIMO Power-save Configuration
  42 + */
  43 +#define MIMO_PS_CFG                    0x1210
  44 +#define MIMO_PS_CFG_MMPS_BB_EN         FIELD32(0x00000001)
  45 +#define MIMO_PS_CFG_MMPS_RX_ANT_NUM    FIELD32(0x00000006)
  46 +#define MIMO_PS_CFG_MMPS_RF_EN         FIELD32(0x00000008)
  47 +#define MIMO_PS_CFG_RX_STBY_POL                FIELD32(0x00000010)
  48 +#define MIMO_PS_CFG_RX_RX_STBY0                FIELD32(0x00000020)
  49 +
  50 +/*
  51   * EDCA_AC0_CFG:
  52   */
  53  #define EDCA_AC0_CFG                   0x1300
  54 @@ -1097,6 +1116,12 @@
  55  #define TX_PWR_CFG_0_OFDM6_CH1         FIELD32(0x00f00000)
  56  #define TX_PWR_CFG_0_OFDM12_CH0                FIELD32(0x0f000000)
  57  #define TX_PWR_CFG_0_OFDM12_CH1                FIELD32(0xf0000000)
  58 +/* bits for new 2T devices */
  59 +#define TX_PWR_CFG_0B_1MBS_2MBS                FIELD32(0x000000ff)
  60 +#define TX_PWR_CFG_0B_5MBS_11MBS               FIELD32(0x0000ff00)
  61 +#define TX_PWR_CFG_0B_6MBS_9MBS                FIELD32(0x00ff0000)
  62 +#define TX_PWR_CFG_0B_12MBS_18MBS      FIELD32(0xff000000)
  63 +
  64
  65  /*
  66   * TX_PWR_CFG_1:
  67 @@ -1119,6 +1144,11 @@
  68  #define TX_PWR_CFG_1_MCS0_CH1          FIELD32(0x00f00000)
  69  #define TX_PWR_CFG_1_MCS2_CH0          FIELD32(0x0f000000)
  70  #define TX_PWR_CFG_1_MCS2_CH1          FIELD32(0xf0000000)
  71 +/* bits for new 2T devices */
  72 +#define TX_PWR_CFG_1B_24MBS_36MBS      FIELD32(0x000000ff)
  73 +#define TX_PWR_CFG_1B_48MBS            FIELD32(0x0000ff00)
  74 +#define TX_PWR_CFG_1B_MCS0_MCS1                FIELD32(0x00ff0000)
  75 +#define TX_PWR_CFG_1B_MCS2_MCS3                FIELD32(0xff000000)
  76
  77  /*
  78   * TX_PWR_CFG_2:
  79 @@ -1141,6 +1171,11 @@
  80  #define TX_PWR_CFG_2_MCS8_CH1          FIELD32(0x00f00000)
  81  #define TX_PWR_CFG_2_MCS10_CH0         FIELD32(0x0f000000)
  82  #define TX_PWR_CFG_2_MCS10_CH1         FIELD32(0xf0000000)
  83 +/* bits for new 2T devices */
  84 +#define TX_PWR_CFG_2B_MCS4_MCS5                FIELD32(0x000000ff)
  85 +#define TX_PWR_CFG_2B_MCS6_MCS7                FIELD32(0x0000ff00)
  86 +#define TX_PWR_CFG_2B_MCS8_MCS9                FIELD32(0x00ff0000)
  87 +#define TX_PWR_CFG_2B_MCS10_MCS11      FIELD32(0xff000000)
  88
  89  /*
  90   * TX_PWR_CFG_3:
  91 @@ -1163,6 +1198,11 @@
  92  #define TX_PWR_CFG_3_STBC0_CH1         FIELD32(0x00f00000)
  93  #define TX_PWR_CFG_3_STBC2_CH0         FIELD32(0x0f000000)
  94  #define TX_PWR_CFG_3_STBC2_CH1         FIELD32(0xf0000000)
  95 +/* bits for new 2T devices */
  96 +#define TX_PWR_CFG_3B_MCS12_MCS13      FIELD32(0x000000ff)
  97 +#define TX_PWR_CFG_3B_MCS14            FIELD32(0x0000ff00)
  98 +#define TX_PWR_CFG_3B_STBC_MCS0_MCS1   FIELD32(0x00ff0000)
  99 +#define TX_PWR_CFG_3B_STBC_MCS2_MSC3   FIELD32(0xff000000)
 100
 101  /*
 102   * TX_PWR_CFG_4:
 103 @@ -1177,6 +1217,10 @@
 104  #define TX_PWR_CFG_3_STBC4_CH1         FIELD32(0x000000f0)
 105  #define TX_PWR_CFG_3_STBC6_CH0         FIELD32(0x00000f00)
 106  #define TX_PWR_CFG_3_STBC6_CH1         FIELD32(0x0000f000)
 107 +/* bits for new 2T devices */
 108 +#define TX_PWR_CFG_4B_STBC_MCS4_MCS5   FIELD32(0x000000ff)
 109 +#define TX_PWR_CFG_4B_STBC_MCS6                FIELD32(0x0000ff00)
 110 +
 111
 112  /*
 113   * TX_PIN_CFG:
 114 @@ -1203,6 +1247,8 @@
 115  #define TX_PIN_CFG_RFTR_POL            FIELD32(0x00020000)
 116  #define TX_PIN_CFG_TRSW_EN             FIELD32(0x00040000)
 117  #define TX_PIN_CFG_TRSW_POL            FIELD32(0x00080000)
 118 +#define TX_PIN_CFG_RFRX_EN             FIELD32(0x00100000)
 119 +#define TX_PIN_CFG_RFRX_POL            FIELD32(0x00200000)
 120  #define TX_PIN_CFG_PA_PE_A2_EN         FIELD32(0x01000000)
 121  #define TX_PIN_CFG_PA_PE_G2_EN         FIELD32(0x02000000)
 122  #define TX_PIN_CFG_PA_PE_A2_POL                FIELD32(0x04000000)
 123 @@ -1549,6 +1595,95 @@
 124  #define TX_PWR_CFG_4_EXT_STBC4_CH2     FIELD32(0x0000000f)
 125  #define TX_PWR_CFG_4_EXT_STBC6_CH2     FIELD32(0x00000f00)
 126
 127 +/* TXn_RF_GAIN_CORRECT: RF Gain Correction for each RF_ALC[3:2]
 128 + * Unit: 0.1 dB, Range: -3.2 dB to 3.1 dB
 129 + */
 130 +#define TX0_RF_GAIN_CORRECT            0x13a0
 131 +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_0        FIELD32(0x0000003f)
 132 +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_1        FIELD32(0x00003f00)
 133 +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_2        FIELD32(0x003f0000)
 134 +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_3        FIELD32(0x3f000000)
 135 +
 136 +#define TX1_RF_GAIN_CORRECT            0x13a4
 137 +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_0        FIELD32(0x0000003f)
 138 +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_1        FIELD32(0x00003f00)
 139 +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_2        FIELD32(0x003f0000)
 140 +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_3        FIELD32(0x3f000000)
 141 +
 142 +/* TXn_RF_GAIN_ATTEN: TXn RF Gain Attenuation Level
 143 + * Format: 7-bit, signed value
 144 + * Unit: 0.5 dB, Range: -20 dB to -5 dB
 145 + */
 146 +#define TX0_RF_GAIN_ATTEN              0x13a8
 147 +#define TX0_RF_GAIN_ATTEN_LEVEL_0      FIELD32(0x0000007f)
 148 +#define TX0_RF_GAIN_ATTEN_LEVEL_1      FIELD32(0x00007f00)
 149 +#define TX0_RF_GAIN_ATTEN_LEVEL_2      FIELD32(0x007f0000)
 150 +#define TX0_RF_GAIN_ATTEN_LEVEL_3      FIELD32(0x7f000000)
 151 +#define TX1_RF_GAIN_ATTEN              0x13ac
 152 +#define TX1_RF_GAIN_ATTEN_LEVEL_0      FIELD32(0x0000007f)
 153 +#define TX1_RF_GAIN_ATTEN_LEVEL_1      FIELD32(0x00007f00)
 154 +#define TX1_RF_GAIN_ATTEN_LEVEL_2      FIELD32(0x007f0000)
 155 +#define TX1_RF_GAIN_ATTEN_LEVEL_3      FIELD32(0x7f000000)
 156 +
 157 +/* TX_ALC_CFG_0: TX Automatic Level Control Configuration 0
 158 + * TX_ALC_LIMIT_n: TXn upper limit
 159 + * TX_ALC_CH_INIT_n: TXn channel initial transmission gain
 160 + * Unit: 0.5 dB, Range: 0 to 23.5 dB
 161 + */
 162 +#define TX_ALC_CFG_0                   0x13b0
 163 +#define TX_ALC_CFG_0_CH_INIT_0         FIELD32(0x0000003f)
 164 +#define TX_ALC_CFG_0_CH_INIT_1         FIELD32(0x00003f00)
 165 +#define TX_ALC_CFG_0_LIMIT_0           FIELD32(0x003f0000)
 166 +#define TX_ALC_CFG_0_LIMIT_1           FIELD32(0x3f000000)
 167 +
 168 +/* TX_ALC_CFG_1: TX Automatic Level Control Configuration 1
 169 + * TX_TEMP_COMP:      TX Power Temperature Compensation
 170 + *                    Unit: 0.5 dB, Range: -10 dB to 10 dB
 171 + * TXn_GAIN_FINE:     TXn Gain Fine Adjustment
 172 + *                    Unit: 0.1 dB, Range: -0.8 dB to 0.7 dB
 173 + * RF_TOS_DLY:        Sets the RF_TOS_EN assertion delay after
 174 + *                    deassertion of PA_PE.
 175 + *                    Unit: 0.25 usec
 176 + * TXn_RF_GAIN_ATTEN: TXn RF gain attentuation selector
 177 + * RF_TOS_TIMEOUT:    time-out value for RF_TOS_ENABLE
 178 + *                    deassertion if RF_TOS_DONE is missing.
 179 + *                    Unit: 0.25 usec
 180 + * RF_TOS_ENABLE:     TX offset calibration enable
 181 + * ROS_BUSY_EN:       RX offset calibration busy enable
 182 + */
 183 +#define TX_ALC_CFG_1                   0x13b4
 184 +#define TX_ALC_CFG_1_TX_TEMP_COMP      FIELD32(0x0000003f)
 185 +#define TX_ALC_CFG_1_TX0_GAIN_FINE     FIELD32(0x00000f00)
 186 +#define TX_ALC_CFG_1_TX1_GAIN_FINE     FIELD32(0x0000f000)
 187 +#define TX_ALC_CFG_1_RF_TOS_DLY                FIELD32(0x00070000)
 188 +#define TX_ALC_CFG_1_TX0_RF_GAIN_ATTEN FIELD32(0x00300000)
 189 +#define TX_ALC_CFG_1_TX1_RF_GAIN_ATTEN FIELD32(0x00c00000)
 190 +#define TX_ALC_CFG_1_RF_TOS_TIMEOUT    FIELD32(0x3f000000)
 191 +#define TX_ALC_CFG_1_RF_TOS_ENABLE     FIELD32(0x40000000)
 192 +#define TX_ALC_CFG_1_ROS_BUSY_EN       FIELD32(0x80000000)
 193 +
 194 +/* TXn_BB_GAIN_ATTEN: TXn RF Gain Attenuation Level
 195 + * Format: 5-bit signed values
 196 + * Unit: 0.5 dB, Range: -8 dB to 7 dB
 197 + */
 198 +#define TX0_BB_GAIN_ATTEN              0x13c0
 199 +#define TX0_BB_GAIN_ATTEN_LEVEL_0      FIELD32(0x0000001f)
 200 +#define TX0_BB_GAIN_ATTEN_LEVEL_1      FIELD32(0x00001f00)
 201 +#define TX0_BB_GAIN_ATTEN_LEVEL_2      FIELD32(0x001f0000)
 202 +#define TX0_BB_GAIN_ATTEN_LEVEL_3      FIELD32(0x1f000000)
 203 +#define TX1_BB_GAIN_ATTEN              0x13c4
 204 +#define TX1_BB_GAIN_ATTEN_LEVEL_0      FIELD32(0x0000001f)
 205 +#define TX1_BB_GAIN_ATTEN_LEVEL_1      FIELD32(0x00001f00)
 206 +#define TX1_BB_GAIN_ATTEN_LEVEL_2      FIELD32(0x001f0000)
 207 +#define TX1_BB_GAIN_ATTEN_LEVEL_3      FIELD32(0x1f000000)
 208 +
 209 +/* TX_ALC_VGA3: TX Automatic Level Correction Variable Gain Amplifier 3 */
 210 +#define TX_ALC_VGA3                    0x13c8
 211 +#define TX_ALC_VGA3_TX0_ALC_VGA3       FIELD32(0x0000001f)
 212 +#define TX_ALC_VGA3_TX1_ALC_VGA3       FIELD32(0x00001f00)
 213 +#define TX_ALC_VGA3_TX0_ALC_VGA2       FIELD32(0x001f0000)
 214 +#define TX_ALC_VGA3_TX1_ALC_VGA2       FIELD32(0x1f000000)
 215 +
 216  /* TX_PWR_CFG_7 */
 217  #define TX_PWR_CFG_7                   0x13d4
 218  #define TX_PWR_CFG_7_OFDM54_CH0                FIELD32(0x0000000f)
 219 @@ -1557,6 +1692,10 @@
 220  #define TX_PWR_CFG_7_MCS7_CH0          FIELD32(0x000f0000)
 221  #define TX_PWR_CFG_7_MCS7_CH1          FIELD32(0x00f00000)
 222  #define TX_PWR_CFG_7_MCS7_CH2          FIELD32(0x0f000000)
 223 +/* bits for new 2T devices */
 224 +#define TX_PWR_CFG_7B_54MBS            FIELD32(0x000000ff)
 225 +#define TX_PWR_CFG_7B_MCS7             FIELD32(0x00ff0000)
 226 +
 227
 228  /* TX_PWR_CFG_8 */
 229  #define TX_PWR_CFG_8                   0x13d8
 230 @@ -1566,12 +1705,17 @@
 231  #define TX_PWR_CFG_8_MCS23_CH0         FIELD32(0x000f0000)
 232  #define TX_PWR_CFG_8_MCS23_CH1         FIELD32(0x00f00000)
 233  #define TX_PWR_CFG_8_MCS23_CH2         FIELD32(0x0f000000)
 234 +/* bits for new 2T devices */
 235 +#define TX_PWR_CFG_8B_MCS15            FIELD32(0x000000ff)
 236 +
 237
 238  /* TX_PWR_CFG_9 */
 239  #define TX_PWR_CFG_9                   0x13dc
 240  #define TX_PWR_CFG_9_STBC7_CH0         FIELD32(0x0000000f)
 241  #define TX_PWR_CFG_9_STBC7_CH1         FIELD32(0x000000f0)
 242  #define TX_PWR_CFG_9_STBC7_CH2         FIELD32(0x00000f00)
 243 +/* bits for new 2T devices */
 244 +#define TX_PWR_CFG_9B_STBC_MCS7                FIELD32(0x000000ff)
 245
 246  /*
 247   * TX_TXBF_CFG:
 248 @@ -2175,6 +2319,12 @@ struct mac_iveiv_entry {
 249  #define RFCSR3_BIT5                    FIELD8(0x20)
 250
 251  /*
 252 + * RFCSR 4:
 253 + * VCOCAL_EN used by MT7620
 254 + */
 255 +#define RFCSR4_VCOCAL_EN               FIELD8(0x80)
 256 +
 257 +/*
 258   * FRCSR 5:
 259   */
 260  #define RFCSR5_R1                      FIELD8(0x0c)
 261 @@ -2450,6 +2600,7 @@ enum rt2800_eeprom_word {
 262         EEPROM_TSSI_BOUND_BG5,
 263         EEPROM_TXPOWER_A1,
 264         EEPROM_TXPOWER_A2,
 265 +       EEPROM_TXPOWER_INIT,
 266         EEPROM_TSSI_BOUND_A1,
 267         EEPROM_TSSI_BOUND_A2,
 268         EEPROM_TSSI_BOUND_A3,
 269 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
 270 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
 271 @@ -60,6 +60,9 @@
 272         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
 273  #define WAIT_FOR_RFCSR(__dev, __reg) \
 274         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
 275 +#define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
 276 +       rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
 277 +                           (__reg))
 278  #define WAIT_FOR_RF(__dev, __reg) \
 279         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
 280  #define WAIT_FOR_MCU(__dev, __reg) \
 281 @@ -151,19 +154,56 @@ static void rt2800_rfcsr_write(struct rt
 282          * Wait until the RFCSR becomes available, afterwards we
 283          * can safely write the new data into the register.
 284          */
 285 -       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 286 -               reg = 0;
 287 -               rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 288 -               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 289 -               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 290 -               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 291 +       switch (rt2x00dev->chip.rf) {
 292 +       case RF7620:
 293 +               if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
 294 +                       reg = 0;
 295 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
 296 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
 297 +                                          word);
 298 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
 299 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
 300 +
 301 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 302 +               }
 303 +               break;
 304 +
 305 +       default:
 306 +               if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 307 +                       reg = 0;
 308 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 309 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 310 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 311 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 312
 313 -               rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 314 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 315 +               }
 316 +               break;
 317         }
 318
 319         mutex_unlock(&rt2x00dev->csr_mutex);
 320  }
 321
 322 +static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
 323 +                                   const unsigned int reg, const u8 value)
 324 +{
 325 +       rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
 326 +}
 327 +
 328 +static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
 329 +                                      const unsigned int reg, const u8 value)
 330 +{
 331 +       rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
 332 +       rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
 333 +}
 334 +
 335 +static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
 336 +                                    const unsigned int reg, const u8 value)
 337 +{
 338 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
 339 +       rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
 340 +}
 341 +
 342  static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 343                               const unsigned int word, u8 *value)
 344  {
 345 @@ -179,22 +219,48 @@ static void rt2800_rfcsr_read(struct rt2
 346          * doesn't become available in time, reg will be 0xffffffff
 347          * which means we return 0xff to the caller.
 348          */
 349 -       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 350 -               reg = 0;
 351 -               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 352 -               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 353 -               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 354 +       switch (rt2x00dev->chip.rf) {
 355 +       case RF7620:
 356 +               if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
 357 +                       reg = 0;
 358 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
 359 +                                          word);
 360 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
 361 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
 362
 363 -               rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 364 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 365
 366 -               WAIT_FOR_RFCSR(rt2x00dev, &reg);
 367 -       }
 368 +                       WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
 369 +               }
 370
 371 -       *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 372 +               *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
 373 +               break;
 374 +
 375 +       default:
 376 +               if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 377 +                       reg = 0;
 378 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 379 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 380 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 381 +
 382 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 383 +
 384 +                       WAIT_FOR_RFCSR(rt2x00dev, &reg);
 385 +               }
 386 +
 387 +               *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 388 +               break;
 389 +       }
 390
 391         mutex_unlock(&rt2x00dev->csr_mutex);
 392  }
 393
 394 +static void rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
 395 +                                  const unsigned int reg, u8 *value)
 396 +{
 397 +       rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)), value);
 398 +}
 399 +
 400  static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 401                             const unsigned int word, const u32 value)
 402  {
 403 @@ -251,6 +317,7 @@ static const unsigned int rt2800_eeprom_
 404         [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
 405         [EEPROM_TXPOWER_A1]             = 0x003c,
 406         [EEPROM_TXPOWER_A2]             = 0x0053,
 407 +       [EEPROM_TXPOWER_INIT]           = 0x0068,
 408         [EEPROM_TSSI_BOUND_A1]          = 0x006a,
 409         [EEPROM_TSSI_BOUND_A2]          = 0x006b,
 410         [EEPROM_TSSI_BOUND_A3]          = 0x006c,
 411 @@ -526,6 +593,16 @@ void rt2800_get_txwi_rxwi_size(struct rt
 412                 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
 413                 break;
 414
 415 +       case RT5390:
 416 +               if (rt2x00dev->chip.rf == RF7620) {
 417 +                       *txwi_size = TXWI_DESC_SIZE_5WORDS;
 418 +                       *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 419 +               } else {
 420 +                       *txwi_size = TXWI_DESC_SIZE_4WORDS;
 421 +                       *rxwi_size = RXWI_DESC_SIZE_4WORDS;
 422 +               }
 423 +               break;
 424 +
 425         case RT5592:
 426                 *txwi_size = TXWI_DESC_SIZE_5WORDS;
 427                 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 428 @@ -3258,6 +3335,258 @@ static void rt2800_config_channel_rf55xx
 429         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
 430  }
 431
 432 +static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
 433 +                                        struct ieee80211_conf *conf,
 434 +                                        struct rf_channel *rf,
 435 +                                        struct channel_info *info)
 436 +{
 437 +       struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 438 +       u8 txrx_agc_fc;
 439 +       u8 rfcsr;
 440 +
 441 +       /* Frequeny plan setting */
 442 +       /* Rdiv setting (stored in rf->rf1)
 443 +        * R13[1:0]
 444 +        */
 445 +       rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
 446 +       rfcsr = rfcsr & (~0x03);
 447 +       if (rt2800_clk_is_20mhz(rt2x00dev))
 448 +               rfcsr |= (rf->rf1 & 0x03);
 449 +
 450 +       rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
 451 +
 452 +       /* N setting (stored in rf->rf2)
 453 +        * R21[0], R20[7:0]
 454 +        */
 455 +       rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
 456 +       rfcsr = (rf->rf2 & 0x00ff);
 457 +       rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
 458 +
 459 +       rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
 460 +       rfcsr = rfcsr & (~0x01);
 461 +       rfcsr |= ((rf->rf2 & 0x0100) >> 8);
 462 +       rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
 463 +
 464 +       /* K setting (stored in rf->rf3[0:7])
 465 +        * R16[3:0] (RF PLL freq selection)
 466 +        */
 467 +       rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
 468 +       rfcsr = rfcsr & (~0x0f);
 469 +       rfcsr |= (rf->rf3 & 0x0f);
 470 +       rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
 471 +
 472 +       /* D setting (stored in rf->rf3[8:15])
 473 +        * R22[2:0] (D=15, R22[2:0]=<111>)
 474 +        */
 475 +       rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
 476 +       rfcsr = rfcsr & (~0x07);
 477 +       rfcsr |= ((rf->rf3 >> 8) & 0x07);
 478 +       rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
 479 +
 480 +       /* Ksd setting (stored in rf->rf4)
 481 +        * Ksd: R19<1:0>,R18<7:0>,R17<7:0>
 482 +        */
 483 +       rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
 484 +       rfcsr = (rf->rf4 & 0x000000ff);
 485 +       rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
 486 +
 487 +       rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
 488 +       rfcsr = ((rf->rf4 & 0x0000ff00) >> 8);
 489 +       rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
 490 +
 491 +       rt2800_rfcsr_read(rt2x00dev, 19, &rfcsr);
 492 +       rfcsr = rfcsr & (~0x03);
 493 +       rfcsr |= ((rf->rf4 & 0x00030000) >> 16);
 494 +       rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
 495 +
 496 +       /* Default: XO=20MHz , SDM mode */
 497 +       rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
 498 +       rfcsr = rfcsr & (~0xE0);
 499 +       rfcsr |= 0x80;
 500 +       rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
 501 +
 502 +       rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
 503 +       rfcsr |= 0x80;
 504 +       rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
 505 +
 506 +       rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
 507 +       if (rt2x00dev->default_ant.tx_chain_num == 1)
 508 +               rfcsr &= (~0x2);
 509 +       else
 510 +               rfcsr |= 0x2;
 511 +       rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 512 +
 513 +       rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
 514 +       if (rt2x00dev->default_ant.tx_chain_num == 1)
 515 +               rfcsr &= (~0x20);
 516 +       else
 517 +               rfcsr |= 0x20;
 518 +       if (rt2x00dev->default_ant.rx_chain_num == 1)
 519 +               rfcsr &= (~0x02);
 520 +       else
 521 +               rfcsr |= 0x02;
 522 +       rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
 523 +
 524 +       rt2800_rfcsr_read(rt2x00dev, 42, &rfcsr);
 525 +       if (rt2x00dev->default_ant.tx_chain_num == 1)
 526 +               rfcsr &= (~0x40);
 527 +       else
 528 +               rfcsr |= 0x40;
 529 +       rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
 530 +
 531 +       /* RF for DC Cal BW */
 532 +       if (conf_is_ht40(conf)) {
 533 +               rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
 534 +               rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
 535 +               rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
 536 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
 537 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
 538 +       } else {
 539 +               rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
 540 +               rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
 541 +               rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
 542 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
 543 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
 544 +       }
 545 +
 546 +       if (conf_is_ht40(conf)) {
 547 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
 548 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
 549 +       } else {
 550 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
 551 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
 552 +       }
 553 +
 554 +       rt2800_rfcsr_read(rt2x00dev, 28, &rfcsr);
 555 +       if (conf_is_ht40(conf) && (rf->channel == 11))
 556 +               rfcsr |= 0x4;
 557 +       else
 558 +               rfcsr &= (~0x4);
 559 +       rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
 560 +
 561 +       if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
 562 +               if (conf_is_ht40(conf)) {
 563 +                       txrx_agc_fc = rt2x00_get_field8(
 564 +                                               drv_data->calibration_bw40,
 565 +                                               RFCSR24_TX_AGC_FC);
 566 +               } else {
 567 +                       txrx_agc_fc = rt2x00_get_field8(
 568 +                                               drv_data->calibration_bw20,
 569 +                                               RFCSR24_TX_AGC_FC);
 570 +               }
 571 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rfcsr);
 572 +               rfcsr &= (~0x3F);
 573 +               rfcsr |= txrx_agc_fc;
 574 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
 575 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rfcsr);
 576 +               rfcsr &= (~0x3F);
 577 +               rfcsr |= txrx_agc_fc;
 578 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
 579 +               rt2800_rfcsr_read_bank(rt2x00dev, 7, 6, &rfcsr);
 580 +               rfcsr &= (~0x3F);
 581 +               rfcsr |= txrx_agc_fc;
 582 +               rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
 583 +               rt2800_rfcsr_read_bank(rt2x00dev, 7, 7, &rfcsr);
 584 +               rfcsr &= (~0x3F);
 585 +               rfcsr |= txrx_agc_fc;
 586 +               rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
 587 +
 588 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rfcsr);
 589 +               rfcsr &= (~0x3F);
 590 +               rfcsr |= txrx_agc_fc;
 591 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
 592 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rfcsr);
 593 +               rfcsr &= (~0x3F);
 594 +               rfcsr |= txrx_agc_fc;
 595 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
 596 +               rt2800_rfcsr_read_bank(rt2x00dev, 7, 58, &rfcsr);
 597 +               rfcsr &= (~0x3F);
 598 +               rfcsr |= txrx_agc_fc;
 599 +               rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
 600 +               rt2800_rfcsr_read_bank(rt2x00dev, 7, 59, &rfcsr);
 601 +               rfcsr &= (~0x3F);
 602 +               rfcsr |= txrx_agc_fc;
 603 +               rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
 604 +       }
 605 +}
 606 +
 607 +static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
 608 +                             struct ieee80211_channel *chan,
 609 +                             int power_level) {
 610 +       u16 eeprom, target_power, max_power;
 611 +       u32 mac_sys_ctrl, mac_status;
 612 +       u32 reg;
 613 +       u8 bbp;
 614 +       int i;
 615 +
 616 +       /* hardware unit is 0.5dBm, limited to 23.5dBm */
 617 +       power_level *= 2;
 618 +       if (power_level > 0x2f)
 619 +               power_level = 0x2f;
 620 +
 621 +       max_power = chan->max_power * 2;
 622 +       if (max_power > 0x2f)
 623 +               max_power = 0x2f;
 624 +
 625 +       rt2800_register_read(rt2x00dev, TX_ALC_CFG_0, &reg);
 626 +       rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
 627 +       rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
 628 +       rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
 629 +       rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
 630 +
 631 +       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
 632 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
 633 +               /* init base power by eeprom target power */
 634 +               rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_INIT,
 635 +                                  &target_power);
 636 +               rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
 637 +               rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
 638 +       }
 639 +       rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
 640 +
 641 +       rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, &reg);
 642 +       rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
 643 +       rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
 644 +
 645 +       /* Save MAC SYS CTRL registers */
 646 +       rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &mac_sys_ctrl);
 647 +       /* Disable Tx/Rx */
 648 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
 649 +       /* Check MAC Tx/Rx idle */
 650 +       for (i = 0; i < 10000; i++) {
 651 +               rt2800_register_read(rt2x00dev, MAC_STATUS_CFG,
 652 +                                    &mac_status);
 653 +               if (mac_status & 0x3)
 654 +                       usleep_range(50, 200);
 655 +               else
 656 +                       break;
 657 +       }
 658 +
 659 +       if (i == 10000)
 660 +               rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
 661 +
 662 +       if (chan->center_freq > 2457) {
 663 +               rt2800_bbp_read(rt2x00dev, 30, &bbp);
 664 +               bbp = 0x40;
 665 +               rt2800_bbp_write(rt2x00dev, 30, bbp);
 666 +               rt2800_rfcsr_write(rt2x00dev, 39, 0);
 667 +               if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
 668 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
 669 +               else
 670 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
 671 +       } else {
 672 +               rt2800_bbp_read(rt2x00dev, 30, &bbp);
 673 +               bbp = 0x1f;
 674 +               rt2800_bbp_write(rt2x00dev, 30, bbp);
 675 +               rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
 676 +               if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
 677 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
 678 +               else
 679 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
 680 +       }
 681 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
 682 +}
 683 +
 684  static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
 685                                            const unsigned int word,
 686                                            const u8 value)
 687 @@ -3414,7 +3743,7 @@ static void rt2800_config_channel(struct
 688                                   struct channel_info *info)
 689  {
 690         u32 reg;
 691 -       unsigned int tx_pin;
 692 +       u32 tx_pin;
 693         u8 bbp, rfcsr;
 694
 695         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
 696 @@ -3468,6 +3797,9 @@ static void rt2800_config_channel(struct
 697         case RF5592:
 698                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
 699                 break;
 700 +       case RF7620:
 701 +               rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
 702 +               break;
 703         default:
 704                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
 705         }
 706 @@ -3574,7 +3906,7 @@ static void rt2800_config_channel(struct
 707                 else if (rt2x00_rt(rt2x00dev, RT3593) ||
 708                          rt2x00_rt(rt2x00dev, RT3883))
 709                         rt2800_bbp_write(rt2x00dev, 82, 0x82);
 710 -               else
 711 +               else if (rt2x00dev->chip.rf != RF7620)
 712                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 713
 714                 if (rt2x00_rt(rt2x00dev, RT3593) ||
 715 @@ -3596,7 +3928,7 @@ static void rt2800_config_channel(struct
 716         if (rt2x00_rt(rt2x00dev, RT3572))
 717                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
 718
 719 -       tx_pin = 0;
 720 +       rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
 721
 722         switch (rt2x00dev->default_ant.tx_chain_num) {
 723         case 3:
 724 @@ -3645,6 +3977,7 @@ static void rt2800_config_channel(struct
 725
 726         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 727         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 728 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */
 729
 730         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 731
 732 @@ -3720,7 +4053,8 @@ static void rt2800_config_channel(struct
 733                 usleep_range(1000, 1500);
 734         }
 735
 736 -       if (rt2x00_rt(rt2x00dev, RT5592)) {
 737 +       if (rt2x00_rt(rt2x00dev, RT5592) ||
 738 +           (rt2x00_rt(rt2x00dev, RT5390) && rt2x00_rf(rt2x00dev, RF7620))) {
 739                 rt2800_bbp_write(rt2x00dev, 195, 141);
 740                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
 741
 742 @@ -4410,6 +4744,128 @@ static void rt2800_config_txpower_rt3593
 743                            (unsigned long) regs[i]);
 744  }
 745
 746 +static void rt2800_config_txpower_mt7620(struct rt2x00_dev *rt2x00dev,
 747 +                                        struct ieee80211_channel *chan,
 748 +                                        int power_level)
 749 +{
 750 +       u32 reg, pwreg;
 751 +       u16 eeprom;
 752 +       u32 data, gdata;
 753 +       u8 t, i;
 754 +       enum nl80211_band band = chan->band;
 755 +       int delta;
 756 +
 757 +       /* Warn user if bw_comp is set in EEPROM */
 758 +       delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
 759 +
 760 +       if (delta)
 761 +               rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
 762 +                           delta);
 763 +
 764 +       /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT40, limit
 765 +        * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
 766 +        * driver does as well, though it looks kinda wrong.
 767 +        * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
 768 +        * the hardware has a problem handling 0x20, and as the code initially
 769 +        * used a fixed offset between HT20 and HT40 rates they had to work-
 770 +        * around that issue and most likely just forgot about it later on.
 771 +        * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
 772 +        * however, the corresponding EEPROM value is not respected by the
 773 +        * vendor driver, so maybe this is rather being taken care of the
 774 +        * TXALC and the driver doesn't need to handle it...?
 775 +        * Though this is all very awkward, just do as they did, as that's what
 776 +        * board vendors expected when they populated the EEPROM...
 777 +        */
 778 +       for (i = 0; i < 5; i++) {
 779 +               rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
 780 +                                             i * 2, &eeprom);
 781 +
 782 +               data = eeprom;
 783 +
 784 +               t = eeprom & 0x3f;
 785 +               if (t == 32)
 786 +                       t++;
 787 +
 788 +               gdata = t;
 789 +
 790 +               t = (eeprom & 0x3f00) >> 8;
 791 +               if (t == 32)
 792 +                       t++;
 793 +
 794 +               gdata |= (t << 8);
 795 +
 796 +               rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
 797 +                                             (i * 2) + 1, &eeprom);
 798 +
 799 +               t = eeprom & 0x3f;
 800 +               if (t == 32)
 801 +                       t++;
 802 +
 803 +               gdata |= (t << 16);
 804 +
 805 +               t = (eeprom & 0x3f00) >> 8;
 806 +               if (t == 32)
 807 +                       t++;
 808 +
 809 +               gdata |= (t << 24);
 810 +               data |= (eeprom << 16);
 811 +
 812 +               if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
 813 +                       /* HT20 */
 814 +                       if (data != 0xffffffff)
 815 +                               rt2800_register_write(rt2x00dev,
 816 +                                                     TX_PWR_CFG_0 + (i * 4),
 817 +                                                     data);
 818 +               } else {
 819 +                       /* HT40 */
 820 +                       if (gdata != 0xffffffff)
 821 +                               rt2800_register_write(rt2x00dev,
 822 +                                                     TX_PWR_CFG_0 + (i * 4),
 823 +                                                     gdata);
 824 +               }
 825 +       }
 826 +
 827 +       /* Aparently Ralink ran out of space in the BYRATE calibration section
 828 +        * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
 829 +        * registers. As recent 2T chips use 8-bit instead of 4-bit values for
 830 +        * power-offsets more space would be needed. Ralink decided to rather
 831 +        * keep the EEPROM layout untouched and rather have some shared values
 832 +        * covering multiple bitrates.
 833 +        * Populate the registers not covered by the EEPROM in the same way the
 834 +        * vendor driver does.
 835 +        */
 836 +
 837 +       /* For OFDM 54MBS use value from OFDM 48MBS */
 838 +       pwreg = 0;
 839 +       rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 840 +       t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
 841 +       rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
 842 +
 843 +       /* For MCS 7 use value from MCS 6 */
 844 +       rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 845 +       t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
 846 +       rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
 847 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
 848 +
 849 +       /* For MCS 15 use value from MCS 14 */
 850 +       pwreg = 0;
 851 +       rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 852 +       t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
 853 +       rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
 854 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
 855 +
 856 +       /* For STBC MCS 7 use value from STBC MCS 6 */
 857 +       pwreg = 0;
 858 +       rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 859 +       t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
 860 +       rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
 861 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
 862 +
 863 +       rt2800_config_alc(rt2x00dev, chan, power_level);
 864 +
 865 +       /* TODO: temperature compensation code! */
 866 +}
 867 +
 868  /*
 869   * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
 870   * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
 871 @@ -4607,6 +5063,8 @@ static void rt2800_config_txpower(struct
 872         if (rt2x00_rt(rt2x00dev, RT3593) ||
 873             rt2x00_rt(rt2x00dev, RT3883))
 874                 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
 875 +       else if (rt2x00_rf(rt2x00dev, RF7620))
 876 +               rt2800_config_txpower_mt7620(rt2x00dev, chan, power_level);
 877         else
 878                 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
 879  }
 880 @@ -4622,6 +5080,7 @@ void rt2800_vco_calibration(struct rt2x0
 881  {
 882         u32     tx_pin;
 883         u8      rfcsr;
 884 +       unsigned long min_sleep = 0;
 885
 886         /*
 887          * A voltage-controlled oscillator(VCO) is an electronic oscillator
 888 @@ -4661,6 +5120,15 @@ void rt2800_vco_calibration(struct rt2x0
 889                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
 890                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
 891                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
 892 +               min_sleep = 1000;
 893 +               break;
 894 +       case RF7620:
 895 +               rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
 896 +               rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
 897 +               rt2800_rfcsr_read(rt2x00dev, 4, &rfcsr);
 898 +               rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
 899 +               rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
 900 +               min_sleep = 2000;
 901                 break;
 902         default:
 903                 WARN_ONCE(1, "Not supported RF chipet %x for VCO recalibration",
 904 @@ -4668,7 +5136,8 @@ void rt2800_vco_calibration(struct rt2x0
 905                 return;
 906         }
 907
 908 -       usleep_range(1000, 1500);
 909 +       if (min_sleep > 0)
 910 +               usleep_range(min_sleep, min_sleep * 2);
 911
 912         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
 913         if (rt2x00dev->rf_channel <= 14) {
 914 @@ -4700,6 +5169,42 @@ void rt2800_vco_calibration(struct rt2x0
 915         }
 916         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 917
 918 +       if (rt2x00_rf(rt2x00dev, RF7620)) {
 919 +               if (rt2x00dev->default_ant.tx_chain_num == 1) {
 920 +                       rt2800_bbp_write(rt2x00dev, 91, 0x07);
 921 +                       rt2800_bbp_write(rt2x00dev, 95, 0x1A);
 922 +                       rt2800_bbp_write(rt2x00dev, 195, 128);
 923 +                       rt2800_bbp_write(rt2x00dev, 196, 0xA0);
 924 +                       rt2800_bbp_write(rt2x00dev, 195, 170);
 925 +                       rt2800_bbp_write(rt2x00dev, 196, 0x12);
 926 +                       rt2800_bbp_write(rt2x00dev, 195, 171);
 927 +                       rt2800_bbp_write(rt2x00dev, 196, 0x10);
 928 +               } else {
 929 +                       rt2800_bbp_write(rt2x00dev, 91, 0x06);
 930 +                       rt2800_bbp_write(rt2x00dev, 95, 0x9A);
 931 +                       rt2800_bbp_write(rt2x00dev, 195, 128);
 932 +                       rt2800_bbp_write(rt2x00dev, 196, 0xE0);
 933 +                       rt2800_bbp_write(rt2x00dev, 195, 170);
 934 +                       rt2800_bbp_write(rt2x00dev, 196, 0x30);
 935 +                       rt2800_bbp_write(rt2x00dev, 195, 171);
 936 +                       rt2800_bbp_write(rt2x00dev, 196, 0x30);
 937 +               }
 938 +
 939 +               if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 940 +                       rt2800_bbp_write(rt2x00dev, 75, 0x60);
 941 +                       rt2800_bbp_write(rt2x00dev, 76, 0x44);
 942 +                       rt2800_bbp_write(rt2x00dev, 79, 0x1C);
 943 +                       rt2800_bbp_write(rt2x00dev, 80, 0x0C);
 944 +                       rt2800_bbp_write(rt2x00dev, 82, 0xB6);
 945 +               }
 946 +
 947 +               /* On 11A, We should delay and wait RF/BBP to be stable
 948 +                * and the appropriate time should be 1000 micro seconds
 949 +                * 2005/06/05 - On 11G, we also need this delay time.
 950 +                * Otherwise it's difficult to pass the WHQL.
 951 +                */
 952 +               usleep_range(1000, 1500);
 953 +       }
 954  }
 955  EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
 956
 957 @@ -5037,6 +5542,24 @@ static int rt2800_init_registers(struct
 958                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
 959                 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
 960                 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
 961 +       } else if (rt2x00_rf(rt2x00dev, RF7620)) {
 962 +               rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
 963 +               rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
 964 +               rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
 965 +               rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002);
 966 +               rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F);
 967 +               rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x06060606);
 968 +               rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
 969 +               rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
 970 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
 971 +               rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
 972 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
 973 +                                     0x3630363A);
 974 +               rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
 975 +                                     0x3630363A);
 976 +               rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, &reg);
 977 +               rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
 978 +               rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
 979         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
 980                    rt2x00_rt(rt2x00dev, RT5392)) {
 981                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
 982 @@ -6075,6 +6598,224 @@ static void rt2800_init_bbp_5592(struct
 983                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
 984  }
 985
 986 +static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
 987 +                                 const u8 reg, const u8 value)
 988 +{
 989 +       rt2800_bbp_write(rt2x00dev, 195, reg);
 990 +       rt2800_bbp_write(rt2x00dev, 196, value);
 991 +}
 992 +
 993 +static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
 994 +                                 const u8 reg, const u8 value)
 995 +{
 996 +       rt2800_bbp_write(rt2x00dev, 158, reg);
 997 +       rt2800_bbp_write(rt2x00dev, 159, value);
 998 +}
 999 +
1000 +static void rt2800_init_bbp_7620(struct rt2x00_dev *rt2x00dev)
1001 +{
1002 +       u8 bbp;
1003 +
1004 +       /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
1005 +       rt2800_bbp_read(rt2x00dev, 105, &bbp);
1006 +       rt2x00_set_field8(&bbp, BBP105_MLD,
1007 +                         rt2x00dev->default_ant.rx_chain_num == 2);
1008 +       rt2800_bbp_write(rt2x00dev, 105, bbp);
1009 +
1010 +       /* Avoid data loss and CRC errors */
1011 +       rt2800_bbp4_mac_if_ctrl(rt2x00dev);
1012 +
1013 +       /* Fix I/Q swap issue */
1014 +       rt2800_bbp_read(rt2x00dev, 1, &bbp);
1015 +       bbp |= 0x04;
1016 +       rt2800_bbp_write(rt2x00dev, 1, bbp);
1017 +
1018 +       /* BBP for G band */
1019 +       rt2800_bbp_write(rt2x00dev, 3, 0x08);
1020 +       rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
1021 +       rt2800_bbp_write(rt2x00dev, 6, 0x08);
1022 +       rt2800_bbp_write(rt2x00dev, 14, 0x09);
1023 +       rt2800_bbp_write(rt2x00dev, 15, 0xFF);
1024 +       rt2800_bbp_write(rt2x00dev, 16, 0x01);
1025 +       rt2800_bbp_write(rt2x00dev, 20, 0x06);
1026 +       rt2800_bbp_write(rt2x00dev, 21, 0x00);
1027 +       rt2800_bbp_write(rt2x00dev, 22, 0x00);
1028 +       rt2800_bbp_write(rt2x00dev, 27, 0x00);
1029 +       rt2800_bbp_write(rt2x00dev, 28, 0x00);
1030 +       rt2800_bbp_write(rt2x00dev, 30, 0x00);
1031 +       rt2800_bbp_write(rt2x00dev, 31, 0x48);
1032 +       rt2800_bbp_write(rt2x00dev, 47, 0x40);
1033 +       rt2800_bbp_write(rt2x00dev, 62, 0x00);
1034 +       rt2800_bbp_write(rt2x00dev, 63, 0x00);
1035 +       rt2800_bbp_write(rt2x00dev, 64, 0x00);
1036 +       rt2800_bbp_write(rt2x00dev, 65, 0x2C);
1037 +       rt2800_bbp_write(rt2x00dev, 66, 0x1C);
1038 +       rt2800_bbp_write(rt2x00dev, 67, 0x20);
1039 +       rt2800_bbp_write(rt2x00dev, 68, 0xDD);
1040 +       rt2800_bbp_write(rt2x00dev, 69, 0x10);
1041 +       rt2800_bbp_write(rt2x00dev, 70, 0x05);
1042 +       rt2800_bbp_write(rt2x00dev, 73, 0x18);
1043 +       rt2800_bbp_write(rt2x00dev, 74, 0x0F);
1044 +       rt2800_bbp_write(rt2x00dev, 75, 0x60);
1045 +       rt2800_bbp_write(rt2x00dev, 76, 0x44);
1046 +       rt2800_bbp_write(rt2x00dev, 77, 0x59);
1047 +       rt2800_bbp_write(rt2x00dev, 78, 0x1E);
1048 +       rt2800_bbp_write(rt2x00dev, 79, 0x1C);
1049 +       rt2800_bbp_write(rt2x00dev, 80, 0x0C);
1050 +       rt2800_bbp_write(rt2x00dev, 81, 0x3A);
1051 +       rt2800_bbp_write(rt2x00dev, 82, 0xB6);
1052 +       rt2800_bbp_write(rt2x00dev, 83, 0x9A);
1053 +       rt2800_bbp_write(rt2x00dev, 84, 0x9A);
1054 +       rt2800_bbp_write(rt2x00dev, 86, 0x38);
1055 +       rt2800_bbp_write(rt2x00dev, 88, 0x90);
1056 +       rt2800_bbp_write(rt2x00dev, 91, 0x04);
1057 +       rt2800_bbp_write(rt2x00dev, 92, 0x02);
1058 +       rt2800_bbp_write(rt2x00dev, 95, 0x9A);
1059 +       rt2800_bbp_write(rt2x00dev, 96, 0x00);
1060 +       rt2800_bbp_write(rt2x00dev, 103, 0xC0);
1061 +       rt2800_bbp_write(rt2x00dev, 104, 0x92);
1062 +       /* FIXME BBP105 owerwrite */
1063 +       rt2800_bbp_write(rt2x00dev, 105, 0x3C);
1064 +       rt2800_bbp_write(rt2x00dev, 106, 0x12);
1065 +       rt2800_bbp_write(rt2x00dev, 109, 0x00);
1066 +       rt2800_bbp_write(rt2x00dev, 134, 0x10);
1067 +       rt2800_bbp_write(rt2x00dev, 135, 0xA6);
1068 +       rt2800_bbp_write(rt2x00dev, 137, 0x04);
1069 +       rt2800_bbp_write(rt2x00dev, 142, 0x30);
1070 +       rt2800_bbp_write(rt2x00dev, 143, 0xF7);
1071 +       rt2800_bbp_write(rt2x00dev, 160, 0xEC);
1072 +       rt2800_bbp_write(rt2x00dev, 161, 0xC4);
1073 +       rt2800_bbp_write(rt2x00dev, 162, 0x77);
1074 +       rt2800_bbp_write(rt2x00dev, 163, 0xF9);
1075 +       rt2800_bbp_write(rt2x00dev, 164, 0x00);
1076 +       rt2800_bbp_write(rt2x00dev, 165, 0x00);
1077 +       rt2800_bbp_write(rt2x00dev, 186, 0x00);
1078 +       rt2800_bbp_write(rt2x00dev, 187, 0x00);
1079 +       rt2800_bbp_write(rt2x00dev, 188, 0x00);
1080 +       rt2800_bbp_write(rt2x00dev, 186, 0x00);
1081 +       rt2800_bbp_write(rt2x00dev, 187, 0x01);
1082 +       rt2800_bbp_write(rt2x00dev, 188, 0x00);
1083 +       rt2800_bbp_write(rt2x00dev, 189, 0x00);
1084 +
1085 +       rt2800_bbp_write(rt2x00dev, 91, 0x06);
1086 +       rt2800_bbp_write(rt2x00dev, 92, 0x04);
1087 +       rt2800_bbp_write(rt2x00dev, 93, 0x54);
1088 +       rt2800_bbp_write(rt2x00dev, 99, 0x50);
1089 +       rt2800_bbp_write(rt2x00dev, 148, 0x84);
1090 +       rt2800_bbp_write(rt2x00dev, 167, 0x80);
1091 +       rt2800_bbp_write(rt2x00dev, 178, 0xFF);
1092 +       rt2800_bbp_write(rt2x00dev, 106, 0x13);
1093 +
1094 +       /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
1095 +       rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
1096 +       rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
1097 +       rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
1098 +       rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
1099 +       rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
1100 +       rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
1101 +       rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
1102 +       rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
1103 +       rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
1104 +       rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
1105 +       rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
1106 +       rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
1107 +       rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
1108 +       rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
1109 +       rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
1110 +       rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
1111 +       rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
1112 +       rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
1113 +       rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
1114 +       rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
1115 +       rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
1116 +       rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
1117 +       rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
1118 +       rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
1119 +       rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
1120 +       rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
1121 +       rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
1122 +       rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
1123 +       rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
1124 +       rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
1125 +       rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
1126 +       rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
1127 +       rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
1128 +       rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
1129 +       rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
1130 +       rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
1131 +       rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
1132 +       rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
1133 +       rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
1134 +       rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
1135 +       rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
1136 +       rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
1137 +       rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
1138 +       rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
1139 +       rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
1140 +       rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
1141 +       rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
1142 +       rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
1143 +       rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
1144 +       rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
1145 +       rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
1146 +       rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
1147 +       rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
1148 +       rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
1149 +       rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
1150 +       rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
1151 +       rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
1152 +       rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
1153 +       rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
1154 +       rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
1155 +       rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
1156 +       rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
1157 +       rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
1158 +       rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
1159 +       rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
1160 +       rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
1161 +       rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
1162 +       rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
1163 +       rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
1164 +       rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
1165 +       rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
1166 +       rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
1167 +       rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
1168 +       rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
1169 +       rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
1170 +       rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
1171 +       rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
1172 +       rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
1173 +       rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
1174 +       rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
1175 +       rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
1176 +       rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
1177 +       rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
1178 +
1179 +       /* BBP for G band DCOC function */
1180 +       rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
1181 +       rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
1182 +       rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
1183 +       rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
1184 +       rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
1185 +       rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
1186 +       rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
1187 +       rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
1188 +       rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
1189 +       rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
1190 +       rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
1191 +       rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
1192 +       rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
1193 +       rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
1194 +       rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
1195 +       rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
1196 +       rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
1197 +       rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
1198 +       rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
1199 +       rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
1200 +
1201 +       rt2800_bbp4_mac_if_ctrl(rt2x00dev);
1202 +}
1203 +
1204  static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1205  {
1206         unsigned int i;
1207 @@ -6117,7 +6858,10 @@ static void rt2800_init_bbp(struct rt2x0
1208                 return;
1209         case RT5390:
1210         case RT5392:
1211 -               rt2800_init_bbp_53xx(rt2x00dev);
1212 +               if (rt2x00dev->chip.rf == RF7620)
1213 +                       rt2800_init_bbp_7620(rt2x00dev);
1214 +               else
1215 +                       rt2800_init_bbp_53xx(rt2x00dev);
1216                 break;
1217         case RT5592:
1218                 rt2800_init_bbp_5592(rt2x00dev);
1219 @@ -7331,6 +8075,269 @@ static void rt2800_init_rfcsr_5592(struc
1220         rt2800_led_open_drain_enable(rt2x00dev);
1221  }
1222
1223 +static void rt2800_init_rfcsr_7620(struct rt2x00_dev *rt2x00dev)
1224 +{
1225 +       /* Initialize RF central register to default value */
1226 +       rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
1227 +       rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
1228 +       rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
1229 +       rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
1230 +       rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
1231 +       rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
1232 +       rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
1233 +       rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
1234 +       rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1235 +       rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
1236 +       rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
1237 +       rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1238 +       rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
1239 +       rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
1240 +       rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
1241 +       rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
1242 +       rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
1243 +       rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
1244 +       rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
1245 +       rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
1246 +       rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
1247 +       rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
1248 +       rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
1249 +       rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
1250 +       rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
1251 +       rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
1252 +       rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
1253 +       rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1254 +       rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
1255 +       rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
1256 +       rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
1257 +       rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
1258 +       rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
1259 +       rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
1260 +       rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
1261 +       rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
1262 +       rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
1263 +       rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
1264 +       rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
1265 +       rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
1266 +       rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
1267 +       rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
1268 +       rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
1269 +       rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
1270 +
1271 +       rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1272 +       if (rt2800_clk_is_20mhz(rt2x00dev))
1273 +               rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
1274 +       else
1275 +               rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
1276 +       rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
1277 +       rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
1278 +       rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
1279 +       rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
1280 +       rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
1281 +       rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
1282 +       rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
1283 +       rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1284 +       rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
1285 +       rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
1286 +       rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
1287 +       rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
1288 +       rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1289 +       rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
1290 +       rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
1291 +       rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
1292 +
1293 +       rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
1294 +       rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
1295 +       rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
1296 +
1297 +       /* Initialize RF channel register to default value */
1298 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
1299 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
1300 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
1301 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
1302 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
1303 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
1304 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
1305 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
1306 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
1307 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
1308 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
1309 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
1310 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
1311 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
1312 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
1313 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
1314 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
1315 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
1316 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
1317 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
1318 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
1319 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
1320 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
1321 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
1322 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
1323 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
1324 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
1325 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
1326 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
1327 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
1328 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
1329 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
1330 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
1331 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
1332 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
1333 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
1334 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
1335 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
1336 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
1337 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
1338 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
1339 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
1340 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
1341 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
1342 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
1343 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
1344 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
1345 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
1346 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
1347 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
1348 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
1349 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
1350 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
1351 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
1352 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
1353 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
1354 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
1355 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
1356 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
1357 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
1358 +
1359 +       rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
1360 +
1361 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
1362 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
1363 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
1364 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
1365 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
1366 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
1367 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
1368 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
1369 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
1370 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
1371 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
1372 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
1373 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
1374 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
1375 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
1376 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
1377 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
1378 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
1379 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x69);
1380 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
1381 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x20);
1382 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
1383 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
1384 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
1385 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
1386 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
1387 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
1388 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
1389 +
1390 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
1391 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
1392 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
1393 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
1394 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
1395 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
1396 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
1397 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
1398 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
1399 +
1400 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
1401 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
1402 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
1403 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
1404 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
1405 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
1406 +
1407 +       /* Initialize RF channel register for DRQFN */
1408 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
1409 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
1410 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
1411 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
1412 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
1413 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
1414 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
1415 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
1416 +
1417 +       /* Initialize RF DC calibration register to default value */
1418 +       rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
1419 +       rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
1420 +       rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
1421 +       rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
1422 +       rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
1423 +       rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
1424 +       rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
1425 +       rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
1426 +       rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
1427 +       rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
1428 +       rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
1429 +       rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
1430 +       rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
1431 +       rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
1432 +       rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
1433 +       rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
1434 +       rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
1435 +       rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
1436 +       rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
1437 +       rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
1438 +       rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
1439 +       rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
1440 +       rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
1441 +       rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
1442 +       rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
1443 +       rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
1444 +       rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
1445 +       rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
1446 +       rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
1447 +       rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
1448 +       rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
1449 +       rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
1450 +       rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
1451 +       rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
1452 +       rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
1453 +       rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
1454 +       rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
1455 +       rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
1456 +       rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
1457 +       rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
1458 +       rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
1459 +       rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
1460 +       rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
1461 +       rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
1462 +       rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
1463 +       rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
1464 +       rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
1465 +       rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
1466 +       rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
1467 +       rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
1468 +       rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
1469 +       rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
1470 +       rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
1471 +       rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
1472 +       rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
1473 +       rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
1474 +       rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
1475 +       rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
1476 +       rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
1477 +
1478 +       rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
1479 +       rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
1480 +       rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
1481 +
1482 +       rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
1483 +       rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
1484 +}
1485 +
1486  static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1487  {
1488         if (rt2800_is_305x_soc(rt2x00dev)) {
1489 @@ -7366,7 +8373,10 @@ static void rt2800_init_rfcsr(struct rt2
1490                 rt2800_init_rfcsr_5350(rt2x00dev);
1491                 break;
1492         case RT5390:
1493 -               rt2800_init_rfcsr_5390(rt2x00dev);
1494 +               if (rt2x00dev->chip.rf == RF7620)
1495 +                       rt2800_init_rfcsr_7620(rt2x00dev);
1496 +               else
1497 +                       rt2800_init_rfcsr_5390(rt2x00dev);
1498                 break;
1499         case RT5392:
1500                 rt2800_init_rfcsr_5392(rt2x00dev);
1501 @@ -7780,6 +8790,7 @@ static int rt2800_init_eeprom(struct rt2
1502         case RF5390:
1503         case RF5392:
1504         case RF5592:
1505 +       case RF7620:
1506                 break;
1507         default:
1508                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
1509 @@ -8258,6 +9269,24 @@ static const struct rf_channel rf_vals_5
1510         {196, 83, 0, 12, 1},
1511  };
1512
1513 +static const struct rf_channel rf_vals_7620[] = {
1514 +       /* Channel, Rdiv, N, K | (D >> 8), Ksd */
1515 +       {1, 3, 0x50, 0 | (0 >> 8), 0x19999},
1516 +       {2, 3, 0x50, 0 | (0 >> 8), 0x24444},
1517 +       {3, 3, 0x50, 0 | (0 >> 8), 0x2EEEE},
1518 +       {4, 3, 0x50, 0 | (0 >> 8), 0x39999},
1519 +       {5, 3, 0x51, 0 | (0 >> 8), 0x04444},
1520 +       {6, 3, 0x51, 0 | (0 >> 8), 0x0EEEE},
1521 +       {7, 3, 0x51, 0 | (0 >> 8), 0x19999},
1522 +       {8, 3, 0x51, 0 | (0 >> 8), 0x24444},
1523 +       {9, 3, 0x51, 0 | (0 >> 8), 0x2EEEE},
1524 +       {10, 3, 0x51, 0 | (0 >> 8), 0x39999},
1525 +       {11, 3, 0x52, 0 | (0 >> 8), 0x04444},
1526 +       {12, 3, 0x52, 0 | (0 >> 8), 0x0EEEE},
1527 +       {13, 3, 0x52, 0 | (0 >> 8), 0x19999},
1528 +       {14, 3, 0x52, 0 | (0 >> 8), 0x33333},
1529 +};
1530 +
1531  static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1532  {
1533         struct hw_mode_spec *spec = &rt2x00dev->spec;
1534 @@ -8361,6 +9390,11 @@ static int rt2800_probe_hw_mode(struct r
1535                         spec->channels = rf_vals_3x;
1536                 break;
1537
1538 +       case RF7620:
1539 +               spec->num_channels = ARRAY_SIZE(rf_vals_7620);
1540 +               spec->channels = rf_vals_7620;
1541 +               break;
1542 +
1543         case RF3052:
1544         case RF3053:
1545                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
1546 @@ -8498,6 +9532,7 @@ static int rt2800_probe_hw_mode(struct r
1547         case RF5390:
1548         case RF5392:
1549         case RF5592:
1550 +       case RF7620:
1551                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
1552                 break;
1553         }