1 /******************************************************************************
3 ** FILE NAME : ifxmips_ptm_amazon_se.c
9 ** DESCRIPTION : PTM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
27 * ####################################
29 * ####################################
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/types.h>
39 #include <linux/errno.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioctl.h>
43 #include <asm/delay.h>
46 * Chip Specific Head File
48 #include <asm/ifx/ifx_types.h>
49 #include <asm/ifx/ifx_regs.h>
50 #include <asm/ifx/common_routines.h>
51 #include <asm/ifx/ifx_pmu.h>
52 #include <asm/ifx/ifx_rcu.h>
53 #include "ifxmips_ptm_adsl.h"
54 #include "ifxmips_ptm_fw_amazon_se.h"
59 * ####################################
61 * ####################################
67 #define EMA_CMD_BUF_LEN 0x0040
68 #define EMA_CMD_BASE_ADDR (0x00001580 << 2)
69 #define EMA_DATA_BUF_LEN 0x0100
70 #define EMA_DATA_BASE_ADDR (0x00000B00 << 2)
71 #define EMA_WRITE_BURST 0x2
72 #define EMA_READ_BURST 0x2
77 * ####################################
79 * ####################################
83 * Hardware Init/Uninit Functions
85 static inline void init_pmu(void);
86 static inline void uninit_pmu(void);
87 static inline void reset_ppe(void);
88 static inline void init_ema(void);
89 static inline void init_mailbox(void);
90 static inline void init_atm_tc(void);
91 static inline void clear_share_buffer(void);
96 * ####################################
98 * ####################################
104 * ####################################
106 * ####################################
109 static inline void init_pmu(void)
111 //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
112 //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
113 PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
114 PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
115 PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
116 //PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
117 PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
118 DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
121 static inline void uninit_pmu(void)
123 PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
124 PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
125 PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
126 //PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
127 PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
128 DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
129 //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
132 static inline void reset_ppe(void)
135 unsigned int etop_cfg;
136 unsigned int etop_mdio_cfg;
137 unsigned int etop_ig_plen_ctrl;
138 unsigned int enet_mac_cfg;
140 etop_cfg = *IFX_PP32_ETOP_CFG;
141 etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG;
142 etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL;
143 enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG;
145 *IFX_PP32_ETOP_CFG = (*IFX_PP32_ETOP_CFG & ~0x03C0) | 0x0001;
148 ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_PTM);
150 *IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg;
151 *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
152 *IFX_PP32_ENET_MAC_CFG = enet_mac_cfg;
153 *IFX_PP32_ETOP_CFG = etop_cfg;
157 static inline void init_ema(void)
159 // Configure share buffer master selection
164 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
165 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
166 IFX_REG_W32(0x000000FF, EMA_IER);
167 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
170 static inline void init_mailbox(void)
172 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
173 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
174 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
175 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
178 static inline void init_atm_tc(void)
180 IFX_REG_W32(0x0F00, DREG_AT_CTRL);
181 IFX_REG_W32(0x3C00, DREG_AR_CTRL);
182 IFX_REG_W32(0x0, DREG_AT_IDLE0);
183 IFX_REG_W32(0x0, DREG_AT_IDLE1);
184 IFX_REG_W32(0x0, DREG_AR_IDLE0);
185 IFX_REG_W32(0x0, DREG_AR_IDLE1);
186 IFX_REG_W32(0x0, RFBI_CFG);
187 IFX_REG_W32(0x0200, SFSM_DBA0);
188 IFX_REG_W32(0x0800, SFSM_DBA1);
189 IFX_REG_W32(0x0321, SFSM_CBA0);
190 IFX_REG_W32(0x0921, SFSM_CBA1);
191 IFX_REG_W32(0x14011, SFSM_CFG0);
192 IFX_REG_W32(0x14011, SFSM_CFG1);
193 IFX_REG_W32(0x0332, FFSM_DBA0);
194 IFX_REG_W32(0x0932, FFSM_DBA1);
195 IFX_REG_W32(0x3000C, FFSM_CFG0);
196 IFX_REG_W32(0x3000C, FFSM_CFG1);
197 IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);
198 IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);
201 static inline void clear_share_buffer(void)
203 volatile u32 *p = SB_RAM0_ADDR(0);
206 for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN; i++ )
212 * Download PPE firmware binary code.
214 * src --- u32 *, binary code buffer
215 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
220 static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
224 if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
225 || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
228 if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
229 IFX_REG_W32(0x00, CDM_CFG);
231 IFX_REG_W32(0x04, CDM_CFG);
234 dest = CDM_CODE_MEMORY(0, 0);
235 while ( code_dword_len-- > 0 )
236 IFX_REG_W32(*code_src++, dest++);
239 dest = CDM_DATA_MEMORY(0, 0);
240 while ( data_dword_len-- > 0 )
241 IFX_REG_W32(*data_src++, dest++);
249 * ####################################
251 * ####################################
254 extern void ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *minor)
256 ASSERT(major != NULL, "pointer is NULL");
257 ASSERT(minor != NULL, "pointer is NULL");
259 *major = FW_VER_ID->major;
260 *minor = FW_VER_ID->minor;
263 void ifx_ptm_init_chip(void)
275 clear_share_buffer();
278 void ifx_ptm_uninit_chip(void)
285 * Initialize and start up PP32.
292 int ifx_pp32_start(int pp32)
296 /* download firmware */
297 ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
302 IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(pp32));
304 /* idle for a while to let PP32 init itself */
318 void ifx_pp32_stop(int pp32)
321 IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(pp32));