2 * DANUBE internal switch ethernet driver.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
30 && defined(CONFIG_DANUBE_SWITCH)
34 #include <asm/danube.h>
35 #include <asm/addrspace.h>
36 #include <asm/pinstrap.h>
39 #define REV_MII_MODE 2
44 #define NUM_RX_DESC PKTBUFSRX
46 #define MAX_PACKET_SIZE 1536
48 #define PHY0_ADDR 1 /*fixme: set the correct value here*/
50 #define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value
51 #define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
53 #define SW_WRITE_REG(reg, value) *((volatile u32*)reg) = (u32)value
54 #define SW_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
56 #define TANTOS_CHIP_ID 0x2599
68 volatile u32 reserved :3;
69 volatile u32 Byteoffset :2;
70 volatile u32 reserve :7;
71 volatile u32 DataLen :16;
78 } danube_rx_descriptor_t;
90 volatile u32 Byteoffset :5;
91 volatile u32 reserved :7;
92 volatile u32 DataLen :16;
99 } danube_tx_descriptor_t;
104 static danube_rx_descriptor_t rx_des_ring[NUM_RX_DESC] __attribute__ ((aligned(8)));
105 static danube_tx_descriptor_t tx_des_ring[NUM_TX_DESC] __attribute__ ((aligned(8)));
106 static int tx_num, rx_num;
108 int danube_switch_init(struct eth_device *dev, bd_t * bis);
109 int danube_switch_send(struct eth_device *dev, volatile void *packet,int length);
110 int danube_switch_recv(struct eth_device *dev);
111 void danube_switch_halt(struct eth_device *dev);
112 static void danube_init_switch_chip(int mode);
113 static void danube_dma_init(void);
117 int danube_switch_initialize(bd_t * bis)
119 struct eth_device *dev;
120 unsigned short chipid;
123 printf("Entered danube_switch_initialize()\n");
126 if (!(dev = (struct eth_device *) malloc (sizeof *dev)))
128 printf("Failed to allocate memory\n");
131 memset(dev, 0, sizeof(*dev));
134 danube_init_switch_chip(REV_MII_MODE);
136 #ifdef CLK_OUT2_25MHZ
137 *DANUBE_GPIO_P0_DIR=0x0000ae78;
138 *DANUBE_GPIO_P0_ALTSEL0=0x00008078;
139 //joelin for Mii-1 *DANUBE_GPIO_P0_ALTSEL1=0x80000080;
140 *DANUBE_GPIO_P0_ALTSEL1=0x80000000; //joelin for Mii-1
141 *DANUBE_CGU_IFCCR=0x00400010;
142 *DANUBE_GPIO_P0_OD=0x0000ae78;
147 *DANUBE_RCU_RST_REQ |=1;
149 *DANUBE_RCU_RST_REQ &=(unsigned long)~1;
151 /*while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
152 *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602;
154 /*while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
155 *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602;
158 sprintf(dev->name, "danube Switch");
159 dev->init = danube_switch_init;
160 dev->halt = danube_switch_halt;
161 dev->send = danube_switch_send;
162 dev->recv = danube_switch_recv;
166 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
167 *DANUBE_PPE_ETOP_MDIO_ACC =0xc1010000;
168 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
169 chipid = (unsigned short)(*DANUBE_PPE_ETOP_MDIO_ACC & 0xffff);
171 if (chipid != TANTOS_CHIP_ID) // not tantos switch.
173 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
174 *DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F;
175 while((*DANUBE_PPE_ETOP_MDIO_ACC)&0x80000000);
176 *DANUBE_PPE_ETOP_MDIO_ACC =0x8003840F;
177 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
178 *DANUBE_PPE_ETOP_MDIO_ACC =0x8005840F;
179 //while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
180 //*DANUBE_PPE_ETOP_MDIO_ACC =0x8006840F;
181 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
182 *DANUBE_PPE_ETOP_MDIO_ACC =0x8007840F;
183 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
184 *DANUBE_PPE_ETOP_MDIO_ACC =0x8008840F;
185 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
186 *DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F;
187 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
188 *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602;
189 #ifdef CLK_OUT2_25MHZ
190 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
191 *DANUBE_PPE_ETOP_MDIO_ACC =0x80334000;
194 else // Tantos switch chip
196 //printf("Tantos Switch detected!!\n\r");
198 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
199 *DANUBE_PPE_ETOP_MDIO_ACC =0x80a10004;
201 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
202 *DANUBE_PPE_ETOP_MDIO_ACC =0x80c10004;
204 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
205 *DANUBE_PPE_ETOP_MDIO_ACC =0x80f50773;
207 /* Software workaround. */
208 /* PHY reset from P0 to P4. */
209 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
212 *DANUBE_PPE_ETOP_MDIO_ACC =0x81218000;
213 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
216 *DANUBE_PPE_ETOP_MDIO_ACC =0x81200400;
217 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
220 *DANUBE_PPE_ETOP_MDIO_ACC =0x81200420;
221 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
224 *DANUBE_PPE_ETOP_MDIO_ACC =0x81200440;
225 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
228 *DANUBE_PPE_ETOP_MDIO_ACC =0x81200460;
229 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
232 *DANUBE_PPE_ETOP_MDIO_ACC =0x81200480;
233 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
240 int danube_switch_init(struct eth_device *dev, bd_t * bis)
248 // serial_puts("i \n\0");
250 *DANUBE_DMA_CS=RX_CHAN_NO;
251 *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
252 *DANUBE_DMA_CPOLL= 0x80000040;
253 /*set descriptor base*/
254 *DANUBE_DMA_CDBA=(u32)rx_des_ring;
255 *DANUBE_DMA_CDLEN=NUM_RX_DESC;
257 *DANUBE_DMA_CCTRL=0x30000;
259 *DANUBE_DMA_CS=TX_CHAN_NO;
260 *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
261 *DANUBE_DMA_CPOLL= 0x80000040;
262 *DANUBE_DMA_CDBA=(u32)tx_des_ring;
263 *DANUBE_DMA_CDLEN=NUM_TX_DESC;
265 *DANUBE_DMA_CCTRL=0x30100;
267 for(i=0;i < NUM_RX_DESC; i++)
269 danube_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_des_ring[i]);
270 rx_desc->status.word=0;
271 rx_desc->status.field.OWN=1;
272 rx_desc->status.field.DataLen=PKTSIZE_ALIGN; /* 1536 */
273 rx_desc->DataPtr=(u32)KSEG1ADDR(NetRxPackets[i]);
276 for(i=0;i < NUM_TX_DESC; i++)
278 danube_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_des_ring[i]);
279 memset(tx_desc, 0, sizeof(tx_des_ring[0]));
281 /* turn on DMA rx & tx channel
283 *DANUBE_DMA_CS=RX_CHAN_NO;
284 *DANUBE_DMA_CCTRL|=1;/*reset and turn on the channel*/
289 void danube_switch_halt(struct eth_device *dev)
295 *DANUBE_DMA_CCTRL&=~1;/*stop the dma channel*/
300 int danube_switch_send(struct eth_device *dev, volatile void *packet,int length)
306 danube_tx_descriptor_t * tx_desc= KSEG1ADDR(&tx_des_ring[tx_num]);
310 printf ("%s: bad packet size: %d\n", dev->name, length);
314 for(i=0; tx_desc->status.field.OWN==1; i++)
318 printf("NO Tx Descriptor...");
325 tx_desc->status.field.Sop=1;
326 tx_desc->status.field.Eop=1;
327 tx_desc->status.field.C=0;
328 tx_desc->DataPtr = (u32)KSEG1ADDR(packet);
330 tx_desc->status.field.DataLen = 60;
332 tx_desc->status.field.DataLen = (u32)length;
335 tx_desc->status.field.OWN=1;
339 if(tx_num==NUM_TX_DESC) tx_num=0;
340 *DANUBE_DMA_CS=TX_CHAN_NO;
342 if(!(*DANUBE_DMA_CCTRL & 1))
343 *DANUBE_DMA_CCTRL|=1;
349 int danube_switch_recv(struct eth_device *dev)
352 danube_rx_descriptor_t * rx_desc;
356 rx_desc = KSEG1ADDR(&rx_des_ring[rx_num]);
358 if ((rx_desc->status.field.C == 0) || (rx_desc->status.field.OWN == 1))
363 length = rx_desc->status.field.DataLen;
366 NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_num]), length - 4);
371 printf("Zero length!!!\n");
374 rx_desc->status.field.Sop=0;
375 rx_desc->status.field.Eop=0;
376 rx_desc->status.field.C=0;
377 rx_desc->status.field.DataLen=PKTSIZE_ALIGN;
378 rx_desc->status.field.OWN=1;
380 if(rx_num==NUM_RX_DESC) rx_num=0;
388 static void danube_init_switch_chip(int mode)
390 /*get and set mac address for MAC*/
392 tmp = getenv ("ethaddr");
394 printf("Can't get environment ethaddr!!!\n");
397 printf("ethaddr=%s\n", tmp);
399 *DANUBE_PMU_PWDCR = *DANUBE_PMU_PWDCR & 0xFFFFEFDF;
400 *DANUBE_PPE32_ETOP_MDIO_CFG &= ~0x6;
401 *DANUBE_PPE32_ENET_MAC_CFG = 0x187;
403 // turn on port0, set to rmii and turn off port1.
404 if (mode==REV_MII_MODE)
406 *DANUBE_PPE32_ETOP_CFG = (*DANUBE_PPE32_ETOP_CFG & 0xfffffffc) | 0x0000000a;
408 else if (mode == MII_MODE)
410 *DANUBE_PPE32_ETOP_CFG = (*DANUBE_PPE32_ETOP_CFG & 0xfffffffc) | 0x00000008;
413 *DANUBE_PPE32_ETOP_IG_PLEN_CTRL = 0x4005ee; // set packetlen.
414 *ENET_MAC_CFG |= 1<<11; /*enable the crc*/
419 static void danube_dma_init(void)
421 // serial_puts("d \n\0");
423 *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
426 *DANUBE_DMA_IRNEN=0;/*disable all the interrupts first*/
428 /* Clear Interrupt Status Register */
429 *DANUBE_DMA_IRNCR=0xfffff;
430 /*disable all the dma interrupts*/
432 /*disable channel 0 and channel 1 interrupts*/
434 *DANUBE_DMA_CS=RX_CHAN_NO;
435 *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
436 *DANUBE_DMA_CPOLL= 0x80000040;
437 /*set descriptor base*/
438 *DANUBE_DMA_CDBA=(u32)rx_des_ring;
439 *DANUBE_DMA_CDLEN=NUM_RX_DESC;
441 *DANUBE_DMA_CCTRL=0x30000;
443 *DANUBE_DMA_CS=TX_CHAN_NO;
444 *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
445 *DANUBE_DMA_CPOLL= 0x80000040;
446 *DANUBE_DMA_CDBA=(u32)tx_des_ring;
447 *DANUBE_DMA_CDLEN=NUM_TX_DESC;
449 *DANUBE_DMA_CCTRL=0x30100;
450 /*enable the poll function and set the poll counter*/
451 //*DANUBE_DMA_CPOLL=DANUBE_DMA_POLL_EN | (DANUBE_DMA_POLL_COUNT<<4);
452 /*set port properties, enable endian conversion for switch*/
454 *DANUBE_DMA_PCTRL|=0xf<<8;/*enable 32 bit endian conversion*/