2 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
5 * Author: Nicolas Pitre
6 * Created: Dec 02, 2004
7 * Copyright: MontaVista Software Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/module.h>
22 #include <sound/ac97_codec.h>
23 #include <sound/pxa2xx-lib.h>
25 #include <mach/irqs.h>
26 #include <mach/regs-ac97.h>
27 #include <mach/audio.h>
29 static DEFINE_MUTEX(car_mutex);
30 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
31 static volatile long gsr_bits;
32 static struct clk *ac97_clk;
33 static struct clk *ac97conf_clk;
34 static int reset_gpio;
36 extern void pxa27x_assert_ac97reset(int reset_gpio, int on);
41 * o Slot 12 read from modem space will hang controller.
42 * o CDONE, SDONE interrupt fails after any slot 12 IO.
44 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
45 * 1 jiffy timeout if interrupt never comes).
48 unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
50 unsigned short val = -1;
51 volatile u32 *reg_addr;
53 mutex_lock(&car_mutex);
55 /* set up primary or secondary codec space */
56 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
57 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
59 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
60 reg_addr += (reg >> 1);
62 /* start read access across the ac97 link */
63 GSR = GSR_CDONE | GSR_SDONE;
66 if (reg == AC97_GPIO_STATUS)
68 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
69 !((GSR | gsr_bits) & GSR_SDONE)) {
70 printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
71 __func__, reg, GSR | gsr_bits);
77 GSR = GSR_CDONE | GSR_SDONE;
80 /* but we've just started another cycle... */
81 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
83 out: mutex_unlock(&car_mutex);
86 EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
88 void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
91 volatile u32 *reg_addr;
93 mutex_lock(&car_mutex);
95 /* set up primary or secondary codec space */
96 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
97 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
99 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
100 reg_addr += (reg >> 1);
102 GSR = GSR_CDONE | GSR_SDONE;
105 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
106 !((GSR | gsr_bits) & GSR_CDONE))
107 printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
108 __func__, reg, GSR | gsr_bits);
110 mutex_unlock(&car_mutex);
112 EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
115 static inline void pxa_ac97_warm_pxa25x(void)
119 GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
120 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
123 static inline void pxa_ac97_cold_pxa25x(void)
125 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
126 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
131 GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
132 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
137 static inline void pxa_ac97_warm_pxa27x(void)
141 /* warm reset broken on Bulverde, so manually keep AC97 reset high */
142 pxa27x_assert_ac97reset(reset_gpio, 1);
145 pxa27x_assert_ac97reset(reset_gpio, 0);
149 static inline void pxa_ac97_cold_pxa27x(void)
151 unsigned int timeout;
153 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
154 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
158 /* PXA27x Developers Manual section 13.5.2.2.1 */
159 clk_enable(ac97conf_clk);
161 clk_disable(ac97conf_clk);
162 GCR = GCR_COLD_RST | GCR_WARM_RST;
163 timeout = 100; /* wait for the codec-ready bit to be set */
164 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
170 static inline void pxa_ac97_warm_pxa3xx(void)
176 /* Can't use interrupts */
178 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
182 static inline void pxa_ac97_cold_pxa3xx(void)
186 /* Hold CLKBPB for 100us */
192 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
193 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
197 /* Can't use interrupts on PXA3xx */
198 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
200 GCR = GCR_WARM_RST | GCR_COLD_RST;
201 while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
206 bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
212 pxa_ac97_warm_pxa25x();
217 pxa_ac97_warm_pxa27x();
222 pxa_ac97_warm_pxa3xx();
226 gsr = GSR | gsr_bits;
227 if (!(gsr & (GSR_PCR | GSR_SCR))) {
228 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
236 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
238 bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
244 pxa_ac97_cold_pxa25x();
249 pxa_ac97_cold_pxa27x();
254 pxa_ac97_cold_pxa3xx();
259 gsr = GSR | gsr_bits;
260 if (!(gsr & (GSR_PCR | GSR_SCR))) {
261 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
269 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
272 void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
274 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
275 GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
277 EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
279 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
289 /* Although we don't use those we still need to clear them
290 since they tend to spuriously trigger when MMC is used
291 (hardware bug? go figure)... */
292 if (cpu_is_pxa27x()) {
305 int pxa2xx_ac97_hw_suspend(void)
307 GCR |= GCR_ACLINK_OFF;
308 clk_disable(ac97_clk);
311 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
313 int pxa2xx_ac97_hw_resume(void)
315 clk_enable(ac97_clk);
318 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
321 int pxa2xx_ac97_hw_probe(struct platform_device *dev)
324 pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
327 switch (pdata->reset_gpio) {
330 reset_gpio = pdata->reset_gpio;
338 dev_err(&dev->dev, "Invalid reset GPIO %d\n",
346 if (cpu_is_pxa27x()) {
347 /* Use GPIO 113 as AC97 Reset on Bulverde */
348 pxa27x_assert_ac97reset(reset_gpio, 0);
349 ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
350 if (IS_ERR(ac97conf_clk)) {
351 ret = PTR_ERR(ac97conf_clk);
357 ac97_clk = clk_get(&dev->dev, "AC97CLK");
358 if (IS_ERR(ac97_clk)) {
359 ret = PTR_ERR(ac97_clk);
364 ret = clk_enable(ac97_clk);
368 ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
375 GCR |= GCR_ACLINK_OFF;
381 clk_put(ac97conf_clk);
387 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
389 void pxa2xx_ac97_hw_remove(struct platform_device *dev)
391 GCR |= GCR_ACLINK_OFF;
392 free_irq(IRQ_AC97, NULL);
394 clk_put(ac97conf_clk);
397 clk_disable(ac97_clk);
401 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
403 MODULE_AUTHOR("Nicolas Pitre");
404 MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
405 MODULE_LICENSE("GPL");