sound/pci/asihpi/hpi6205.c

   1 /******************************************************************************
   2
   3     AudioScience HPI driver
   4     Copyright (C) 1997-2010  AudioScience Inc. <support@audioscience.com>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of version 2 of the GNU General Public License as
   8     published by the Free Software Foundation;
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18
  19  Hardware Programming Interface (HPI) for AudioScience
  20  ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters.
  21  These PCI and PCIe bus adapters are based on a
  22  TMS320C6205 PCI bus mastering DSP,
  23  and (except ASI50xx) TI TMS320C6xxx floating point DSP
  24
  25  Exported function:
  26  void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
  27
  28 (C) Copyright AudioScience Inc. 1998-2010
  29 *******************************************************************************/
  30 #define SOURCEFILE_NAME "hpi6205.c"
  31
  32 #include "hpi_internal.h"
  33 #include "hpimsginit.h"
  34 #include "hpidebug.h"
  35 #include "hpi6205.h"
  36 #include "hpidspcd.h"
  37 #include "hpicmn.h"
  38
  39 /*****************************************************************************/
  40 /* HPI6205 specific error codes */
  41 #define HPI6205_ERROR_BASE 1000 /* not actually used anywhere */
  42
  43 /* operational/messaging errors */
  44 #define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT     1015
  45 #define HPI6205_ERROR_MSG_RESP_TIMEOUT          1016
  46
  47 /* initialization/bootload errors */
  48 #define HPI6205_ERROR_6205_NO_IRQ               1002
  49 #define HPI6205_ERROR_6205_INIT_FAILED          1003
  50 #define HPI6205_ERROR_6205_REG                  1006
  51 #define HPI6205_ERROR_6205_DSPPAGE              1007
  52 #define HPI6205_ERROR_C6713_HPIC                1009
  53 #define HPI6205_ERROR_C6713_HPIA                1010
  54 #define HPI6205_ERROR_C6713_PLL                 1011
  55 #define HPI6205_ERROR_DSP_INTMEM                1012
  56 #define HPI6205_ERROR_DSP_EXTMEM                1013
  57 #define HPI6205_ERROR_DSP_PLD                   1014
  58 #define HPI6205_ERROR_6205_EEPROM               1017
  59 #define HPI6205_ERROR_DSP_EMIF                  1018
  60
  61 /*****************************************************************************/
  62 /* for C6205 PCI i/f */
  63 /* Host Status Register (HSR) bitfields */
  64 #define C6205_HSR_INTSRC        0x01
  65 #define C6205_HSR_INTAVAL       0x02
  66 #define C6205_HSR_INTAM         0x04
  67 #define C6205_HSR_CFGERR        0x08
  68 #define C6205_HSR_EEREAD        0x10
  69 /* Host-to-DSP Control Register (HDCR) bitfields */
  70 #define C6205_HDCR_WARMRESET    0x01
  71 #define C6205_HDCR_DSPINT       0x02
  72 #define C6205_HDCR_PCIBOOT      0x04
  73 /* DSP Page Register (DSPP) bitfields, */
  74 /* defines 4 Mbyte page that BAR0 points to */
  75 #define C6205_DSPP_MAP1         0x400
  76
  77 /* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP.
  78  * BAR1 maps to non-prefetchable 8 Mbyte memory block
  79  * of DSP memory mapped registers (starting at 0x01800000).
  80  * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this
  81  * needs to be added to the BAR1 base address set in the PCI config reg
  82  */
  83 #define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L)
  84 #define C6205_BAR1_HSR  (C6205_BAR1_PCI_IO_OFFSET)
  85 #define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4)
  86 #define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8)
  87
  88 /* used to control LED (revA) and reset C6713 (revB) */
  89 #define C6205_BAR0_TIMER1_CTL (0x01980000L)
  90
  91 /* For first 6713 in CE1 space, using DA17,16,2 */
  92 #define HPICL_ADDR      0x01400000L
  93 #define HPICH_ADDR      0x01400004L
  94 #define HPIAL_ADDR      0x01410000L
  95 #define HPIAH_ADDR      0x01410004L
  96 #define HPIDIL_ADDR     0x01420000L
  97 #define HPIDIH_ADDR     0x01420004L
  98 #define HPIDL_ADDR      0x01430000L
  99 #define HPIDH_ADDR      0x01430004L
 100
 101 #define C6713_EMIF_GCTL         0x01800000
 102 #define C6713_EMIF_CE1          0x01800004
 103 #define C6713_EMIF_CE0          0x01800008
 104 #define C6713_EMIF_CE2          0x01800010
 105 #define C6713_EMIF_CE3          0x01800014
 106 #define C6713_EMIF_SDRAMCTL     0x01800018
 107 #define C6713_EMIF_SDRAMTIMING  0x0180001C
 108 #define C6713_EMIF_SDRAMEXT     0x01800020
 109
 110 struct hpi_hw_obj {
 111         /* PCI registers */
 112         __iomem u32 *prHSR;
 113         __iomem u32 *prHDCR;
 114         __iomem u32 *prDSPP;
 115
 116         u32 dsp_page;
 117
 118         struct consistent_dma_area h_locked_mem;
 119         struct bus_master_interface *p_interface_buffer;
 120
 121         u16 flag_outstream_just_reset[HPI_MAX_STREAMS];
 122         /* a non-NULL handle means there is an HPI allocated buffer */
 123         struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS];
 124         struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS];
 125         /* non-zero size means a buffer exists, may be external */
 126         u32 instream_host_buffer_size[HPI_MAX_STREAMS];
 127         u32 outstream_host_buffer_size[HPI_MAX_STREAMS];
 128
 129         struct consistent_dma_area h_control_cache;
 130         struct consistent_dma_area h_async_event_buffer;
 131 /*      struct hpi_control_cache_single *pControlCache; */
 132         struct hpi_async_event *p_async_event_buffer;
 133         struct hpi_control_cache *p_cache;
 134 };
 135
 136 /*****************************************************************************/
 137 /* local prototypes */
 138
 139 #define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write)
 140
 141 static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us);
 142
 143 static void send_dsp_command(struct hpi_hw_obj *phw, int cmd);
 144
 145 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
 146         u32 *pos_error_code);
 147
 148 static u16 message_response_sequence(struct hpi_adapter_obj *pao,
 149         struct hpi_message *phm, struct hpi_response *phr);
 150
 151 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
 152         struct hpi_response *phr);
 153
 154 #define HPI6205_TIMEOUT 1000000
 155
 156 static void subsys_create_adapter(struct hpi_message *phm,
 157         struct hpi_response *phr);
 158 static void subsys_delete_adapter(struct hpi_message *phm,
 159         struct hpi_response *phr);
 160
 161 static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
 162         u32 *pos_error_code);
 163
 164 static void delete_adapter_obj(struct hpi_adapter_obj *pao);
 165
 166 static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
 167         struct hpi_message *phm, struct hpi_response *phr);
 168
 169 static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
 170         struct hpi_message *phm, struct hpi_response *phr);
 171
 172 static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
 173         struct hpi_message *phm, struct hpi_response *phr);
 174 static void outstream_write(struct hpi_adapter_obj *pao,
 175         struct hpi_message *phm, struct hpi_response *phr);
 176
 177 static void outstream_get_info(struct hpi_adapter_obj *pao,
 178         struct hpi_message *phm, struct hpi_response *phr);
 179
 180 static void outstream_start(struct hpi_adapter_obj *pao,
 181         struct hpi_message *phm, struct hpi_response *phr);
 182
 183 static void outstream_open(struct hpi_adapter_obj *pao,
 184         struct hpi_message *phm, struct hpi_response *phr);
 185
 186 static void outstream_reset(struct hpi_adapter_obj *pao,
 187         struct hpi_message *phm, struct hpi_response *phr);
 188
 189 static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
 190         struct hpi_message *phm, struct hpi_response *phr);
 191
 192 static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
 193         struct hpi_message *phm, struct hpi_response *phr);
 194
 195 static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
 196         struct hpi_message *phm, struct hpi_response *phr);
 197
 198 static void instream_read(struct hpi_adapter_obj *pao,
 199         struct hpi_message *phm, struct hpi_response *phr);
 200
 201 static void instream_get_info(struct hpi_adapter_obj *pao,
 202         struct hpi_message *phm, struct hpi_response *phr);
 203
 204 static void instream_start(struct hpi_adapter_obj *pao,
 205         struct hpi_message *phm, struct hpi_response *phr);
 206
 207 static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
 208         u32 address);
 209
 210 static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
 211         int dsp_index, u32 address, u32 data);
 212
 213 static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao,
 214         int dsp_index);
 215
 216 static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
 217         u32 address, u32 length);
 218
 219 static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
 220         int dsp_index);
 221
 222 static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
 223         int dsp_index);
 224
 225 static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index);
 226
 227 /*****************************************************************************/
 228
 229 static void subsys_message(struct hpi_message *phm, struct hpi_response *phr)
 230 {
 231         switch (phm->function) {
 232         case HPI_SUBSYS_CREATE_ADAPTER:
 233                 subsys_create_adapter(phm, phr);
 234                 break;
 235         case HPI_SUBSYS_DELETE_ADAPTER:
 236                 subsys_delete_adapter(phm, phr);
 237                 break;
 238         default:
 239                 phr->error = HPI_ERROR_INVALID_FUNC;
 240                 break;
 241         }
 242 }
 243
 244 static void control_message(struct hpi_adapter_obj *pao,
 245         struct hpi_message *phm, struct hpi_response *phr)
 246 {
 247
 248         struct hpi_hw_obj *phw = pao->priv;
 249         u16 pending_cache_error = 0;
 250
 251         switch (phm->function) {
 252         case HPI_CONTROL_GET_STATE:
 253                 if (pao->has_control_cache) {
 254                         rmb();  /* make sure we see updates DMAed from DSP */
 255                         if (hpi_check_control_cache(phw->p_cache, phm, phr)) {
 256                                 break;
 257                         } else if (phm->u.c.attribute == HPI_METER_PEAK) {
 258                                 pending_cache_error =
 259                                         HPI_ERROR_CONTROL_CACHING;
 260                         }
 261                 }
 262                 hw_message(pao, phm, phr);
 263                 if (pending_cache_error && !phr->error)
 264                         phr->error = pending_cache_error;
 265                 break;
 266         case HPI_CONTROL_GET_INFO:
 267                 hw_message(pao, phm, phr);
 268                 break;
 269         case HPI_CONTROL_SET_STATE:
 270                 hw_message(pao, phm, phr);
 271                 if (pao->has_control_cache)
 272                         hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm,
 273                                 phr);
 274                 break;
 275         default:
 276                 phr->error = HPI_ERROR_INVALID_FUNC;
 277                 break;
 278         }
 279 }
 280
 281 static void adapter_message(struct hpi_adapter_obj *pao,
 282         struct hpi_message *phm, struct hpi_response *phr)
 283 {
 284         switch (phm->function) {
 285         default:
 286                 hw_message(pao, phm, phr);
 287                 break;
 288         }
 289 }
 290
 291 static void outstream_message(struct hpi_adapter_obj *pao,
 292         struct hpi_message *phm, struct hpi_response *phr)
 293 {
 294
 295         if (phm->obj_index >= HPI_MAX_STREAMS) {
 296                 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
 297                 HPI_DEBUG_LOG(WARNING,
 298                         "Message referencing invalid stream %d "
 299                         "on adapter index %d\n", phm->obj_index,
 300                         phm->adapter_index);
 301                 return;
 302         }
 303
 304         switch (phm->function) {
 305         case HPI_OSTREAM_WRITE:
 306                 outstream_write(pao, phm, phr);
 307                 break;
 308         case HPI_OSTREAM_GET_INFO:
 309                 outstream_get_info(pao, phm, phr);
 310                 break;
 311         case HPI_OSTREAM_HOSTBUFFER_ALLOC:
 312                 outstream_host_buffer_allocate(pao, phm, phr);
 313                 break;
 314         case HPI_OSTREAM_HOSTBUFFER_GET_INFO:
 315                 outstream_host_buffer_get_info(pao, phm, phr);
 316                 break;
 317         case HPI_OSTREAM_HOSTBUFFER_FREE:
 318                 outstream_host_buffer_free(pao, phm, phr);
 319                 break;
 320         case HPI_OSTREAM_START:
 321                 outstream_start(pao, phm, phr);
 322                 break;
 323         case HPI_OSTREAM_OPEN:
 324                 outstream_open(pao, phm, phr);
 325                 break;
 326         case HPI_OSTREAM_RESET:
 327                 outstream_reset(pao, phm, phr);
 328                 break;
 329         default:
 330                 hw_message(pao, phm, phr);
 331                 break;
 332         }
 333 }
 334
 335 static void instream_message(struct hpi_adapter_obj *pao,
 336         struct hpi_message *phm, struct hpi_response *phr)
 337 {
 338
 339         if (phm->obj_index >= HPI_MAX_STREAMS) {
 340                 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
 341                 HPI_DEBUG_LOG(WARNING,
 342                         "Message referencing invalid stream %d "
 343                         "on adapter index %d\n", phm->obj_index,
 344                         phm->adapter_index);
 345                 return;
 346         }
 347
 348         switch (phm->function) {
 349         case HPI_ISTREAM_READ:
 350                 instream_read(pao, phm, phr);
 351                 break;
 352         case HPI_ISTREAM_GET_INFO:
 353                 instream_get_info(pao, phm, phr);
 354                 break;
 355         case HPI_ISTREAM_HOSTBUFFER_ALLOC:
 356                 instream_host_buffer_allocate(pao, phm, phr);
 357                 break;
 358         case HPI_ISTREAM_HOSTBUFFER_GET_INFO:
 359                 instream_host_buffer_get_info(pao, phm, phr);
 360                 break;
 361         case HPI_ISTREAM_HOSTBUFFER_FREE:
 362                 instream_host_buffer_free(pao, phm, phr);
 363                 break;
 364         case HPI_ISTREAM_START:
 365                 instream_start(pao, phm, phr);
 366                 break;
 367         default:
 368                 hw_message(pao, phm, phr);
 369                 break;
 370         }
 371 }
 372
 373 /*****************************************************************************/
 374 /** Entry point to this HPI backend
 375  * All calls to the HPI start here
 376  */
 377 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
 378 {
 379         struct hpi_adapter_obj *pao = NULL;
 380
 381         /* subsytem messages are processed by every HPI.
 382          * All other messages are ignored unless the adapter index matches
 383          * an adapter in the HPI
 384          */
 385         /* HPI_DEBUG_LOG(DEBUG, "HPI Obj=%d, Func=%d\n", phm->wObject,
 386            phm->wFunction); */
 387
 388         /* if Dsp has crashed then do not communicate with it any more */
 389         if (phm->object != HPI_OBJ_SUBSYSTEM) {
 390                 pao = hpi_find_adapter(phm->adapter_index);
 391                 if (!pao) {
 392                         HPI_DEBUG_LOG(DEBUG,
 393                                 " %d,%d refused, for another HPI?\n",
 394                                 phm->object, phm->function);
 395                         return;
 396                 }
 397
 398                 if ((pao->dsp_crashed >= 10)
 399                         && (phm->function != HPI_ADAPTER_DEBUG_READ)) {
 400                         /* allow last resort debug read even after crash */
 401                         hpi_init_response(phr, phm->object, phm->function,
 402                                 HPI_ERROR_DSP_HARDWARE);
 403                         HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n",
 404                                 phm->object, phm->function);
 405                         return;
 406                 }
 407         }
 408
 409         /* Init default response  */
 410         if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
 411                 phr->error = HPI_ERROR_PROCESSING_MESSAGE;
 412
 413         HPI_DEBUG_LOG(VERBOSE, "start of switch\n");
 414         switch (phm->type) {
 415         case HPI_TYPE_MESSAGE:
 416                 switch (phm->object) {
 417                 case HPI_OBJ_SUBSYSTEM:
 418                         subsys_message(phm, phr);
 419                         break;
 420
 421                 case HPI_OBJ_ADAPTER:
 422                         adapter_message(pao, phm, phr);
 423                         break;
 424
 425                 case HPI_OBJ_CONTROLEX:
 426                 case HPI_OBJ_CONTROL:
 427                         control_message(pao, phm, phr);
 428                         break;
 429
 430                 case HPI_OBJ_OSTREAM:
 431                         outstream_message(pao, phm, phr);
 432                         break;
 433
 434                 case HPI_OBJ_ISTREAM:
 435                         instream_message(pao, phm, phr);
 436                         break;
 437
 438                 default:
 439                         hw_message(pao, phm, phr);
 440                         break;
 441                 }
 442                 break;
 443
 444         default:
 445                 phr->error = HPI_ERROR_INVALID_TYPE;
 446                 break;
 447         }
 448 }
 449
 450 /*****************************************************************************/
 451 /* SUBSYSTEM */
 452
 453 /** Create an adapter object and initialise it based on resource information
 454  * passed in in the message
 455  * *** NOTE - you cannot use this function AND the FindAdapters function at the
 456  * same time, the application must use only one of them to get the adapters ***
 457  */
 458 static void subsys_create_adapter(struct hpi_message *phm,
 459         struct hpi_response *phr)
 460 {
 461         /* create temp adapter obj, because we don't know what index yet */
 462         struct hpi_adapter_obj ao;
 463         u32 os_error_code;
 464         u16 err;
 465
 466         HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n");
 467
 468         memset(&ao, 0, sizeof(ao));
 469
 470         ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
 471         if (!ao.priv) {
 472                 HPI_DEBUG_LOG(ERROR, "cant get mem for adapter object\n");
 473                 phr->error = HPI_ERROR_MEMORY_ALLOC;
 474                 return;
 475         }
 476
 477         ao.pci = *phm->u.s.resource.r.pci;
 478         err = create_adapter_obj(&ao, &os_error_code);
 479         if (err) {
 480                 delete_adapter_obj(&ao);
 481                 phr->error = err;
 482                 phr->u.s.data = os_error_code;
 483                 return;
 484         }
 485
 486         phr->u.s.aw_adapter_list[ao.index] = ao.adapter_type;
 487         phr->u.s.adapter_index = ao.index;
 488         phr->u.s.num_adapters++;
 489         phr->error = 0;
 490 }
 491
 492 /** delete an adapter - required by WDM driver */
 493 static void subsys_delete_adapter(struct hpi_message *phm,
 494         struct hpi_response *phr)
 495 {
 496         struct hpi_adapter_obj *pao;
 497         struct hpi_hw_obj *phw;
 498
 499         pao = hpi_find_adapter(phm->obj_index);
 500         if (!pao) {
 501                 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
 502                 return;
 503         }
 504         phw = (struct hpi_hw_obj *)pao->priv;
 505         /* reset adapter h/w */
 506         /* Reset C6713 #1 */
 507         boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
 508         /* reset C6205 */
 509         iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR);
 510
 511         delete_adapter_obj(pao);
 512         hpi_delete_adapter(pao);
 513         phr->error = 0;
 514 }
 515
 516 /** Create adapter object
 517   allocate buffers, bootload DSPs, initialise control cache
 518 */
 519 static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
 520         u32 *pos_error_code)
 521 {
 522         struct hpi_hw_obj *phw = pao->priv;
 523         struct bus_master_interface *interface;
 524         u32 phys_addr;
 525 #ifndef HPI6205_NO_HSR_POLL
 526         u32 time_out = HPI6205_TIMEOUT;
 527         u32 temp1;
 528 #endif
 529         int i;
 530         u16 err;
 531
 532         /* init error reporting */
 533         pao->dsp_crashed = 0;
 534
 535         for (i = 0; i < HPI_MAX_STREAMS; i++)
 536                 phw->flag_outstream_just_reset[i] = 1;
 537
 538         /* The C6205 memory area 1 is 8Mbyte window into DSP registers */
 539         phw->prHSR =
 540                 pao->pci.ap_mem_base[1] +
 541                 C6205_BAR1_HSR / sizeof(*pao->pci.ap_mem_base[1]);
 542         phw->prHDCR =
 543                 pao->pci.ap_mem_base[1] +
 544                 C6205_BAR1_HDCR / sizeof(*pao->pci.ap_mem_base[1]);
 545         phw->prDSPP =
 546                 pao->pci.ap_mem_base[1] +
 547                 C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]);
 548
 549         pao->has_control_cache = 0;
 550
 551         if (hpios_locked_mem_alloc(&phw->h_locked_mem,
 552                         sizeof(struct bus_master_interface),
 553                         pao->pci.pci_dev))
 554                 phw->p_interface_buffer = NULL;
 555         else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem,
 556                         (void *)&phw->p_interface_buffer))
 557                 phw->p_interface_buffer = NULL;
 558
 559         HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n",
 560                 phw->p_interface_buffer);
 561
 562         if (phw->p_interface_buffer) {
 563                 memset((void *)phw->p_interface_buffer, 0,
 564                         sizeof(struct bus_master_interface));
 565                 phw->p_interface_buffer->dsp_ack = H620_HIF_UNKNOWN;
 566         }
 567
 568         err = adapter_boot_load_dsp(pao, pos_error_code);
 569         if (err)
 570                 /* no need to clean up as SubSysCreateAdapter */
 571                 /* calls DeleteAdapter on error. */
 572                 return err;
 573
 574         HPI_DEBUG_LOG(INFO, "load DSP code OK\n");
 575
 576         /* allow boot load even if mem alloc wont work */
 577         if (!phw->p_interface_buffer)
 578                 return HPI_ERROR_MEMORY_ALLOC;
 579
 580         interface = phw->p_interface_buffer;
 581
 582 #ifndef HPI6205_NO_HSR_POLL
 583         /* wait for first interrupt indicating the DSP init is done */
 584         time_out = HPI6205_TIMEOUT * 10;
 585         temp1 = 0;
 586         while (((temp1 & C6205_HSR_INTSRC) == 0) && --time_out)
 587                 temp1 = ioread32(phw->prHSR);
 588
 589         if (temp1 & C6205_HSR_INTSRC)
 590                 HPI_DEBUG_LOG(INFO,
 591                         "Interrupt confirming DSP code running OK\n");
 592         else {
 593                 HPI_DEBUG_LOG(ERROR,
 594                         "Timed out waiting for interrupt "
 595                         "confirming DSP code running\n");
 596                 return HPI6205_ERROR_6205_NO_IRQ;
 597         }
 598
 599         /* reset the interrupt */
 600         iowrite32(C6205_HSR_INTSRC, phw->prHSR);
 601 #endif
 602
 603         /* make sure the DSP has started ok */
 604         if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) {
 605                 HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n");
 606                 return HPI6205_ERROR_6205_INIT_FAILED;
 607         }
 608         /* Note that *pao, *phw are zeroed after allocation,
 609          * so pointers and flags are NULL by default.
 610          * Allocate bus mastering control cache buffer and tell the DSP about it
 611          */
 612         if (interface->control_cache.number_of_controls) {
 613                 u8 *p_control_cache_virtual;
 614
 615                 err = hpios_locked_mem_alloc(&phw->h_control_cache,
 616                         interface->control_cache.size_in_bytes,
 617                         pao->pci.pci_dev);
 618                 if (!err)
 619                         err = hpios_locked_mem_get_virt_addr(&phw->
 620                                 h_control_cache,
 621                                 (void *)&p_control_cache_virtual);
 622                 if (!err) {
 623                         memset(p_control_cache_virtual, 0,
 624                                 interface->control_cache.size_in_bytes);
 625
 626                         phw->p_cache =
 627                                 hpi_alloc_control_cache(interface->
 628                                 control_cache.number_of_controls,
 629                                 interface->control_cache.size_in_bytes,
 630                                 p_control_cache_virtual);
 631                         if (!phw->p_cache)
 632                                 err = HPI_ERROR_MEMORY_ALLOC;
 633                 }
 634                 if (!err) {
 635                         err = hpios_locked_mem_get_phys_addr(&phw->
 636                                 h_control_cache, &phys_addr);
 637                         interface->control_cache.physical_address32 =
 638                                 phys_addr;
 639                 }
 640
 641                 if (!err)
 642                         pao->has_control_cache = 1;
 643                 else {
 644                         if (hpios_locked_mem_valid(&phw->h_control_cache))
 645                                 hpios_locked_mem_free(&phw->h_control_cache);
 646                         pao->has_control_cache = 0;
 647                 }
 648         }
 649         /* allocate bus mastering async buffer and tell the DSP about it */
 650         if (interface->async_buffer.b.size) {
 651                 err = hpios_locked_mem_alloc(&phw->h_async_event_buffer,
 652                         interface->async_buffer.b.size *
 653                         sizeof(struct hpi_async_event), pao->pci.pci_dev);
 654                 if (!err)
 655                         err = hpios_locked_mem_get_virt_addr
 656                                 (&phw->h_async_event_buffer, (void *)
 657                                 &phw->p_async_event_buffer);
 658                 if (!err)
 659                         memset((void *)phw->p_async_event_buffer, 0,
 660                                 interface->async_buffer.b.size *
 661                                 sizeof(struct hpi_async_event));
 662                 if (!err) {
 663                         err = hpios_locked_mem_get_phys_addr
 664                                 (&phw->h_async_event_buffer, &phys_addr);
 665                         interface->async_buffer.physical_address32 =
 666                                 phys_addr;
 667                 }
 668                 if (err) {
 669                         if (hpios_locked_mem_valid(&phw->
 670                                         h_async_event_buffer)) {
 671                                 hpios_locked_mem_free
 672                                         (&phw->h_async_event_buffer);
 673                                 phw->p_async_event_buffer = NULL;
 674                         }
 675                 }
 676         }
 677         send_dsp_command(phw, H620_HIF_IDLE);
 678
 679         {
 680                 struct hpi_message hm;
 681                 struct hpi_response hr;
 682                 u32 max_streams;
 683
 684                 HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n");
 685                 memset(&hm, 0, sizeof(hm));
 686                 hm.type = HPI_TYPE_MESSAGE;
 687                 hm.size = sizeof(hm);
 688                 hm.object = HPI_OBJ_ADAPTER;
 689                 hm.function = HPI_ADAPTER_GET_INFO;
 690                 hm.adapter_index = 0;
 691                 memset(&hr, 0, sizeof(hr));
 692                 hr.size = sizeof(hr);
 693
 694                 err = message_response_sequence(pao, &hm, &hr);
 695                 if (err) {
 696                         HPI_DEBUG_LOG(ERROR, "message transport error %d\n",
 697                                 err);
 698                         return err;
 699                 }
 700                 if (hr.error)
 701                         return hr.error;
 702
 703                 pao->adapter_type = hr.u.ax.info.adapter_type;
 704                 pao->index = hr.u.ax.info.adapter_index;
 705
 706                 max_streams =
 707                         hr.u.ax.info.num_outstreams +
 708                         hr.u.ax.info.num_instreams;
 709
 710                 hpios_locked_mem_prepare((max_streams * 6) / 10, max_streams,
 711                         65536, pao->pci.pci_dev);
 712
 713                 HPI_DEBUG_LOG(VERBOSE,
 714                         "got adapter info type %x index %d serial %d\n",
 715                         hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index,
 716                         hr.u.ax.info.serial_number);
 717         }
 718
 719         pao->open = 0;  /* upon creation the adapter is closed */
 720
 721         if (phw->p_cache)
 722                 phw->p_cache->adap_idx = pao->index;
 723
 724         HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
 725
 726         return hpi_add_adapter(pao);
 727 }
 728
 729 /** Free memory areas allocated by adapter
 730  * this routine is called from SubSysDeleteAdapter,
 731   * and SubSysCreateAdapter if duplicate index
 732 */
 733 static void delete_adapter_obj(struct hpi_adapter_obj *pao)
 734 {
 735         struct hpi_hw_obj *phw;
 736         int i;
 737
 738         phw = pao->priv;
 739
 740         if (hpios_locked_mem_valid(&phw->h_async_event_buffer)) {
 741                 hpios_locked_mem_free(&phw->h_async_event_buffer);
 742                 phw->p_async_event_buffer = NULL;
 743         }
 744
 745         if (hpios_locked_mem_valid(&phw->h_control_cache)) {
 746                 hpios_locked_mem_free(&phw->h_control_cache);
 747                 hpi_free_control_cache(phw->p_cache);
 748         }
 749
 750         if (hpios_locked_mem_valid(&phw->h_locked_mem)) {
 751                 hpios_locked_mem_free(&phw->h_locked_mem);
 752                 phw->p_interface_buffer = NULL;
 753         }
 754
 755         for (i = 0; i < HPI_MAX_STREAMS; i++)
 756                 if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) {
 757                         hpios_locked_mem_free(&phw->instream_host_buffers[i]);
 758                         /*?phw->InStreamHostBuffers[i] = NULL; */
 759                         phw->instream_host_buffer_size[i] = 0;
 760                 }
 761
 762         for (i = 0; i < HPI_MAX_STREAMS; i++)
 763                 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) {
 764                         hpios_locked_mem_free(&phw->outstream_host_buffers
 765                                 [i]);
 766                         phw->outstream_host_buffer_size[i] = 0;
 767                 }
 768
 769         hpios_locked_mem_unprepare(pao->pci.pci_dev);
 770
 771         kfree(phw);
 772 }
 773
 774 /*****************************************************************************/
 775 /* OutStream Host buffer functions */
 776
 777 /** Allocate or attach buffer for busmastering
 778 */
 779 static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
 780         struct hpi_message *phm, struct hpi_response *phr)
 781 {
 782         u16 err = 0;
 783         u32 command = phm->u.d.u.buffer.command;
 784         struct hpi_hw_obj *phw = pao->priv;
 785         struct bus_master_interface *interface = phw->p_interface_buffer;
 786
 787         hpi_init_response(phr, phm->object, phm->function, 0);
 788
 789         if (command == HPI_BUFFER_CMD_EXTERNAL
 790                 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
 791                 /* ALLOC phase, allocate a buffer with power of 2 size,
 792                    get its bus address for PCI bus mastering
 793                  */
 794                 phm->u.d.u.buffer.buffer_size =
 795                         roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
 796                 /* return old size and allocated size,
 797                    so caller can detect change */
 798                 phr->u.d.u.stream_info.data_available =
 799                         phw->outstream_host_buffer_size[phm->obj_index];
 800                 phr->u.d.u.stream_info.buffer_size =
 801                         phm->u.d.u.buffer.buffer_size;
 802
 803                 if (phw->outstream_host_buffer_size[phm->obj_index] ==
 804                         phm->u.d.u.buffer.buffer_size) {
 805                         /* Same size, no action required */
 806                         return;
 807                 }
 808
 809                 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
 810                                         obj_index]))
 811                         hpios_locked_mem_free(&phw->outstream_host_buffers
 812                                 [phm->obj_index]);
 813
 814                 err = hpios_locked_mem_alloc(&phw->outstream_host_buffers
 815                         [phm->obj_index], phm->u.d.u.buffer.buffer_size,
 816                         pao->pci.pci_dev);
 817
 818                 if (err) {
 819                         phr->error = HPI_ERROR_INVALID_DATASIZE;
 820                         phw->outstream_host_buffer_size[phm->obj_index] = 0;
 821                         return;
 822                 }
 823
 824                 err = hpios_locked_mem_get_phys_addr
 825                         (&phw->outstream_host_buffers[phm->obj_index],
 826                         &phm->u.d.u.buffer.pci_address);
 827                 /* get the phys addr into msg for single call alloc caller
 828                  * needs to do this for split alloc (or use the same message)
 829                  * return the phy address for split alloc in the respose too
 830                  */
 831                 phr->u.d.u.stream_info.auxiliary_data_available =
 832                         phm->u.d.u.buffer.pci_address;
 833
 834                 if (err) {
 835                         hpios_locked_mem_free(&phw->outstream_host_buffers
 836                                 [phm->obj_index]);
 837                         phw->outstream_host_buffer_size[phm->obj_index] = 0;
 838                         phr->error = HPI_ERROR_MEMORY_ALLOC;
 839                         return;
 840                 }
 841         }
 842
 843         if (command == HPI_BUFFER_CMD_EXTERNAL
 844                 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
 845                 /* GRANT phase.  Set up the BBM status, tell the DSP about
 846                    the buffer so it can start using BBM.
 847                  */
 848                 struct hpi_hostbuffer_status *status;
 849
 850                 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
 851                                 buffer_size - 1)) {
 852                         HPI_DEBUG_LOG(ERROR,
 853                                 "Buffer size must be 2^N not %d\n",
 854                                 phm->u.d.u.buffer.buffer_size);
 855                         phr->error = HPI_ERROR_INVALID_DATASIZE;
 856                         return;
 857                 }
 858                 phw->outstream_host_buffer_size[phm->obj_index] =
 859                         phm->u.d.u.buffer.buffer_size;
 860                 status = &interface->outstream_host_buffer_status[phm->
 861                         obj_index];
 862                 status->samples_processed = 0;
 863                 status->stream_state = HPI_STATE_STOPPED;
 864                 status->dSP_index = 0;
 865                 status->host_index = status->dSP_index;
 866                 status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
 867                 status->auxiliary_data_available = 0;
 868
 869                 hw_message(pao, phm, phr);
 870
 871                 if (phr->error
 872                         && hpios_locked_mem_valid(&phw->
 873                                 outstream_host_buffers[phm->obj_index])) {
 874                         hpios_locked_mem_free(&phw->outstream_host_buffers
 875                                 [phm->obj_index]);
 876                         phw->outstream_host_buffer_size[phm->obj_index] = 0;
 877                 }
 878         }
 879 }
 880
 881 static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
 882         struct hpi_message *phm, struct hpi_response *phr)
 883 {
 884         struct hpi_hw_obj *phw = pao->priv;
 885         struct bus_master_interface *interface = phw->p_interface_buffer;
 886         struct hpi_hostbuffer_status *status;
 887         u8 *p_bbm_data;
 888
 889         if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
 890                                 obj_index])) {
 891                 if (hpios_locked_mem_get_virt_addr(&phw->
 892                                 outstream_host_buffers[phm->obj_index],
 893                                 (void *)&p_bbm_data)) {
 894                         phr->error = HPI_ERROR_INVALID_OPERATION;
 895                         return;
 896                 }
 897                 status = &interface->outstream_host_buffer_status[phm->
 898                         obj_index];
 899                 hpi_init_response(phr, HPI_OBJ_OSTREAM,
 900                         HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0);
 901                 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
 902                 phr->u.d.u.hostbuffer_info.p_status = status;
 903         } else {
 904                 hpi_init_response(phr, HPI_OBJ_OSTREAM,
 905                         HPI_OSTREAM_HOSTBUFFER_GET_INFO,
 906                         HPI_ERROR_INVALID_OPERATION);
 907         }
 908 }
 909
 910 static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
 911         struct hpi_message *phm, struct hpi_response *phr)
 912 {
 913         struct hpi_hw_obj *phw = pao->priv;
 914         u32 command = phm->u.d.u.buffer.command;
 915
 916         if (phw->outstream_host_buffer_size[phm->obj_index]) {
 917                 if (command == HPI_BUFFER_CMD_EXTERNAL
 918                         || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
 919                         phw->outstream_host_buffer_size[phm->obj_index] = 0;
 920                         hw_message(pao, phm, phr);
 921                         /* Tell adapter to stop using the host buffer. */
 922                 }
 923                 if (command == HPI_BUFFER_CMD_EXTERNAL
 924                         || command == HPI_BUFFER_CMD_INTERNAL_FREE)
 925                         hpios_locked_mem_free(&phw->outstream_host_buffers
 926                                 [phm->obj_index]);
 927         }
 928         /* Should HPI_ERROR_INVALID_OPERATION be returned
 929            if no host buffer is allocated? */
 930         else
 931                 hpi_init_response(phr, HPI_OBJ_OSTREAM,
 932                         HPI_OSTREAM_HOSTBUFFER_FREE, 0);
 933
 934 }
 935
 936 static u32 outstream_get_space_available(struct hpi_hostbuffer_status *status)
 937 {
 938         return status->size_in_bytes - (status->host_index -
 939                 status->dSP_index);
 940 }
 941
 942 static void outstream_write(struct hpi_adapter_obj *pao,
 943         struct hpi_message *phm, struct hpi_response *phr)
 944 {
 945         struct hpi_hw_obj *phw = pao->priv;
 946         struct bus_master_interface *interface = phw->p_interface_buffer;
 947         struct hpi_hostbuffer_status *status;
 948         u32 space_available;
 949
 950         if (!phw->outstream_host_buffer_size[phm->obj_index]) {
 951                 /* there  is no BBM buffer, write via message */
 952                 hw_message(pao, phm, phr);
 953                 return;
 954         }
 955
 956         hpi_init_response(phr, phm->object, phm->function, 0);
 957         status = &interface->outstream_host_buffer_status[phm->obj_index];
 958
 959         space_available = outstream_get_space_available(status);
 960         if (space_available < phm->u.d.u.data.data_size) {
 961                 phr->error = HPI_ERROR_INVALID_DATASIZE;
 962                 return;
 963         }
 964
 965         /* HostBuffers is used to indicate host buffer is internally allocated.
 966            otherwise, assumed external, data written externally */
 967         if (phm->u.d.u.data.pb_data
 968                 && hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
 969                                 obj_index])) {
 970                 u8 *p_bbm_data;
 971                 u32 l_first_write;
 972                 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
 973
 974                 if (hpios_locked_mem_get_virt_addr(&phw->
 975                                 outstream_host_buffers[phm->obj_index],
 976                                 (void *)&p_bbm_data)) {
 977                         phr->error = HPI_ERROR_INVALID_OPERATION;
 978                         return;
 979                 }
 980
 981                 /* either all data,
 982                    or enough to fit from current to end of BBM buffer */
 983                 l_first_write =
 984                         min(phm->u.d.u.data.data_size,
 985                         status->size_in_bytes -
 986                         (status->host_index & (status->size_in_bytes - 1)));
 987
 988                 memcpy(p_bbm_data +
 989                         (status->host_index & (status->size_in_bytes - 1)),
 990                         p_app_data, l_first_write);
 991                 /* remaining data if any */
 992                 memcpy(p_bbm_data, p_app_data + l_first_write,
 993                         phm->u.d.u.data.data_size - l_first_write);
 994         }
 995
 996         /*
 997          * This version relies on the DSP code triggering an OStream buffer
 998          * update immediately following a SET_FORMAT call. The host has
 999          * already written data into the BBM buffer, but the DSP won't know
1000          * about it until dwHostIndex is adjusted.
1001          */
1002         if (phw->flag_outstream_just_reset[phm->obj_index]) {
1003                 /* Format can only change after reset. Must tell DSP. */
1004                 u16 function = phm->function;
1005                 phw->flag_outstream_just_reset[phm->obj_index] = 0;
1006                 phm->function = HPI_OSTREAM_SET_FORMAT;
1007                 hw_message(pao, phm, phr);      /* send the format to the DSP */
1008                 phm->function = function;
1009                 if (phr->error)
1010                         return;
1011         }
1012
1013         status->host_index += phm->u.d.u.data.data_size;
1014 }
1015
1016 static void outstream_get_info(struct hpi_adapter_obj *pao,
1017         struct hpi_message *phm, struct hpi_response *phr)
1018 {
1019         struct hpi_hw_obj *phw = pao->priv;
1020         struct bus_master_interface *interface = phw->p_interface_buffer;
1021         struct hpi_hostbuffer_status *status;
1022
1023         if (!phw->outstream_host_buffer_size[phm->obj_index]) {
1024                 hw_message(pao, phm, phr);
1025                 return;
1026         }
1027
1028         hpi_init_response(phr, phm->object, phm->function, 0);
1029
1030         status = &interface->outstream_host_buffer_status[phm->obj_index];
1031
1032         phr->u.d.u.stream_info.state = (u16)status->stream_state;
1033         phr->u.d.u.stream_info.samples_transferred =
1034                 status->samples_processed;
1035         phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
1036         phr->u.d.u.stream_info.data_available =
1037                 status->size_in_bytes - outstream_get_space_available(status);
1038         phr->u.d.u.stream_info.auxiliary_data_available =
1039                 status->auxiliary_data_available;
1040 }
1041
1042 static void outstream_start(struct hpi_adapter_obj *pao,
1043         struct hpi_message *phm, struct hpi_response *phr)
1044 {
1045         hw_message(pao, phm, phr);
1046 }
1047
1048 static void outstream_reset(struct hpi_adapter_obj *pao,
1049         struct hpi_message *phm, struct hpi_response *phr)
1050 {
1051         struct hpi_hw_obj *phw = pao->priv;
1052         phw->flag_outstream_just_reset[phm->obj_index] = 1;
1053         hw_message(pao, phm, phr);
1054 }
1055
1056 static void outstream_open(struct hpi_adapter_obj *pao,
1057         struct hpi_message *phm, struct hpi_response *phr)
1058 {
1059         outstream_reset(pao, phm, phr);
1060 }
1061
1062 /*****************************************************************************/
1063 /* InStream Host buffer functions */
1064
1065 static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
1066         struct hpi_message *phm, struct hpi_response *phr)
1067 {
1068         u16 err = 0;
1069         u32 command = phm->u.d.u.buffer.command;
1070         struct hpi_hw_obj *phw = pao->priv;
1071         struct bus_master_interface *interface = phw->p_interface_buffer;
1072
1073         hpi_init_response(phr, phm->object, phm->function, 0);
1074
1075         if (command == HPI_BUFFER_CMD_EXTERNAL
1076                 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
1077
1078                 phm->u.d.u.buffer.buffer_size =
1079                         roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
1080                 phr->u.d.u.stream_info.data_available =
1081                         phw->instream_host_buffer_size[phm->obj_index];
1082                 phr->u.d.u.stream_info.buffer_size =
1083                         phm->u.d.u.buffer.buffer_size;
1084
1085                 if (phw->instream_host_buffer_size[phm->obj_index] ==
1086                         phm->u.d.u.buffer.buffer_size) {
1087                         /* Same size, no action required */
1088                         return;
1089                 }
1090
1091                 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1092                                         obj_index]))
1093                         hpios_locked_mem_free(&phw->instream_host_buffers
1094                                 [phm->obj_index]);
1095
1096                 err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm->
1097                                 obj_index], phm->u.d.u.buffer.buffer_size,
1098                         pao->pci.pci_dev);
1099
1100                 if (err) {
1101                         phr->error = HPI_ERROR_INVALID_DATASIZE;
1102                         phw->instream_host_buffer_size[phm->obj_index] = 0;
1103                         return;
1104                 }
1105
1106                 err = hpios_locked_mem_get_phys_addr
1107                         (&phw->instream_host_buffers[phm->obj_index],
1108                         &phm->u.d.u.buffer.pci_address);
1109                 /* get the phys addr into msg for single call alloc. Caller
1110                    needs to do this for split alloc so return the phy address */
1111                 phr->u.d.u.stream_info.auxiliary_data_available =
1112                         phm->u.d.u.buffer.pci_address;
1113                 if (err) {
1114                         hpios_locked_mem_free(&phw->instream_host_buffers
1115                                 [phm->obj_index]);
1116                         phw->instream_host_buffer_size[phm->obj_index] = 0;
1117                         phr->error = HPI_ERROR_MEMORY_ALLOC;
1118                         return;
1119                 }
1120         }
1121
1122         if (command == HPI_BUFFER_CMD_EXTERNAL
1123                 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
1124                 struct hpi_hostbuffer_status *status;
1125
1126                 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
1127                                 buffer_size - 1)) {
1128                         HPI_DEBUG_LOG(ERROR,
1129                                 "Buffer size must be 2^N not %d\n",
1130                                 phm->u.d.u.buffer.buffer_size);
1131                         phr->error = HPI_ERROR_INVALID_DATASIZE;
1132                         return;
1133                 }
1134
1135                 phw->instream_host_buffer_size[phm->obj_index] =
1136                         phm->u.d.u.buffer.buffer_size;
1137                 status = &interface->instream_host_buffer_status[phm->
1138                         obj_index];
1139                 status->samples_processed = 0;
1140                 status->stream_state = HPI_STATE_STOPPED;
1141                 status->dSP_index = 0;
1142                 status->host_index = status->dSP_index;
1143                 status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
1144                 status->auxiliary_data_available = 0;
1145
1146                 hw_message(pao, phm, phr);
1147                 if (phr->error
1148                         && hpios_locked_mem_valid(&phw->
1149                                 instream_host_buffers[phm->obj_index])) {
1150                         hpios_locked_mem_free(&phw->instream_host_buffers
1151                                 [phm->obj_index]);
1152                         phw->instream_host_buffer_size[phm->obj_index] = 0;
1153                 }
1154         }
1155 }
1156
1157 static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
1158         struct hpi_message *phm, struct hpi_response *phr)
1159 {
1160         struct hpi_hw_obj *phw = pao->priv;
1161         struct bus_master_interface *interface = phw->p_interface_buffer;
1162         struct hpi_hostbuffer_status *status;
1163         u8 *p_bbm_data;
1164
1165         if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1166                                 obj_index])) {
1167                 if (hpios_locked_mem_get_virt_addr(&phw->
1168                                 instream_host_buffers[phm->obj_index],
1169                                 (void *)&p_bbm_data)) {
1170                         phr->error = HPI_ERROR_INVALID_OPERATION;
1171                         return;
1172                 }
1173                 status = &interface->instream_host_buffer_status[phm->
1174                         obj_index];
1175                 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1176                         HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0);
1177                 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
1178                 phr->u.d.u.hostbuffer_info.p_status = status;
1179         } else {
1180                 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1181                         HPI_ISTREAM_HOSTBUFFER_GET_INFO,
1182                         HPI_ERROR_INVALID_OPERATION);
1183         }
1184 }
1185
1186 static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
1187         struct hpi_message *phm, struct hpi_response *phr)
1188 {
1189         struct hpi_hw_obj *phw = pao->priv;
1190         u32 command = phm->u.d.u.buffer.command;
1191
1192         if (phw->instream_host_buffer_size[phm->obj_index]) {
1193                 if (command == HPI_BUFFER_CMD_EXTERNAL
1194                         || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
1195                         phw->instream_host_buffer_size[phm->obj_index] = 0;
1196                         hw_message(pao, phm, phr);
1197                 }
1198
1199                 if (command == HPI_BUFFER_CMD_EXTERNAL
1200                         || command == HPI_BUFFER_CMD_INTERNAL_FREE)
1201                         hpios_locked_mem_free(&phw->instream_host_buffers
1202                                 [phm->obj_index]);
1203
1204         } else {
1205                 /* Should HPI_ERROR_INVALID_OPERATION be returned
1206                    if no host buffer is allocated? */
1207                 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1208                         HPI_ISTREAM_HOSTBUFFER_FREE, 0);
1209
1210         }
1211
1212 }
1213
1214 static void instream_start(struct hpi_adapter_obj *pao,
1215         struct hpi_message *phm, struct hpi_response *phr)
1216 {
1217         hw_message(pao, phm, phr);
1218 }
1219
1220 static u32 instream_get_bytes_available(struct hpi_hostbuffer_status *status)
1221 {
1222         return status->dSP_index - status->host_index;
1223 }
1224
1225 static void instream_read(struct hpi_adapter_obj *pao,
1226         struct hpi_message *phm, struct hpi_response *phr)
1227 {
1228         struct hpi_hw_obj *phw = pao->priv;
1229         struct bus_master_interface *interface = phw->p_interface_buffer;
1230         struct hpi_hostbuffer_status *status;
1231         u32 data_available;
1232         u8 *p_bbm_data;
1233         u32 l_first_read;
1234         u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
1235
1236         if (!phw->instream_host_buffer_size[phm->obj_index]) {
1237                 hw_message(pao, phm, phr);
1238                 return;
1239         }
1240         hpi_init_response(phr, phm->object, phm->function, 0);
1241
1242         status = &interface->instream_host_buffer_status[phm->obj_index];
1243         data_available = instream_get_bytes_available(status);
1244         if (data_available < phm->u.d.u.data.data_size) {
1245                 phr->error = HPI_ERROR_INVALID_DATASIZE;
1246                 return;
1247         }
1248
1249         if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1250                                 obj_index])) {
1251                 if (hpios_locked_mem_get_virt_addr(&phw->
1252                                 instream_host_buffers[phm->obj_index],
1253                                 (void *)&p_bbm_data)) {
1254                         phr->error = HPI_ERROR_INVALID_OPERATION;
1255                         return;
1256                 }
1257
1258                 /* either all data,
1259                    or enough to fit from current to end of BBM buffer */
1260                 l_first_read =
1261                         min(phm->u.d.u.data.data_size,
1262                         status->size_in_bytes -
1263                         (status->host_index & (status->size_in_bytes - 1)));
1264
1265                 memcpy(p_app_data,
1266                         p_bbm_data +
1267                         (status->host_index & (status->size_in_bytes - 1)),
1268                         l_first_read);
1269                 /* remaining data if any */
1270                 memcpy(p_app_data + l_first_read, p_bbm_data,
1271                         phm->u.d.u.data.data_size - l_first_read);
1272         }
1273         status->host_index += phm->u.d.u.data.data_size;
1274 }
1275
1276 static void instream_get_info(struct hpi_adapter_obj *pao,
1277         struct hpi_message *phm, struct hpi_response *phr)
1278 {
1279         struct hpi_hw_obj *phw = pao->priv;
1280         struct bus_master_interface *interface = phw->p_interface_buffer;
1281         struct hpi_hostbuffer_status *status;
1282         if (!phw->instream_host_buffer_size[phm->obj_index]) {
1283                 hw_message(pao, phm, phr);
1284                 return;
1285         }
1286
1287         status = &interface->instream_host_buffer_status[phm->obj_index];
1288
1289         hpi_init_response(phr, phm->object, phm->function, 0);
1290
1291         phr->u.d.u.stream_info.state = (u16)status->stream_state;
1292         phr->u.d.u.stream_info.samples_transferred =
1293                 status->samples_processed;
1294         phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
1295         phr->u.d.u.stream_info.data_available =
1296                 instream_get_bytes_available(status);
1297         phr->u.d.u.stream_info.auxiliary_data_available =
1298                 status->auxiliary_data_available;
1299 }
1300
1301 /*****************************************************************************/
1302 /* LOW-LEVEL */
1303 #define HPI6205_MAX_FILES_TO_LOAD 2
1304
1305 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
1306         u32 *pos_error_code)
1307 {
1308         struct hpi_hw_obj *phw = pao->priv;
1309         struct dsp_code dsp_code;
1310         u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD];
1311         u16 firmware_id = pao->pci.pci_dev->subsystem_device;
1312         u32 temp;
1313         int dsp = 0, i = 0;
1314         u16 err = 0;
1315
1316         boot_code_id[0] = HPI_ADAPTER_ASI(0x6205);
1317
1318         /* special cases where firmware_id != subsys ID */
1319         switch (firmware_id) {
1320         case HPI_ADAPTER_FAMILY_ASI(0x5000):
1321                 boot_code_id[0] = firmware_id;
1322                 firmware_id = 0;
1323                 break;
1324         case HPI_ADAPTER_FAMILY_ASI(0x5300):
1325         case HPI_ADAPTER_FAMILY_ASI(0x5400):
1326         case HPI_ADAPTER_FAMILY_ASI(0x6300):
1327                 firmware_id = HPI_ADAPTER_FAMILY_ASI(0x6400);
1328                 break;
1329         case HPI_ADAPTER_FAMILY_ASI(0x5600):
1330         case HPI_ADAPTER_FAMILY_ASI(0x6500):
1331                 firmware_id = HPI_ADAPTER_FAMILY_ASI(0x6600);
1332                 break;
1333         case HPI_ADAPTER_FAMILY_ASI(0x8800):
1334                 firmware_id = HPI_ADAPTER_FAMILY_ASI(0x8900);
1335                 break;
1336         }
1337         boot_code_id[1] = firmware_id;
1338
1339         /* reset DSP by writing a 1 to the WARMRESET bit */
1340         temp = C6205_HDCR_WARMRESET;
1341         iowrite32(temp, phw->prHDCR);
1342         hpios_delay_micro_seconds(1000);
1343
1344         /* check that PCI i/f was configured by EEPROM */
1345         temp = ioread32(phw->prHSR);
1346         if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) !=
1347                 C6205_HSR_EEREAD)
1348                 return HPI6205_ERROR_6205_EEPROM;
1349         temp |= 0x04;
1350         /* disable PINTA interrupt */
1351         iowrite32(temp, phw->prHSR);
1352
1353         /* check control register reports PCI boot mode */
1354         temp = ioread32(phw->prHDCR);
1355         if (!(temp & C6205_HDCR_PCIBOOT))
1356                 return HPI6205_ERROR_6205_REG;
1357
1358         /* try writing a few numbers to the DSP page register */
1359         /* and reading them back. */
1360         temp = 3;
1361         iowrite32(temp, phw->prDSPP);
1362         if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1363                 return HPI6205_ERROR_6205_DSPPAGE;
1364         temp = 2;
1365         iowrite32(temp, phw->prDSPP);
1366         if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1367                 return HPI6205_ERROR_6205_DSPPAGE;
1368         temp = 1;
1369         iowrite32(temp, phw->prDSPP);
1370         if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1371                 return HPI6205_ERROR_6205_DSPPAGE;
1372         /* reset DSP page to the correct number */
1373         temp = 0;
1374         iowrite32(temp, phw->prDSPP);
1375         if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1376                 return HPI6205_ERROR_6205_DSPPAGE;
1377         phw->dsp_page = 0;
1378
1379         /* release 6713 from reset before 6205 is bootloaded.
1380            This ensures that the EMIF is inactive,
1381            and the 6713 HPI gets the correct bootmode etc
1382          */
1383         if (boot_code_id[1] != 0) {
1384                 /* DSP 1 is a C6713 */
1385                 /* CLKX0 <- '1' release the C6205 bootmode pulldowns */
1386                 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002202);
1387                 hpios_delay_micro_seconds(100);
1388                 /* Reset the 6713 #1 - revB */
1389                 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
1390
1391                 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1392                 boot_loader_read_mem32(pao, 0, 0);
1393
1394                 hpios_delay_micro_seconds(100);
1395                 /* Release C6713 from reset - revB */
1396                 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4);
1397                 hpios_delay_micro_seconds(100);
1398         }
1399
1400         for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) {
1401                 /* is there a DSP to load? */
1402                 if (boot_code_id[dsp] == 0)
1403                         continue;
1404
1405                 err = boot_loader_config_emif(pao, dsp);
1406                 if (err)
1407                         return err;
1408
1409                 err = boot_loader_test_internal_memory(pao, dsp);
1410                 if (err)
1411                         return err;
1412
1413                 err = boot_loader_test_external_memory(pao, dsp);
1414                 if (err)
1415                         return err;
1416
1417                 err = boot_loader_test_pld(pao, dsp);
1418                 if (err)
1419                         return err;
1420
1421                 /* write the DSP code down into the DSPs memory */
1422                 dsp_code.ps_dev = pao->pci.pci_dev;
1423                 err = hpi_dsp_code_open(boot_code_id[dsp], &dsp_code,
1424                         pos_error_code);
1425                 if (err)
1426                         return err;
1427
1428                 while (1) {
1429                         u32 length;
1430                         u32 address;
1431                         u32 type;
1432                         u32 *pcode;
1433
1434                         err = hpi_dsp_code_read_word(&dsp_code, &length);
1435                         if (err)
1436                                 break;
1437                         if (length == 0xFFFFFFFF)
1438                                 break;  /* end of code */
1439
1440                         err = hpi_dsp_code_read_word(&dsp_code, &address);
1441                         if (err)
1442                                 break;
1443                         err = hpi_dsp_code_read_word(&dsp_code, &type);
1444                         if (err)
1445                                 break;
1446                         err = hpi_dsp_code_read_block(length, &dsp_code,
1447                                 &pcode);
1448                         if (err)
1449                                 break;
1450                         for (i = 0; i < (int)length; i++) {
1451                                 boot_loader_write_mem32(pao, dsp, address,
1452                                         *pcode);
1453                                 /* dummy read every 4 words */
1454                                 /* for 6205 advisory 1.4.4 */
1455                                 if (i % 4 == 0)
1456                                         boot_loader_read_mem32(pao, dsp,
1457                                                 address);
1458                                 pcode++;
1459                                 address += 4;
1460                         }
1461
1462                 }
1463                 if (err) {
1464                         hpi_dsp_code_close(&dsp_code);
1465                         return err;
1466                 }
1467
1468                 /* verify code */
1469                 hpi_dsp_code_rewind(&dsp_code);
1470                 while (1) {
1471                         u32 length = 0;
1472                         u32 address = 0;
1473                         u32 type = 0;
1474                         u32 *pcode = NULL;
1475                         u32 data = 0;
1476
1477                         hpi_dsp_code_read_word(&dsp_code, &length);
1478                         if (length == 0xFFFFFFFF)
1479                                 break;  /* end of code */
1480
1481                         hpi_dsp_code_read_word(&dsp_code, &address);
1482                         hpi_dsp_code_read_word(&dsp_code, &type);
1483                         hpi_dsp_code_read_block(length, &dsp_code, &pcode);
1484
1485                         for (i = 0; i < (int)length; i++) {
1486                                 data = boot_loader_read_mem32(pao, dsp,
1487                                         address);
1488                                 if (data != *pcode) {
1489                                         err = 0;
1490                                         break;
1491                                 }
1492                                 pcode++;
1493                                 address += 4;
1494                         }
1495                         if (err)
1496                                 break;
1497                 }
1498                 hpi_dsp_code_close(&dsp_code);
1499                 if (err)
1500                         return err;
1501         }
1502
1503         /* After bootloading all DSPs, start DSP0 running
1504          * The DSP0 code will handle starting and synchronizing with its slaves
1505          */
1506         if (phw->p_interface_buffer) {
1507                 /* we need to tell the card the physical PCI address */
1508                 u32 physicalPC_iaddress;
1509                 struct bus_master_interface *interface =
1510                         phw->p_interface_buffer;
1511                 u32 host_mailbox_address_on_dsp;
1512                 u32 physicalPC_iaddress_verify = 0;
1513                 int time_out = 10;
1514                 /* set ack so we know when DSP is ready to go */
1515                 /* (dwDspAck will be changed to HIF_RESET) */
1516                 interface->dsp_ack = H620_HIF_UNKNOWN;
1517                 wmb();  /* ensure ack is written before dsp writes back */
1518
1519                 err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem,
1520                         &physicalPC_iaddress);
1521
1522                 /* locate the host mailbox on the DSP. */
1523                 host_mailbox_address_on_dsp = 0x80000000;
1524                 while ((physicalPC_iaddress != physicalPC_iaddress_verify)
1525                         && time_out--) {
1526                         boot_loader_write_mem32(pao, 0,
1527                                 host_mailbox_address_on_dsp,
1528                                 physicalPC_iaddress);
1529                         physicalPC_iaddress_verify =
1530                                 boot_loader_read_mem32(pao, 0,
1531                                 host_mailbox_address_on_dsp);
1532                 }
1533         }
1534         HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n");
1535         /* enable interrupts */
1536         temp = ioread32(phw->prHSR);
1537         temp &= ~(u32)C6205_HSR_INTAM;
1538         iowrite32(temp, phw->prHSR);
1539
1540         /* start code running... */
1541         temp = ioread32(phw->prHDCR);
1542         temp |= (u32)C6205_HDCR_DSPINT;
1543         iowrite32(temp, phw->prHDCR);
1544
1545         /* give the DSP 10ms to start up */
1546         hpios_delay_micro_seconds(10000);
1547         return err;
1548
1549 }
1550
1551 /*****************************************************************************/
1552 /* Bootloader utility functions */
1553
1554 static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
1555         u32 address)
1556 {
1557         struct hpi_hw_obj *phw = pao->priv;
1558         u32 data = 0;
1559         __iomem u32 *p_data;
1560
1561         if (dsp_index == 0) {
1562                 /* DSP 0 is always C6205 */
1563                 if ((address >= 0x01800000) & (address < 0x02000000)) {
1564                         /* BAR1 register access */
1565                         p_data = pao->pci.ap_mem_base[1] +
1566                                 (address & 0x007fffff) /
1567                                 sizeof(*pao->pci.ap_mem_base[1]);
1568                         /* HPI_DEBUG_LOG(WARNING,
1569                            "BAR1 access %08x\n", dwAddress); */
1570                 } else {
1571                         u32 dw4M_page = address >> 22L;
1572                         if (dw4M_page != phw->dsp_page) {
1573                                 phw->dsp_page = dw4M_page;
1574                                 /* *INDENT OFF* */
1575                                 iowrite32(phw->dsp_page, phw->prDSPP);
1576                                 /* *INDENT-ON* */
1577                         }
1578                         address &= 0x3fffff;    /* address within 4M page */
1579                         /* BAR0 memory access */
1580                         p_data = pao->pci.ap_mem_base[0] +
1581                                 address / sizeof(u32);
1582                 }
1583                 data = ioread32(p_data);
1584         } else if (dsp_index == 1) {
1585                 /* DSP 1 is a C6713 */
1586                 u32 lsb;
1587                 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
1588                 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1589                 lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR);
1590                 data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR);
1591                 data = (data << 16) | (lsb & 0xFFFF);
1592         }
1593         return data;
1594 }
1595
1596 static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
1597         int dsp_index, u32 address, u32 data)
1598 {
1599         struct hpi_hw_obj *phw = pao->priv;
1600         __iomem u32 *p_data;
1601         /*      u32 dwVerifyData=0; */
1602
1603         if (dsp_index == 0) {
1604                 /* DSP 0 is always C6205 */
1605                 if ((address >= 0x01800000) & (address < 0x02000000)) {
1606                         /* BAR1 - DSP  register access using */
1607                         /* Non-prefetchable PCI access */
1608                         p_data = pao->pci.ap_mem_base[1] +
1609                                 (address & 0x007fffff) /
1610                                 sizeof(*pao->pci.ap_mem_base[1]);
1611                 } else {
1612                         /* BAR0 access - all of DSP memory using */
1613                         /* pre-fetchable PCI access */
1614                         u32 dw4M_page = address >> 22L;
1615                         if (dw4M_page != phw->dsp_page) {
1616                                 phw->dsp_page = dw4M_page;
1617                                 /* *INDENT-OFF* */
1618                                 iowrite32(phw->dsp_page, phw->prDSPP);
1619                                 /* *INDENT-ON* */
1620                         }
1621                         address &= 0x3fffff;    /* address within 4M page */
1622                         p_data = pao->pci.ap_mem_base[0] +
1623                                 address / sizeof(u32);
1624                 }
1625                 iowrite32(data, p_data);
1626         } else if (dsp_index == 1) {
1627                 /* DSP 1 is a C6713 */
1628                 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
1629                 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1630
1631                 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1632                 boot_loader_read_mem32(pao, 0, 0);
1633
1634                 boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data);
1635                 boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16);
1636
1637                 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1638                 boot_loader_read_mem32(pao, 0, 0);
1639         }
1640 }
1641
1642 static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index)
1643 {
1644         if (dsp_index == 0) {
1645                 u32 setting;
1646
1647                 /* DSP 0 is always C6205 */
1648
1649                 /* Set the EMIF */
1650                 /* memory map of C6205 */
1651                 /* 00000000-0000FFFF    16Kx32 internal program */
1652                 /* 00400000-00BFFFFF    CE0     2Mx32 SDRAM running @ 100MHz */
1653
1654                 /* EMIF config */
1655                 /*------------ */
1656                 /* Global EMIF control */
1657                 boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779);
1658 #define WS_OFS 28
1659 #define WST_OFS 22
1660 #define WH_OFS 20
1661 #define RS_OFS 16
1662 #define RST_OFS 8
1663 #define MTYPE_OFS 4
1664 #define RH_OFS 0
1665
1666                 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */
1667                 setting = 0x00000030;
1668                 boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting);
1669                 if (setting != boot_loader_read_mem32(pao, dsp_index,
1670                                 0x01800008))
1671                         return HPI6205_ERROR_DSP_EMIF;
1672
1673                 /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */
1674                 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1675                 /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */
1676                 /* WST should be 71, but 63  is max possible */
1677                 setting =
1678                         (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) |
1679                         (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1680                         (2L << MTYPE_OFS);
1681                 boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting);
1682                 if (setting != boot_loader_read_mem32(pao, dsp_index,
1683                                 0x01800004))
1684                         return HPI6205_ERROR_DSP_EMIF;
1685
1686                 /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */
1687                 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1688                 /* plenty of wait states */
1689                 setting =
1690                         (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) |
1691                         (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1692                         (2L << MTYPE_OFS);
1693                 boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting);
1694                 if (setting != boot_loader_read_mem32(pao, dsp_index,
1695                                 0x01800010))
1696                         return HPI6205_ERROR_DSP_EMIF;
1697
1698                 /* EMIF CE3 setup - 32 bit async. */
1699                 /* This is the PLD on the ASI5000 cards only */
1700                 setting =
1701                         (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) |
1702                         (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) |
1703                         (2L << MTYPE_OFS);
1704                 boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting);
1705                 if (setting != boot_loader_read_mem32(pao, dsp_index,
1706                                 0x01800014))
1707                         return HPI6205_ERROR_DSP_EMIF;
1708
1709                 /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */
1710                 /*  need to use this else DSP code crashes? */
1711                 boot_loader_write_mem32(pao, dsp_index, 0x01800018,
1712                         0x07117000);
1713
1714                 /* EMIF SDRAM Refresh Timing */
1715                 /* EMIF SDRAM timing  (orig = 0x410, emulator = 0x61a) */
1716                 boot_loader_write_mem32(pao, dsp_index, 0x0180001C,
1717                         0x00000410);
1718
1719         } else if (dsp_index == 1) {
1720                 /* test access to the C6713s HPI registers */
1721                 u32 write_data = 0, read_data = 0, i = 0;
1722
1723                 /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */
1724                 write_data = 1;
1725                 boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data);
1726                 boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data);
1727                 /* C67 HPI is on lower 16bits of 32bit EMIF */
1728                 read_data =
1729                         0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR);
1730                 if (write_data != read_data) {
1731                         HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data,
1732                                 read_data);
1733                         return HPI6205_ERROR_C6713_HPIC;
1734                 }
1735                 /* HPIA - walking ones test */
1736                 write_data = 1;
1737                 for (i = 0; i < 32; i++) {
1738                         boot_loader_write_mem32(pao, 0, HPIAL_ADDR,
1739                                 write_data);
1740                         boot_loader_write_mem32(pao, 0, HPIAH_ADDR,
1741                                 (write_data >> 16));
1742                         read_data =
1743                                 0xFFFF & boot_loader_read_mem32(pao, 0,
1744                                 HPIAL_ADDR);
1745                         read_data =
1746                                 read_data | ((0xFFFF &
1747                                         boot_loader_read_mem32(pao, 0,
1748                                                 HPIAH_ADDR))
1749                                 << 16);
1750                         if (read_data != write_data) {
1751                                 HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n",
1752                                         write_data, read_data);
1753                                 return HPI6205_ERROR_C6713_HPIA;
1754                         }
1755                         write_data = write_data << 1;
1756                 }
1757
1758                 /* setup C67x PLL
1759                  *  ** C6713 datasheet says we cannot program PLL from HPI,
1760                  * and indeed if we try to set the PLL multiply from the HPI,
1761                  * the PLL does not seem to lock, so we enable the PLL and
1762                  * use the default multiply of x 7, which for a 27MHz clock
1763                  * gives a DSP speed of 189MHz
1764                  */
1765                 /* bypass PLL */
1766                 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000);
1767                 hpios_delay_micro_seconds(1000);
1768                 /* EMIF = 189/3=63MHz */
1769                 boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002);
1770                 /* peri = 189/2 */
1771                 boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001);
1772                 /* cpu  = 189/1 */
1773                 boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000);
1774                 hpios_delay_micro_seconds(1000);
1775                 /* ** SGT test to take GPO3 high when we start the PLL */
1776                 /* and low when the delay is completed */
1777                 /* FSX0 <- '1' (GPO3) */
1778                 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A);
1779                 /* PLL not bypassed */
1780                 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001);
1781                 hpios_delay_micro_seconds(1000);
1782                 /* FSX0 <- '0' (GPO3) */
1783                 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02);
1784
1785                 /* 6205 EMIF CE1 resetup - 32 bit async. */
1786                 /* Now 6713 #1 is running at 189MHz can reduce waitstates */
1787                 boot_loader_write_mem32(pao, 0, 0x01800004,     /* CE1 */
1788                         (1L << WS_OFS) | (8L << WST_OFS) | (1L << WH_OFS) |
1789                         (1L << RS_OFS) | (12L << RST_OFS) | (1L << RH_OFS) |
1790                         (2L << MTYPE_OFS));
1791
1792                 hpios_delay_micro_seconds(1000);
1793
1794                 /* check that we can read one of the PLL registers */
1795                 /* PLL should not be bypassed! */
1796                 if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF)
1797                         != 0x0001) {
1798                         return HPI6205_ERROR_C6713_PLL;
1799                 }
1800                 /* setup C67x EMIF  (note this is the only use of
1801                    BAR1 via BootLoader_WriteMem32) */
1802                 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL,
1803                         0x000034A8);
1804                 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0,
1805                         0x00000030);
1806                 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT,
1807                         0x001BDF29);
1808                 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL,
1809                         0x47117000);
1810                 boot_loader_write_mem32(pao, dsp_index,
1811                         C6713_EMIF_SDRAMTIMING, 0x00000410);
1812
1813                 hpios_delay_micro_seconds(1000);
1814         } else if (dsp_index == 2) {
1815                 /* DSP 2 is a C6713 */
1816         }
1817
1818         return 0;
1819 }
1820
1821 static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
1822         u32 start_address, u32 length)
1823 {
1824         u32 i = 0, j = 0;
1825         u32 test_addr = 0;
1826         u32 test_data = 0, data = 0;
1827
1828         length = 1000;
1829
1830         /* for 1st word, test each bit in the 32bit word, */
1831         /* dwLength specifies number of 32bit words to test */
1832         /*for(i=0; i<dwLength; i++) */
1833         i = 0;
1834         {
1835                 test_addr = start_address + i * 4;
1836                 test_data = 0x00000001;
1837                 for (j = 0; j < 32; j++) {
1838                         boot_loader_write_mem32(pao, dsp_index, test_addr,
1839                                 test_data);
1840                         data = boot_loader_read_mem32(pao, dsp_index,
1841                                 test_addr);
1842                         if (data != test_data) {
1843                                 HPI_DEBUG_LOG(VERBOSE,
1844                                         "Memtest error details  "
1845                                         "%08x %08x %08x %i\n", test_addr,
1846                                         test_data, data, dsp_index);
1847                                 return 1;       /* error */
1848                         }
1849                         test_data = test_data << 1;
1850                 }       /* for(j) */
1851         }       /* for(i) */
1852
1853         /* for the next 100 locations test each location, leaving it as zero */
1854         /* write a zero to the next word in memory before we read */
1855         /* the previous write to make sure every memory location is unique */
1856         for (i = 0; i < 100; i++) {
1857                 test_addr = start_address + i * 4;
1858                 test_data = 0xA5A55A5A;
1859                 boot_loader_write_mem32(pao, dsp_index, test_addr, test_data);
1860                 boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0);
1861                 data = boot_loader_read_mem32(pao, dsp_index, test_addr);
1862                 if (data != test_data) {
1863                         HPI_DEBUG_LOG(VERBOSE,
1864                                 "Memtest error details  "
1865                                 "%08x %08x %08x %i\n", test_addr, test_data,
1866                                 data, dsp_index);
1867                         return 1;       /* error */
1868                 }
1869                 /* leave location as zero */
1870                 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1871         }
1872
1873         /* zero out entire memory block */
1874         for (i = 0; i < length; i++) {
1875                 test_addr = start_address + i * 4;
1876                 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1877         }
1878         return 0;
1879 }
1880
1881 static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
1882         int dsp_index)
1883 {
1884         int err = 0;
1885         if (dsp_index == 0) {
1886                 /* DSP 0 is a C6205 */
1887                 /* 64K prog mem */
1888                 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1889                         0x10000);
1890                 if (!err)
1891                         /* 64K data mem */
1892                         err = boot_loader_test_memory(pao, dsp_index,
1893                                 0x80000000, 0x10000);
1894         } else if (dsp_index == 1) {
1895                 /* DSP 1 is a C6713 */
1896                 /* 192K internal mem */
1897                 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1898                         0x30000);
1899                 if (!err)
1900                         /* 64K internal mem / L2 cache */
1901                         err = boot_loader_test_memory(pao, dsp_index,
1902                                 0x00030000, 0x10000);
1903         }
1904
1905         if (err)
1906                 return HPI6205_ERROR_DSP_INTMEM;
1907         else
1908                 return 0;
1909 }
1910
1911 static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
1912         int dsp_index)
1913 {
1914         u32 dRAM_start_address = 0;
1915         u32 dRAM_size = 0;
1916
1917         if (dsp_index == 0) {
1918                 /* only test for SDRAM if an ASI5000 card */
1919                 if (pao->pci.pci_dev->subsystem_device == 0x5000) {
1920                         /* DSP 0 is always C6205 */
1921                         dRAM_start_address = 0x00400000;
1922                         dRAM_size = 0x200000;
1923                         /*dwDRAMinc=1024; */
1924                 } else
1925                         return 0;
1926         } else if (dsp_index == 1) {
1927                 /* DSP 1 is a C6713 */
1928                 dRAM_start_address = 0x80000000;
1929                 dRAM_size = 0x200000;
1930                 /*dwDRAMinc=1024; */
1931         }
1932
1933         if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address,
1934                         dRAM_size))
1935                 return HPI6205_ERROR_DSP_EXTMEM;
1936         return 0;
1937 }
1938
1939 static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index)
1940 {
1941         u32 data = 0;
1942         if (dsp_index == 0) {
1943                 /* only test for DSP0 PLD on ASI5000 card */
1944                 if (pao->pci.pci_dev->subsystem_device == 0x5000) {
1945                         /* PLD is located at CE3=0x03000000 */
1946                         data = boot_loader_read_mem32(pao, dsp_index,
1947                                 0x03000008);
1948                         if ((data & 0xF) != 0x5)
1949                                 return HPI6205_ERROR_DSP_PLD;
1950                         data = boot_loader_read_mem32(pao, dsp_index,
1951                                 0x0300000C);
1952                         if ((data & 0xF) != 0xA)
1953                                 return HPI6205_ERROR_DSP_PLD;
1954                 }
1955         } else if (dsp_index == 1) {
1956                 /* DSP 1 is a C6713 */
1957                 if (pao->pci.pci_dev->subsystem_device == 0x8700) {
1958                         /* PLD is located at CE1=0x90000000 */
1959                         data = boot_loader_read_mem32(pao, dsp_index,
1960                                 0x90000010);
1961                         if ((data & 0xFF) != 0xAA)
1962                                 return HPI6205_ERROR_DSP_PLD;
1963                         /* 8713 - LED on */
1964                         boot_loader_write_mem32(pao, dsp_index, 0x90000000,
1965                                 0x02);
1966                 }
1967         }
1968         return 0;
1969 }
1970
1971 /** Transfer data to or from DSP
1972  nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA
1973 */
1974 static short hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data,
1975         u32 data_size, int operation)
1976 {
1977         struct hpi_hw_obj *phw = pao->priv;
1978         u32 data_transferred = 0;
1979         u16 err = 0;
1980 #ifndef HPI6205_NO_HSR_POLL
1981         u32 time_out;
1982 #endif
1983         u32 temp2;
1984         struct bus_master_interface *interface = phw->p_interface_buffer;
1985
1986         if (!p_data)
1987                 return HPI_ERROR_INVALID_DATA_POINTER;
1988
1989         data_size &= ~3L;       /* round data_size down to nearest 4 bytes */
1990
1991         /* make sure state is IDLE */
1992         if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT))
1993                 return HPI_ERROR_DSP_HARDWARE;
1994
1995         while (data_transferred < data_size) {
1996                 u32 this_copy = data_size - data_transferred;
1997
1998                 if (this_copy > HPI6205_SIZEOF_DATA)
1999                         this_copy = HPI6205_SIZEOF_DATA;
2000
2001                 if (operation == H620_HIF_SEND_DATA)
2002                         memcpy((void *)&interface->u.b_data[0],
2003                                 &p_data[data_transferred], this_copy);
2004
2005                 interface->transfer_size_in_bytes = this_copy;
2006
2007 #ifdef HPI6205_NO_HSR_POLL
2008                 /* DSP must change this back to nOperation */
2009                 interface->dsp_ack = H620_HIF_IDLE;
2010 #endif
2011
2012                 send_dsp_command(phw, operation);
2013
2014 #ifdef HPI6205_NO_HSR_POLL
2015                 temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT);
2016                 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
2017                         HPI6205_TIMEOUT - temp2, this_copy);
2018
2019                 if (!temp2) {
2020                         /* timed out */
2021                         HPI_DEBUG_LOG(ERROR,
2022                                 "Timed out waiting for " "state %d got %d\n",
2023                                 operation, interface->dsp_ack);
2024
2025                         break;
2026                 }
2027 #else
2028                 /* spin waiting on the result */
2029                 time_out = HPI6205_TIMEOUT;
2030                 temp2 = 0;
2031                 while ((temp2 == 0) && time_out--) {
2032                         /* give 16k bus mastering transfer time to happen */
2033                         /*(16k / 132Mbytes/s = 122usec) */
2034                         hpios_delay_micro_seconds(20);
2035                         temp2 = ioread32(phw->prHSR);
2036                         temp2 &= C6205_HSR_INTSRC;
2037                 }
2038                 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
2039                         HPI6205_TIMEOUT - time_out, this_copy);
2040                 if (temp2 == C6205_HSR_INTSRC) {
2041                         HPI_DEBUG_LOG(VERBOSE,
2042                                 "Interrupt from HIF <data> OK\n");
2043                         /*
2044                            if(interface->dwDspAck != nOperation) {
2045                            HPI_DEBUG_LOG(DEBUG("interface->dwDspAck=%d,
2046                            expected %d \n",
2047                            interface->dwDspAck,nOperation);
2048                            }
2049                          */
2050                 }
2051 /* need to handle this differently... */
2052                 else {
2053                         HPI_DEBUG_LOG(ERROR,
2054                                 "Interrupt from HIF <data> BAD\n");
2055                         err = HPI_ERROR_DSP_HARDWARE;
2056                 }
2057
2058                 /* reset the interrupt from the DSP */
2059                 iowrite32(C6205_HSR_INTSRC, phw->prHSR);
2060 #endif
2061                 if (operation == H620_HIF_GET_DATA)
2062                         memcpy(&p_data[data_transferred],
2063                                 (void *)&interface->u.b_data[0], this_copy);
2064
2065                 data_transferred += this_copy;
2066         }
2067         if (interface->dsp_ack != operation)
2068                 HPI_DEBUG_LOG(DEBUG, "interface->dsp_ack=%d, expected %d\n",
2069                         interface->dsp_ack, operation);
2070         /*                      err=HPI_ERROR_DSP_HARDWARE; */
2071
2072         send_dsp_command(phw, H620_HIF_IDLE);
2073
2074         return err;
2075 }
2076
2077 /* wait for up to timeout_us microseconds for the DSP
2078    to signal state by DMA into dwDspAck
2079 */
2080 static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us)
2081 {
2082         struct bus_master_interface *interface = phw->p_interface_buffer;
2083         int t = timeout_us / 4;
2084
2085         rmb();  /* ensure interface->dsp_ack is up to date */
2086         while ((interface->dsp_ack != state) && --t) {
2087                 hpios_delay_micro_seconds(4);
2088                 rmb();  /* DSP changes dsp_ack by DMA */
2089         }
2090
2091         /*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */
2092         return t * 4;
2093 }
2094
2095 /* set the busmaster interface to cmd, then interrupt the DSP */
2096 static void send_dsp_command(struct hpi_hw_obj *phw, int cmd)
2097 {
2098         struct bus_master_interface *interface = phw->p_interface_buffer;
2099
2100         u32 r;
2101
2102         interface->host_cmd = cmd;
2103         wmb();  /* DSP gets state by DMA, make sure it is written to memory */
2104         /* before we interrupt the DSP */
2105         r = ioread32(phw->prHDCR);
2106         r |= (u32)C6205_HDCR_DSPINT;
2107         iowrite32(r, phw->prHDCR);
2108         r &= ~(u32)C6205_HDCR_DSPINT;
2109         iowrite32(r, phw->prHDCR);
2110 }
2111
2112 static unsigned int message_count;
2113
2114 static u16 message_response_sequence(struct hpi_adapter_obj *pao,
2115         struct hpi_message *phm, struct hpi_response *phr)
2116 {
2117 #ifndef HPI6205_NO_HSR_POLL
2118         u32 temp2;
2119 #endif
2120         u32 time_out, time_out2;
2121         struct hpi_hw_obj *phw = pao->priv;
2122         struct bus_master_interface *interface = phw->p_interface_buffer;
2123         u16 err = 0;
2124
2125         message_count++;
2126         if (phm->size > sizeof(interface->u)) {
2127                 phr->error = HPI_ERROR_MESSAGE_BUFFER_TOO_SMALL;
2128                 phr->specific_error = sizeof(interface->u);
2129                 phr->size = sizeof(struct hpi_response_header);
2130                 HPI_DEBUG_LOG(ERROR,
2131                         "message len %d too big for buffer %ld \n", phm->size,
2132                         sizeof(interface->u));
2133                 return 0;
2134         }
2135
2136         /* Assume buffer of type struct bus_master_interface
2137            is allocated "noncacheable" */
2138
2139         if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2140                 HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n");
2141                 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
2142         }
2143
2144         memcpy(&interface->u.message_buffer, phm, phm->size);
2145         /* signal we want a response */
2146         send_dsp_command(phw, H620_HIF_GET_RESP);
2147
2148         time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT);
2149
2150         if (!time_out2) {
2151                 HPI_DEBUG_LOG(ERROR,
2152                         "(%u) Timed out waiting for " "GET_RESP state [%x]\n",
2153                         message_count, interface->dsp_ack);
2154         } else {
2155                 HPI_DEBUG_LOG(VERBOSE,
2156                         "(%u) transition to GET_RESP after %u\n",
2157                         message_count, HPI6205_TIMEOUT - time_out2);
2158         }
2159         /* spin waiting on HIF interrupt flag (end of msg process) */
2160         time_out = HPI6205_TIMEOUT;
2161
2162 #ifndef HPI6205_NO_HSR_POLL
2163         temp2 = 0;
2164         while ((temp2 == 0) && --time_out) {
2165                 temp2 = ioread32(phw->prHSR);
2166                 temp2 &= C6205_HSR_INTSRC;
2167                 hpios_delay_micro_seconds(1);
2168         }
2169         if (temp2 == C6205_HSR_INTSRC) {
2170                 rmb();  /* ensure we see latest value for dsp_ack */
2171                 if ((interface->dsp_ack != H620_HIF_GET_RESP)) {
2172                         HPI_DEBUG_LOG(DEBUG,
2173                                 "(%u)interface->dsp_ack(0x%x) != "
2174                                 "H620_HIF_GET_RESP, t=%u\n", message_count,
2175                                 interface->dsp_ack,
2176                                 HPI6205_TIMEOUT - time_out);
2177                 } else {
2178                         HPI_DEBUG_LOG(VERBOSE,
2179                                 "(%u)int with GET_RESP after %u\n",
2180                                 message_count, HPI6205_TIMEOUT - time_out);
2181                 }
2182
2183         } else {
2184                 /* can we do anything else in response to the error ? */
2185                 HPI_DEBUG_LOG(ERROR,
2186                         "Interrupt from HIF module BAD (function %x)\n",
2187                         phm->function);
2188         }
2189
2190         /* reset the interrupt from the DSP */
2191         iowrite32(C6205_HSR_INTSRC, phw->prHSR);
2192 #endif
2193
2194         /* read the result */
2195         if (time_out) {
2196                 if (interface->u.response_buffer.size <= phr->size)
2197                         memcpy(phr, &interface->u.response_buffer,
2198                                 interface->u.response_buffer.size);
2199                 else {
2200                         HPI_DEBUG_LOG(ERROR,
2201                                 "response len %d too big for buffer %d\n",
2202                                 interface->u.response_buffer.size, phr->size);
2203                         memcpy(phr, &interface->u.response_buffer,
2204                                 sizeof(struct hpi_response_header));
2205                         phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL;
2206                         phr->specific_error =
2207                                 interface->u.response_buffer.size;
2208                         phr->size = sizeof(struct hpi_response_header);
2209                 }
2210         }
2211         /* set interface back to idle */
2212         send_dsp_command(phw, H620_HIF_IDLE);
2213
2214         if (!time_out || !time_out2) {
2215                 HPI_DEBUG_LOG(DEBUG, "something timed out!\n");
2216                 return HPI6205_ERROR_MSG_RESP_TIMEOUT;
2217         }
2218         /* special case for adapter close - */
2219         /* wait for the DSP to indicate it is idle */
2220         if (phm->function == HPI_ADAPTER_CLOSE) {
2221                 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2222                         HPI_DEBUG_LOG(DEBUG,
2223                                 "Timeout waiting for idle "
2224                                 "(on adapter_close)\n");
2225                         return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
2226                 }
2227         }
2228         err = hpi_validate_response(phm, phr);
2229         return err;
2230 }
2231
2232 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
2233         struct hpi_response *phr)
2234 {
2235
2236         u16 err = 0;
2237
2238         hpios_dsplock_lock(pao);
2239
2240         err = message_response_sequence(pao, phm, phr);
2241
2242         /* maybe an error response */
2243         if (err) {
2244                 /* something failed in the HPI/DSP interface */
2245                 phr->error = err;
2246                 pao->dsp_crashed++;
2247
2248                 /* just the header of the response is valid */
2249                 phr->size = sizeof(struct hpi_response_header);
2250                 goto err;
2251         } else
2252                 pao->dsp_crashed = 0;
2253
2254         if (phr->error != 0)    /* something failed in the DSP */
2255                 goto err;
2256
2257         switch (phm->function) {
2258         case HPI_OSTREAM_WRITE:
2259         case HPI_ISTREAM_ANC_WRITE:
2260                 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
2261                         phm->u.d.u.data.data_size, H620_HIF_SEND_DATA);
2262                 break;
2263
2264         case HPI_ISTREAM_READ:
2265         case HPI_OSTREAM_ANC_READ:
2266                 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
2267                         phm->u.d.u.data.data_size, H620_HIF_GET_DATA);
2268                 break;
2269
2270         case HPI_CONTROL_SET_STATE:
2271                 if (phm->object == HPI_OBJ_CONTROLEX
2272                         && phm->u.cx.attribute == HPI_COBRANET_SET_DATA)
2273                         err = hpi6205_transfer_data(pao,
2274                                 phm->u.cx.u.cobranet_bigdata.pb_data,
2275                                 phm->u.cx.u.cobranet_bigdata.byte_count,
2276                                 H620_HIF_SEND_DATA);
2277                 break;
2278
2279         case HPI_CONTROL_GET_STATE:
2280                 if (phm->object == HPI_OBJ_CONTROLEX
2281                         && phm->u.cx.attribute == HPI_COBRANET_GET_DATA)
2282                         err = hpi6205_transfer_data(pao,
2283                                 phm->u.cx.u.cobranet_bigdata.pb_data,
2284                                 phr->u.cx.u.cobranet_data.byte_count,
2285                                 H620_HIF_GET_DATA);
2286                 break;
2287         }
2288         phr->error = err;
2289
2290 err:
2291         hpios_dsplock_unlock(pao);
2292
2293         return;
2294 }