2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
23 #include <sound/driver.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gameport.h>
31 #include <linux/moduleparam.h>
32 #include <linux/mutex.h>
33 #include <sound/core.h>
34 #include <sound/info.h>
35 #include <sound/control.h>
36 #include <sound/pcm.h>
37 #include <sound/rawmidi.h>
38 #include <sound/mpu401.h>
39 #include <sound/opl3.h>
41 #include <sound/asoundef.h>
42 #include <sound/initval.h>
44 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
45 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
46 MODULE_LICENSE("GPL");
47 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
50 "{C-Media,CMI8338B}}");
52 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
53 #define SUPPORT_JOYSTICK 1
56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
59 static long mpu_port[SNDRV_CARDS];
60 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
62 #ifdef SUPPORT_JOYSTICK
63 static int joystick_port[SNDRV_CARDS];
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
68 module_param_array(id, charp, NULL, 0444);
69 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
70 module_param_array(enable, bool, NULL, 0444);
71 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
72 module_param_array(mpu_port, long, NULL, 0444);
73 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
74 module_param_array(fm_port, long, NULL, 0444);
75 MODULE_PARM_DESC(fm_port, "FM port.");
76 module_param_array(soft_ac3, bool, NULL, 0444);
77 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
78 #ifdef SUPPORT_JOYSTICK
79 module_param_array(joystick_port, int, NULL, 0444);
80 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
84 * CM8x38 registers definition
87 #define CM_REG_FUNCTRL0 0x00
88 #define CM_RST_CH1 0x00080000
89 #define CM_RST_CH0 0x00040000
90 #define CM_CHEN1 0x00020000 /* ch1: enable */
91 #define CM_CHEN0 0x00010000 /* ch0: enable */
92 #define CM_PAUSE1 0x00000008 /* ch1: pause */
93 #define CM_PAUSE0 0x00000004 /* ch0: pause */
94 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
95 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
97 #define CM_REG_FUNCTRL1 0x04
98 #define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */
99 #define CM_ASFC_SHIFT 13
100 #define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */
101 #define CM_DSFC_SHIFT 10
102 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
103 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
104 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */
105 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
106 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
107 #define CM_BREQ 0x00000010 /* bus master enabled */
108 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
109 #define CM_UART_EN 0x00000004 /* UART */
110 #define CM_JYSTK_EN 0x00000002 /* joy stick */
112 #define CM_REG_CHFORMAT 0x08
114 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
115 #define CM_CHB3D 0x20000000 /* 4 channels */
117 #define CM_CHIP_MASK1 0x1f000000
118 #define CM_CHIP_037 0x01000000
120 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
121 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
122 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
123 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
125 #define CM_ADCBITLEN_MASK 0x0000C000
126 #define CM_ADCBITLEN_16 0x00000000
127 #define CM_ADCBITLEN_15 0x00004000
128 #define CM_ADCBITLEN_14 0x00008000
129 #define CM_ADCBITLEN_13 0x0000C000
131 #define CM_ADCDACLEN_MASK 0x00003000
132 #define CM_ADCDACLEN_060 0x00000000
133 #define CM_ADCDACLEN_066 0x00001000
134 #define CM_ADCDACLEN_130 0x00002000
135 #define CM_ADCDACLEN_280 0x00003000
137 #define CM_CH1_SRATE_176K 0x00000800
138 #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
139 #define CM_CH1_SRATE_88K 0x00000400
140 #define CM_CH0_SRATE_176K 0x00000200
141 #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
142 #define CM_CH0_SRATE_88K 0x00000100
144 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
145 #define CM_DBLSPDS 0x00000040
147 #define CM_CH1FMT_MASK 0x0000000C
148 #define CM_CH1FMT_SHIFT 2
149 #define CM_CH0FMT_MASK 0x00000003
150 #define CM_CH0FMT_SHIFT 0
152 #define CM_REG_INT_HLDCLR 0x0C
153 #define CM_CHIP_MASK2 0xff000000
154 #define CM_CHIP_039 0x04000000
155 #define CM_CHIP_039_6CH 0x01000000
156 #define CM_CHIP_055 0x08000000
157 #define CM_CHIP_8768 0x20000000
158 #define CM_TDMA_INT_EN 0x00040000
159 #define CM_CH1_INT_EN 0x00020000
160 #define CM_CH0_INT_EN 0x00010000
161 #define CM_INT_HOLD 0x00000002
162 #define CM_INT_CLEAR 0x00000001
164 #define CM_REG_INT_STATUS 0x10
165 #define CM_INTR 0x80000000
166 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
167 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
168 #define CM_UARTINT 0x00010000
169 #define CM_LTDMAINT 0x00008000
170 #define CM_HTDMAINT 0x00004000
171 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
172 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
173 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
174 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
175 #define CM_CH1BUSY 0x00000008
176 #define CM_CH0BUSY 0x00000004
177 #define CM_CHINT1 0x00000002
178 #define CM_CHINT0 0x00000001
180 #define CM_REG_LEGACY_CTRL 0x14
181 #define CM_NXCHG 0x80000000 /* h/w multi channels? */
182 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
183 #define CM_VMPU_330 0x00000000
184 #define CM_VMPU_320 0x20000000
185 #define CM_VMPU_310 0x40000000
186 #define CM_VMPU_300 0x60000000
187 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
188 #define CM_VSBSEL_220 0x00000000
189 #define CM_VSBSEL_240 0x04000000
190 #define CM_VSBSEL_260 0x08000000
191 #define CM_VSBSEL_280 0x0C000000
192 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
193 #define CM_FMSEL_388 0x00000000
194 #define CM_FMSEL_3C8 0x01000000
195 #define CM_FMSEL_3E0 0x02000000
196 #define CM_FMSEL_3E8 0x03000000
197 #define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */
198 #define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */
199 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
200 #define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
201 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
202 #define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */
204 #define CM_REG_MISC_CTRL 0x18
205 #define CM_PWD 0x80000000
206 #define CM_RESET 0x40000000
207 #define CM_SFIL_MASK 0x30000000
208 #define CM_TXVX 0x08000000
209 #define CM_N4SPK3D 0x04000000 /* 4ch output */
210 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
211 #define CM_SPDIF48K 0x01000000 /* write */
212 #define CM_SPATUS48K 0x01000000 /* read */
213 #define CM_ENDBDAC 0x00800000 /* enable dual dac */
214 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
215 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
216 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */
217 #define CM_FM_EN 0x00080000 /* enalbe FM */
218 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
219 #define CM_VIDWPDSB 0x00010000
220 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
221 #define CM_MASK_EN 0x00004000
222 #define CM_VIDWPPRT 0x00002000
223 #define CM_SFILENB 0x00001000
224 #define CM_MMODE_MASK 0x00000E00
225 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
226 #define CM_ENCENTER 0x00000080
227 #define CM_FLINKON 0x00000040
228 #define CM_FLINKOFF 0x00000020
229 #define CM_MIDSMP 0x00000010
230 #define CM_UPDDMA_MASK 0x0000000C
231 #define CM_TWAIT_MASK 0x00000003
234 #define CM_REG_MIXER0 0x20
236 #define CM_REG_SB16_DATA 0x22
237 #define CM_REG_SB16_ADDR 0x23
239 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
240 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
241 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
242 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
244 #define CM_REG_MIXER1 0x24
245 #define CM_FMMUTE 0x80 /* mute FM */
246 #define CM_FMMUTE_SHIFT 7
247 #define CM_WSMUTE 0x40 /* mute PCM */
248 #define CM_WSMUTE_SHIFT 6
249 #define CM_SPK4 0x20 /* lin-in -> rear line out */
250 #define CM_SPK4_SHIFT 5
251 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
252 #define CM_REAR2FRONT_SHIFT 4
253 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
254 #define CM_WAVEINL_SHIFT 3
255 #define CM_WAVEINR 0x04 /* digical wave rec. right */
256 #define CM_WAVEINR_SHIFT 2
257 #define CM_X3DEN 0x02 /* 3D surround enable */
258 #define CM_X3DEN_SHIFT 1
259 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
260 #define CM_CDPLAY_SHIFT 0
262 #define CM_REG_MIXER2 0x25
263 #define CM_RAUXREN 0x80 /* AUX right capture */
264 #define CM_RAUXREN_SHIFT 7
265 #define CM_RAUXLEN 0x40 /* AUX left capture */
266 #define CM_RAUXLEN_SHIFT 6
267 #define CM_VAUXRM 0x20 /* AUX right mute */
268 #define CM_VAUXRM_SHIFT 5
269 #define CM_VAUXLM 0x10 /* AUX left mute */
270 #define CM_VAUXLM_SHIFT 4
271 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
272 #define CM_VADMIC_SHIFT 1
273 #define CM_MICGAINZ 0x01 /* mic boost */
274 #define CM_MICGAINZ_SHIFT 0
276 #define CM_REG_MIXER3 0x24
277 #define CM_REG_AUX_VOL 0x26
278 #define CM_VAUXL_MASK 0xf0
279 #define CM_VAUXR_MASK 0x0f
281 #define CM_REG_MISC 0x27
282 #define CM_XGPO1 0x20
283 // #define CM_XGPBIO 0x04
284 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
285 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
286 #define CM_SPDVALID 0x02 /* spdif input valid check */
287 #define CM_DMAUTO 0x01
289 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
291 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
292 * or identical with AC97 codec?
294 #define CM_REG_EXTERN_CODEC CM_REG_AC97
297 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
299 #define CM_REG_MPU_PCI 0x40
302 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
304 #define CM_REG_FM_PCI 0x50
307 * access from SB-mixer port
309 #define CM_REG_EXTENT_IND 0xf0
310 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
311 #define CM_VPHONE_SHIFT 5
312 #define CM_VPHOM 0x10 /* Phone mute control */
313 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
314 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
315 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
316 #define CM_VADMIC3 0x01 /* Mic record boost */
319 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
320 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
323 #define CM_REG_PLL 0xf8
328 #define CM_REG_CH0_FRAME1 0x80 /* base address */
329 #define CM_REG_CH0_FRAME2 0x84
330 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
331 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
332 #define CM_REG_EXT_MISC 0x90
333 #define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */
334 #define CM_CHB3D8C 0x20 /* 7.1 channels support */
335 #define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */
336 #define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */
337 #define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */
338 #define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */
339 #define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */
344 #define CM_EXTENT_CODEC 0x100
345 #define CM_EXTENT_MIDI 0x2
346 #define CM_EXTENT_SYNTH 0x4
350 * channels for playback / capture
356 * flags to check device open/close
358 #define CM_OPEN_NONE 0
359 #define CM_OPEN_CH_MASK 0x01
360 #define CM_OPEN_DAC 0x10
361 #define CM_OPEN_ADC 0x20
362 #define CM_OPEN_SPDIF 0x40
363 #define CM_OPEN_MCHAN 0x80
364 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
365 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
366 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
367 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
368 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
369 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
373 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
374 #define CM_PLAYBACK_SPDF CM_SPDF_1
375 #define CM_CAPTURE_SPDF CM_SPDF_0
377 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
378 #define CM_PLAYBACK_SPDF CM_SPDF_0
379 #define CM_CAPTURE_SPDF CM_SPDF_1
388 struct snd_pcm_substream *substream;
389 int running; /* dac/adc running? */
390 unsigned int dma_size; /* in frames */
391 unsigned int period_size; /* in frames */
392 unsigned int offset; /* physical address of the buffer */
393 unsigned int fmt; /* format bits */
394 int ch; /* channel (0/1) */
395 unsigned int is_dac; /* is dac? */
400 /* mixer elements toggled/resumed during ac3 playback */
401 struct cmipci_mixer_auto_switches {
402 const char *name; /* switch to toggle */
403 int toggle_on; /* value to change when ac3 mode */
405 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
406 {"PCM Playback Switch", 0},
407 {"IEC958 Output Switch", 1},
408 {"IEC958 Mix Analog", 0},
409 // {"IEC958 Out To DAC", 1}, // no longer used
412 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
415 struct snd_card *card;
418 unsigned int device; /* device ID */
421 unsigned long iobase;
422 unsigned int ctrl; /* FUNCTRL0 current value */
424 struct snd_pcm *pcm; /* DAC/ADC PCM */
425 struct snd_pcm *pcm2; /* 2nd DAC */
426 struct snd_pcm *pcm_spdif; /* SPDIF */
430 unsigned int can_ac3_sw: 1;
431 unsigned int can_ac3_hw: 1;
432 unsigned int can_multi_ch: 1;
433 unsigned int do_soft_ac3: 1;
435 unsigned int spdif_playback_avail: 1; /* spdif ready? */
436 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
437 int spdif_counter; /* for software AC3 */
439 unsigned int dig_status;
440 unsigned int dig_pcm_status;
442 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
444 int opened[2]; /* open mode */
445 struct mutex open_mutex;
447 unsigned int mixer_insensitive: 1;
448 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
449 int mixer_res_status[CM_SAVED_MIXERS];
451 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
454 struct snd_rawmidi *rmidi;
456 #ifdef SUPPORT_JOYSTICK
457 struct gameport *gameport;
463 unsigned int saved_regs[0x20];
464 unsigned char saved_mixers[0x20];
469 /* read/write operations for dword register */
470 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
472 outl(data, cm->iobase + cmd);
475 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
477 return inl(cm->iobase + cmd);
480 /* read/write operations for word register */
481 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
483 outw(data, cm->iobase + cmd);
486 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
488 return inw(cm->iobase + cmd);
491 /* read/write operations for byte register */
492 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
494 outb(data, cm->iobase + cmd);
497 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
499 return inb(cm->iobase + cmd);
502 /* bit operations for dword register */
503 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
505 unsigned int val, oval;
506 val = oval = inl(cm->iobase + cmd);
510 outl(val, cm->iobase + cmd);
514 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
516 unsigned int val, oval;
517 val = oval = inl(cm->iobase + cmd);
521 outl(val, cm->iobase + cmd);
525 /* bit operations for byte register */
526 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
528 unsigned char val, oval;
529 val = oval = inb(cm->iobase + cmd);
533 outb(val, cm->iobase + cmd);
537 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
539 unsigned char val, oval;
540 val = oval = inb(cm->iobase + cmd);
544 outb(val, cm->iobase + cmd);
554 * calculate frequency
557 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
559 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
562 for (i = 0; i < ARRAY_SIZE(rates); i++) {
563 if (rates[i] == rate)
570 #ifdef USE_VAR48KRATE
572 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
573 * does it this way .. maybe not. Never get any information from C-Media about
574 * that <werner@suse.de>.
576 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
578 unsigned int delta, tolerance;
581 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
586 tolerance = rate*CM_TOLERANCE_RATE;
588 for (xn = (1+2); xn < (0x1f+2); xn++) {
589 for (xm = (1+2); xm < (0xff+2); xm++) {
590 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
598 * If we found one, remember this,
599 * and try to find a closer one
601 if (delta < tolerance) {
613 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
614 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
615 * at the register CM_REG_FUNCTRL1 (0x04).
616 * Problem: other ways are also possible (any information about that?)
618 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
620 unsigned int reg = CM_REG_PLL + slot;
622 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
623 * for DSFC/ASFC (000 upto 111).
626 /* FIXME: Init (Do we've to set an other register first before programming?) */
628 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
629 snd_cmipci_write_b(cm, reg, rate>>8);
630 snd_cmipci_write_b(cm, reg, rate&0xff);
632 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
634 #endif /* USE_VAR48KRATE */
636 static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
637 struct snd_pcm_hw_params *hw_params)
639 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
642 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
643 struct snd_pcm_hw_params *hw_params)
645 struct cmipci *cm = snd_pcm_substream_chip(substream);
646 if (params_channels(hw_params) > 2) {
647 mutex_lock(&cm->open_mutex);
648 if (cm->opened[CM_CH_PLAY]) {
649 mutex_unlock(&cm->open_mutex);
652 /* reserve the channel A */
653 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
654 mutex_unlock(&cm->open_mutex);
656 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
659 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
661 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
662 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
663 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
667 static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
669 return snd_pcm_lib_free_pages(substream);
676 static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8};
677 static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
682 static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
687 static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
693 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
696 if (! cm->can_multi_ch)
698 if (rec->fmt != 0x03) /* stereo 16bit only */
701 spin_lock_irq(&cm->reg_lock);
702 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
703 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
705 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
706 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
708 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
709 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
712 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
713 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
715 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
716 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
718 if (cm->chip_version == 68) {
720 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
722 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
725 spin_unlock_irq(&cm->reg_lock);
728 if (cm->can_multi_ch) {
729 spin_lock_irq(&cm->reg_lock);
730 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
731 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
732 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
733 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
734 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
735 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
736 spin_unlock_irq(&cm->reg_lock);
744 * prepare playback/capture channel
745 * channel to be used must have been set in rec->ch.
747 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
748 struct snd_pcm_substream *substream)
750 unsigned int reg, freq, val;
751 struct snd_pcm_runtime *runtime = substream->runtime;
755 if (snd_pcm_format_width(runtime->format) >= 16) {
757 if (snd_pcm_format_width(runtime->format) > 16)
758 rec->shift++; /* 24/32bit */
760 if (runtime->channels > 1)
762 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
763 snd_printd("cannot set dac channels\n");
767 rec->offset = runtime->dma_addr;
768 /* buffer and period sizes in frame */
769 rec->dma_size = runtime->buffer_size << rec->shift;
770 rec->period_size = runtime->period_size << rec->shift;
771 if (runtime->channels > 2) {
773 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
774 rec->period_size = (rec->period_size * runtime->channels) / 2;
777 spin_lock_irq(&cm->reg_lock);
779 /* set buffer address */
780 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
781 snd_cmipci_write(cm, reg, rec->offset);
782 /* program sample counts */
783 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
784 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
785 snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1);
787 /* set adc/dac flag */
788 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
793 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
794 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
796 /* set sample rate */
797 freq = snd_cmipci_rate_freq(runtime->rate);
798 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
800 val &= ~CM_ASFC_MASK;
801 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
803 val &= ~CM_DSFC_MASK;
804 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
806 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
807 //snd_printd("cmipci: functrl1 = %08x\n", val);
810 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
812 val &= ~CM_CH1FMT_MASK;
813 val |= rec->fmt << CM_CH1FMT_SHIFT;
815 val &= ~CM_CH0FMT_MASK;
816 val |= rec->fmt << CM_CH0FMT_SHIFT;
818 if (cm->chip_version == 68) {
819 if (runtime->rate == 88200)
820 val |= CM_CH0_SRATE_88K << (rec->ch * 2);
822 val &= ~(CM_CH0_SRATE_88K << (rec->ch * 2));
823 if (runtime->rate == 96000)
824 val |= CM_CH0_SRATE_96K << (rec->ch * 2);
826 val &= ~(CM_CH0_SRATE_96K << (rec->ch * 2));
828 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
829 //snd_printd("cmipci: chformat = %08x\n", val);
832 spin_unlock_irq(&cm->reg_lock);
840 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
841 struct snd_pcm_substream *substream, int cmd)
843 unsigned int inthld, chen, reset, pause;
846 inthld = CM_CH0_INT_EN << rec->ch;
847 chen = CM_CHEN0 << rec->ch;
848 reset = CM_RST_CH0 << rec->ch;
849 pause = CM_PAUSE0 << rec->ch;
851 spin_lock(&cm->reg_lock);
853 case SNDRV_PCM_TRIGGER_START:
856 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
859 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
860 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
862 case SNDRV_PCM_TRIGGER_STOP:
864 /* disable interrupt */
865 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
868 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
869 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
871 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
872 case SNDRV_PCM_TRIGGER_SUSPEND:
874 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
876 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
877 case SNDRV_PCM_TRIGGER_RESUME:
879 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
885 spin_unlock(&cm->reg_lock);
890 * return the current pointer
892 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
893 struct snd_pcm_substream *substream)
899 #if 1 // this seems better..
900 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
901 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
904 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
905 ptr = snd_cmipci_read(cm, reg) - rec->offset;
906 ptr = bytes_to_frames(substream->runtime, ptr);
908 if (substream->runtime->channels > 2)
909 ptr = (ptr * 2) / substream->runtime->channels;
917 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
920 struct cmipci *cm = snd_pcm_substream_chip(substream);
921 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);
924 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
926 struct cmipci *cm = snd_pcm_substream_chip(substream);
927 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
936 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
939 struct cmipci *cm = snd_pcm_substream_chip(substream);
940 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);
943 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
945 struct cmipci *cm = snd_pcm_substream_chip(substream);
946 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
951 * hw preparation for spdif
954 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
955 struct snd_ctl_elem_info *uinfo)
957 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
962 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
963 struct snd_ctl_elem_value *ucontrol)
965 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
968 spin_lock_irq(&chip->reg_lock);
969 for (i = 0; i < 4; i++)
970 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
971 spin_unlock_irq(&chip->reg_lock);
975 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
976 struct snd_ctl_elem_value *ucontrol)
978 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
983 spin_lock_irq(&chip->reg_lock);
984 for (i = 0; i < 4; i++)
985 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
986 change = val != chip->dig_status;
987 chip->dig_status = val;
988 spin_unlock_irq(&chip->reg_lock);
992 static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata =
994 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
995 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
996 .info = snd_cmipci_spdif_default_info,
997 .get = snd_cmipci_spdif_default_get,
998 .put = snd_cmipci_spdif_default_put
1001 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1002 struct snd_ctl_elem_info *uinfo)
1004 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1009 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1010 struct snd_ctl_elem_value *ucontrol)
1012 ucontrol->value.iec958.status[0] = 0xff;
1013 ucontrol->value.iec958.status[1] = 0xff;
1014 ucontrol->value.iec958.status[2] = 0xff;
1015 ucontrol->value.iec958.status[3] = 0xff;
1019 static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata =
1021 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1022 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1023 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1024 .info = snd_cmipci_spdif_mask_info,
1025 .get = snd_cmipci_spdif_mask_get,
1028 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1029 struct snd_ctl_elem_info *uinfo)
1031 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1036 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1037 struct snd_ctl_elem_value *ucontrol)
1039 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1042 spin_lock_irq(&chip->reg_lock);
1043 for (i = 0; i < 4; i++)
1044 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1045 spin_unlock_irq(&chip->reg_lock);
1049 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1050 struct snd_ctl_elem_value *ucontrol)
1052 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1057 spin_lock_irq(&chip->reg_lock);
1058 for (i = 0; i < 4; i++)
1059 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1060 change = val != chip->dig_pcm_status;
1061 chip->dig_pcm_status = val;
1062 spin_unlock_irq(&chip->reg_lock);
1066 static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata =
1068 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1069 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1070 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1071 .info = snd_cmipci_spdif_stream_info,
1072 .get = snd_cmipci_spdif_stream_get,
1073 .put = snd_cmipci_spdif_stream_put
1079 /* save mixer setting and mute for AC3 playback */
1080 static int save_mixer_state(struct cmipci *cm)
1082 if (! cm->mixer_insensitive) {
1083 struct snd_ctl_elem_value *val;
1086 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1089 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1090 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1093 memset(val, 0, sizeof(*val));
1095 cm->mixer_res_status[i] = val->value.integer.value[0];
1096 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1097 event = SNDRV_CTL_EVENT_MASK_INFO;
1098 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1099 ctl->put(ctl, val); /* toggle */
1100 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1102 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1103 snd_ctl_notify(cm->card, event, &ctl->id);
1107 cm->mixer_insensitive = 1;
1113 /* restore the previously saved mixer status */
1114 static void restore_mixer_state(struct cmipci *cm)
1116 if (cm->mixer_insensitive) {
1117 struct snd_ctl_elem_value *val;
1120 val = kmalloc(sizeof(*val), GFP_KERNEL);
1123 cm->mixer_insensitive = 0; /* at first clear this;
1124 otherwise the changes will be ignored */
1125 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1126 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1130 memset(val, 0, sizeof(*val));
1131 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1133 event = SNDRV_CTL_EVENT_MASK_INFO;
1134 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1135 val->value.integer.value[0] = cm->mixer_res_status[i];
1137 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1139 snd_ctl_notify(cm->card, event, &ctl->id);
1146 /* spinlock held! */
1147 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1151 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1153 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1155 if (cm->can_ac3_hw) {
1156 /* SPD24SEL for 037, 0x02 */
1157 /* SPD24SEL for 039, 0x20, but cannot be set */
1158 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1159 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1160 } else { /* can_ac3_sw */
1161 /* SPD32SEL for 037 & 039, 0x20 */
1162 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1163 /* set 176K sample rate to fix 033 HW bug */
1164 if (cm->chip_version == 33) {
1165 if (rate >= 48000) {
1166 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1168 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1174 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1175 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1177 if (cm->can_ac3_hw) {
1178 /* chip model >= 37 */
1179 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1180 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1181 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1183 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1184 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1187 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1188 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1189 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1194 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1198 rate = subs->runtime->rate;
1201 if ((err = save_mixer_state(cm)) < 0)
1204 spin_lock_irq(&cm->reg_lock);
1205 cm->spdif_playback_avail = up;
1207 /* they are controlled via "IEC958 Output Switch" */
1208 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1209 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1210 if (cm->spdif_playback_enabled)
1211 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1212 setup_ac3(cm, subs, do_ac3, rate);
1214 if (rate == 48000 || rate == 96000)
1215 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1217 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1219 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1221 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1223 /* they are controlled via "IEC958 Output Switch" */
1224 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1225 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1226 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1227 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1228 setup_ac3(cm, subs, 0, 0);
1230 spin_unlock_irq(&cm->reg_lock);
1239 /* playback - enable spdif only on the certain condition */
1240 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1242 struct cmipci *cm = snd_pcm_substream_chip(substream);
1243 int rate = substream->runtime->rate;
1244 int err, do_spdif, do_ac3 = 0;
1246 do_spdif = (rate >= 44100 &&
1247 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1248 substream->runtime->channels == 2);
1249 if (do_spdif && cm->can_ac3_hw)
1250 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1251 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1253 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1256 /* playback (via device #2) - enable spdif always */
1257 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1259 struct cmipci *cm = snd_pcm_substream_chip(substream);
1263 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1265 do_ac3 = 1; /* doesn't matter */
1266 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1268 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1271 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1273 struct cmipci *cm = snd_pcm_substream_chip(substream);
1274 setup_spdif_playback(cm, substream, 0, 0);
1275 restore_mixer_state(cm);
1276 return snd_cmipci_hw_free(substream);
1280 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1282 struct cmipci *cm = snd_pcm_substream_chip(substream);
1283 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1286 /* capture with spdif (via device #2) */
1287 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1289 struct cmipci *cm = snd_pcm_substream_chip(substream);
1291 spin_lock_irq(&cm->reg_lock);
1292 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1293 spin_unlock_irq(&cm->reg_lock);
1295 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1298 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1300 struct cmipci *cm = snd_pcm_substream_chip(subs);
1302 spin_lock_irq(&cm->reg_lock);
1303 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1304 spin_unlock_irq(&cm->reg_lock);
1306 return snd_cmipci_hw_free(subs);
1313 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1315 struct cmipci *cm = dev_id;
1316 unsigned int status, mask = 0;
1318 /* fastpath out, to ease interrupt sharing */
1319 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1320 if (!(status & CM_INTR))
1323 /* acknowledge interrupt */
1324 spin_lock(&cm->reg_lock);
1325 if (status & CM_CHINT0)
1326 mask |= CM_CH0_INT_EN;
1327 if (status & CM_CHINT1)
1328 mask |= CM_CH1_INT_EN;
1329 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1330 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1331 spin_unlock(&cm->reg_lock);
1333 if (cm->rmidi && (status & CM_UARTINT))
1334 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1337 if ((status & CM_CHINT0) && cm->channel[0].running)
1338 snd_pcm_period_elapsed(cm->channel[0].substream);
1339 if ((status & CM_CHINT1) && cm->channel[1].running)
1340 snd_pcm_period_elapsed(cm->channel[1].substream);
1349 /* playback on channel A */
1350 static struct snd_pcm_hardware snd_cmipci_playback =
1352 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1353 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1354 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1355 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1356 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1361 .buffer_bytes_max = (128*1024),
1362 .period_bytes_min = 64,
1363 .period_bytes_max = (128*1024),
1365 .periods_max = 1024,
1369 /* capture on channel B */
1370 static struct snd_pcm_hardware snd_cmipci_capture =
1372 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1373 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1374 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1375 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1376 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1381 .buffer_bytes_max = (128*1024),
1382 .period_bytes_min = 64,
1383 .period_bytes_max = (128*1024),
1385 .periods_max = 1024,
1389 /* playback on channel B - stereo 16bit only? */
1390 static struct snd_pcm_hardware snd_cmipci_playback2 =
1392 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1393 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1394 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1395 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1396 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1401 .buffer_bytes_max = (128*1024),
1402 .period_bytes_min = 64,
1403 .period_bytes_max = (128*1024),
1405 .periods_max = 1024,
1409 /* spdif playback on channel A */
1410 static struct snd_pcm_hardware snd_cmipci_playback_spdif =
1412 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1413 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1414 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1415 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1416 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1421 .buffer_bytes_max = (128*1024),
1422 .period_bytes_min = 64,
1423 .period_bytes_max = (128*1024),
1425 .periods_max = 1024,
1429 /* spdif playback on channel A (32bit, IEC958 subframes) */
1430 static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1432 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1433 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1434 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1435 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1436 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1441 .buffer_bytes_max = (128*1024),
1442 .period_bytes_min = 64,
1443 .period_bytes_max = (128*1024),
1445 .periods_max = 1024,
1449 /* spdif capture on channel B */
1450 static struct snd_pcm_hardware snd_cmipci_capture_spdif =
1452 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1453 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1454 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1455 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1456 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1461 .buffer_bytes_max = (128*1024),
1462 .period_bytes_min = 64,
1463 .period_bytes_max = (128*1024),
1465 .periods_max = 1024,
1470 * check device open/close
1472 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1474 int ch = mode & CM_OPEN_CH_MASK;
1476 /* FIXME: a file should wait until the device becomes free
1477 * when it's opened on blocking mode. however, since the current
1478 * pcm framework doesn't pass file pointer before actually opened,
1479 * we can't know whether blocking mode or not in open callback..
1481 mutex_lock(&cm->open_mutex);
1482 if (cm->opened[ch]) {
1483 mutex_unlock(&cm->open_mutex);
1486 cm->opened[ch] = mode;
1487 cm->channel[ch].substream = subs;
1488 if (! (mode & CM_OPEN_DAC)) {
1489 /* disable dual DAC mode */
1490 cm->channel[ch].is_dac = 0;
1491 spin_lock_irq(&cm->reg_lock);
1492 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1493 spin_unlock_irq(&cm->reg_lock);
1495 mutex_unlock(&cm->open_mutex);
1499 static void close_device_check(struct cmipci *cm, int mode)
1501 int ch = mode & CM_OPEN_CH_MASK;
1503 mutex_lock(&cm->open_mutex);
1504 if (cm->opened[ch] == mode) {
1505 if (cm->channel[ch].substream) {
1506 snd_cmipci_ch_reset(cm, ch);
1507 cm->channel[ch].running = 0;
1508 cm->channel[ch].substream = NULL;
1511 if (! cm->channel[ch].is_dac) {
1512 /* enable dual DAC mode again */
1513 cm->channel[ch].is_dac = 1;
1514 spin_lock_irq(&cm->reg_lock);
1515 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1516 spin_unlock_irq(&cm->reg_lock);
1519 mutex_unlock(&cm->open_mutex);
1525 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1527 struct cmipci *cm = snd_pcm_substream_chip(substream);
1528 struct snd_pcm_runtime *runtime = substream->runtime;
1531 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1533 runtime->hw = snd_cmipci_playback;
1534 if (cm->chip_version == 68) {
1535 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1536 SNDRV_PCM_RATE_96000;
1537 runtime->hw.rate_max = 96000;
1539 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1540 cm->dig_pcm_status = cm->dig_status;
1544 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1546 struct cmipci *cm = snd_pcm_substream_chip(substream);
1547 struct snd_pcm_runtime *runtime = substream->runtime;
1550 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1552 runtime->hw = snd_cmipci_capture;
1553 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1554 runtime->hw.rate_min = 41000;
1555 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1557 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1561 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1563 struct cmipci *cm = snd_pcm_substream_chip(substream);
1564 struct snd_pcm_runtime *runtime = substream->runtime;
1567 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1569 runtime->hw = snd_cmipci_playback2;
1570 mutex_lock(&cm->open_mutex);
1571 if (! cm->opened[CM_CH_PLAY]) {
1572 if (cm->can_multi_ch) {
1573 runtime->hw.channels_max = cm->max_channels;
1574 if (cm->max_channels == 4)
1575 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1576 else if (cm->max_channels == 6)
1577 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1578 else if (cm->max_channels == 8)
1579 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1581 if (cm->chip_version == 68) {
1582 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1583 SNDRV_PCM_RATE_96000;
1584 runtime->hw.rate_max = 96000;
1586 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1588 mutex_unlock(&cm->open_mutex);
1592 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1594 struct cmipci *cm = snd_pcm_substream_chip(substream);
1595 struct snd_pcm_runtime *runtime = substream->runtime;
1598 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1600 if (cm->can_ac3_hw) {
1601 runtime->hw = snd_cmipci_playback_spdif;
1602 if (cm->chip_version >= 37) {
1603 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1604 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1606 if (cm->chip_version == 68) {
1607 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1608 SNDRV_PCM_RATE_96000;
1609 runtime->hw.rate_max = 96000;
1612 runtime->hw = snd_cmipci_playback_iec958_subframe;
1614 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1615 cm->dig_pcm_status = cm->dig_status;
1619 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1621 struct cmipci *cm = snd_pcm_substream_chip(substream);
1622 struct snd_pcm_runtime *runtime = substream->runtime;
1625 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1627 runtime->hw = snd_cmipci_capture_spdif;
1628 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1636 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1638 struct cmipci *cm = snd_pcm_substream_chip(substream);
1639 close_device_check(cm, CM_OPEN_PLAYBACK);
1643 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1645 struct cmipci *cm = snd_pcm_substream_chip(substream);
1646 close_device_check(cm, CM_OPEN_CAPTURE);
1650 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1652 struct cmipci *cm = snd_pcm_substream_chip(substream);
1653 close_device_check(cm, CM_OPEN_PLAYBACK2);
1654 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1658 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1660 struct cmipci *cm = snd_pcm_substream_chip(substream);
1661 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1665 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1667 struct cmipci *cm = snd_pcm_substream_chip(substream);
1668 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1676 static struct snd_pcm_ops snd_cmipci_playback_ops = {
1677 .open = snd_cmipci_playback_open,
1678 .close = snd_cmipci_playback_close,
1679 .ioctl = snd_pcm_lib_ioctl,
1680 .hw_params = snd_cmipci_hw_params,
1681 .hw_free = snd_cmipci_playback_hw_free,
1682 .prepare = snd_cmipci_playback_prepare,
1683 .trigger = snd_cmipci_playback_trigger,
1684 .pointer = snd_cmipci_playback_pointer,
1687 static struct snd_pcm_ops snd_cmipci_capture_ops = {
1688 .open = snd_cmipci_capture_open,
1689 .close = snd_cmipci_capture_close,
1690 .ioctl = snd_pcm_lib_ioctl,
1691 .hw_params = snd_cmipci_hw_params,
1692 .hw_free = snd_cmipci_hw_free,
1693 .prepare = snd_cmipci_capture_prepare,
1694 .trigger = snd_cmipci_capture_trigger,
1695 .pointer = snd_cmipci_capture_pointer,
1698 static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1699 .open = snd_cmipci_playback2_open,
1700 .close = snd_cmipci_playback2_close,
1701 .ioctl = snd_pcm_lib_ioctl,
1702 .hw_params = snd_cmipci_playback2_hw_params,
1703 .hw_free = snd_cmipci_hw_free,
1704 .prepare = snd_cmipci_capture_prepare, /* channel B */
1705 .trigger = snd_cmipci_capture_trigger, /* channel B */
1706 .pointer = snd_cmipci_capture_pointer, /* channel B */
1709 static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1710 .open = snd_cmipci_playback_spdif_open,
1711 .close = snd_cmipci_playback_spdif_close,
1712 .ioctl = snd_pcm_lib_ioctl,
1713 .hw_params = snd_cmipci_hw_params,
1714 .hw_free = snd_cmipci_playback_hw_free,
1715 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1716 .trigger = snd_cmipci_playback_trigger,
1717 .pointer = snd_cmipci_playback_pointer,
1720 static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1721 .open = snd_cmipci_capture_spdif_open,
1722 .close = snd_cmipci_capture_spdif_close,
1723 .ioctl = snd_pcm_lib_ioctl,
1724 .hw_params = snd_cmipci_hw_params,
1725 .hw_free = snd_cmipci_capture_spdif_hw_free,
1726 .prepare = snd_cmipci_capture_spdif_prepare,
1727 .trigger = snd_cmipci_capture_trigger,
1728 .pointer = snd_cmipci_capture_pointer,
1735 static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device)
1737 struct snd_pcm *pcm;
1740 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1744 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1745 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1747 pcm->private_data = cm;
1748 pcm->info_flags = 0;
1749 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1752 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1753 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1758 static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1760 struct snd_pcm *pcm;
1763 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1767 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1769 pcm->private_data = cm;
1770 pcm->info_flags = 0;
1771 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1774 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1775 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1780 static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1782 struct snd_pcm *pcm;
1785 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1789 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1790 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1792 pcm->private_data = cm;
1793 pcm->info_flags = 0;
1794 strcpy(pcm->name, "C-Media PCI IEC958");
1795 cm->pcm_spdif = pcm;
1797 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1798 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1805 * - CM8338/8738 has a compatible mixer interface with SB16, but
1806 * lack of some elements like tone control, i/o gain and AGC.
1807 * - Access to native registers:
1809 * - Output mute switches
1812 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1814 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1815 outb(data, s->iobase + CM_REG_SB16_DATA);
1818 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1822 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1823 v = inb(s->iobase + CM_REG_SB16_DATA);
1828 * general mixer element
1830 struct cmipci_sb_reg {
1831 unsigned int left_reg, right_reg;
1832 unsigned int left_shift, right_shift;
1834 unsigned int invert: 1;
1835 unsigned int stereo: 1;
1838 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1839 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1841 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1842 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1843 .info = snd_cmipci_info_volume, \
1844 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1845 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1848 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1849 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1850 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1851 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1853 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1855 r->left_reg = val & 0xff;
1856 r->right_reg = (val >> 8) & 0xff;
1857 r->left_shift = (val >> 16) & 0x07;
1858 r->right_shift = (val >> 19) & 0x07;
1859 r->invert = (val >> 22) & 1;
1860 r->stereo = (val >> 23) & 1;
1861 r->mask = (val >> 24) & 0xff;
1864 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
1865 struct snd_ctl_elem_info *uinfo)
1867 struct cmipci_sb_reg reg;
1869 cmipci_sb_reg_decode(®, kcontrol->private_value);
1870 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1871 uinfo->count = reg.stereo + 1;
1872 uinfo->value.integer.min = 0;
1873 uinfo->value.integer.max = reg.mask;
1877 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
1878 struct snd_ctl_elem_value *ucontrol)
1880 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1881 struct cmipci_sb_reg reg;
1884 cmipci_sb_reg_decode(®, kcontrol->private_value);
1885 spin_lock_irq(&cm->reg_lock);
1886 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1888 val = reg.mask - val;
1889 ucontrol->value.integer.value[0] = val;
1891 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1893 val = reg.mask - val;
1894 ucontrol->value.integer.value[1] = val;
1896 spin_unlock_irq(&cm->reg_lock);
1900 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
1901 struct snd_ctl_elem_value *ucontrol)
1903 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1904 struct cmipci_sb_reg reg;
1906 int left, right, oleft, oright;
1908 cmipci_sb_reg_decode(®, kcontrol->private_value);
1909 left = ucontrol->value.integer.value[0] & reg.mask;
1911 left = reg.mask - left;
1912 left <<= reg.left_shift;
1914 right = ucontrol->value.integer.value[1] & reg.mask;
1916 right = reg.mask - right;
1917 right <<= reg.right_shift;
1920 spin_lock_irq(&cm->reg_lock);
1921 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1922 left |= oleft & ~(reg.mask << reg.left_shift);
1923 change = left != oleft;
1925 if (reg.left_reg != reg.right_reg) {
1926 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1927 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1930 right |= oright & ~(reg.mask << reg.right_shift);
1931 change |= right != oright;
1932 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1934 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1935 spin_unlock_irq(&cm->reg_lock);
1940 * input route (left,right) -> (left,right)
1942 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1943 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1944 .info = snd_cmipci_info_input_sw, \
1945 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1946 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1949 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
1950 struct snd_ctl_elem_info *uinfo)
1952 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1954 uinfo->value.integer.min = 0;
1955 uinfo->value.integer.max = 1;
1959 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
1960 struct snd_ctl_elem_value *ucontrol)
1962 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1963 struct cmipci_sb_reg reg;
1966 cmipci_sb_reg_decode(®, kcontrol->private_value);
1967 spin_lock_irq(&cm->reg_lock);
1968 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1969 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1970 spin_unlock_irq(&cm->reg_lock);
1971 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
1972 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
1973 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
1974 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
1978 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
1979 struct snd_ctl_elem_value *ucontrol)
1981 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1982 struct cmipci_sb_reg reg;
1984 int val1, val2, oval1, oval2;
1986 cmipci_sb_reg_decode(®, kcontrol->private_value);
1987 spin_lock_irq(&cm->reg_lock);
1988 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1989 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1990 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1991 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1992 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
1993 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
1994 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
1995 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
1996 change = val1 != oval1 || val2 != oval2;
1997 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
1998 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
1999 spin_unlock_irq(&cm->reg_lock);
2004 * native mixer switches/volumes
2007 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2008 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2009 .info = snd_cmipci_info_native_mixer, \
2010 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2011 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2014 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2015 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2016 .info = snd_cmipci_info_native_mixer, \
2017 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2018 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2021 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2022 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2023 .info = snd_cmipci_info_native_mixer, \
2024 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2025 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2028 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2029 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2030 .info = snd_cmipci_info_native_mixer, \
2031 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2032 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2035 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2036 struct snd_ctl_elem_info *uinfo)
2038 struct cmipci_sb_reg reg;
2040 cmipci_sb_reg_decode(®, kcontrol->private_value);
2041 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2042 uinfo->count = reg.stereo + 1;
2043 uinfo->value.integer.min = 0;
2044 uinfo->value.integer.max = reg.mask;
2049 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2050 struct snd_ctl_elem_value *ucontrol)
2052 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2053 struct cmipci_sb_reg reg;
2054 unsigned char oreg, val;
2056 cmipci_sb_reg_decode(®, kcontrol->private_value);
2057 spin_lock_irq(&cm->reg_lock);
2058 oreg = inb(cm->iobase + reg.left_reg);
2059 val = (oreg >> reg.left_shift) & reg.mask;
2061 val = reg.mask - val;
2062 ucontrol->value.integer.value[0] = val;
2064 val = (oreg >> reg.right_shift) & reg.mask;
2066 val = reg.mask - val;
2067 ucontrol->value.integer.value[1] = val;
2069 spin_unlock_irq(&cm->reg_lock);
2073 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2074 struct snd_ctl_elem_value *ucontrol)
2076 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2077 struct cmipci_sb_reg reg;
2078 unsigned char oreg, nreg, val;
2080 cmipci_sb_reg_decode(®, kcontrol->private_value);
2081 spin_lock_irq(&cm->reg_lock);
2082 oreg = inb(cm->iobase + reg.left_reg);
2083 val = ucontrol->value.integer.value[0] & reg.mask;
2085 val = reg.mask - val;
2086 nreg = oreg & ~(reg.mask << reg.left_shift);
2087 nreg |= (val << reg.left_shift);
2089 val = ucontrol->value.integer.value[1] & reg.mask;
2091 val = reg.mask - val;
2092 nreg &= ~(reg.mask << reg.right_shift);
2093 nreg |= (val << reg.right_shift);
2095 outb(nreg, cm->iobase + reg.left_reg);
2096 spin_unlock_irq(&cm->reg_lock);
2097 return (nreg != oreg);
2101 * special case - check mixer sensitivity
2103 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2104 struct snd_ctl_elem_value *ucontrol)
2106 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2107 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2110 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2111 struct snd_ctl_elem_value *ucontrol)
2113 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2114 if (cm->mixer_insensitive) {
2118 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2122 static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = {
2123 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2124 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2125 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2126 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2127 { /* switch with sensitivity */
2128 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2129 .name = "PCM Playback Switch",
2130 .info = snd_cmipci_info_native_mixer,
2131 .get = snd_cmipci_get_native_mixer_sensitive,
2132 .put = snd_cmipci_put_native_mixer_sensitive,
2133 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2135 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2136 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2137 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2138 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2139 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2140 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2141 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2142 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2143 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2144 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2145 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2146 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2147 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2148 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2149 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2150 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2151 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2152 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2153 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2154 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2155 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2156 CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2157 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2164 struct cmipci_switch_args {
2165 int reg; /* register index */
2166 unsigned int mask; /* mask bits */
2167 unsigned int mask_on; /* mask bits to turn on */
2168 unsigned int is_byte: 1; /* byte access? */
2169 unsigned int ac3_sensitive: 1; /* access forbidden during
2170 * non-audio operation?
2174 #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2176 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2177 struct snd_ctl_elem_value *ucontrol,
2178 struct cmipci_switch_args *args)
2181 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2183 spin_lock_irq(&cm->reg_lock);
2184 if (args->ac3_sensitive && cm->mixer_insensitive) {
2185 ucontrol->value.integer.value[0] = 0;
2186 spin_unlock_irq(&cm->reg_lock);
2190 val = inb(cm->iobase + args->reg);
2192 val = snd_cmipci_read(cm, args->reg);
2193 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2194 spin_unlock_irq(&cm->reg_lock);
2198 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2199 struct snd_ctl_elem_value *ucontrol)
2201 struct cmipci_switch_args *args;
2202 args = (struct cmipci_switch_args *)kcontrol->private_value;
2203 snd_assert(args != NULL, return -EINVAL);
2204 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2207 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2208 struct snd_ctl_elem_value *ucontrol,
2209 struct cmipci_switch_args *args)
2213 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2215 spin_lock_irq(&cm->reg_lock);
2216 if (args->ac3_sensitive && cm->mixer_insensitive) {
2218 spin_unlock_irq(&cm->reg_lock);
2222 val = inb(cm->iobase + args->reg);
2224 val = snd_cmipci_read(cm, args->reg);
2225 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2226 args->mask_on : (args->mask & ~args->mask_on));
2229 if (ucontrol->value.integer.value[0])
2230 val |= args->mask_on;
2232 val |= (args->mask & ~args->mask_on);
2234 outb((unsigned char)val, cm->iobase + args->reg);
2236 snd_cmipci_write(cm, args->reg, val);
2238 spin_unlock_irq(&cm->reg_lock);
2242 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2243 struct snd_ctl_elem_value *ucontrol)
2245 struct cmipci_switch_args *args;
2246 args = (struct cmipci_switch_args *)kcontrol->private_value;
2247 snd_assert(args != NULL, return -EINVAL);
2248 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2251 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2252 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2255 .mask_on = xmask_on, \
2256 .is_byte = xis_byte, \
2257 .ac3_sensitive = xac3, \
2260 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2261 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2263 #if 0 /* these will be controlled in pcm device */
2264 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2265 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2267 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2268 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2269 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2270 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2271 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2272 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2273 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2274 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2275 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2276 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2277 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2278 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2279 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2280 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2282 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2284 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2286 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2287 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
2288 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
2289 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2290 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2292 #define DEFINE_SWITCH(sname, stype, sarg) \
2295 .info = snd_cmipci_uswitch_info, \
2296 .get = snd_cmipci_uswitch_get, \
2297 .put = snd_cmipci_uswitch_put, \
2298 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2301 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2302 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2306 * callbacks for spdif output switch
2307 * needs toggle two registers..
2309 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2310 struct snd_ctl_elem_value *ucontrol)
2313 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2314 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2318 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2319 struct snd_ctl_elem_value *ucontrol)
2321 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2323 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2324 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2326 if (ucontrol->value.integer.value[0]) {
2327 if (chip->spdif_playback_avail)
2328 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2330 if (chip->spdif_playback_avail)
2331 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2334 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2339 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2340 struct snd_ctl_elem_info *uinfo)
2342 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2343 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2344 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2346 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2347 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2348 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2349 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2353 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2356 if (cm->chip_version >= 39) {
2357 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2358 if (val & CM_LINE_AS_BASS)
2361 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2367 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2368 struct snd_ctl_elem_value *ucontrol)
2370 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2372 spin_lock_irq(&cm->reg_lock);
2373 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2374 spin_unlock_irq(&cm->reg_lock);
2378 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2379 struct snd_ctl_elem_value *ucontrol)
2381 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2384 spin_lock_irq(&cm->reg_lock);
2385 if (ucontrol->value.enumerated.item[0] == 2)
2386 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2388 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2389 if (ucontrol->value.enumerated.item[0] == 1)
2390 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2392 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2393 spin_unlock_irq(&cm->reg_lock);
2397 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2398 struct snd_ctl_elem_info *uinfo)
2400 static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2401 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2403 uinfo->value.enumerated.items = 2;
2404 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2405 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2406 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2410 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2411 struct snd_ctl_elem_value *ucontrol)
2413 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2414 /* same bit as spdi_phase */
2415 spin_lock_irq(&cm->reg_lock);
2416 ucontrol->value.enumerated.item[0] =
2417 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2418 spin_unlock_irq(&cm->reg_lock);
2422 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2423 struct snd_ctl_elem_value *ucontrol)
2425 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2428 spin_lock_irq(&cm->reg_lock);
2429 if (ucontrol->value.enumerated.item[0])
2430 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2432 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2433 spin_unlock_irq(&cm->reg_lock);
2437 /* both for CM8338/8738 */
2438 static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = {
2439 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2441 .name = "Line-In Mode",
2442 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2443 .info = snd_cmipci_line_in_mode_info,
2444 .get = snd_cmipci_line_in_mode_get,
2445 .put = snd_cmipci_line_in_mode_put,
2449 /* for non-multichannel chips */
2450 static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata =
2451 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2453 /* only for CM8738 */
2454 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = {
2455 #if 0 /* controlled in pcm device */
2456 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2457 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2458 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2460 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2461 { .name = "IEC958 Output Switch",
2462 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2463 .info = snd_cmipci_uswitch_info,
2464 .get = snd_cmipci_spdout_enable_get,
2465 .put = snd_cmipci_spdout_enable_put,
2467 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2468 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2469 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2470 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2471 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2472 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2475 /* only for model 033/037 */
2476 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = {
2477 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2478 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2479 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2482 /* only for model 039 or later */
2483 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = {
2484 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2485 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2487 .name = "Mic-In Mode",
2488 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2489 .info = snd_cmipci_mic_in_mode_info,
2490 .get = snd_cmipci_mic_in_mode_get,
2491 .put = snd_cmipci_mic_in_mode_put,
2495 /* card control switches */
2496 static struct snd_kcontrol_new snd_cmipci_control_switches[] __devinitdata = {
2497 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2498 DEFINE_CARD_SWITCH("Modem", modem),
2502 static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2504 struct snd_card *card;
2505 struct snd_kcontrol_new *sw;
2506 struct snd_kcontrol *kctl;
2510 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2514 strcpy(card->mixername, "CMedia PCI");
2516 spin_lock_irq(&cm->reg_lock);
2517 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2518 spin_unlock_irq(&cm->reg_lock);
2520 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2521 if (cm->chip_version == 68) { // 8768 has no PCM volume
2522 if (!strcmp(snd_cmipci_mixers[idx].name,
2523 "PCM Playback Volume"))
2526 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2530 /* mixer switches */
2531 sw = snd_cmipci_mixer_switches;
2532 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2533 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2537 if (! cm->can_multi_ch) {
2538 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2542 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2543 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2544 sw = snd_cmipci_8738_mixer_switches;
2545 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2546 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2550 if (cm->can_ac3_hw) {
2551 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2553 kctl->id.device = pcm_spdif_device;
2554 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2556 kctl->id.device = pcm_spdif_device;
2557 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2559 kctl->id.device = pcm_spdif_device;
2561 if (cm->chip_version <= 37) {
2562 sw = snd_cmipci_old_mixer_switches;
2563 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2564 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2570 if (cm->chip_version >= 39) {
2571 sw = snd_cmipci_extra_mixer_switches;
2572 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2573 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2580 sw = snd_cmipci_control_switches;
2581 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2582 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2587 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2588 struct snd_ctl_elem_id id;
2589 struct snd_kcontrol *ctl;
2590 memset(&id, 0, sizeof(id));
2591 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2592 strcpy(id.name, cm_saved_mixer[idx].name);
2593 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2594 cm->mixer_res_ctl[idx] = ctl;
2605 #ifdef CONFIG_PROC_FS
2606 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2607 struct snd_info_buffer *buffer)
2609 struct cmipci *cm = entry->private_data;
2612 snd_iprintf(buffer, "%s\n\n", cm->card->longname);
2613 for (i = 0; i < 0x40; i++) {
2614 int v = inb(cm->iobase + i);
2616 snd_iprintf(buffer, "%02x: ", i);
2617 snd_iprintf(buffer, "%02x", v);
2619 snd_iprintf(buffer, "\n");
2621 snd_iprintf(buffer, " ");
2625 static void __devinit snd_cmipci_proc_init(struct cmipci *cm)
2627 struct snd_info_entry *entry;
2629 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2630 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read);
2632 #else /* !CONFIG_PROC_FS */
2633 static inline void snd_cmipci_proc_init(struct cmipci *cm) {}
2637 static struct pci_device_id snd_cmipci_ids[] = {
2638 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2639 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2640 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2641 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2642 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2648 * check chip version and capabilities
2649 * driver name is modified according to the chip model
2651 static void __devinit query_chip(struct cmipci *cm)
2653 unsigned int detect;
2655 /* check reg 0Ch, bit 24-31 */
2656 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2658 /* check reg 08h, bit 24-28 */
2659 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2662 cm->chip_version = 33;
2663 if (cm->do_soft_ac3)
2669 cm->chip_version = 37;
2673 cm->chip_version = 39;
2677 cm->max_channels = 2;
2679 if (detect & CM_CHIP_039) {
2680 cm->chip_version = 39;
2681 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2682 cm->max_channels = 6;
2684 cm->max_channels = 4;
2685 } else if (detect & CM_CHIP_8768) {
2686 cm->chip_version = 68;
2687 cm->max_channels = 8;
2689 cm->chip_version = 55;
2690 cm->max_channels = 6;
2693 cm->can_multi_ch = 1;
2697 #ifdef SUPPORT_JOYSTICK
2698 static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2700 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2701 struct gameport *gp;
2702 struct resource *r = NULL;
2705 if (joystick_port[dev] == 0)
2708 if (joystick_port[dev] == 1) { /* auto-detect */
2709 for (i = 0; ports[i]; i++) {
2711 r = request_region(io_port, 1, "CMIPCI gameport");
2716 io_port = joystick_port[dev];
2717 r = request_region(io_port, 1, "CMIPCI gameport");
2721 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2725 cm->gameport = gp = gameport_allocate_port();
2727 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2728 release_and_free_resource(r);
2731 gameport_set_name(gp, "C-Media Gameport");
2732 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2733 gameport_set_dev_parent(gp, &cm->pci->dev);
2735 gameport_set_port_data(gp, r);
2737 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2739 gameport_register_port(cm->gameport);
2744 static void snd_cmipci_free_gameport(struct cmipci *cm)
2747 struct resource *r = gameport_get_port_data(cm->gameport);
2749 gameport_unregister_port(cm->gameport);
2750 cm->gameport = NULL;
2752 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2753 release_and_free_resource(r);
2757 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2758 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2761 static int snd_cmipci_free(struct cmipci *cm)
2764 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2765 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2766 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2767 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2768 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2769 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2770 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2773 snd_cmipci_mixer_write(cm, 0, 0);
2775 synchronize_irq(cm->irq);
2777 free_irq(cm->irq, cm);
2780 snd_cmipci_free_gameport(cm);
2781 pci_release_regions(cm->pci);
2782 pci_disable_device(cm->pci);
2787 static int snd_cmipci_dev_free(struct snd_device *device)
2789 struct cmipci *cm = device->device_data;
2790 return snd_cmipci_free(cm);
2793 static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2797 struct snd_opl3 *opl3;
2803 if (cm->chip_version >= 39) {
2804 /* first try FM regs in PCI port range */
2805 iosynth = cm->iobase + CM_REG_FM_PCI;
2806 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2807 OPL3_HW_OPL3, 1, &opl3);
2812 /* then try legacy ports */
2813 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2816 case 0x3E8: val |= CM_FMSEL_3E8; break;
2817 case 0x3E0: val |= CM_FMSEL_3E0; break;
2818 case 0x3C8: val |= CM_FMSEL_3C8; break;
2819 case 0x388: val |= CM_FMSEL_388; break;
2823 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2825 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2827 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2828 OPL3_HW_OPL3, 0, &opl3) < 0) {
2829 printk(KERN_ERR "cmipci: no OPL device at %#lx, "
2830 "skipping...\n", iosynth);
2834 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2835 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2841 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2842 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2846 static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2847 int dev, struct cmipci **rcmipci)
2851 static struct snd_device_ops ops = {
2852 .dev_free = snd_cmipci_dev_free,
2856 int integrated_midi = 0;
2858 int pcm_index, pcm_spdif_index;
2859 static struct pci_device_id intel_82437vx[] = {
2860 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2866 if ((err = pci_enable_device(pci)) < 0)
2869 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
2871 pci_disable_device(pci);
2875 spin_lock_init(&cm->reg_lock);
2876 mutex_init(&cm->open_mutex);
2877 cm->device = pci->device;
2881 cm->channel[0].ch = 0;
2882 cm->channel[1].ch = 1;
2883 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2885 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2887 pci_disable_device(pci);
2890 cm->iobase = pci_resource_start(pci, 0);
2892 if (request_irq(pci->irq, snd_cmipci_interrupt,
2893 IRQF_SHARED, card->driver, cm)) {
2894 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2895 snd_cmipci_free(cm);
2900 pci_set_master(cm->pci);
2903 * check chip version, max channels and capabilities
2906 cm->chip_version = 0;
2907 cm->max_channels = 2;
2908 cm->do_soft_ac3 = soft_ac3[dev];
2910 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
2911 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
2913 /* added -MCx suffix for chip supporting multi-channels */
2914 if (cm->can_multi_ch)
2915 sprintf(cm->card->driver + strlen(cm->card->driver),
2916 "-MC%d", cm->max_channels);
2917 else if (cm->can_ac3_sw)
2918 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2920 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2921 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2924 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
2926 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
2929 /* initialize codec registers */
2930 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2931 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2932 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2933 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2934 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2936 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2937 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2939 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2941 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2943 /* Set Bus Master Request */
2944 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2946 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2947 switch (pci->device) {
2948 case PCI_DEVICE_ID_CMEDIA_CM8738:
2949 case PCI_DEVICE_ID_CMEDIA_CM8738B:
2950 if (!pci_dev_present(intel_82437vx))
2951 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2957 if (cm->chip_version < 68) {
2958 val = pci->device < 0x110 ? 8338 : 8738;
2960 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
2968 switch ((pci->subsystem_vendor << 16) |
2969 pci->subsystem_device) {
2984 sprintf(card->shortname, "C-Media CMI%d", val);
2985 if (cm->chip_version < 68)
2986 sprintf(modelstr, " (model %d)", cm->chip_version);
2989 sprintf(card->longname, "%s%s at %#lx, irq %i",
2990 card->shortname, modelstr, cm->iobase, cm->irq);
2992 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
2993 snd_cmipci_free(cm);
2997 if (cm->chip_version >= 39) {
2998 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
2999 if (val != 0x00 && val != 0xff) {
3000 iomidi = cm->iobase + CM_REG_MPU_PCI;
3001 integrated_midi = 1;
3004 if (!integrated_midi) {
3006 iomidi = mpu_port[dev];
3008 case 0x320: val = CM_VMPU_320; break;
3009 case 0x310: val = CM_VMPU_310; break;
3010 case 0x300: val = CM_VMPU_300; break;
3011 case 0x330: val = CM_VMPU_330; break;
3016 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3018 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3019 if (inb(iomidi + 1) == 0xff) {
3020 snd_printk(KERN_ERR "cannot enable MPU-401 port"
3021 " at %#lx\n", iomidi);
3022 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3029 if (cm->chip_version < 68) {
3030 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3036 snd_cmipci_mixer_write(cm, 0, 0);
3038 snd_cmipci_proc_init(cm);
3040 /* create pcm devices */
3041 pcm_index = pcm_spdif_index = 0;
3042 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3045 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3048 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3049 pcm_spdif_index = pcm_index;
3050 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3054 /* create mixer interface & switches */
3055 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3059 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3062 MPU401_INFO_INTEGRATED : 0),
3063 cm->irq, 0, &cm->rmidi)) < 0) {
3064 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
3068 #ifdef USE_VAR48KRATE
3069 for (val = 0; val < ARRAY_SIZE(rates); val++)
3070 snd_cmipci_set_pll(cm, rates[val], val);
3073 * (Re-)Enable external switch spdo_48k
3075 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3076 #endif /* USE_VAR48KRATE */
3078 if (snd_cmipci_create_gameport(cm, dev) < 0)
3079 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3081 snd_card_set_dev(card, &pci->dev);
3090 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3092 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
3093 const struct pci_device_id *pci_id)
3096 struct snd_card *card;
3100 if (dev >= SNDRV_CARDS)
3102 if (! enable[dev]) {
3107 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3111 switch (pci->device) {
3112 case PCI_DEVICE_ID_CMEDIA_CM8738:
3113 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3114 strcpy(card->driver, "CMI8738");
3116 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3117 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3118 strcpy(card->driver, "CMI8338");
3121 strcpy(card->driver, "CMIPCI");
3125 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3126 snd_card_free(card);
3129 card->private_data = cm;
3131 if ((err = snd_card_register(card)) < 0) {
3132 snd_card_free(card);
3135 pci_set_drvdata(pci, card);
3141 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3143 snd_card_free(pci_get_drvdata(pci));
3144 pci_set_drvdata(pci, NULL);
3152 static unsigned char saved_regs[] = {
3153 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3154 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3155 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3156 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3157 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3160 static unsigned char saved_mixers[] = {
3161 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3162 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3163 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3164 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3165 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3166 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3167 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3168 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3171 static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state)
3173 struct snd_card *card = pci_get_drvdata(pci);
3174 struct cmipci *cm = card->private_data;
3177 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3179 snd_pcm_suspend_all(cm->pcm);
3180 snd_pcm_suspend_all(cm->pcm2);
3181 snd_pcm_suspend_all(cm->pcm_spdif);
3183 /* save registers */
3184 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3185 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3186 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3187 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3190 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3192 pci_disable_device(pci);
3193 pci_save_state(pci);
3194 pci_set_power_state(pci, pci_choose_state(pci, state));
3198 static int snd_cmipci_resume(struct pci_dev *pci)
3200 struct snd_card *card = pci_get_drvdata(pci);
3201 struct cmipci *cm = card->private_data;
3204 pci_set_power_state(pci, PCI_D0);
3205 pci_restore_state(pci);
3206 if (pci_enable_device(pci) < 0) {
3207 printk(KERN_ERR "cmipci: pci_enable_device failed, "
3208 "disabling device\n");
3209 snd_card_disconnect(card);
3212 pci_set_master(pci);
3214 /* reset / initialize to a sane state */
3215 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3216 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3217 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3218 snd_cmipci_mixer_write(cm, 0, 0);
3220 /* restore registers */
3221 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3222 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3223 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3224 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3226 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3229 #endif /* CONFIG_PM */
3231 static struct pci_driver driver = {
3232 .name = "C-Media PCI",
3233 .id_table = snd_cmipci_ids,
3234 .probe = snd_cmipci_probe,
3235 .remove = __devexit_p(snd_cmipci_remove),
3237 .suspend = snd_cmipci_suspend,
3238 .resume = snd_cmipci_resume,
3242 static int __init alsa_card_cmipci_init(void)
3244 return pci_register_driver(&driver);
3247 static void __exit alsa_card_cmipci_exit(void)
3249 pci_unregister_driver(&driver);
3252 module_init(alsa_card_cmipci_init)
3253 module_exit(alsa_card_cmipci_exit)