3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
68 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
69 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
70 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
71 static char *model[SNDRV_CARDS];
72 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
73 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
74 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
75 static int probe_only[SNDRV_CARDS];
76 static int jackpoll_ms[SNDRV_CARDS];
77 static bool single_cmd;
78 static int enable_msi = -1;
79 #ifdef CONFIG_SND_HDA_PATCH_LOADER
80 static char *patch[SNDRV_CARDS];
82 #ifdef CONFIG_SND_HDA_INPUT_BEEP
83 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
84 CONFIG_SND_HDA_INPUT_BEEP_MODE};
87 module_param_array(index, int, NULL, 0444);
88 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
89 module_param_array(id, charp, NULL, 0444);
90 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
91 module_param_array(enable, bool, NULL, 0444);
92 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
93 module_param_array(model, charp, NULL, 0444);
94 MODULE_PARM_DESC(model, "Use the given board model.");
95 module_param_array(position_fix, int, NULL, 0444);
96 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
97 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
98 module_param_array(bdl_pos_adj, int, NULL, 0644);
99 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
100 module_param_array(probe_mask, int, NULL, 0444);
101 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
102 module_param_array(probe_only, int, NULL, 0444);
103 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
104 module_param_array(jackpoll_ms, int, NULL, 0444);
105 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
106 module_param(single_cmd, bool, 0444);
107 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
108 "(for debugging only).");
109 module_param(enable_msi, bint, 0444);
110 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
111 #ifdef CONFIG_SND_HDA_PATCH_LOADER
112 module_param_array(patch, charp, NULL, 0444);
113 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
115 #ifdef CONFIG_SND_HDA_INPUT_BEEP
116 module_param_array(beep_mode, bool, NULL, 0444);
117 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
118 "(0=off, 1=on) (default=1).");
122 static int param_set_xint(const char *val, const struct kernel_param *kp);
123 static struct kernel_param_ops param_ops_xint = {
124 .set = param_set_xint,
125 .get = param_get_int,
127 #define param_check_xint param_check_int
129 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
130 module_param(power_save, xint, 0644);
131 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
132 "(in second, 0 = disable).");
134 /* reset the HD-audio controller in power save mode.
135 * this may give more power-saving, but will take longer time to
138 static bool power_save_controller = 1;
139 module_param(power_save_controller, bool, 0644);
140 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
141 #endif /* CONFIG_PM */
143 static int align_buffer_size = -1;
144 module_param(align_buffer_size, bint, 0644);
145 MODULE_PARM_DESC(align_buffer_size,
146 "Force buffer and period sizes to be multiple of 128 bytes.");
149 static bool hda_snoop = true;
150 module_param_named(snoop, hda_snoop, bool, 0444);
151 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
152 #define azx_snoop(chip) (chip)->snoop
154 #define hda_snoop true
155 #define azx_snoop(chip) true
159 MODULE_LICENSE("GPL");
160 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
192 MODULE_DESCRIPTION("Intel HDA driver");
194 #ifdef CONFIG_SND_VERBOSE_PRINTK
195 #define SFX /* nop */
197 #define SFX "hda-intel "
200 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
201 #ifdef CONFIG_SND_HDA_CODEC_HDMI
202 #define SUPPORT_VGA_SWITCHEROO
210 #define ICH6_REG_GCAP 0x00
211 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
212 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
213 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
214 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
215 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
216 #define ICH6_REG_VMIN 0x02
217 #define ICH6_REG_VMAJ 0x03
218 #define ICH6_REG_OUTPAY 0x04
219 #define ICH6_REG_INPAY 0x06
220 #define ICH6_REG_GCTL 0x08
221 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
222 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
223 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
224 #define ICH6_REG_WAKEEN 0x0c
225 #define ICH6_REG_STATESTS 0x0e
226 #define ICH6_REG_GSTS 0x10
227 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
228 #define ICH6_REG_INTCTL 0x20
229 #define ICH6_REG_INTSTS 0x24
230 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
231 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
232 #define ICH6_REG_SSYNC 0x38
233 #define ICH6_REG_CORBLBASE 0x40
234 #define ICH6_REG_CORBUBASE 0x44
235 #define ICH6_REG_CORBWP 0x48
236 #define ICH6_REG_CORBRP 0x4a
237 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
238 #define ICH6_REG_CORBCTL 0x4c
239 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
240 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
241 #define ICH6_REG_CORBSTS 0x4d
242 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
243 #define ICH6_REG_CORBSIZE 0x4e
245 #define ICH6_REG_RIRBLBASE 0x50
246 #define ICH6_REG_RIRBUBASE 0x54
247 #define ICH6_REG_RIRBWP 0x58
248 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
249 #define ICH6_REG_RINTCNT 0x5a
250 #define ICH6_REG_RIRBCTL 0x5c
251 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
252 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
253 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
254 #define ICH6_REG_RIRBSTS 0x5d
255 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
256 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
257 #define ICH6_REG_RIRBSIZE 0x5e
259 #define ICH6_REG_IC 0x60
260 #define ICH6_REG_IR 0x64
261 #define ICH6_REG_IRS 0x68
262 #define ICH6_IRS_VALID (1<<1)
263 #define ICH6_IRS_BUSY (1<<0)
265 #define ICH6_REG_DPLBASE 0x70
266 #define ICH6_REG_DPUBASE 0x74
267 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
269 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
270 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
272 /* stream register offsets from stream base */
273 #define ICH6_REG_SD_CTL 0x00
274 #define ICH6_REG_SD_STS 0x03
275 #define ICH6_REG_SD_LPIB 0x04
276 #define ICH6_REG_SD_CBL 0x08
277 #define ICH6_REG_SD_LVI 0x0c
278 #define ICH6_REG_SD_FIFOW 0x0e
279 #define ICH6_REG_SD_FIFOSIZE 0x10
280 #define ICH6_REG_SD_FORMAT 0x12
281 #define ICH6_REG_SD_BDLPL 0x18
282 #define ICH6_REG_SD_BDLPU 0x1c
285 #define ICH6_PCIREG_TCSEL 0x44
291 /* max number of SDs */
292 /* ICH, ATI and VIA have 4 playback and 4 capture */
293 #define ICH6_NUM_CAPTURE 4
294 #define ICH6_NUM_PLAYBACK 4
296 /* ULI has 6 playback and 5 capture */
297 #define ULI_NUM_CAPTURE 5
298 #define ULI_NUM_PLAYBACK 6
300 /* ATI HDMI has 1 playback and 0 capture */
301 #define ATIHDMI_NUM_CAPTURE 0
302 #define ATIHDMI_NUM_PLAYBACK 1
304 /* TERA has 4 playback and 3 capture */
305 #define TERA_NUM_CAPTURE 3
306 #define TERA_NUM_PLAYBACK 4
308 /* this number is statically defined for simplicity */
309 #define MAX_AZX_DEV 16
311 /* max number of fragments - we may use more if allocating more pages for BDL */
312 #define BDL_SIZE 4096
313 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
314 #define AZX_MAX_FRAG 32
315 /* max buffer size - no h/w limit, you can increase as you like */
316 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
318 /* RIRB int mask: overrun[2], response[0] */
319 #define RIRB_INT_RESPONSE 0x01
320 #define RIRB_INT_OVERRUN 0x04
321 #define RIRB_INT_MASK 0x05
323 /* STATESTS int mask: S3,SD2,SD1,SD0 */
324 #define AZX_MAX_CODECS 8
325 #define AZX_DEFAULT_CODECS 4
326 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
329 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
330 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
331 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
332 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
333 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
334 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
335 #define SD_CTL_STREAM_TAG_SHIFT 20
337 /* SD_CTL and SD_STS */
338 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
339 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
340 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
341 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
345 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
347 /* INTCTL and INTSTS */
348 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
349 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
350 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
352 /* below are so far hardcoded - should read registers in future */
353 #define ICH6_MAX_CORB_ENTRIES 256
354 #define ICH6_MAX_RIRB_ENTRIES 256
356 /* position fix mode */
365 /* Defines for ATI HD Audio support in SB450 south bridge */
366 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
367 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
369 /* Defines for Nvidia HDA support */
370 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
371 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
372 #define NVIDIA_HDA_ISTRM_COH 0x4d
373 #define NVIDIA_HDA_OSTRM_COH 0x4c
374 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
376 /* Defines for Intel SCH HDA snoop control */
377 #define INTEL_SCH_HDA_DEVC 0x78
378 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
380 /* Define IN stream 0 FIFO size offset in VIA controller */
381 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
382 /* Define VIA HD Audio Device ID*/
383 #define VIA_HDAC_DEVICE_ID 0x3288
385 /* HD Audio class code */
386 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
392 struct snd_dma_buffer bdl; /* BDL buffer */
393 u32 *posbuf; /* position buffer pointer */
395 unsigned int bufsize; /* size of the play buffer in bytes */
396 unsigned int period_bytes; /* size of the period in bytes */
397 unsigned int frags; /* number for period in the play buffer */
398 unsigned int fifo_size; /* FIFO size */
399 unsigned long start_wallclk; /* start + minimum wallclk */
400 unsigned long period_wallclk; /* wallclk for period */
402 void __iomem *sd_addr; /* stream descriptor pointer */
404 u32 sd_int_sta_mask; /* stream int status mask */
407 struct snd_pcm_substream *substream; /* assigned substream,
410 unsigned int format_val; /* format value to be set in the
411 * controller and the codec
413 unsigned char stream_tag; /* assigned stream */
414 unsigned char index; /* stream index */
415 int assigned_key; /* last device# key assigned to */
417 unsigned int opened :1;
418 unsigned int running :1;
419 unsigned int irq_pending :1;
420 unsigned int prepared:1;
421 unsigned int locked:1;
424 * A flag to ensure DMA position is 0
425 * when link position is not greater than FIFO size
427 unsigned int insufficient :1;
428 unsigned int wc_marked:1;
429 unsigned int no_period_wakeup:1;
431 struct timecounter azx_tc;
432 struct cyclecounter azx_cc;
434 #ifdef CONFIG_SND_HDA_DSP_LOADER
435 struct mutex dsp_mutex;
439 /* DSP lock helpers */
440 #ifdef CONFIG_SND_HDA_DSP_LOADER
441 #define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
442 #define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
443 #define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
444 #define dsp_is_locked(dev) ((dev)->locked)
446 #define dsp_lock_init(dev) do {} while (0)
447 #define dsp_lock(dev) do {} while (0)
448 #define dsp_unlock(dev) do {} while (0)
449 #define dsp_is_locked(dev) 0
454 u32 *buf; /* CORB/RIRB buffer
455 * Each CORB entry is 4byte, RIRB is 8byte
457 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
459 unsigned short rp, wp; /* read/write pointers */
460 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
461 u32 res[AZX_MAX_CODECS]; /* last read value */
467 struct hda_codec *codec;
468 struct hda_pcm_stream *hinfo[2];
469 struct list_head list;
473 struct snd_card *card;
477 /* chip type specific */
479 unsigned int driver_caps;
480 int playback_streams;
481 int playback_index_offset;
483 int capture_index_offset;
488 void __iomem *remap_addr;
493 struct mutex open_mutex;
494 struct completion probe_wait;
496 /* streams (x num_streams) */
497 struct azx_dev *azx_dev;
500 struct list_head pcm_list; /* azx_pcm list */
503 unsigned short codec_mask;
504 int codec_probe_mask; /* copied from probe_mask option */
506 unsigned int beep_mode;
512 /* CORB/RIRB and position buffers */
513 struct snd_dma_buffer rb;
514 struct snd_dma_buffer posbuf;
516 #ifdef CONFIG_SND_HDA_PATCH_LOADER
517 const struct firmware *fw;
521 int position_fix[2]; /* for both playback/capture streams */
523 unsigned int running :1;
524 unsigned int initialized :1;
525 unsigned int single_cmd :1;
526 unsigned int polling_mode :1;
528 unsigned int irq_pending_warned :1;
529 unsigned int probing :1; /* codec probing phase */
530 unsigned int snoop:1;
531 unsigned int align_buffer_size:1;
532 unsigned int region_requested:1;
534 /* VGA-switcheroo setup */
535 unsigned int use_vga_switcheroo:1;
536 unsigned int vga_switcheroo_registered:1;
537 unsigned int init_failed:1; /* delayed init failed */
538 unsigned int disabled:1; /* disabled by VGA-switcher */
541 unsigned int last_cmd[AZX_MAX_CODECS];
543 /* for pending irqs */
544 struct work_struct irq_pending_work;
546 #ifdef CONFIG_SND_HDA_I915
547 struct work_struct probe_work;
550 /* reboot notifier (for mysterious hangup problem at power-down) */
551 struct notifier_block reboot_notifier;
553 /* card list (for power_save trigger) */
554 struct list_head list;
556 #ifdef CONFIG_SND_HDA_DSP_LOADER
557 struct azx_dev saved_azx_dev;
560 /* secondary power domain for hdmi audio under vga device */
561 struct dev_pm_domain hdmi_pm_domain;
564 #define CREATE_TRACE_POINTS
565 #include "hda_intel_trace.h"
574 AZX_DRIVER_ATIHDMI_NS,
583 AZX_NUM_DRIVERS, /* keep this as last entry */
586 /* driver quirks (capabilities) */
587 /* bits 0-7 are used for indicating driver type */
588 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
589 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
590 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
591 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
592 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
593 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
594 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
595 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
596 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
597 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
598 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
599 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
600 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
601 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
602 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
603 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
604 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
605 #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
606 #define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 power well support */
608 /* quirks for Intel PCH */
609 #define AZX_DCAPS_INTEL_PCH_NOPM \
610 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
611 AZX_DCAPS_COUNT_LPIB_DELAY)
613 #define AZX_DCAPS_INTEL_PCH \
614 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
616 /* quirks for ATI SB / AMD Hudson */
617 #define AZX_DCAPS_PRESET_ATI_SB \
618 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
619 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
621 /* quirks for ATI/AMD HDMI */
622 #define AZX_DCAPS_PRESET_ATI_HDMI \
623 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
625 /* quirks for Nvidia */
626 #define AZX_DCAPS_PRESET_NVIDIA \
627 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
628 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
630 #define AZX_DCAPS_PRESET_CTHDA \
631 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
634 * VGA-switcher support
636 #ifdef SUPPORT_VGA_SWITCHEROO
637 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
639 #define use_vga_switcheroo(chip) 0
642 static char *driver_short_names[] = {
643 [AZX_DRIVER_ICH] = "HDA Intel",
644 [AZX_DRIVER_PCH] = "HDA Intel PCH",
645 [AZX_DRIVER_SCH] = "HDA Intel MID",
646 [AZX_DRIVER_ATI] = "HDA ATI SB",
647 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
648 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
649 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
650 [AZX_DRIVER_SIS] = "HDA SIS966",
651 [AZX_DRIVER_ULI] = "HDA ULI M5461",
652 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
653 [AZX_DRIVER_TERA] = "HDA Teradici",
654 [AZX_DRIVER_CTX] = "HDA Creative",
655 [AZX_DRIVER_CTHDA] = "HDA Creative",
656 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
660 * macros for easy use
662 #define azx_writel(chip,reg,value) \
663 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
664 #define azx_readl(chip,reg) \
665 readl((chip)->remap_addr + ICH6_REG_##reg)
666 #define azx_writew(chip,reg,value) \
667 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
668 #define azx_readw(chip,reg) \
669 readw((chip)->remap_addr + ICH6_REG_##reg)
670 #define azx_writeb(chip,reg,value) \
671 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
672 #define azx_readb(chip,reg) \
673 readb((chip)->remap_addr + ICH6_REG_##reg)
675 #define azx_sd_writel(dev,reg,value) \
676 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
677 #define azx_sd_readl(dev,reg) \
678 readl((dev)->sd_addr + ICH6_REG_##reg)
679 #define azx_sd_writew(dev,reg,value) \
680 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
681 #define azx_sd_readw(dev,reg) \
682 readw((dev)->sd_addr + ICH6_REG_##reg)
683 #define azx_sd_writeb(dev,reg,value) \
684 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
685 #define azx_sd_readb(dev,reg) \
686 readb((dev)->sd_addr + ICH6_REG_##reg)
688 /* for pcm support */
689 #define get_azx_dev(substream) (substream->runtime->private_data)
692 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
698 if (!dmab || !dmab->area || !dmab->bytes)
701 #ifdef CONFIG_SND_DMA_SGBUF
702 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
703 struct snd_sg_buf *sgbuf = dmab->private_data;
705 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
707 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
712 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
714 set_memory_wc((unsigned long)dmab->area, pages);
716 set_memory_wb((unsigned long)dmab->area, pages);
719 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
722 __mark_pages_wc(chip, buf, on);
724 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
725 struct snd_pcm_substream *substream, bool on)
727 if (azx_dev->wc_marked != on) {
728 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
729 azx_dev->wc_marked = on;
733 /* NOP for other archs */
734 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
738 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
739 struct snd_pcm_substream *substream, bool on)
744 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
745 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
747 * Interface for HD codec
751 * CORB / RIRB interface
753 static int azx_alloc_cmd_io(struct azx *chip)
757 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
758 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
759 snd_dma_pci_data(chip->pci),
760 PAGE_SIZE, &chip->rb);
762 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
765 mark_pages_wc(chip, &chip->rb, true);
769 static void azx_init_cmd_io(struct azx *chip)
771 spin_lock_irq(&chip->reg_lock);
773 chip->corb.addr = chip->rb.addr;
774 chip->corb.buf = (u32 *)chip->rb.area;
775 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
776 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
778 /* set the corb size to 256 entries (ULI requires explicitly) */
779 azx_writeb(chip, CORBSIZE, 0x02);
780 /* set the corb write pointer to 0 */
781 azx_writew(chip, CORBWP, 0);
782 /* reset the corb hw read pointer */
783 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
784 /* enable corb dma */
785 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
788 chip->rirb.addr = chip->rb.addr + 2048;
789 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
790 chip->rirb.wp = chip->rirb.rp = 0;
791 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
792 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
793 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
795 /* set the rirb size to 256 entries (ULI requires explicitly) */
796 azx_writeb(chip, RIRBSIZE, 0x02);
797 /* reset the rirb hw write pointer */
798 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
799 /* set N=1, get RIRB response interrupt for new entry */
800 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
801 azx_writew(chip, RINTCNT, 0xc0);
803 azx_writew(chip, RINTCNT, 1);
804 /* enable rirb dma and response irq */
805 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
806 spin_unlock_irq(&chip->reg_lock);
809 static void azx_free_cmd_io(struct azx *chip)
811 spin_lock_irq(&chip->reg_lock);
812 /* disable ringbuffer DMAs */
813 azx_writeb(chip, RIRBCTL, 0);
814 azx_writeb(chip, CORBCTL, 0);
815 spin_unlock_irq(&chip->reg_lock);
818 static unsigned int azx_command_addr(u32 cmd)
820 unsigned int addr = cmd >> 28;
822 if (addr >= AZX_MAX_CODECS) {
830 static unsigned int azx_response_addr(u32 res)
832 unsigned int addr = res & 0xf;
834 if (addr >= AZX_MAX_CODECS) {
843 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
845 struct azx *chip = bus->private_data;
846 unsigned int addr = azx_command_addr(val);
849 spin_lock_irq(&chip->reg_lock);
851 /* add command to corb */
852 wp = azx_readw(chip, CORBWP);
854 /* something wrong, controller likely turned to D3 */
855 spin_unlock_irq(&chip->reg_lock);
859 wp %= ICH6_MAX_CORB_ENTRIES;
861 rp = azx_readw(chip, CORBRP);
863 /* oops, it's full */
864 spin_unlock_irq(&chip->reg_lock);
868 chip->rirb.cmds[addr]++;
869 chip->corb.buf[wp] = cpu_to_le32(val);
870 azx_writel(chip, CORBWP, wp);
872 spin_unlock_irq(&chip->reg_lock);
877 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
879 /* retrieve RIRB entry - called from interrupt handler */
880 static void azx_update_rirb(struct azx *chip)
886 wp = azx_readw(chip, RIRBWP);
888 /* something wrong, controller likely turned to D3 */
892 if (wp == chip->rirb.wp)
896 while (chip->rirb.rp != wp) {
898 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
900 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
901 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
902 res = le32_to_cpu(chip->rirb.buf[rp]);
903 addr = azx_response_addr(res_ex);
904 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
905 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
906 else if (chip->rirb.cmds[addr]) {
907 chip->rirb.res[addr] = res;
909 chip->rirb.cmds[addr]--;
911 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
915 chip->last_cmd[addr]);
919 /* receive a response */
920 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
923 struct azx *chip = bus->private_data;
924 unsigned long timeout;
925 unsigned long loopcounter;
929 timeout = jiffies + msecs_to_jiffies(1000);
931 for (loopcounter = 0;; loopcounter++) {
932 if (chip->polling_mode || do_poll) {
933 spin_lock_irq(&chip->reg_lock);
934 azx_update_rirb(chip);
935 spin_unlock_irq(&chip->reg_lock);
937 if (!chip->rirb.cmds[addr]) {
942 chip->poll_count = 0;
943 return chip->rirb.res[addr]; /* the last value */
945 if (time_after(jiffies, timeout))
947 if (bus->needs_damn_long_delay || loopcounter > 3000)
948 msleep(2); /* temporary workaround */
955 if (!bus->no_response_fallback)
958 if (!chip->polling_mode && chip->poll_count < 2) {
959 snd_printdd(SFX "%s: azx_get_response timeout, "
960 "polling the codec once: last cmd=0x%08x\n",
961 pci_name(chip->pci), chip->last_cmd[addr]);
968 if (!chip->polling_mode) {
969 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
970 "switching to polling mode: last cmd=0x%08x\n",
971 pci_name(chip->pci), chip->last_cmd[addr]);
972 chip->polling_mode = 1;
977 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
978 "disabling MSI: last cmd=0x%08x\n",
979 pci_name(chip->pci), chip->last_cmd[addr]);
980 free_irq(chip->irq, chip);
982 pci_disable_msi(chip->pci);
984 if (azx_acquire_irq(chip, 1) < 0) {
992 /* If this critical timeout happens during the codec probing
993 * phase, this is likely an access to a non-existing codec
994 * slot. Better to return an error and reset the system.
999 /* a fatal communication error; need either to reset or to fallback
1000 * to the single_cmd mode
1002 bus->rirb_error = 1;
1003 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
1004 bus->response_reset = 1;
1005 return -1; /* give a chance to retry */
1008 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
1009 "switching to single_cmd mode: last cmd=0x%08x\n",
1010 chip->last_cmd[addr]);
1011 chip->single_cmd = 1;
1012 bus->response_reset = 0;
1013 /* release CORB/RIRB */
1014 azx_free_cmd_io(chip);
1015 /* disable unsolicited responses */
1016 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
1021 * Use the single immediate command instead of CORB/RIRB for simplicity
1023 * Note: according to Intel, this is not preferred use. The command was
1024 * intended for the BIOS only, and may get confused with unsolicited
1025 * responses. So, we shouldn't use it for normal operation from the
1027 * I left the codes, however, for debugging/testing purposes.
1030 /* receive a response */
1031 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1036 /* check IRV busy bit */
1037 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1038 /* reuse rirb.res as the response return value */
1039 chip->rirb.res[addr] = azx_readl(chip, IR);
1044 if (printk_ratelimit())
1045 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1046 pci_name(chip->pci), azx_readw(chip, IRS));
1047 chip->rirb.res[addr] = -1;
1051 /* send a command */
1052 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1054 struct azx *chip = bus->private_data;
1055 unsigned int addr = azx_command_addr(val);
1058 bus->rirb_error = 0;
1060 /* check ICB busy bit */
1061 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1062 /* Clear IRV valid bit */
1063 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1065 azx_writel(chip, IC, val);
1066 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1068 return azx_single_wait_for_response(chip, addr);
1072 if (printk_ratelimit())
1073 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1074 pci_name(chip->pci), azx_readw(chip, IRS), val);
1078 /* receive a response */
1079 static unsigned int azx_single_get_response(struct hda_bus *bus,
1082 struct azx *chip = bus->private_data;
1083 return chip->rirb.res[addr];
1087 * The below are the main callbacks from hda_codec.
1089 * They are just the skeleton to call sub-callbacks according to the
1090 * current setting of chip->single_cmd.
1093 /* send a command */
1094 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1096 struct azx *chip = bus->private_data;
1100 chip->last_cmd[azx_command_addr(val)] = val;
1101 if (chip->single_cmd)
1102 return azx_single_send_cmd(bus, val);
1104 return azx_corb_send_cmd(bus, val);
1107 /* get a response */
1108 static unsigned int azx_get_response(struct hda_bus *bus,
1111 struct azx *chip = bus->private_data;
1114 if (chip->single_cmd)
1115 return azx_single_get_response(bus, addr);
1117 return azx_rirb_get_response(bus, addr);
1121 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1124 #ifdef CONFIG_SND_HDA_DSP_LOADER
1125 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1126 unsigned int byte_size,
1127 struct snd_dma_buffer *bufp);
1128 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1129 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1130 struct snd_dma_buffer *dmab);
1133 /* enter link reset */
1134 static void azx_enter_link_reset(struct azx *chip)
1136 unsigned long timeout;
1138 /* reset controller */
1139 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1141 timeout = jiffies + msecs_to_jiffies(100);
1142 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
1143 time_before(jiffies, timeout))
1144 usleep_range(500, 1000);
1147 /* exit link reset */
1148 static void azx_exit_link_reset(struct azx *chip)
1150 unsigned long timeout;
1152 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1154 timeout = jiffies + msecs_to_jiffies(100);
1155 while (!azx_readb(chip, GCTL) &&
1156 time_before(jiffies, timeout))
1157 usleep_range(500, 1000);
1160 /* reset codec link */
1161 static int azx_reset(struct azx *chip, int full_reset)
1166 /* clear STATESTS */
1167 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1169 /* reset controller */
1170 azx_enter_link_reset(chip);
1172 /* delay for >= 100us for codec PLL to settle per spec
1173 * Rev 0.9 section 5.5.1
1175 usleep_range(500, 1000);
1177 /* Bring controller out of reset */
1178 azx_exit_link_reset(chip);
1180 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1181 usleep_range(1000, 1200);
1184 /* check to see if controller is ready */
1185 if (!azx_readb(chip, GCTL)) {
1186 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1190 /* Accept unsolicited responses */
1191 if (!chip->single_cmd)
1192 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1196 if (!chip->codec_mask) {
1197 chip->codec_mask = azx_readw(chip, STATESTS);
1198 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1206 * Lowlevel interface
1209 /* enable interrupts */
1210 static void azx_int_enable(struct azx *chip)
1212 /* enable controller CIE and GIE */
1213 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1214 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1217 /* disable interrupts */
1218 static void azx_int_disable(struct azx *chip)
1222 /* disable interrupts in stream descriptor */
1223 for (i = 0; i < chip->num_streams; i++) {
1224 struct azx_dev *azx_dev = &chip->azx_dev[i];
1225 azx_sd_writeb(azx_dev, SD_CTL,
1226 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1229 /* disable SIE for all streams */
1230 azx_writeb(chip, INTCTL, 0);
1232 /* disable controller CIE and GIE */
1233 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1234 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1237 /* clear interrupts */
1238 static void azx_int_clear(struct azx *chip)
1242 /* clear stream status */
1243 for (i = 0; i < chip->num_streams; i++) {
1244 struct azx_dev *azx_dev = &chip->azx_dev[i];
1245 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1248 /* clear STATESTS */
1249 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1251 /* clear rirb status */
1252 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1254 /* clear int status */
1255 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1258 /* start a stream */
1259 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1262 * Before stream start, initialize parameter
1264 azx_dev->insufficient = 1;
1267 azx_writel(chip, INTCTL,
1268 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1269 /* set DMA start and interrupt mask */
1270 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1271 SD_CTL_DMA_START | SD_INT_MASK);
1275 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1277 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1278 ~(SD_CTL_DMA_START | SD_INT_MASK));
1279 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1283 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1285 azx_stream_clear(chip, azx_dev);
1287 azx_writel(chip, INTCTL,
1288 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1293 * reset and start the controller registers
1295 static void azx_init_chip(struct azx *chip, int full_reset)
1297 if (chip->initialized)
1300 /* reset controller */
1301 azx_reset(chip, full_reset);
1303 /* initialize interrupts */
1304 azx_int_clear(chip);
1305 azx_int_enable(chip);
1307 /* initialize the codec command I/O */
1308 if (!chip->single_cmd)
1309 azx_init_cmd_io(chip);
1311 /* program the position buffer */
1312 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1313 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1315 chip->initialized = 1;
1319 * initialize the PCI registers
1321 /* update bits in a PCI register byte */
1322 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1323 unsigned char mask, unsigned char val)
1327 pci_read_config_byte(pci, reg, &data);
1329 data |= (val & mask);
1330 pci_write_config_byte(pci, reg, data);
1333 static void azx_init_pci(struct azx *chip)
1335 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1336 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1337 * Ensuring these bits are 0 clears playback static on some HD Audio
1339 * The PCI register TCSEL is defined in the Intel manuals.
1341 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1342 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1343 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1346 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1347 * we need to enable snoop.
1349 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1350 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1351 update_pci_byte(chip->pci,
1352 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1353 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1356 /* For NVIDIA HDA, enable snoop */
1357 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1358 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1359 update_pci_byte(chip->pci,
1360 NVIDIA_HDA_TRANSREG_ADDR,
1361 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1362 update_pci_byte(chip->pci,
1363 NVIDIA_HDA_ISTRM_COH,
1364 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1365 update_pci_byte(chip->pci,
1366 NVIDIA_HDA_OSTRM_COH,
1367 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1370 /* Enable SCH/PCH snoop if needed */
1371 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1372 unsigned short snoop;
1373 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1374 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1375 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1376 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1377 if (!azx_snoop(chip))
1378 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1379 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1380 pci_read_config_word(chip->pci,
1381 INTEL_SCH_HDA_DEVC, &snoop);
1383 snd_printdd(SFX "%s: SCH snoop: %s\n",
1384 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1385 ? "Disabled" : "Enabled");
1390 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1395 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1397 struct azx *chip = dev_id;
1398 struct azx_dev *azx_dev;
1403 #ifdef CONFIG_PM_RUNTIME
1404 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1405 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1409 spin_lock(&chip->reg_lock);
1411 if (chip->disabled) {
1412 spin_unlock(&chip->reg_lock);
1416 status = azx_readl(chip, INTSTS);
1417 if (status == 0 || status == 0xffffffff) {
1418 spin_unlock(&chip->reg_lock);
1422 for (i = 0; i < chip->num_streams; i++) {
1423 azx_dev = &chip->azx_dev[i];
1424 if (status & azx_dev->sd_int_sta_mask) {
1425 sd_status = azx_sd_readb(azx_dev, SD_STS);
1426 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1427 if (!azx_dev->substream || !azx_dev->running ||
1428 !(sd_status & SD_INT_COMPLETE))
1430 /* check whether this IRQ is really acceptable */
1431 ok = azx_position_ok(chip, azx_dev);
1433 azx_dev->irq_pending = 0;
1434 spin_unlock(&chip->reg_lock);
1435 snd_pcm_period_elapsed(azx_dev->substream);
1436 spin_lock(&chip->reg_lock);
1437 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1438 /* bogus IRQ, process it later */
1439 azx_dev->irq_pending = 1;
1440 queue_work(chip->bus->workq,
1441 &chip->irq_pending_work);
1446 /* clear rirb int */
1447 status = azx_readb(chip, RIRBSTS);
1448 if (status & RIRB_INT_MASK) {
1449 if (status & RIRB_INT_RESPONSE) {
1450 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1452 azx_update_rirb(chip);
1454 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1458 /* clear state status int */
1459 if (azx_readw(chip, STATESTS) & 0x04)
1460 azx_writew(chip, STATESTS, 0x04);
1462 spin_unlock(&chip->reg_lock);
1469 * set up a BDL entry
1471 static int setup_bdle(struct azx *chip,
1472 struct snd_dma_buffer *dmab,
1473 struct azx_dev *azx_dev, u32 **bdlp,
1474 int ofs, int size, int with_ioc)
1482 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1485 addr = snd_sgbuf_get_addr(dmab, ofs);
1486 /* program the address field of the BDL entry */
1487 bdl[0] = cpu_to_le32((u32)addr);
1488 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1489 /* program the size field of the BDL entry */
1490 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1491 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1492 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1493 u32 remain = 0x1000 - (ofs & 0xfff);
1497 bdl[2] = cpu_to_le32(chunk);
1498 /* program the IOC to enable interrupt
1499 * only when the whole fragment is processed
1502 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1512 * set up BDL entries
1514 static int azx_setup_periods(struct azx *chip,
1515 struct snd_pcm_substream *substream,
1516 struct azx_dev *azx_dev)
1519 int i, ofs, periods, period_bytes;
1522 /* reset BDL address */
1523 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1524 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1526 period_bytes = azx_dev->period_bytes;
1527 periods = azx_dev->bufsize / period_bytes;
1529 /* program the initial BDL entries */
1530 bdl = (u32 *)azx_dev->bdl.area;
1533 pos_adj = bdl_pos_adj[chip->dev_index];
1534 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1535 struct snd_pcm_runtime *runtime = substream->runtime;
1536 int pos_align = pos_adj;
1537 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1539 pos_adj = pos_align;
1541 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1543 pos_adj = frames_to_bytes(runtime, pos_adj);
1544 if (pos_adj >= period_bytes) {
1545 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1546 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1549 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1551 &bdl, ofs, pos_adj, true);
1557 for (i = 0; i < periods; i++) {
1558 if (i == periods - 1 && pos_adj)
1559 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1561 period_bytes - pos_adj, 0);
1563 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1566 !azx_dev->no_period_wakeup);
1573 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1574 pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1579 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1584 azx_stream_clear(chip, azx_dev);
1586 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1587 SD_CTL_STREAM_RESET);
1590 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1593 val &= ~SD_CTL_STREAM_RESET;
1594 azx_sd_writeb(azx_dev, SD_CTL, val);
1598 /* waiting for hardware to report that the stream is out of reset */
1599 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1603 /* reset first position - may not be synced with hw at this time */
1604 *azx_dev->posbuf = 0;
1608 * set up the SD for streaming
1610 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1613 /* make sure the run bit is zero for SD */
1614 azx_stream_clear(chip, azx_dev);
1615 /* program the stream_tag */
1616 val = azx_sd_readl(azx_dev, SD_CTL);
1617 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1618 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1619 if (!azx_snoop(chip))
1620 val |= SD_CTL_TRAFFIC_PRIO;
1621 azx_sd_writel(azx_dev, SD_CTL, val);
1623 /* program the length of samples in cyclic buffer */
1624 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1626 /* program the stream format */
1627 /* this value needs to be the same as the one programmed */
1628 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1630 /* program the stream LVI (last valid index) of the BDL */
1631 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1633 /* program the BDL address */
1634 /* lower BDL address */
1635 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1636 /* upper BDL address */
1637 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1639 /* enable the position buffer */
1640 if (chip->position_fix[0] != POS_FIX_LPIB ||
1641 chip->position_fix[1] != POS_FIX_LPIB) {
1642 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1643 azx_writel(chip, DPLBASE,
1644 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1647 /* set the interrupt enable bits in the descriptor control register */
1648 azx_sd_writel(azx_dev, SD_CTL,
1649 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1655 * Probe the given codec address
1657 static int probe_codec(struct azx *chip, int addr)
1659 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1660 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1663 mutex_lock(&chip->bus->cmd_mutex);
1665 azx_send_cmd(chip->bus, cmd);
1666 res = azx_get_response(chip->bus, addr);
1668 mutex_unlock(&chip->bus->cmd_mutex);
1671 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1675 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1676 struct hda_pcm *cpcm);
1677 static void azx_stop_chip(struct azx *chip);
1679 static void azx_bus_reset(struct hda_bus *bus)
1681 struct azx *chip = bus->private_data;
1684 azx_stop_chip(chip);
1685 azx_init_chip(chip, 1);
1687 if (chip->initialized) {
1689 list_for_each_entry(p, &chip->pcm_list, list)
1690 snd_pcm_suspend_all(p->pcm);
1691 snd_hda_suspend(chip->bus);
1692 snd_hda_resume(chip->bus);
1698 static int get_jackpoll_interval(struct azx *chip)
1700 int i = jackpoll_ms[chip->dev_index];
1704 if (i < 50 || i > 60000)
1707 j = msecs_to_jiffies(i);
1709 snd_printk(KERN_WARNING SFX
1710 "jackpoll_ms value out of range: %d\n", i);
1715 * Codec initialization
1718 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1719 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1720 [AZX_DRIVER_NVIDIA] = 8,
1721 [AZX_DRIVER_TERA] = 1,
1724 static int azx_codec_create(struct azx *chip, const char *model)
1726 struct hda_bus_template bus_temp;
1730 memset(&bus_temp, 0, sizeof(bus_temp));
1731 bus_temp.private_data = chip;
1732 bus_temp.modelname = model;
1733 bus_temp.pci = chip->pci;
1734 bus_temp.ops.command = azx_send_cmd;
1735 bus_temp.ops.get_response = azx_get_response;
1736 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1737 bus_temp.ops.bus_reset = azx_bus_reset;
1739 bus_temp.power_save = &power_save;
1740 bus_temp.ops.pm_notify = azx_power_notify;
1742 #ifdef CONFIG_SND_HDA_DSP_LOADER
1743 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1744 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1745 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1748 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1752 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1753 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1754 chip->bus->needs_damn_long_delay = 1;
1758 max_slots = azx_max_codecs[chip->driver_type];
1760 max_slots = AZX_DEFAULT_CODECS;
1762 /* First try to probe all given codec slots */
1763 for (c = 0; c < max_slots; c++) {
1764 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1765 if (probe_codec(chip, c) < 0) {
1766 /* Some BIOSen give you wrong codec addresses
1769 snd_printk(KERN_WARNING SFX
1770 "%s: Codec #%d probe error; "
1771 "disabling it...\n", pci_name(chip->pci), c);
1772 chip->codec_mask &= ~(1 << c);
1773 /* More badly, accessing to a non-existing
1774 * codec often screws up the controller chip,
1775 * and disturbs the further communications.
1776 * Thus if an error occurs during probing,
1777 * better to reset the controller chip to
1778 * get back to the sanity state.
1780 azx_stop_chip(chip);
1781 azx_init_chip(chip, 1);
1786 /* AMD chipsets often cause the communication stalls upon certain
1787 * sequence like the pin-detection. It seems that forcing the synced
1788 * access works around the stall. Grrr...
1790 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1791 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1792 pci_name(chip->pci));
1793 chip->bus->sync_write = 1;
1794 chip->bus->allow_bus_reset = 1;
1797 /* Then create codec instances */
1798 for (c = 0; c < max_slots; c++) {
1799 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1800 struct hda_codec *codec;
1801 err = snd_hda_codec_new(chip->bus, c, &codec);
1804 codec->jackpoll_interval = get_jackpoll_interval(chip);
1805 codec->beep_mode = chip->beep_mode;
1810 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1816 /* configure each codec instance */
1817 static int azx_codec_configure(struct azx *chip)
1819 struct hda_codec *codec;
1820 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1821 snd_hda_codec_configure(codec);
1831 /* assign a stream for the PCM */
1832 static inline struct azx_dev *
1833 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1836 struct azx_dev *res = NULL;
1837 /* make a non-zero unique key for the substream */
1838 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1839 (substream->stream + 1);
1841 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1842 dev = chip->playback_index_offset;
1843 nums = chip->playback_streams;
1845 dev = chip->capture_index_offset;
1846 nums = chip->capture_streams;
1848 for (i = 0; i < nums; i++, dev++) {
1849 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1851 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1853 if (res->assigned_key == key) {
1855 res->assigned_key = key;
1856 dsp_unlock(azx_dev);
1860 dsp_unlock(azx_dev);
1865 res->assigned_key = key;
1871 /* release the assigned stream */
1872 static inline void azx_release_device(struct azx_dev *azx_dev)
1874 azx_dev->opened = 0;
1877 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1879 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1880 struct snd_pcm_substream *substream = azx_dev->substream;
1881 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1882 struct azx *chip = apcm->chip;
1884 return azx_readl(chip, WALLCLK);
1887 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1888 bool force, cycle_t last)
1890 struct azx_dev *azx_dev = get_azx_dev(substream);
1891 struct timecounter *tc = &azx_dev->azx_tc;
1892 struct cyclecounter *cc = &azx_dev->azx_cc;
1895 cc->read = azx_cc_read;
1896 cc->mask = CLOCKSOURCE_MASK(32);
1899 * Converting from 24 MHz to ns means applying a 125/3 factor.
1900 * To avoid any saturation issues in intermediate operations,
1901 * the 125 factor is applied first. The division is applied
1902 * last after reading the timecounter value.
1903 * Applying the 1/3 factor as part of the multiplication
1904 * requires at least 20 bits for a decent precision, however
1905 * overflows occur after about 4 hours or less, not a option.
1908 cc->mult = 125; /* saturation after 195 years */
1911 nsec = 0; /* audio time is elapsed time since trigger */
1912 timecounter_init(tc, cc, nsec);
1915 * force timecounter to use predefined value,
1916 * used for synchronized starts
1918 tc->cycle_last = last;
1921 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
1924 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1925 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1926 u64 codec_frames, codec_nsecs;
1928 if (!hinfo->ops.get_delay)
1931 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1932 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1933 substream->runtime->rate);
1935 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1936 return nsec + codec_nsecs;
1938 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1941 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1942 struct timespec *ts)
1944 struct azx_dev *azx_dev = get_azx_dev(substream);
1947 nsec = timecounter_read(&azx_dev->azx_tc);
1948 nsec = div_u64(nsec, 3); /* can be optimized */
1949 nsec = azx_adjust_codec_delay(substream, nsec);
1951 *ts = ns_to_timespec(nsec);
1956 static struct snd_pcm_hardware azx_pcm_hw = {
1957 .info = (SNDRV_PCM_INFO_MMAP |
1958 SNDRV_PCM_INFO_INTERLEAVED |
1959 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1960 SNDRV_PCM_INFO_MMAP_VALID |
1961 /* No full-resume yet implemented */
1962 /* SNDRV_PCM_INFO_RESUME |*/
1963 SNDRV_PCM_INFO_PAUSE |
1964 SNDRV_PCM_INFO_SYNC_START |
1965 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1966 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1967 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1968 .rates = SNDRV_PCM_RATE_48000,
1973 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1974 .period_bytes_min = 128,
1975 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1977 .periods_max = AZX_MAX_FRAG,
1981 static int azx_pcm_open(struct snd_pcm_substream *substream)
1983 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1984 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1985 struct azx *chip = apcm->chip;
1986 struct azx_dev *azx_dev;
1987 struct snd_pcm_runtime *runtime = substream->runtime;
1988 unsigned long flags;
1992 mutex_lock(&chip->open_mutex);
1993 azx_dev = azx_assign_device(chip, substream);
1994 if (azx_dev == NULL) {
1995 mutex_unlock(&chip->open_mutex);
1998 runtime->hw = azx_pcm_hw;
1999 runtime->hw.channels_min = hinfo->channels_min;
2000 runtime->hw.channels_max = hinfo->channels_max;
2001 runtime->hw.formats = hinfo->formats;
2002 runtime->hw.rates = hinfo->rates;
2003 snd_pcm_limit_hw_rates(runtime);
2004 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
2006 /* avoid wrap-around with wall-clock */
2007 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
2011 if (chip->align_buffer_size)
2012 /* constrain buffer sizes to be multiple of 128
2013 bytes. This is more efficient in terms of memory
2014 access but isn't required by the HDA spec and
2015 prevents users from specifying exact period/buffer
2016 sizes. For example for 44.1kHz, a period size set
2017 to 20ms will be rounded to 19.59ms. */
2020 /* Don't enforce steps on buffer sizes, still need to
2021 be multiple of 4 bytes (HDA spec). Tested on Intel
2022 HDA controllers, may not work on all devices where
2023 option needs to be disabled */
2026 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2028 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2030 snd_hda_power_up_d3wait(apcm->codec);
2031 err = hinfo->ops.open(hinfo, apcm->codec, substream);
2033 azx_release_device(azx_dev);
2034 snd_hda_power_down(apcm->codec);
2035 mutex_unlock(&chip->open_mutex);
2038 snd_pcm_limit_hw_rates(runtime);
2040 if (snd_BUG_ON(!runtime->hw.channels_min) ||
2041 snd_BUG_ON(!runtime->hw.channels_max) ||
2042 snd_BUG_ON(!runtime->hw.formats) ||
2043 snd_BUG_ON(!runtime->hw.rates)) {
2044 azx_release_device(azx_dev);
2045 hinfo->ops.close(hinfo, apcm->codec, substream);
2046 snd_hda_power_down(apcm->codec);
2047 mutex_unlock(&chip->open_mutex);
2051 /* disable WALLCLOCK timestamps for capture streams
2052 until we figure out how to handle digital inputs */
2053 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2054 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2056 spin_lock_irqsave(&chip->reg_lock, flags);
2057 azx_dev->substream = substream;
2058 azx_dev->running = 0;
2059 spin_unlock_irqrestore(&chip->reg_lock, flags);
2061 runtime->private_data = azx_dev;
2062 snd_pcm_set_sync(substream);
2063 mutex_unlock(&chip->open_mutex);
2067 static int azx_pcm_close(struct snd_pcm_substream *substream)
2069 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2070 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2071 struct azx *chip = apcm->chip;
2072 struct azx_dev *azx_dev = get_azx_dev(substream);
2073 unsigned long flags;
2075 mutex_lock(&chip->open_mutex);
2076 spin_lock_irqsave(&chip->reg_lock, flags);
2077 azx_dev->substream = NULL;
2078 azx_dev->running = 0;
2079 spin_unlock_irqrestore(&chip->reg_lock, flags);
2080 azx_release_device(azx_dev);
2081 hinfo->ops.close(hinfo, apcm->codec, substream);
2082 snd_hda_power_down(apcm->codec);
2083 mutex_unlock(&chip->open_mutex);
2087 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2088 struct snd_pcm_hw_params *hw_params)
2090 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2091 struct azx *chip = apcm->chip;
2092 struct azx_dev *azx_dev = get_azx_dev(substream);
2096 if (dsp_is_locked(azx_dev)) {
2101 mark_runtime_wc(chip, azx_dev, substream, false);
2102 azx_dev->bufsize = 0;
2103 azx_dev->period_bytes = 0;
2104 azx_dev->format_val = 0;
2105 ret = snd_pcm_lib_malloc_pages(substream,
2106 params_buffer_bytes(hw_params));
2109 mark_runtime_wc(chip, azx_dev, substream, true);
2111 dsp_unlock(azx_dev);
2115 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2117 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2118 struct azx_dev *azx_dev = get_azx_dev(substream);
2119 struct azx *chip = apcm->chip;
2120 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2122 /* reset BDL address */
2124 if (!dsp_is_locked(azx_dev)) {
2125 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2126 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2127 azx_sd_writel(azx_dev, SD_CTL, 0);
2128 azx_dev->bufsize = 0;
2129 azx_dev->period_bytes = 0;
2130 azx_dev->format_val = 0;
2133 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2135 mark_runtime_wc(chip, azx_dev, substream, false);
2136 azx_dev->prepared = 0;
2137 dsp_unlock(azx_dev);
2138 return snd_pcm_lib_free_pages(substream);
2141 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2143 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2144 struct azx *chip = apcm->chip;
2145 struct azx_dev *azx_dev = get_azx_dev(substream);
2146 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2147 struct snd_pcm_runtime *runtime = substream->runtime;
2148 unsigned int bufsize, period_bytes, format_val, stream_tag;
2150 struct hda_spdif_out *spdif =
2151 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2152 unsigned short ctls = spdif ? spdif->ctls : 0;
2155 if (dsp_is_locked(azx_dev)) {
2160 azx_stream_reset(chip, azx_dev);
2161 format_val = snd_hda_calc_stream_format(runtime->rate,
2167 snd_printk(KERN_ERR SFX
2168 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2169 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2174 bufsize = snd_pcm_lib_buffer_bytes(substream);
2175 period_bytes = snd_pcm_lib_period_bytes(substream);
2177 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2178 pci_name(chip->pci), bufsize, format_val);
2180 if (bufsize != azx_dev->bufsize ||
2181 period_bytes != azx_dev->period_bytes ||
2182 format_val != azx_dev->format_val ||
2183 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2184 azx_dev->bufsize = bufsize;
2185 azx_dev->period_bytes = period_bytes;
2186 azx_dev->format_val = format_val;
2187 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2188 err = azx_setup_periods(chip, substream, azx_dev);
2193 /* wallclk has 24Mhz clock source */
2194 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2195 runtime->rate) * 1000);
2196 azx_setup_controller(chip, azx_dev);
2197 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2198 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2200 azx_dev->fifo_size = 0;
2202 stream_tag = azx_dev->stream_tag;
2203 /* CA-IBG chips need the playback stream starting from 1 */
2204 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2205 stream_tag > chip->capture_streams)
2206 stream_tag -= chip->capture_streams;
2207 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2208 azx_dev->format_val, substream);
2212 azx_dev->prepared = 1;
2213 dsp_unlock(azx_dev);
2217 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2219 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2220 struct azx *chip = apcm->chip;
2221 struct azx_dev *azx_dev;
2222 struct snd_pcm_substream *s;
2223 int rstart = 0, start, nsync = 0, sbits = 0;
2226 azx_dev = get_azx_dev(substream);
2227 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2229 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2233 case SNDRV_PCM_TRIGGER_START:
2235 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2236 case SNDRV_PCM_TRIGGER_RESUME:
2239 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2240 case SNDRV_PCM_TRIGGER_SUSPEND:
2241 case SNDRV_PCM_TRIGGER_STOP:
2248 snd_pcm_group_for_each_entry(s, substream) {
2249 if (s->pcm->card != substream->pcm->card)
2251 azx_dev = get_azx_dev(s);
2252 sbits |= 1 << azx_dev->index;
2254 snd_pcm_trigger_done(s, substream);
2257 spin_lock(&chip->reg_lock);
2259 /* first, set SYNC bits of corresponding streams */
2260 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2261 azx_writel(chip, OLD_SSYNC,
2262 azx_readl(chip, OLD_SSYNC) | sbits);
2264 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2266 snd_pcm_group_for_each_entry(s, substream) {
2267 if (s->pcm->card != substream->pcm->card)
2269 azx_dev = get_azx_dev(s);
2271 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2273 azx_dev->start_wallclk -=
2274 azx_dev->period_wallclk;
2275 azx_stream_start(chip, azx_dev);
2277 azx_stream_stop(chip, azx_dev);
2279 azx_dev->running = start;
2281 spin_unlock(&chip->reg_lock);
2283 /* wait until all FIFOs get ready */
2284 for (timeout = 5000; timeout; timeout--) {
2286 snd_pcm_group_for_each_entry(s, substream) {
2287 if (s->pcm->card != substream->pcm->card)
2289 azx_dev = get_azx_dev(s);
2290 if (!(azx_sd_readb(azx_dev, SD_STS) &
2299 /* wait until all RUN bits are cleared */
2300 for (timeout = 5000; timeout; timeout--) {
2302 snd_pcm_group_for_each_entry(s, substream) {
2303 if (s->pcm->card != substream->pcm->card)
2305 azx_dev = get_azx_dev(s);
2306 if (azx_sd_readb(azx_dev, SD_CTL) &
2315 spin_lock(&chip->reg_lock);
2316 /* reset SYNC bits */
2317 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2318 azx_writel(chip, OLD_SSYNC,
2319 azx_readl(chip, OLD_SSYNC) & ~sbits);
2321 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2323 azx_timecounter_init(substream, 0, 0);
2327 /* same start cycle for master and group */
2328 azx_dev = get_azx_dev(substream);
2329 cycle_last = azx_dev->azx_tc.cycle_last;
2331 snd_pcm_group_for_each_entry(s, substream) {
2332 if (s->pcm->card != substream->pcm->card)
2334 azx_timecounter_init(s, 1, cycle_last);
2338 spin_unlock(&chip->reg_lock);
2342 /* get the current DMA position with correction on VIA chips */
2343 static unsigned int azx_via_get_position(struct azx *chip,
2344 struct azx_dev *azx_dev)
2346 unsigned int link_pos, mini_pos, bound_pos;
2347 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2348 unsigned int fifo_size;
2350 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2351 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2352 /* Playback, no problem using link position */
2358 * use mod to get the DMA position just like old chipset
2360 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2361 mod_dma_pos %= azx_dev->period_bytes;
2363 /* azx_dev->fifo_size can't get FIFO size of in stream.
2364 * Get from base address + offset.
2366 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2368 if (azx_dev->insufficient) {
2369 /* Link position never gather than FIFO size */
2370 if (link_pos <= fifo_size)
2373 azx_dev->insufficient = 0;
2376 if (link_pos <= fifo_size)
2377 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2379 mini_pos = link_pos - fifo_size;
2381 /* Find nearest previous boudary */
2382 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2383 mod_link_pos = link_pos % azx_dev->period_bytes;
2384 if (mod_link_pos >= fifo_size)
2385 bound_pos = link_pos - mod_link_pos;
2386 else if (mod_dma_pos >= mod_mini_pos)
2387 bound_pos = mini_pos - mod_mini_pos;
2389 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2390 if (bound_pos >= azx_dev->bufsize)
2394 /* Calculate real DMA position we want */
2395 return bound_pos + mod_dma_pos;
2398 static unsigned int azx_get_position(struct azx *chip,
2399 struct azx_dev *azx_dev,
2402 struct snd_pcm_substream *substream = azx_dev->substream;
2403 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2405 int stream = substream->stream;
2406 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2409 switch (chip->position_fix[stream]) {
2412 pos = azx_sd_readl(azx_dev, SD_LPIB);
2414 case POS_FIX_VIACOMBO:
2415 pos = azx_via_get_position(chip, azx_dev);
2418 /* use the position buffer */
2419 pos = le32_to_cpu(*azx_dev->posbuf);
2420 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2421 if (!pos || pos == (u32)-1) {
2423 "hda-intel: Invalid position buffer, "
2424 "using LPIB read method instead.\n");
2425 chip->position_fix[stream] = POS_FIX_LPIB;
2426 pos = azx_sd_readl(azx_dev, SD_LPIB);
2428 chip->position_fix[stream] = POS_FIX_POSBUF;
2433 if (pos >= azx_dev->bufsize)
2436 /* calculate runtime delay from LPIB */
2437 if (substream->runtime &&
2438 chip->position_fix[stream] == POS_FIX_POSBUF &&
2439 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2440 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2441 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2442 delay = pos - lpib_pos;
2444 delay = lpib_pos - pos;
2446 delay += azx_dev->bufsize;
2447 if (delay >= azx_dev->period_bytes) {
2448 snd_printk(KERN_WARNING SFX
2449 "%s: Unstable LPIB (%d >= %d); "
2450 "disabling LPIB delay counting\n",
2451 pci_name(chip->pci), delay, azx_dev->period_bytes);
2453 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2455 delay = bytes_to_frames(substream->runtime, delay);
2458 if (substream->runtime) {
2459 if (hinfo->ops.get_delay)
2460 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2462 substream->runtime->delay = delay;
2465 trace_azx_get_position(chip, azx_dev, pos, delay);
2469 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2471 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2472 struct azx *chip = apcm->chip;
2473 struct azx_dev *azx_dev = get_azx_dev(substream);
2474 return bytes_to_frames(substream->runtime,
2475 azx_get_position(chip, azx_dev, false));
2479 * Check whether the current DMA position is acceptable for updating
2480 * periods. Returns non-zero if it's OK.
2482 * Many HD-audio controllers appear pretty inaccurate about
2483 * the update-IRQ timing. The IRQ is issued before actually the
2484 * data is processed. So, we need to process it afterwords in a
2487 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2492 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2493 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2494 return -1; /* bogus (too early) interrupt */
2496 pos = azx_get_position(chip, azx_dev, true);
2498 if (WARN_ONCE(!azx_dev->period_bytes,
2499 "hda-intel: zero azx_dev->period_bytes"))
2500 return -1; /* this shouldn't happen! */
2501 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2502 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2503 /* NG - it's below the first next period boundary */
2504 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2505 azx_dev->start_wallclk += wallclk;
2506 return 1; /* OK, it's fine */
2510 * The work for pending PCM period updates.
2512 static void azx_irq_pending_work(struct work_struct *work)
2514 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2517 if (!chip->irq_pending_warned) {
2519 "hda-intel: IRQ timing workaround is activated "
2520 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2521 chip->card->number);
2522 chip->irq_pending_warned = 1;
2527 spin_lock_irq(&chip->reg_lock);
2528 for (i = 0; i < chip->num_streams; i++) {
2529 struct azx_dev *azx_dev = &chip->azx_dev[i];
2530 if (!azx_dev->irq_pending ||
2531 !azx_dev->substream ||
2534 ok = azx_position_ok(chip, azx_dev);
2536 azx_dev->irq_pending = 0;
2537 spin_unlock(&chip->reg_lock);
2538 snd_pcm_period_elapsed(azx_dev->substream);
2539 spin_lock(&chip->reg_lock);
2540 } else if (ok < 0) {
2541 pending = 0; /* too early */
2545 spin_unlock_irq(&chip->reg_lock);
2552 /* clear irq_pending flags and assure no on-going workq */
2553 static void azx_clear_irq_pending(struct azx *chip)
2557 spin_lock_irq(&chip->reg_lock);
2558 for (i = 0; i < chip->num_streams; i++)
2559 chip->azx_dev[i].irq_pending = 0;
2560 spin_unlock_irq(&chip->reg_lock);
2564 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2565 struct vm_area_struct *area)
2567 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2568 struct azx *chip = apcm->chip;
2569 if (!azx_snoop(chip))
2570 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2571 return snd_pcm_lib_default_mmap(substream, area);
2574 #define azx_pcm_mmap NULL
2577 static struct snd_pcm_ops azx_pcm_ops = {
2578 .open = azx_pcm_open,
2579 .close = azx_pcm_close,
2580 .ioctl = snd_pcm_lib_ioctl,
2581 .hw_params = azx_pcm_hw_params,
2582 .hw_free = azx_pcm_hw_free,
2583 .prepare = azx_pcm_prepare,
2584 .trigger = azx_pcm_trigger,
2585 .pointer = azx_pcm_pointer,
2586 .wall_clock = azx_get_wallclock_tstamp,
2587 .mmap = azx_pcm_mmap,
2588 .page = snd_pcm_sgbuf_ops_page,
2591 static void azx_pcm_free(struct snd_pcm *pcm)
2593 struct azx_pcm *apcm = pcm->private_data;
2595 list_del(&apcm->list);
2600 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2603 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2604 struct hda_pcm *cpcm)
2606 struct azx *chip = bus->private_data;
2607 struct snd_pcm *pcm;
2608 struct azx_pcm *apcm;
2609 int pcm_dev = cpcm->device;
2613 list_for_each_entry(apcm, &chip->pcm_list, list) {
2614 if (apcm->pcm->device == pcm_dev) {
2615 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2616 pci_name(chip->pci), pcm_dev);
2620 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2621 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2622 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2626 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2627 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2632 apcm->codec = codec;
2633 pcm->private_data = apcm;
2634 pcm->private_free = azx_pcm_free;
2635 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2636 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2637 list_add_tail(&apcm->list, &chip->pcm_list);
2639 for (s = 0; s < 2; s++) {
2640 apcm->hinfo[s] = &cpcm->stream[s];
2641 if (cpcm->stream[s].substreams)
2642 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2644 /* buffer pre-allocation */
2645 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2646 if (size > MAX_PREALLOC_SIZE)
2647 size = MAX_PREALLOC_SIZE;
2648 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2649 snd_dma_pci_data(chip->pci),
2650 size, MAX_PREALLOC_SIZE);
2655 * mixer creation - all stuff is implemented in hda module
2657 static int azx_mixer_create(struct azx *chip)
2659 return snd_hda_build_controls(chip->bus);
2664 * initialize SD streams
2666 static int azx_init_stream(struct azx *chip)
2670 /* initialize each stream (aka device)
2671 * assign the starting bdl address to each stream (device)
2674 for (i = 0; i < chip->num_streams; i++) {
2675 struct azx_dev *azx_dev = &chip->azx_dev[i];
2676 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2677 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2678 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2679 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2680 azx_dev->sd_int_sta_mask = 1 << i;
2681 /* stream tag: must be non-zero and unique */
2683 azx_dev->stream_tag = i + 1;
2689 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2691 if (request_irq(chip->pci->irq, azx_interrupt,
2692 chip->msi ? 0 : IRQF_SHARED,
2693 KBUILD_MODNAME, chip)) {
2694 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2695 "disabling device\n", chip->pci->irq);
2697 snd_card_disconnect(chip->card);
2700 chip->irq = chip->pci->irq;
2701 pci_intx(chip->pci, !chip->msi);
2706 static void azx_stop_chip(struct azx *chip)
2708 if (!chip->initialized)
2711 /* disable interrupts */
2712 azx_int_disable(chip);
2713 azx_int_clear(chip);
2715 /* disable CORB/RIRB */
2716 azx_free_cmd_io(chip);
2718 /* disable position buffer */
2719 azx_writel(chip, DPLBASE, 0);
2720 azx_writel(chip, DPUBASE, 0);
2722 chip->initialized = 0;
2725 #ifdef CONFIG_SND_HDA_DSP_LOADER
2727 * DSP loading code (e.g. for CA0132)
2730 /* use the first stream for loading DSP */
2731 static struct azx_dev *
2732 azx_get_dsp_loader_dev(struct azx *chip)
2734 return &chip->azx_dev[chip->playback_index_offset];
2737 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2738 unsigned int byte_size,
2739 struct snd_dma_buffer *bufp)
2742 struct azx *chip = bus->private_data;
2743 struct azx_dev *azx_dev;
2746 azx_dev = azx_get_dsp_loader_dev(chip);
2749 spin_lock_irq(&chip->reg_lock);
2750 if (azx_dev->running || azx_dev->locked) {
2751 spin_unlock_irq(&chip->reg_lock);
2755 azx_dev->prepared = 0;
2756 chip->saved_azx_dev = *azx_dev;
2757 azx_dev->locked = 1;
2758 spin_unlock_irq(&chip->reg_lock);
2760 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2761 snd_dma_pci_data(chip->pci),
2766 mark_pages_wc(chip, bufp, true);
2767 azx_dev->bufsize = byte_size;
2768 azx_dev->period_bytes = byte_size;
2769 azx_dev->format_val = format;
2771 azx_stream_reset(chip, azx_dev);
2773 /* reset BDL address */
2774 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2775 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2778 bdl = (u32 *)azx_dev->bdl.area;
2779 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2783 azx_setup_controller(chip, azx_dev);
2784 dsp_unlock(azx_dev);
2785 return azx_dev->stream_tag;
2788 mark_pages_wc(chip, bufp, false);
2789 snd_dma_free_pages(bufp);
2791 spin_lock_irq(&chip->reg_lock);
2792 if (azx_dev->opened)
2793 *azx_dev = chip->saved_azx_dev;
2794 azx_dev->locked = 0;
2795 spin_unlock_irq(&chip->reg_lock);
2797 dsp_unlock(azx_dev);
2801 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2803 struct azx *chip = bus->private_data;
2804 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2807 azx_stream_start(chip, azx_dev);
2809 azx_stream_stop(chip, azx_dev);
2810 azx_dev->running = start;
2813 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2814 struct snd_dma_buffer *dmab)
2816 struct azx *chip = bus->private_data;
2817 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2819 if (!dmab->area || !azx_dev->locked)
2823 /* reset BDL address */
2824 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2825 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2826 azx_sd_writel(azx_dev, SD_CTL, 0);
2827 azx_dev->bufsize = 0;
2828 azx_dev->period_bytes = 0;
2829 azx_dev->format_val = 0;
2831 mark_pages_wc(chip, dmab, false);
2832 snd_dma_free_pages(dmab);
2835 spin_lock_irq(&chip->reg_lock);
2836 if (azx_dev->opened)
2837 *azx_dev = chip->saved_azx_dev;
2838 azx_dev->locked = 0;
2839 spin_unlock_irq(&chip->reg_lock);
2840 dsp_unlock(azx_dev);
2842 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2845 /* power-up/down the controller */
2846 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2848 struct azx *chip = bus->private_data;
2850 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2854 pm_runtime_get_sync(&chip->pci->dev);
2856 pm_runtime_put_sync(&chip->pci->dev);
2859 static DEFINE_MUTEX(card_list_lock);
2860 static LIST_HEAD(card_list);
2862 static void azx_add_card_list(struct azx *chip)
2864 mutex_lock(&card_list_lock);
2865 list_add(&chip->list, &card_list);
2866 mutex_unlock(&card_list_lock);
2869 static void azx_del_card_list(struct azx *chip)
2871 mutex_lock(&card_list_lock);
2872 list_del_init(&chip->list);
2873 mutex_unlock(&card_list_lock);
2876 /* trigger power-save check at writing parameter */
2877 static int param_set_xint(const char *val, const struct kernel_param *kp)
2880 struct hda_codec *c;
2881 int prev = power_save;
2882 int ret = param_set_int(val, kp);
2884 if (ret || prev == power_save)
2887 mutex_lock(&card_list_lock);
2888 list_for_each_entry(chip, &card_list, list) {
2889 if (!chip->bus || chip->disabled)
2891 list_for_each_entry(c, &chip->bus->codec_list, list)
2892 snd_hda_power_sync(c);
2894 mutex_unlock(&card_list_lock);
2898 #define azx_add_card_list(chip) /* NOP */
2899 #define azx_del_card_list(chip) /* NOP */
2900 #endif /* CONFIG_PM */
2902 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2906 static int azx_suspend(struct device *dev)
2908 struct pci_dev *pci = to_pci_dev(dev);
2909 struct snd_card *card = dev_get_drvdata(dev);
2910 struct azx *chip = card->private_data;
2916 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2917 azx_clear_irq_pending(chip);
2918 list_for_each_entry(p, &chip->pcm_list, list)
2919 snd_pcm_suspend_all(p->pcm);
2920 if (chip->initialized)
2921 snd_hda_suspend(chip->bus);
2922 azx_stop_chip(chip);
2923 azx_enter_link_reset(chip);
2924 if (chip->irq >= 0) {
2925 free_irq(chip->irq, chip);
2929 pci_disable_msi(chip->pci);
2930 pci_disable_device(pci);
2931 pci_save_state(pci);
2932 pci_set_power_state(pci, PCI_D3hot);
2933 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2934 hda_display_power(false);
2938 static int azx_resume(struct device *dev)
2940 struct pci_dev *pci = to_pci_dev(dev);
2941 struct snd_card *card = dev_get_drvdata(dev);
2942 struct azx *chip = card->private_data;
2947 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2948 hda_display_power(true);
2949 pci_set_power_state(pci, PCI_D0);
2950 pci_restore_state(pci);
2951 if (pci_enable_device(pci) < 0) {
2952 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2953 "disabling device\n");
2954 snd_card_disconnect(card);
2957 pci_set_master(pci);
2959 if (pci_enable_msi(pci) < 0)
2961 if (azx_acquire_irq(chip, 1) < 0)
2965 azx_init_chip(chip, 1);
2967 snd_hda_resume(chip->bus);
2968 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2971 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2973 #ifdef CONFIG_PM_RUNTIME
2974 static int azx_runtime_suspend(struct device *dev)
2976 struct snd_card *card = dev_get_drvdata(dev);
2977 struct azx *chip = card->private_data;
2982 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2985 /* enable controller wake up event */
2986 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
2989 azx_stop_chip(chip);
2990 if (!chip->bus->avoid_link_reset)
2991 azx_enter_link_reset(chip);
2992 azx_clear_irq_pending(chip);
2993 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2994 hda_display_power(false);
2998 static int azx_runtime_resume(struct device *dev)
3000 struct snd_card *card = dev_get_drvdata(dev);
3001 struct azx *chip = card->private_data;
3002 struct hda_bus *bus;
3003 struct hda_codec *codec;
3009 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3012 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3013 hda_display_power(true);
3015 /* Read STATESTS before controller reset */
3016 status = azx_readw(chip, STATESTS);
3019 azx_init_chip(chip, 1);
3022 if (status && bus) {
3023 list_for_each_entry(codec, &bus->codec_list, list)
3024 if (status & (1 << codec->addr))
3025 queue_delayed_work(codec->bus->workq,
3026 &codec->jackpoll_work, codec->jackpoll_interval);
3029 /* disable controller Wake Up event*/
3030 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
3031 ~STATESTS_INT_MASK);
3036 static int azx_runtime_idle(struct device *dev)
3038 struct snd_card *card = dev_get_drvdata(dev);
3039 struct azx *chip = card->private_data;
3044 if (!power_save_controller ||
3045 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3051 #endif /* CONFIG_PM_RUNTIME */
3054 static const struct dev_pm_ops azx_pm = {
3055 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3056 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
3059 #define AZX_PM_OPS &azx_pm
3061 #define AZX_PM_OPS NULL
3062 #endif /* CONFIG_PM */
3066 * reboot notifier for hang-up problem at power-down
3068 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3070 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
3071 snd_hda_bus_reboot_notify(chip->bus);
3072 azx_stop_chip(chip);
3076 static void azx_notifier_register(struct azx *chip)
3078 chip->reboot_notifier.notifier_call = azx_halt;
3079 register_reboot_notifier(&chip->reboot_notifier);
3082 static void azx_notifier_unregister(struct azx *chip)
3084 if (chip->reboot_notifier.notifier_call)
3085 unregister_reboot_notifier(&chip->reboot_notifier);
3088 static int azx_probe_continue(struct azx *chip);
3090 #ifdef SUPPORT_VGA_SWITCHEROO
3091 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
3093 static void azx_vs_set_state(struct pci_dev *pci,
3094 enum vga_switcheroo_state state)
3096 struct snd_card *card = pci_get_drvdata(pci);
3097 struct azx *chip = card->private_data;
3100 wait_for_completion(&chip->probe_wait);
3101 if (chip->init_failed)
3104 disabled = (state == VGA_SWITCHEROO_OFF);
3105 if (chip->disabled == disabled)
3109 chip->disabled = disabled;
3111 snd_printk(KERN_INFO SFX
3112 "%s: Start delayed initialization\n",
3113 pci_name(chip->pci));
3114 if (azx_probe_continue(chip) < 0) {
3115 snd_printk(KERN_ERR SFX
3116 "%s: initialization error\n",
3117 pci_name(chip->pci));
3118 chip->init_failed = true;
3122 snd_printk(KERN_INFO SFX
3123 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3124 disabled ? "Disabling" : "Enabling");
3126 pm_runtime_put_sync_suspend(&pci->dev);
3127 azx_suspend(&pci->dev);
3128 /* when we get suspended by vga switcheroo we end up in D3cold,
3129 * however we have no ACPI handle, so pci/acpi can't put us there,
3130 * put ourselves there */
3131 pci->current_state = PCI_D3cold;
3132 chip->disabled = true;
3133 if (snd_hda_lock_devices(chip->bus))
3134 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3135 pci_name(chip->pci));
3137 snd_hda_unlock_devices(chip->bus);
3138 pm_runtime_get_noresume(&pci->dev);
3139 chip->disabled = false;
3140 azx_resume(&pci->dev);
3145 static bool azx_vs_can_switch(struct pci_dev *pci)
3147 struct snd_card *card = pci_get_drvdata(pci);
3148 struct azx *chip = card->private_data;
3150 wait_for_completion(&chip->probe_wait);
3151 if (chip->init_failed)
3153 if (chip->disabled || !chip->bus)
3155 if (snd_hda_lock_devices(chip->bus))
3157 snd_hda_unlock_devices(chip->bus);
3161 static void init_vga_switcheroo(struct azx *chip)
3163 struct pci_dev *p = get_bound_vga(chip->pci);
3165 snd_printk(KERN_INFO SFX
3166 "%s: Handle VGA-switcheroo audio client\n",
3167 pci_name(chip->pci));
3168 chip->use_vga_switcheroo = 1;
3173 static const struct vga_switcheroo_client_ops azx_vs_ops = {
3174 .set_gpu_state = azx_vs_set_state,
3175 .can_switch = azx_vs_can_switch,
3178 static int register_vga_switcheroo(struct azx *chip)
3182 if (!chip->use_vga_switcheroo)
3184 /* FIXME: currently only handling DIS controller
3185 * is there any machine with two switchable HDMI audio controllers?
3187 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
3192 chip->vga_switcheroo_registered = 1;
3194 /* register as an optimus hdmi audio power domain */
3195 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(&chip->pci->dev, &chip->hdmi_pm_domain);
3199 #define init_vga_switcheroo(chip) /* NOP */
3200 #define register_vga_switcheroo(chip) 0
3201 #define check_hdmi_disabled(pci) false
3202 #endif /* SUPPORT_VGA_SWITCHER */
3207 static int azx_free(struct azx *chip)
3209 struct pci_dev *pci = chip->pci;
3212 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
3214 pm_runtime_get_noresume(&pci->dev);
3216 azx_del_card_list(chip);
3218 azx_notifier_unregister(chip);
3220 chip->init_failed = 1; /* to be sure */
3221 complete_all(&chip->probe_wait);
3223 if (use_vga_switcheroo(chip)) {
3224 if (chip->disabled && chip->bus)
3225 snd_hda_unlock_devices(chip->bus);
3226 if (chip->vga_switcheroo_registered)
3227 vga_switcheroo_unregister_client(chip->pci);
3230 if (chip->initialized) {
3231 azx_clear_irq_pending(chip);
3232 for (i = 0; i < chip->num_streams; i++)
3233 azx_stream_stop(chip, &chip->azx_dev[i]);
3234 azx_stop_chip(chip);
3238 free_irq(chip->irq, (void*)chip);
3240 pci_disable_msi(chip->pci);
3241 if (chip->remap_addr)
3242 iounmap(chip->remap_addr);
3244 if (chip->azx_dev) {
3245 for (i = 0; i < chip->num_streams; i++)
3246 if (chip->azx_dev[i].bdl.area) {
3247 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
3248 snd_dma_free_pages(&chip->azx_dev[i].bdl);
3251 if (chip->rb.area) {
3252 mark_pages_wc(chip, &chip->rb, false);
3253 snd_dma_free_pages(&chip->rb);
3255 if (chip->posbuf.area) {
3256 mark_pages_wc(chip, &chip->posbuf, false);
3257 snd_dma_free_pages(&chip->posbuf);
3259 if (chip->region_requested)
3260 pci_release_regions(chip->pci);
3261 pci_disable_device(chip->pci);
3262 kfree(chip->azx_dev);
3263 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3265 release_firmware(chip->fw);
3267 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3268 hda_display_power(false);
3276 static int azx_dev_free(struct snd_device *device)
3278 return azx_free(device->device_data);
3281 #ifdef SUPPORT_VGA_SWITCHEROO
3283 * Check of disabled HDMI controller by vga-switcheroo
3285 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
3289 /* check only discrete GPU */
3290 switch (pci->vendor) {
3291 case PCI_VENDOR_ID_ATI:
3292 case PCI_VENDOR_ID_AMD:
3293 case PCI_VENDOR_ID_NVIDIA:
3294 if (pci->devfn == 1) {
3295 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3296 pci->bus->number, 0);
3298 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3308 static bool check_hdmi_disabled(struct pci_dev *pci)
3310 bool vga_inactive = false;
3311 struct pci_dev *p = get_bound_vga(pci);
3314 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
3315 vga_inactive = true;
3318 return vga_inactive;
3320 #endif /* SUPPORT_VGA_SWITCHEROO */
3323 * white/black-listing for position_fix
3325 static struct snd_pci_quirk position_fix_list[] = {
3326 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3327 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
3328 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
3329 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3330 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
3331 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3332 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3333 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3334 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3335 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3336 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3337 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3338 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3339 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3343 static int check_position_fix(struct azx *chip, int fix)
3345 const struct snd_pci_quirk *q;
3350 case POS_FIX_POSBUF:
3351 case POS_FIX_VIACOMBO:
3356 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3359 "hda_intel: position_fix set to %d "
3360 "for device %04x:%04x\n",
3361 q->value, q->subvendor, q->subdevice);
3365 /* Check VIA/ATI HD Audio Controller exist */
3366 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3367 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3368 return POS_FIX_VIACOMBO;
3370 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3371 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3372 return POS_FIX_LPIB;
3374 return POS_FIX_AUTO;
3378 * black-lists for probe_mask
3380 static struct snd_pci_quirk probe_mask_list[] = {
3381 /* Thinkpad often breaks the controller communication when accessing
3382 * to the non-working (or non-existing) modem codec slot.
3384 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3385 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3386 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3388 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3389 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3390 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3391 /* forced codec slots */
3392 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3393 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3394 /* WinFast VP200 H (Teradici) user reported broken communication */
3395 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3399 #define AZX_FORCE_CODEC_MASK 0x100
3401 static void check_probe_mask(struct azx *chip, int dev)
3403 const struct snd_pci_quirk *q;
3405 chip->codec_probe_mask = probe_mask[dev];
3406 if (chip->codec_probe_mask == -1) {
3407 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3410 "hda_intel: probe_mask set to 0x%x "
3411 "for device %04x:%04x\n",
3412 q->value, q->subvendor, q->subdevice);
3413 chip->codec_probe_mask = q->value;
3417 /* check forced option */
3418 if (chip->codec_probe_mask != -1 &&
3419 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3420 chip->codec_mask = chip->codec_probe_mask & 0xff;
3421 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3427 * white/black-list for enable_msi
3429 static struct snd_pci_quirk msi_black_list[] = {
3430 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3431 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3432 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3433 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
3434 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3435 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3439 static void check_msi(struct azx *chip)
3441 const struct snd_pci_quirk *q;
3443 if (enable_msi >= 0) {
3444 chip->msi = !!enable_msi;
3447 chip->msi = 1; /* enable MSI as default */
3448 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3451 "hda_intel: msi for device %04x:%04x set to %d\n",
3452 q->subvendor, q->subdevice, q->value);
3453 chip->msi = q->value;
3457 /* NVidia chipsets seem to cause troubles with MSI */
3458 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3459 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3464 /* check the snoop mode availability */
3465 static void azx_check_snoop_available(struct azx *chip)
3467 bool snoop = chip->snoop;
3469 switch (chip->driver_type) {
3470 case AZX_DRIVER_VIA:
3471 /* force to non-snoop mode for a new VIA controller
3476 pci_read_config_byte(chip->pci, 0x42, &val);
3477 if (!(val & 0x80) && chip->pci->revision == 0x30)
3481 case AZX_DRIVER_ATIHDMI_NS:
3482 /* new ATI HDMI requires non-snoop */
3485 case AZX_DRIVER_CTHDA:
3490 if (snoop != chip->snoop) {
3491 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3492 pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3493 chip->snoop = snoop;
3497 #ifdef CONFIG_SND_HDA_I915
3498 static void azx_probe_work(struct work_struct *work)
3500 azx_probe_continue(container_of(work, struct azx, probe_work));
3507 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3508 int dev, unsigned int driver_caps,
3511 static struct snd_device_ops ops = {
3512 .dev_free = azx_dev_free,
3519 err = pci_enable_device(pci);
3523 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3525 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3526 pci_disable_device(pci);
3530 spin_lock_init(&chip->reg_lock);
3531 mutex_init(&chip->open_mutex);
3535 chip->driver_caps = driver_caps;
3536 chip->driver_type = driver_caps & 0xff;
3538 chip->dev_index = dev;
3539 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3540 INIT_LIST_HEAD(&chip->pcm_list);
3541 INIT_LIST_HEAD(&chip->list);
3542 init_vga_switcheroo(chip);
3543 init_completion(&chip->probe_wait);
3545 chip->position_fix[0] = chip->position_fix[1] =
3546 check_position_fix(chip, position_fix[dev]);
3547 /* combo mode uses LPIB for playback */
3548 if (chip->position_fix[0] == POS_FIX_COMBO) {
3549 chip->position_fix[0] = POS_FIX_LPIB;
3550 chip->position_fix[1] = POS_FIX_AUTO;
3553 check_probe_mask(chip, dev);
3555 chip->single_cmd = single_cmd;
3556 chip->snoop = hda_snoop;
3557 azx_check_snoop_available(chip);
3559 if (bdl_pos_adj[dev] < 0) {
3560 switch (chip->driver_type) {
3561 case AZX_DRIVER_ICH:
3562 case AZX_DRIVER_PCH:
3563 bdl_pos_adj[dev] = 1;
3566 bdl_pos_adj[dev] = 32;
3571 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3573 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3574 pci_name(chip->pci));
3579 #ifdef CONFIG_SND_HDA_I915
3580 /* continue probing in work context as may trigger request module */
3581 INIT_WORK(&chip->probe_work, azx_probe_work);
3589 static int azx_first_init(struct azx *chip)
3591 int dev = chip->dev_index;
3592 struct pci_dev *pci = chip->pci;
3593 struct snd_card *card = chip->card;
3595 unsigned short gcap;
3597 #if BITS_PER_LONG != 64
3598 /* Fix up base address on ULI M5461 */
3599 if (chip->driver_type == AZX_DRIVER_ULI) {
3601 pci_read_config_word(pci, 0x40, &tmp3);
3602 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3603 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3607 err = pci_request_regions(pci, "ICH HD audio");
3610 chip->region_requested = 1;
3612 chip->addr = pci_resource_start(pci, 0);
3613 chip->remap_addr = pci_ioremap_bar(pci, 0);
3614 if (chip->remap_addr == NULL) {
3615 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3620 if (pci_enable_msi(pci) < 0)
3623 if (azx_acquire_irq(chip, 0) < 0)
3626 pci_set_master(pci);
3627 synchronize_irq(chip->irq);
3629 gcap = azx_readw(chip, GCAP);
3630 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3632 /* disable SB600 64bit support for safety */
3633 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3634 struct pci_dev *p_smbus;
3635 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3636 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3639 if (p_smbus->revision < 0x30)
3640 gcap &= ~ICH6_GCAP_64OK;
3641 pci_dev_put(p_smbus);
3645 /* disable 64bit DMA address on some devices */
3646 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3647 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3648 gcap &= ~ICH6_GCAP_64OK;
3651 /* disable buffer size rounding to 128-byte multiples if supported */
3652 if (align_buffer_size >= 0)
3653 chip->align_buffer_size = !!align_buffer_size;
3655 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3656 chip->align_buffer_size = 0;
3657 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3658 chip->align_buffer_size = 1;
3660 chip->align_buffer_size = 1;
3663 /* allow 64bit DMA address if supported by H/W */
3664 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3665 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3667 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3668 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3671 /* read number of streams from GCAP register instead of using
3674 chip->capture_streams = (gcap >> 8) & 0x0f;
3675 chip->playback_streams = (gcap >> 12) & 0x0f;
3676 if (!chip->playback_streams && !chip->capture_streams) {
3677 /* gcap didn't give any info, switching to old method */
3679 switch (chip->driver_type) {
3680 case AZX_DRIVER_ULI:
3681 chip->playback_streams = ULI_NUM_PLAYBACK;
3682 chip->capture_streams = ULI_NUM_CAPTURE;
3684 case AZX_DRIVER_ATIHDMI:
3685 case AZX_DRIVER_ATIHDMI_NS:
3686 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3687 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3689 case AZX_DRIVER_GENERIC:
3691 chip->playback_streams = ICH6_NUM_PLAYBACK;
3692 chip->capture_streams = ICH6_NUM_CAPTURE;
3696 chip->capture_index_offset = 0;
3697 chip->playback_index_offset = chip->capture_streams;
3698 chip->num_streams = chip->playback_streams + chip->capture_streams;
3699 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3701 if (!chip->azx_dev) {
3702 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
3706 for (i = 0; i < chip->num_streams; i++) {
3707 dsp_lock_init(&chip->azx_dev[i]);
3708 /* allocate memory for the BDL for each stream */
3709 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3710 snd_dma_pci_data(chip->pci),
3711 BDL_SIZE, &chip->azx_dev[i].bdl);
3713 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
3716 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3718 /* allocate memory for the position buffer */
3719 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3720 snd_dma_pci_data(chip->pci),
3721 chip->num_streams * 8, &chip->posbuf);
3723 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
3726 mark_pages_wc(chip, &chip->posbuf, true);
3727 /* allocate CORB/RIRB */
3728 err = azx_alloc_cmd_io(chip);
3732 /* initialize streams */
3733 azx_init_stream(chip);
3735 /* initialize chip */
3737 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3739 /* codec detection */
3740 if (!chip->codec_mask) {
3741 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
3745 strcpy(card->driver, "HDA-Intel");
3746 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3747 sizeof(card->shortname));
3748 snprintf(card->longname, sizeof(card->longname),
3749 "%s at 0x%lx irq %i",
3750 card->shortname, chip->addr, chip->irq);
3755 static void power_down_all_codecs(struct azx *chip)
3758 /* The codecs were powered up in snd_hda_codec_new().
3759 * Now all initialization done, so turn them down if possible
3761 struct hda_codec *codec;
3762 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3763 snd_hda_power_down(codec);
3768 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3769 /* callback from request_firmware_nowait() */
3770 static void azx_firmware_cb(const struct firmware *fw, void *context)
3772 struct snd_card *card = context;
3773 struct azx *chip = card->private_data;
3774 struct pci_dev *pci = chip->pci;
3777 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3778 pci_name(chip->pci));
3783 if (!chip->disabled) {
3784 /* continue probing */
3785 if (azx_probe_continue(chip))
3791 snd_card_free(card);
3792 pci_set_drvdata(pci, NULL);
3796 static int azx_probe(struct pci_dev *pci,
3797 const struct pci_device_id *pci_id)
3800 struct snd_card *card;
3805 if (dev >= SNDRV_CARDS)
3812 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3814 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
3818 snd_card_set_dev(card, &pci->dev);
3820 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3823 card->private_data = chip;
3825 pci_set_drvdata(pci, card);
3827 err = register_vga_switcheroo(chip);
3829 snd_printk(KERN_ERR SFX
3830 "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
3834 if (check_hdmi_disabled(pci)) {
3835 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
3837 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
3838 chip->disabled = true;
3841 probe_now = !chip->disabled;
3843 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3844 if (patch[dev] && *patch[dev]) {
3845 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3846 pci_name(pci), patch[dev]);
3847 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3848 &pci->dev, GFP_KERNEL, card,
3852 probe_now = false; /* continued in azx_firmware_cb() */
3854 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3856 /* continue probing in work context, avoid request_module deadlock */
3857 if (probe_now && (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)) {
3858 #ifdef CONFIG_SND_HDA_I915
3860 schedule_work(&chip->probe_work);
3862 snd_printk(KERN_ERR SFX "Haswell must build in CONFIG_SND_HDA_I915\n");
3867 err = azx_probe_continue(chip);
3873 complete_all(&chip->probe_wait);
3877 snd_card_free(card);
3881 static int azx_probe_continue(struct azx *chip)
3883 struct pci_dev *pci = chip->pci;
3884 int dev = chip->dev_index;
3887 /* Request power well for Haswell HDA controller and codec */
3888 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3889 #ifdef CONFIG_SND_HDA_I915
3890 err = hda_i915_init();
3892 snd_printk(KERN_ERR SFX "Error request power-well from i915\n");
3896 hda_display_power(true);
3899 err = azx_first_init(chip);
3903 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3904 chip->beep_mode = beep_mode[dev];
3907 /* create codec instances */
3908 err = azx_codec_create(chip, model[dev]);
3911 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3913 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3918 release_firmware(chip->fw); /* no longer needed */
3923 if ((probe_only[dev] & 1) == 0) {
3924 err = azx_codec_configure(chip);
3929 /* create PCM streams */
3930 err = snd_hda_build_pcms(chip->bus);
3934 /* create mixer controls */
3935 err = azx_mixer_create(chip);
3939 err = snd_card_register(chip->card);
3944 power_down_all_codecs(chip);
3945 azx_notifier_register(chip);
3946 azx_add_card_list(chip);
3947 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
3948 pm_runtime_put_noidle(&pci->dev);
3953 chip->init_failed = 1;
3957 static void azx_remove(struct pci_dev *pci)
3959 struct snd_card *card = pci_get_drvdata(pci);
3962 snd_card_free(card);
3966 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3968 { PCI_DEVICE(0x8086, 0x1c20),
3969 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3971 { PCI_DEVICE(0x8086, 0x1d20),
3972 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3974 { PCI_DEVICE(0x8086, 0x1e20),
3975 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3977 { PCI_DEVICE(0x8086, 0x8c20),
3978 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3980 { PCI_DEVICE(0x8086, 0x8d20),
3981 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3982 { PCI_DEVICE(0x8086, 0x8d21),
3983 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3985 { PCI_DEVICE(0x8086, 0x9c20),
3986 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3988 { PCI_DEVICE(0x8086, 0x9c21),
3989 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3990 /* Wildcat Point-LP */
3991 { PCI_DEVICE(0x8086, 0x9ca0),
3992 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3994 { PCI_DEVICE(0x8086, 0x0a0c),
3995 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
3996 AZX_DCAPS_I915_POWERWELL },
3997 { PCI_DEVICE(0x8086, 0x0c0c),
3998 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
3999 AZX_DCAPS_I915_POWERWELL },
4000 { PCI_DEVICE(0x8086, 0x0d0c),
4001 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
4002 AZX_DCAPS_I915_POWERWELL },
4004 { PCI_DEVICE(0x8086, 0x3b56),
4005 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4007 { PCI_DEVICE(0x8086, 0x811b),
4008 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4010 { PCI_DEVICE(0x8086, 0x080a),
4011 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4013 { PCI_DEVICE(0x8086, 0x0f04),
4014 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
4016 { PCI_DEVICE(0x8086, 0x2668),
4017 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4018 AZX_DCAPS_BUFSIZE }, /* ICH6 */
4019 { PCI_DEVICE(0x8086, 0x27d8),
4020 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4021 AZX_DCAPS_BUFSIZE }, /* ICH7 */
4022 { PCI_DEVICE(0x8086, 0x269a),
4023 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4024 AZX_DCAPS_BUFSIZE }, /* ESB2 */
4025 { PCI_DEVICE(0x8086, 0x284b),
4026 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4027 AZX_DCAPS_BUFSIZE }, /* ICH8 */
4028 { PCI_DEVICE(0x8086, 0x293e),
4029 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4030 AZX_DCAPS_BUFSIZE }, /* ICH9 */
4031 { PCI_DEVICE(0x8086, 0x293f),
4032 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4033 AZX_DCAPS_BUFSIZE }, /* ICH9 */
4034 { PCI_DEVICE(0x8086, 0x3a3e),
4035 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4036 AZX_DCAPS_BUFSIZE }, /* ICH10 */
4037 { PCI_DEVICE(0x8086, 0x3a6e),
4038 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4039 AZX_DCAPS_BUFSIZE }, /* ICH10 */
4041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
4042 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4043 .class_mask = 0xffffff,
4044 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
4045 /* ATI SB 450/600/700/800/900 */
4046 { PCI_DEVICE(0x1002, 0x437b),
4047 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4048 { PCI_DEVICE(0x1002, 0x4383),
4049 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4051 { PCI_DEVICE(0x1022, 0x780d),
4052 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
4054 { PCI_DEVICE(0x1002, 0x793b),
4055 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4056 { PCI_DEVICE(0x1002, 0x7919),
4057 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4058 { PCI_DEVICE(0x1002, 0x960f),
4059 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4060 { PCI_DEVICE(0x1002, 0x970f),
4061 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4062 { PCI_DEVICE(0x1002, 0xaa00),
4063 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4064 { PCI_DEVICE(0x1002, 0xaa08),
4065 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4066 { PCI_DEVICE(0x1002, 0xaa10),
4067 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4068 { PCI_DEVICE(0x1002, 0xaa18),
4069 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4070 { PCI_DEVICE(0x1002, 0xaa20),
4071 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4072 { PCI_DEVICE(0x1002, 0xaa28),
4073 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4074 { PCI_DEVICE(0x1002, 0xaa30),
4075 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4076 { PCI_DEVICE(0x1002, 0xaa38),
4077 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4078 { PCI_DEVICE(0x1002, 0xaa40),
4079 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4080 { PCI_DEVICE(0x1002, 0xaa48),
4081 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4082 { PCI_DEVICE(0x1002, 0x9902),
4083 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4084 { PCI_DEVICE(0x1002, 0xaaa0),
4085 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4086 { PCI_DEVICE(0x1002, 0xaaa8),
4087 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4088 { PCI_DEVICE(0x1002, 0xaab0),
4089 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4090 /* VIA VT8251/VT8237A */
4091 { PCI_DEVICE(0x1106, 0x3288),
4092 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
4093 /* VIA GFX VT7122/VX900 */
4094 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
4095 /* VIA GFX VT6122/VX11 */
4096 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
4098 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
4100 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
4102 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
4103 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4104 .class_mask = 0xffffff,
4105 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
4107 { PCI_DEVICE(0x6549, 0x1200),
4108 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4109 { PCI_DEVICE(0x6549, 0x2200),
4110 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4111 /* Creative X-Fi (CA0110-IBG) */
4113 { PCI_DEVICE(0x1102, 0x0010),
4114 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4115 { PCI_DEVICE(0x1102, 0x0012),
4116 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4117 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
4118 /* the following entry conflicts with snd-ctxfi driver,
4119 * as ctxfi driver mutates from HD-audio to native mode with
4120 * a special command sequence.
4122 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4123 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4124 .class_mask = 0xffffff,
4125 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4126 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4128 /* this entry seems still valid -- i.e. without emu20kx chip */
4129 { PCI_DEVICE(0x1102, 0x0009),
4130 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4131 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4134 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
4135 /* VMware HDAudio */
4136 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
4137 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
4138 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4139 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4140 .class_mask = 0xffffff,
4141 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4142 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4143 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4144 .class_mask = 0xffffff,
4145 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4148 MODULE_DEVICE_TABLE(pci, azx_ids);
4150 /* pci_driver definition */
4151 static struct pci_driver azx_driver = {
4152 .name = KBUILD_MODNAME,
4153 .id_table = azx_ids,
4155 .remove = azx_remove,
4161 module_pci_driver(azx_driver);