3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
50 /* for snoop control */
51 #include <asm/pgtable.h>
52 #include <asm/cacheflush.h>
54 #include <sound/core.h>
55 #include <sound/initval.h>
56 #include <linux/vgaarb.h>
57 #include <linux/vga_switcheroo.h>
58 #include "hda_codec.h"
61 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
62 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
63 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
64 static char *model[SNDRV_CARDS];
65 static int position_fix[SNDRV_CARDS];
66 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
67 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
68 static int probe_only[SNDRV_CARDS];
69 static bool single_cmd;
70 static int enable_msi = -1;
71 #ifdef CONFIG_SND_HDA_PATCH_LOADER
72 static char *patch[SNDRV_CARDS];
74 #ifdef CONFIG_SND_HDA_INPUT_BEEP
75 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
76 CONFIG_SND_HDA_INPUT_BEEP_MODE};
79 module_param_array(index, int, NULL, 0444);
80 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
81 module_param_array(id, charp, NULL, 0444);
82 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
83 module_param_array(enable, bool, NULL, 0444);
84 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
85 module_param_array(model, charp, NULL, 0444);
86 MODULE_PARM_DESC(model, "Use the given board model.");
87 module_param_array(position_fix, int, NULL, 0444);
88 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
89 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
90 module_param_array(bdl_pos_adj, int, NULL, 0644);
91 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
92 module_param_array(probe_mask, int, NULL, 0444);
93 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
94 module_param_array(probe_only, int, NULL, 0444);
95 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
96 module_param(single_cmd, bool, 0444);
97 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
98 "(for debugging only).");
99 module_param(enable_msi, bint, 0444);
100 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
101 #ifdef CONFIG_SND_HDA_PATCH_LOADER
102 module_param_array(patch, charp, NULL, 0444);
103 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
105 #ifdef CONFIG_SND_HDA_INPUT_BEEP
106 module_param_array(beep_mode, bool, NULL, 0444);
107 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
108 "(0=off, 1=on) (default=1).");
111 #ifdef CONFIG_SND_HDA_POWER_SAVE
112 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
113 module_param(power_save, int, 0644);
114 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
115 "(in second, 0 = disable).");
117 /* reset the HD-audio controller in power save mode.
118 * this may give more power-saving, but will take longer time to
121 static bool power_save_controller = 1;
122 module_param(power_save_controller, bool, 0644);
123 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
126 static int align_buffer_size = -1;
127 module_param(align_buffer_size, bint, 0644);
128 MODULE_PARM_DESC(align_buffer_size,
129 "Force buffer and period sizes to be multiple of 128 bytes.");
132 static bool hda_snoop = true;
133 module_param_named(snoop, hda_snoop, bool, 0444);
134 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
135 #define azx_snoop(chip) (chip)->snoop
137 #define hda_snoop true
138 #define azx_snoop(chip) true
142 MODULE_LICENSE("GPL");
143 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
173 MODULE_DESCRIPTION("Intel HDA driver");
175 #ifdef CONFIG_SND_VERBOSE_PRINTK
176 #define SFX /* nop */
178 #define SFX "hda-intel: "
181 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
182 #ifdef CONFIG_SND_HDA_CODEC_HDMI
183 #define SUPPORT_VGA_SWITCHEROO
191 #define ICH6_REG_GCAP 0x00
192 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
193 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
194 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
195 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
196 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
197 #define ICH6_REG_VMIN 0x02
198 #define ICH6_REG_VMAJ 0x03
199 #define ICH6_REG_OUTPAY 0x04
200 #define ICH6_REG_INPAY 0x06
201 #define ICH6_REG_GCTL 0x08
202 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
203 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
204 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
205 #define ICH6_REG_WAKEEN 0x0c
206 #define ICH6_REG_STATESTS 0x0e
207 #define ICH6_REG_GSTS 0x10
208 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
209 #define ICH6_REG_INTCTL 0x20
210 #define ICH6_REG_INTSTS 0x24
211 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
212 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
213 #define ICH6_REG_SSYNC 0x38
214 #define ICH6_REG_CORBLBASE 0x40
215 #define ICH6_REG_CORBUBASE 0x44
216 #define ICH6_REG_CORBWP 0x48
217 #define ICH6_REG_CORBRP 0x4a
218 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
219 #define ICH6_REG_CORBCTL 0x4c
220 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
221 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
222 #define ICH6_REG_CORBSTS 0x4d
223 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
224 #define ICH6_REG_CORBSIZE 0x4e
226 #define ICH6_REG_RIRBLBASE 0x50
227 #define ICH6_REG_RIRBUBASE 0x54
228 #define ICH6_REG_RIRBWP 0x58
229 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
230 #define ICH6_REG_RINTCNT 0x5a
231 #define ICH6_REG_RIRBCTL 0x5c
232 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
233 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
234 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
235 #define ICH6_REG_RIRBSTS 0x5d
236 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
237 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
238 #define ICH6_REG_RIRBSIZE 0x5e
240 #define ICH6_REG_IC 0x60
241 #define ICH6_REG_IR 0x64
242 #define ICH6_REG_IRS 0x68
243 #define ICH6_IRS_VALID (1<<1)
244 #define ICH6_IRS_BUSY (1<<0)
246 #define ICH6_REG_DPLBASE 0x70
247 #define ICH6_REG_DPUBASE 0x74
248 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
250 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
251 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
253 /* stream register offsets from stream base */
254 #define ICH6_REG_SD_CTL 0x00
255 #define ICH6_REG_SD_STS 0x03
256 #define ICH6_REG_SD_LPIB 0x04
257 #define ICH6_REG_SD_CBL 0x08
258 #define ICH6_REG_SD_LVI 0x0c
259 #define ICH6_REG_SD_FIFOW 0x0e
260 #define ICH6_REG_SD_FIFOSIZE 0x10
261 #define ICH6_REG_SD_FORMAT 0x12
262 #define ICH6_REG_SD_BDLPL 0x18
263 #define ICH6_REG_SD_BDLPU 0x1c
266 #define ICH6_PCIREG_TCSEL 0x44
272 /* max number of SDs */
273 /* ICH, ATI and VIA have 4 playback and 4 capture */
274 #define ICH6_NUM_CAPTURE 4
275 #define ICH6_NUM_PLAYBACK 4
277 /* ULI has 6 playback and 5 capture */
278 #define ULI_NUM_CAPTURE 5
279 #define ULI_NUM_PLAYBACK 6
281 /* ATI HDMI has 1 playback and 0 capture */
282 #define ATIHDMI_NUM_CAPTURE 0
283 #define ATIHDMI_NUM_PLAYBACK 1
285 /* TERA has 4 playback and 3 capture */
286 #define TERA_NUM_CAPTURE 3
287 #define TERA_NUM_PLAYBACK 4
289 /* this number is statically defined for simplicity */
290 #define MAX_AZX_DEV 16
292 /* max number of fragments - we may use more if allocating more pages for BDL */
293 #define BDL_SIZE 4096
294 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
295 #define AZX_MAX_FRAG 32
296 /* max buffer size - no h/w limit, you can increase as you like */
297 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
299 /* RIRB int mask: overrun[2], response[0] */
300 #define RIRB_INT_RESPONSE 0x01
301 #define RIRB_INT_OVERRUN 0x04
302 #define RIRB_INT_MASK 0x05
304 /* STATESTS int mask: S3,SD2,SD1,SD0 */
305 #define AZX_MAX_CODECS 8
306 #define AZX_DEFAULT_CODECS 4
307 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
310 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
311 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
312 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
313 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
314 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
315 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
316 #define SD_CTL_STREAM_TAG_SHIFT 20
318 /* SD_CTL and SD_STS */
319 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
320 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
321 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
322 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
326 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
328 /* INTCTL and INTSTS */
329 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
330 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
331 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
333 /* below are so far hardcoded - should read registers in future */
334 #define ICH6_MAX_CORB_ENTRIES 256
335 #define ICH6_MAX_RIRB_ENTRIES 256
337 /* position fix mode */
346 /* Defines for ATI HD Audio support in SB450 south bridge */
347 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
348 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
350 /* Defines for Nvidia HDA support */
351 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
352 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
353 #define NVIDIA_HDA_ISTRM_COH 0x4d
354 #define NVIDIA_HDA_OSTRM_COH 0x4c
355 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
357 /* Defines for Intel SCH HDA snoop control */
358 #define INTEL_SCH_HDA_DEVC 0x78
359 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
361 /* Define IN stream 0 FIFO size offset in VIA controller */
362 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
363 /* Define VIA HD Audio Device ID*/
364 #define VIA_HDAC_DEVICE_ID 0x3288
366 /* HD Audio class code */
367 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
373 struct snd_dma_buffer bdl; /* BDL buffer */
374 u32 *posbuf; /* position buffer pointer */
376 unsigned int bufsize; /* size of the play buffer in bytes */
377 unsigned int period_bytes; /* size of the period in bytes */
378 unsigned int frags; /* number for period in the play buffer */
379 unsigned int fifo_size; /* FIFO size */
380 unsigned long start_wallclk; /* start + minimum wallclk */
381 unsigned long period_wallclk; /* wallclk for period */
383 void __iomem *sd_addr; /* stream descriptor pointer */
385 u32 sd_int_sta_mask; /* stream int status mask */
388 struct snd_pcm_substream *substream; /* assigned substream,
391 unsigned int format_val; /* format value to be set in the
392 * controller and the codec
394 unsigned char stream_tag; /* assigned stream */
395 unsigned char index; /* stream index */
396 int assigned_key; /* last device# key assigned to */
398 unsigned int opened :1;
399 unsigned int running :1;
400 unsigned int irq_pending :1;
403 * A flag to ensure DMA position is 0
404 * when link position is not greater than FIFO size
406 unsigned int insufficient :1;
407 unsigned int wc_marked:1;
412 u32 *buf; /* CORB/RIRB buffer
413 * Each CORB entry is 4byte, RIRB is 8byte
415 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
417 unsigned short rp, wp; /* read/write pointers */
418 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
419 u32 res[AZX_MAX_CODECS]; /* last read value */
425 struct hda_codec *codec;
426 struct hda_pcm_stream *hinfo[2];
427 struct list_head list;
431 struct snd_card *card;
435 /* chip type specific */
437 unsigned int driver_caps;
438 int playback_streams;
439 int playback_index_offset;
441 int capture_index_offset;
446 void __iomem *remap_addr;
451 struct mutex open_mutex;
453 /* streams (x num_streams) */
454 struct azx_dev *azx_dev;
457 struct list_head pcm_list; /* azx_pcm list */
460 unsigned short codec_mask;
461 int codec_probe_mask; /* copied from probe_mask option */
463 unsigned int beep_mode;
469 /* CORB/RIRB and position buffers */
470 struct snd_dma_buffer rb;
471 struct snd_dma_buffer posbuf;
474 int position_fix[2]; /* for both playback/capture streams */
476 unsigned int running :1;
477 unsigned int initialized :1;
478 unsigned int single_cmd :1;
479 unsigned int polling_mode :1;
481 unsigned int irq_pending_warned :1;
482 unsigned int probing :1; /* codec probing phase */
483 unsigned int snoop:1;
484 unsigned int align_buffer_size:1;
485 unsigned int region_requested:1;
487 /* VGA-switcheroo setup */
488 unsigned int use_vga_switcheroo:1;
489 unsigned int init_failed:1; /* delayed init failed */
490 unsigned int disabled:1; /* disabled by VGA-switcher */
493 unsigned int last_cmd[AZX_MAX_CODECS];
495 /* for pending irqs */
496 struct work_struct irq_pending_work;
498 /* reboot notifier (for mysterious hangup problem at power-down) */
499 struct notifier_block reboot_notifier;
509 AZX_DRIVER_ATIHDMI_NS,
518 AZX_NUM_DRIVERS, /* keep this as last entry */
521 /* driver quirks (capabilities) */
522 /* bits 0-7 are used for indicating driver type */
523 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
524 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
525 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
526 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
527 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
528 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
529 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
530 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
531 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
532 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
533 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
534 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
535 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
536 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
537 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
538 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
539 #define AZX_DCAPS_POSFIX_COMBO (1 << 24) /* Use COMBO as default */
541 /* quirks for ATI SB / AMD Hudson */
542 #define AZX_DCAPS_PRESET_ATI_SB \
543 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
544 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
546 /* quirks for ATI/AMD HDMI */
547 #define AZX_DCAPS_PRESET_ATI_HDMI \
548 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
550 /* quirks for Nvidia */
551 #define AZX_DCAPS_PRESET_NVIDIA \
552 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
553 AZX_DCAPS_ALIGN_BUFSIZE)
555 #define AZX_DCAPS_PRESET_CTHDA \
556 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
559 * VGA-switcher support
561 #ifdef SUPPORT_VGA_SWITCHEROO
562 #define DELAYED_INIT_MARK
563 #define DELAYED_INITDATA_MARK
564 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
566 #define DELAYED_INIT_MARK __devinit
567 #define DELAYED_INITDATA_MARK __devinitdata
568 #define use_vga_switcheroo(chip) 0
571 static char *driver_short_names[] DELAYED_INITDATA_MARK = {
572 [AZX_DRIVER_ICH] = "HDA Intel",
573 [AZX_DRIVER_PCH] = "HDA Intel PCH",
574 [AZX_DRIVER_SCH] = "HDA Intel MID",
575 [AZX_DRIVER_ATI] = "HDA ATI SB",
576 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
577 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
578 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
579 [AZX_DRIVER_SIS] = "HDA SIS966",
580 [AZX_DRIVER_ULI] = "HDA ULI M5461",
581 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
582 [AZX_DRIVER_TERA] = "HDA Teradici",
583 [AZX_DRIVER_CTX] = "HDA Creative",
584 [AZX_DRIVER_CTHDA] = "HDA Creative",
585 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
589 * macros for easy use
591 #define azx_writel(chip,reg,value) \
592 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
593 #define azx_readl(chip,reg) \
594 readl((chip)->remap_addr + ICH6_REG_##reg)
595 #define azx_writew(chip,reg,value) \
596 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
597 #define azx_readw(chip,reg) \
598 readw((chip)->remap_addr + ICH6_REG_##reg)
599 #define azx_writeb(chip,reg,value) \
600 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
601 #define azx_readb(chip,reg) \
602 readb((chip)->remap_addr + ICH6_REG_##reg)
604 #define azx_sd_writel(dev,reg,value) \
605 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
606 #define azx_sd_readl(dev,reg) \
607 readl((dev)->sd_addr + ICH6_REG_##reg)
608 #define azx_sd_writew(dev,reg,value) \
609 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
610 #define azx_sd_readw(dev,reg) \
611 readw((dev)->sd_addr + ICH6_REG_##reg)
612 #define azx_sd_writeb(dev,reg,value) \
613 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
614 #define azx_sd_readb(dev,reg) \
615 readb((dev)->sd_addr + ICH6_REG_##reg)
617 /* for pcm support */
618 #define get_azx_dev(substream) (substream->runtime->private_data)
621 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
626 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
628 set_memory_wc((unsigned long)addr, pages);
630 set_memory_wb((unsigned long)addr, pages);
634 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
637 __mark_pages_wc(chip, buf->area, buf->bytes, on);
639 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
640 struct snd_pcm_runtime *runtime, bool on)
642 if (azx_dev->wc_marked != on) {
643 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
644 azx_dev->wc_marked = on;
648 /* NOP for other archs */
649 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
653 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
654 struct snd_pcm_runtime *runtime, bool on)
659 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
660 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
662 * Interface for HD codec
666 * CORB / RIRB interface
668 static int azx_alloc_cmd_io(struct azx *chip)
672 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
673 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
674 snd_dma_pci_data(chip->pci),
675 PAGE_SIZE, &chip->rb);
677 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
680 mark_pages_wc(chip, &chip->rb, true);
684 static void azx_init_cmd_io(struct azx *chip)
686 spin_lock_irq(&chip->reg_lock);
688 chip->corb.addr = chip->rb.addr;
689 chip->corb.buf = (u32 *)chip->rb.area;
690 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
691 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
693 /* set the corb size to 256 entries (ULI requires explicitly) */
694 azx_writeb(chip, CORBSIZE, 0x02);
695 /* set the corb write pointer to 0 */
696 azx_writew(chip, CORBWP, 0);
697 /* reset the corb hw read pointer */
698 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
699 /* enable corb dma */
700 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
703 chip->rirb.addr = chip->rb.addr + 2048;
704 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
705 chip->rirb.wp = chip->rirb.rp = 0;
706 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
707 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
708 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
710 /* set the rirb size to 256 entries (ULI requires explicitly) */
711 azx_writeb(chip, RIRBSIZE, 0x02);
712 /* reset the rirb hw write pointer */
713 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
714 /* set N=1, get RIRB response interrupt for new entry */
715 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
716 azx_writew(chip, RINTCNT, 0xc0);
718 azx_writew(chip, RINTCNT, 1);
719 /* enable rirb dma and response irq */
720 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
721 spin_unlock_irq(&chip->reg_lock);
724 static void azx_free_cmd_io(struct azx *chip)
726 spin_lock_irq(&chip->reg_lock);
727 /* disable ringbuffer DMAs */
728 azx_writeb(chip, RIRBCTL, 0);
729 azx_writeb(chip, CORBCTL, 0);
730 spin_unlock_irq(&chip->reg_lock);
733 static unsigned int azx_command_addr(u32 cmd)
735 unsigned int addr = cmd >> 28;
737 if (addr >= AZX_MAX_CODECS) {
745 static unsigned int azx_response_addr(u32 res)
747 unsigned int addr = res & 0xf;
749 if (addr >= AZX_MAX_CODECS) {
758 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
760 struct azx *chip = bus->private_data;
761 unsigned int addr = azx_command_addr(val);
764 spin_lock_irq(&chip->reg_lock);
766 /* add command to corb */
767 wp = azx_readb(chip, CORBWP);
769 wp %= ICH6_MAX_CORB_ENTRIES;
771 chip->rirb.cmds[addr]++;
772 chip->corb.buf[wp] = cpu_to_le32(val);
773 azx_writel(chip, CORBWP, wp);
775 spin_unlock_irq(&chip->reg_lock);
780 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
782 /* retrieve RIRB entry - called from interrupt handler */
783 static void azx_update_rirb(struct azx *chip)
789 wp = azx_readb(chip, RIRBWP);
790 if (wp == chip->rirb.wp)
794 while (chip->rirb.rp != wp) {
796 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
798 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
799 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
800 res = le32_to_cpu(chip->rirb.buf[rp]);
801 addr = azx_response_addr(res_ex);
802 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
803 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
804 else if (chip->rirb.cmds[addr]) {
805 chip->rirb.res[addr] = res;
807 chip->rirb.cmds[addr]--;
809 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
812 chip->last_cmd[addr]);
816 /* receive a response */
817 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
820 struct azx *chip = bus->private_data;
821 unsigned long timeout;
822 unsigned long loopcounter;
826 timeout = jiffies + msecs_to_jiffies(1000);
828 for (loopcounter = 0;; loopcounter++) {
829 if (chip->polling_mode || do_poll) {
830 spin_lock_irq(&chip->reg_lock);
831 azx_update_rirb(chip);
832 spin_unlock_irq(&chip->reg_lock);
834 if (!chip->rirb.cmds[addr]) {
839 chip->poll_count = 0;
840 return chip->rirb.res[addr]; /* the last value */
842 if (time_after(jiffies, timeout))
844 if (bus->needs_damn_long_delay || loopcounter > 3000)
845 msleep(2); /* temporary workaround */
852 if (!chip->polling_mode && chip->poll_count < 2) {
853 snd_printdd(SFX "azx_get_response timeout, "
854 "polling the codec once: last cmd=0x%08x\n",
855 chip->last_cmd[addr]);
862 if (!chip->polling_mode) {
863 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
864 "switching to polling mode: last cmd=0x%08x\n",
865 chip->last_cmd[addr]);
866 chip->polling_mode = 1;
871 snd_printk(KERN_WARNING SFX "No response from codec, "
872 "disabling MSI: last cmd=0x%08x\n",
873 chip->last_cmd[addr]);
874 free_irq(chip->irq, chip);
876 pci_disable_msi(chip->pci);
878 if (azx_acquire_irq(chip, 1) < 0) {
886 /* If this critical timeout happens during the codec probing
887 * phase, this is likely an access to a non-existing codec
888 * slot. Better to return an error and reset the system.
893 /* a fatal communication error; need either to reset or to fallback
894 * to the single_cmd mode
897 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
898 bus->response_reset = 1;
899 return -1; /* give a chance to retry */
902 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
903 "switching to single_cmd mode: last cmd=0x%08x\n",
904 chip->last_cmd[addr]);
905 chip->single_cmd = 1;
906 bus->response_reset = 0;
907 /* release CORB/RIRB */
908 azx_free_cmd_io(chip);
909 /* disable unsolicited responses */
910 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
915 * Use the single immediate command instead of CORB/RIRB for simplicity
917 * Note: according to Intel, this is not preferred use. The command was
918 * intended for the BIOS only, and may get confused with unsolicited
919 * responses. So, we shouldn't use it for normal operation from the
921 * I left the codes, however, for debugging/testing purposes.
924 /* receive a response */
925 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
930 /* check IRV busy bit */
931 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
932 /* reuse rirb.res as the response return value */
933 chip->rirb.res[addr] = azx_readl(chip, IR);
938 if (printk_ratelimit())
939 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
940 azx_readw(chip, IRS));
941 chip->rirb.res[addr] = -1;
946 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
948 struct azx *chip = bus->private_data;
949 unsigned int addr = azx_command_addr(val);
954 /* check ICB busy bit */
955 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
956 /* Clear IRV valid bit */
957 azx_writew(chip, IRS, azx_readw(chip, IRS) |
959 azx_writel(chip, IC, val);
960 azx_writew(chip, IRS, azx_readw(chip, IRS) |
962 return azx_single_wait_for_response(chip, addr);
966 if (printk_ratelimit())
967 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
968 azx_readw(chip, IRS), val);
972 /* receive a response */
973 static unsigned int azx_single_get_response(struct hda_bus *bus,
976 struct azx *chip = bus->private_data;
977 return chip->rirb.res[addr];
981 * The below are the main callbacks from hda_codec.
983 * They are just the skeleton to call sub-callbacks according to the
984 * current setting of chip->single_cmd.
988 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
990 struct azx *chip = bus->private_data;
994 chip->last_cmd[azx_command_addr(val)] = val;
995 if (chip->single_cmd)
996 return azx_single_send_cmd(bus, val);
998 return azx_corb_send_cmd(bus, val);
1001 /* get a response */
1002 static unsigned int azx_get_response(struct hda_bus *bus,
1005 struct azx *chip = bus->private_data;
1008 if (chip->single_cmd)
1009 return azx_single_get_response(bus, addr);
1011 return azx_rirb_get_response(bus, addr);
1014 #ifdef CONFIG_SND_HDA_POWER_SAVE
1015 static void azx_power_notify(struct hda_bus *bus);
1018 /* reset codec link */
1019 static int azx_reset(struct azx *chip, int full_reset)
1026 /* clear STATESTS */
1027 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1029 /* reset controller */
1030 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1033 while (azx_readb(chip, GCTL) && --count)
1036 /* delay for >= 100us for codec PLL to settle per spec
1037 * Rev 0.9 section 5.5.1
1041 /* Bring controller out of reset */
1042 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1045 while (!azx_readb(chip, GCTL) && --count)
1048 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1052 /* check to see if controller is ready */
1053 if (!azx_readb(chip, GCTL)) {
1054 snd_printd(SFX "azx_reset: controller not ready!\n");
1058 /* Accept unsolicited responses */
1059 if (!chip->single_cmd)
1060 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1064 if (!chip->codec_mask) {
1065 chip->codec_mask = azx_readw(chip, STATESTS);
1066 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1074 * Lowlevel interface
1077 /* enable interrupts */
1078 static void azx_int_enable(struct azx *chip)
1080 /* enable controller CIE and GIE */
1081 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1082 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1085 /* disable interrupts */
1086 static void azx_int_disable(struct azx *chip)
1090 /* disable interrupts in stream descriptor */
1091 for (i = 0; i < chip->num_streams; i++) {
1092 struct azx_dev *azx_dev = &chip->azx_dev[i];
1093 azx_sd_writeb(azx_dev, SD_CTL,
1094 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1097 /* disable SIE for all streams */
1098 azx_writeb(chip, INTCTL, 0);
1100 /* disable controller CIE and GIE */
1101 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1102 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1105 /* clear interrupts */
1106 static void azx_int_clear(struct azx *chip)
1110 /* clear stream status */
1111 for (i = 0; i < chip->num_streams; i++) {
1112 struct azx_dev *azx_dev = &chip->azx_dev[i];
1113 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1116 /* clear STATESTS */
1117 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1119 /* clear rirb status */
1120 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1122 /* clear int status */
1123 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1126 /* start a stream */
1127 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1130 * Before stream start, initialize parameter
1132 azx_dev->insufficient = 1;
1135 azx_writel(chip, INTCTL,
1136 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1137 /* set DMA start and interrupt mask */
1138 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1139 SD_CTL_DMA_START | SD_INT_MASK);
1143 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1145 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1146 ~(SD_CTL_DMA_START | SD_INT_MASK));
1147 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1151 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1153 azx_stream_clear(chip, azx_dev);
1155 azx_writel(chip, INTCTL,
1156 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1161 * reset and start the controller registers
1163 static void azx_init_chip(struct azx *chip, int full_reset)
1165 if (chip->initialized)
1168 /* reset controller */
1169 azx_reset(chip, full_reset);
1171 /* initialize interrupts */
1172 azx_int_clear(chip);
1173 azx_int_enable(chip);
1175 /* initialize the codec command I/O */
1176 if (!chip->single_cmd)
1177 azx_init_cmd_io(chip);
1179 /* program the position buffer */
1180 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1181 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1183 chip->initialized = 1;
1187 * initialize the PCI registers
1189 /* update bits in a PCI register byte */
1190 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1191 unsigned char mask, unsigned char val)
1195 pci_read_config_byte(pci, reg, &data);
1197 data |= (val & mask);
1198 pci_write_config_byte(pci, reg, data);
1201 static void azx_init_pci(struct azx *chip)
1203 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1204 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1205 * Ensuring these bits are 0 clears playback static on some HD Audio
1207 * The PCI register TCSEL is defined in the Intel manuals.
1209 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1210 snd_printdd(SFX "Clearing TCSEL\n");
1211 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1214 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1215 * we need to enable snoop.
1217 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1218 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1219 update_pci_byte(chip->pci,
1220 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1221 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1224 /* For NVIDIA HDA, enable snoop */
1225 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1226 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1227 update_pci_byte(chip->pci,
1228 NVIDIA_HDA_TRANSREG_ADDR,
1229 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1230 update_pci_byte(chip->pci,
1231 NVIDIA_HDA_ISTRM_COH,
1232 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1233 update_pci_byte(chip->pci,
1234 NVIDIA_HDA_OSTRM_COH,
1235 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1238 /* Enable SCH/PCH snoop if needed */
1239 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1240 unsigned short snoop;
1241 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1242 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1243 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1244 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1245 if (!azx_snoop(chip))
1246 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1247 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1248 pci_read_config_word(chip->pci,
1249 INTEL_SCH_HDA_DEVC, &snoop);
1251 snd_printdd(SFX "SCH snoop: %s\n",
1252 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1253 ? "Disabled" : "Enabled");
1258 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1263 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1265 struct azx *chip = dev_id;
1266 struct azx_dev *azx_dev;
1271 spin_lock(&chip->reg_lock);
1273 if (chip->disabled) {
1274 spin_unlock(&chip->reg_lock);
1278 status = azx_readl(chip, INTSTS);
1280 spin_unlock(&chip->reg_lock);
1284 for (i = 0; i < chip->num_streams; i++) {
1285 azx_dev = &chip->azx_dev[i];
1286 if (status & azx_dev->sd_int_sta_mask) {
1287 sd_status = azx_sd_readb(azx_dev, SD_STS);
1288 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1289 if (!azx_dev->substream || !azx_dev->running ||
1290 !(sd_status & SD_INT_COMPLETE))
1292 /* check whether this IRQ is really acceptable */
1293 ok = azx_position_ok(chip, azx_dev);
1295 azx_dev->irq_pending = 0;
1296 spin_unlock(&chip->reg_lock);
1297 snd_pcm_period_elapsed(azx_dev->substream);
1298 spin_lock(&chip->reg_lock);
1299 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1300 /* bogus IRQ, process it later */
1301 azx_dev->irq_pending = 1;
1302 queue_work(chip->bus->workq,
1303 &chip->irq_pending_work);
1308 /* clear rirb int */
1309 status = azx_readb(chip, RIRBSTS);
1310 if (status & RIRB_INT_MASK) {
1311 if (status & RIRB_INT_RESPONSE) {
1312 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1314 azx_update_rirb(chip);
1316 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1320 /* clear state status int */
1321 if (azx_readb(chip, STATESTS) & 0x04)
1322 azx_writeb(chip, STATESTS, 0x04);
1324 spin_unlock(&chip->reg_lock);
1331 * set up a BDL entry
1333 static int setup_bdle(struct azx *chip,
1334 struct snd_pcm_substream *substream,
1335 struct azx_dev *azx_dev, u32 **bdlp,
1336 int ofs, int size, int with_ioc)
1344 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1347 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1348 /* program the address field of the BDL entry */
1349 bdl[0] = cpu_to_le32((u32)addr);
1350 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1351 /* program the size field of the BDL entry */
1352 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1353 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1354 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1355 u32 remain = 0x1000 - (ofs & 0xfff);
1359 bdl[2] = cpu_to_le32(chunk);
1360 /* program the IOC to enable interrupt
1361 * only when the whole fragment is processed
1364 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1374 * set up BDL entries
1376 static int azx_setup_periods(struct azx *chip,
1377 struct snd_pcm_substream *substream,
1378 struct azx_dev *azx_dev)
1381 int i, ofs, periods, period_bytes;
1384 /* reset BDL address */
1385 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1386 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1388 period_bytes = azx_dev->period_bytes;
1389 periods = azx_dev->bufsize / period_bytes;
1391 /* program the initial BDL entries */
1392 bdl = (u32 *)azx_dev->bdl.area;
1395 pos_adj = bdl_pos_adj[chip->dev_index];
1397 struct snd_pcm_runtime *runtime = substream->runtime;
1398 int pos_align = pos_adj;
1399 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1401 pos_adj = pos_align;
1403 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1405 pos_adj = frames_to_bytes(runtime, pos_adj);
1406 if (pos_adj >= period_bytes) {
1407 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1408 bdl_pos_adj[chip->dev_index]);
1411 ofs = setup_bdle(chip, substream, azx_dev,
1413 !substream->runtime->no_period_wakeup);
1419 for (i = 0; i < periods; i++) {
1420 if (i == periods - 1 && pos_adj)
1421 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1422 period_bytes - pos_adj, 0);
1424 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1426 !substream->runtime->no_period_wakeup);
1433 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1434 azx_dev->bufsize, period_bytes);
1439 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1444 azx_stream_clear(chip, azx_dev);
1446 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1447 SD_CTL_STREAM_RESET);
1450 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1453 val &= ~SD_CTL_STREAM_RESET;
1454 azx_sd_writeb(azx_dev, SD_CTL, val);
1458 /* waiting for hardware to report that the stream is out of reset */
1459 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1463 /* reset first position - may not be synced with hw at this time */
1464 *azx_dev->posbuf = 0;
1468 * set up the SD for streaming
1470 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1473 /* make sure the run bit is zero for SD */
1474 azx_stream_clear(chip, azx_dev);
1475 /* program the stream_tag */
1476 val = azx_sd_readl(azx_dev, SD_CTL);
1477 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1478 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1479 if (!azx_snoop(chip))
1480 val |= SD_CTL_TRAFFIC_PRIO;
1481 azx_sd_writel(azx_dev, SD_CTL, val);
1483 /* program the length of samples in cyclic buffer */
1484 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1486 /* program the stream format */
1487 /* this value needs to be the same as the one programmed */
1488 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1490 /* program the stream LVI (last valid index) of the BDL */
1491 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1493 /* program the BDL address */
1494 /* lower BDL address */
1495 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1496 /* upper BDL address */
1497 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1499 /* enable the position buffer */
1500 if (chip->position_fix[0] != POS_FIX_LPIB ||
1501 chip->position_fix[1] != POS_FIX_LPIB) {
1502 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1503 azx_writel(chip, DPLBASE,
1504 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1507 /* set the interrupt enable bits in the descriptor control register */
1508 azx_sd_writel(azx_dev, SD_CTL,
1509 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1515 * Probe the given codec address
1517 static int probe_codec(struct azx *chip, int addr)
1519 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1520 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1523 mutex_lock(&chip->bus->cmd_mutex);
1525 azx_send_cmd(chip->bus, cmd);
1526 res = azx_get_response(chip->bus, addr);
1528 mutex_unlock(&chip->bus->cmd_mutex);
1531 snd_printdd(SFX "codec #%d probed OK\n", addr);
1535 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1536 struct hda_pcm *cpcm);
1537 static void azx_stop_chip(struct azx *chip);
1539 static void azx_bus_reset(struct hda_bus *bus)
1541 struct azx *chip = bus->private_data;
1544 azx_stop_chip(chip);
1545 azx_init_chip(chip, 1);
1547 if (chip->initialized) {
1549 list_for_each_entry(p, &chip->pcm_list, list)
1550 snd_pcm_suspend_all(p->pcm);
1551 snd_hda_suspend(chip->bus);
1552 snd_hda_resume(chip->bus);
1559 * Codec initialization
1562 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1563 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
1564 [AZX_DRIVER_NVIDIA] = 8,
1565 [AZX_DRIVER_TERA] = 1,
1568 static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1570 struct hda_bus_template bus_temp;
1574 memset(&bus_temp, 0, sizeof(bus_temp));
1575 bus_temp.private_data = chip;
1576 bus_temp.modelname = model;
1577 bus_temp.pci = chip->pci;
1578 bus_temp.ops.command = azx_send_cmd;
1579 bus_temp.ops.get_response = azx_get_response;
1580 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1581 bus_temp.ops.bus_reset = azx_bus_reset;
1582 #ifdef CONFIG_SND_HDA_POWER_SAVE
1583 bus_temp.power_save = &power_save;
1584 bus_temp.ops.pm_notify = azx_power_notify;
1587 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1591 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1592 snd_printd(SFX "Enable delay in RIRB handling\n");
1593 chip->bus->needs_damn_long_delay = 1;
1597 max_slots = azx_max_codecs[chip->driver_type];
1599 max_slots = AZX_DEFAULT_CODECS;
1601 /* First try to probe all given codec slots */
1602 for (c = 0; c < max_slots; c++) {
1603 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1604 if (probe_codec(chip, c) < 0) {
1605 /* Some BIOSen give you wrong codec addresses
1608 snd_printk(KERN_WARNING SFX
1609 "Codec #%d probe error; "
1610 "disabling it...\n", c);
1611 chip->codec_mask &= ~(1 << c);
1612 /* More badly, accessing to a non-existing
1613 * codec often screws up the controller chip,
1614 * and disturbs the further communications.
1615 * Thus if an error occurs during probing,
1616 * better to reset the controller chip to
1617 * get back to the sanity state.
1619 azx_stop_chip(chip);
1620 azx_init_chip(chip, 1);
1625 /* AMD chipsets often cause the communication stalls upon certain
1626 * sequence like the pin-detection. It seems that forcing the synced
1627 * access works around the stall. Grrr...
1629 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1630 snd_printd(SFX "Enable sync_write for stable communication\n");
1631 chip->bus->sync_write = 1;
1632 chip->bus->allow_bus_reset = 1;
1635 /* Then create codec instances */
1636 for (c = 0; c < max_slots; c++) {
1637 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1638 struct hda_codec *codec;
1639 err = snd_hda_codec_new(chip->bus, c, &codec);
1642 codec->beep_mode = chip->beep_mode;
1647 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1653 /* configure each codec instance */
1654 static int __devinit azx_codec_configure(struct azx *chip)
1656 struct hda_codec *codec;
1657 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1658 snd_hda_codec_configure(codec);
1668 /* assign a stream for the PCM */
1669 static inline struct azx_dev *
1670 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1673 struct azx_dev *res = NULL;
1674 /* make a non-zero unique key for the substream */
1675 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1676 (substream->stream + 1);
1678 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1679 dev = chip->playback_index_offset;
1680 nums = chip->playback_streams;
1682 dev = chip->capture_index_offset;
1683 nums = chip->capture_streams;
1685 for (i = 0; i < nums; i++, dev++)
1686 if (!chip->azx_dev[dev].opened) {
1687 res = &chip->azx_dev[dev];
1688 if (res->assigned_key == key)
1693 res->assigned_key = key;
1698 /* release the assigned stream */
1699 static inline void azx_release_device(struct azx_dev *azx_dev)
1701 azx_dev->opened = 0;
1704 static struct snd_pcm_hardware azx_pcm_hw = {
1705 .info = (SNDRV_PCM_INFO_MMAP |
1706 SNDRV_PCM_INFO_INTERLEAVED |
1707 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1708 SNDRV_PCM_INFO_MMAP_VALID |
1709 /* No full-resume yet implemented */
1710 /* SNDRV_PCM_INFO_RESUME |*/
1711 SNDRV_PCM_INFO_PAUSE |
1712 SNDRV_PCM_INFO_SYNC_START |
1713 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1714 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1715 .rates = SNDRV_PCM_RATE_48000,
1720 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1721 .period_bytes_min = 128,
1722 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1724 .periods_max = AZX_MAX_FRAG,
1728 static int azx_pcm_open(struct snd_pcm_substream *substream)
1730 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1731 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1732 struct azx *chip = apcm->chip;
1733 struct azx_dev *azx_dev;
1734 struct snd_pcm_runtime *runtime = substream->runtime;
1735 unsigned long flags;
1739 mutex_lock(&chip->open_mutex);
1740 azx_dev = azx_assign_device(chip, substream);
1741 if (azx_dev == NULL) {
1742 mutex_unlock(&chip->open_mutex);
1745 runtime->hw = azx_pcm_hw;
1746 runtime->hw.channels_min = hinfo->channels_min;
1747 runtime->hw.channels_max = hinfo->channels_max;
1748 runtime->hw.formats = hinfo->formats;
1749 runtime->hw.rates = hinfo->rates;
1750 snd_pcm_limit_hw_rates(runtime);
1751 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1752 if (chip->align_buffer_size)
1753 /* constrain buffer sizes to be multiple of 128
1754 bytes. This is more efficient in terms of memory
1755 access but isn't required by the HDA spec and
1756 prevents users from specifying exact period/buffer
1757 sizes. For example for 44.1kHz, a period size set
1758 to 20ms will be rounded to 19.59ms. */
1761 /* Don't enforce steps on buffer sizes, still need to
1762 be multiple of 4 bytes (HDA spec). Tested on Intel
1763 HDA controllers, may not work on all devices where
1764 option needs to be disabled */
1767 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1769 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1771 snd_hda_power_up_d3wait(apcm->codec);
1772 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1774 azx_release_device(azx_dev);
1775 snd_hda_power_down(apcm->codec);
1776 mutex_unlock(&chip->open_mutex);
1779 snd_pcm_limit_hw_rates(runtime);
1781 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1782 snd_BUG_ON(!runtime->hw.channels_max) ||
1783 snd_BUG_ON(!runtime->hw.formats) ||
1784 snd_BUG_ON(!runtime->hw.rates)) {
1785 azx_release_device(azx_dev);
1786 hinfo->ops.close(hinfo, apcm->codec, substream);
1787 snd_hda_power_down(apcm->codec);
1788 mutex_unlock(&chip->open_mutex);
1791 spin_lock_irqsave(&chip->reg_lock, flags);
1792 azx_dev->substream = substream;
1793 azx_dev->running = 0;
1794 spin_unlock_irqrestore(&chip->reg_lock, flags);
1796 runtime->private_data = azx_dev;
1797 snd_pcm_set_sync(substream);
1798 mutex_unlock(&chip->open_mutex);
1802 static int azx_pcm_close(struct snd_pcm_substream *substream)
1804 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1805 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1806 struct azx *chip = apcm->chip;
1807 struct azx_dev *azx_dev = get_azx_dev(substream);
1808 unsigned long flags;
1810 mutex_lock(&chip->open_mutex);
1811 spin_lock_irqsave(&chip->reg_lock, flags);
1812 azx_dev->substream = NULL;
1813 azx_dev->running = 0;
1814 spin_unlock_irqrestore(&chip->reg_lock, flags);
1815 azx_release_device(azx_dev);
1816 hinfo->ops.close(hinfo, apcm->codec, substream);
1817 snd_hda_power_down(apcm->codec);
1818 mutex_unlock(&chip->open_mutex);
1822 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1823 struct snd_pcm_hw_params *hw_params)
1825 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1826 struct azx *chip = apcm->chip;
1827 struct snd_pcm_runtime *runtime = substream->runtime;
1828 struct azx_dev *azx_dev = get_azx_dev(substream);
1831 mark_runtime_wc(chip, azx_dev, runtime, false);
1832 azx_dev->bufsize = 0;
1833 azx_dev->period_bytes = 0;
1834 azx_dev->format_val = 0;
1835 ret = snd_pcm_lib_malloc_pages(substream,
1836 params_buffer_bytes(hw_params));
1839 mark_runtime_wc(chip, azx_dev, runtime, true);
1843 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1845 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1846 struct azx_dev *azx_dev = get_azx_dev(substream);
1847 struct azx *chip = apcm->chip;
1848 struct snd_pcm_runtime *runtime = substream->runtime;
1849 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1851 /* reset BDL address */
1852 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1853 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1854 azx_sd_writel(azx_dev, SD_CTL, 0);
1855 azx_dev->bufsize = 0;
1856 azx_dev->period_bytes = 0;
1857 azx_dev->format_val = 0;
1859 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1861 mark_runtime_wc(chip, azx_dev, runtime, false);
1862 return snd_pcm_lib_free_pages(substream);
1865 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1867 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1868 struct azx *chip = apcm->chip;
1869 struct azx_dev *azx_dev = get_azx_dev(substream);
1870 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1871 struct snd_pcm_runtime *runtime = substream->runtime;
1872 unsigned int bufsize, period_bytes, format_val, stream_tag;
1874 struct hda_spdif_out *spdif =
1875 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1876 unsigned short ctls = spdif ? spdif->ctls : 0;
1878 azx_stream_reset(chip, azx_dev);
1879 format_val = snd_hda_calc_stream_format(runtime->rate,
1885 snd_printk(KERN_ERR SFX
1886 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1887 runtime->rate, runtime->channels, runtime->format);
1891 bufsize = snd_pcm_lib_buffer_bytes(substream);
1892 period_bytes = snd_pcm_lib_period_bytes(substream);
1894 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1895 bufsize, format_val);
1897 if (bufsize != azx_dev->bufsize ||
1898 period_bytes != azx_dev->period_bytes ||
1899 format_val != azx_dev->format_val) {
1900 azx_dev->bufsize = bufsize;
1901 azx_dev->period_bytes = period_bytes;
1902 azx_dev->format_val = format_val;
1903 err = azx_setup_periods(chip, substream, azx_dev);
1908 /* wallclk has 24Mhz clock source */
1909 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1910 runtime->rate) * 1000);
1911 azx_setup_controller(chip, azx_dev);
1912 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1913 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1915 azx_dev->fifo_size = 0;
1917 stream_tag = azx_dev->stream_tag;
1918 /* CA-IBG chips need the playback stream starting from 1 */
1919 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1920 stream_tag > chip->capture_streams)
1921 stream_tag -= chip->capture_streams;
1922 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1923 azx_dev->format_val, substream);
1926 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1928 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1929 struct azx *chip = apcm->chip;
1930 struct azx_dev *azx_dev;
1931 struct snd_pcm_substream *s;
1932 int rstart = 0, start, nsync = 0, sbits = 0;
1936 case SNDRV_PCM_TRIGGER_START:
1938 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1939 case SNDRV_PCM_TRIGGER_RESUME:
1942 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1943 case SNDRV_PCM_TRIGGER_SUSPEND:
1944 case SNDRV_PCM_TRIGGER_STOP:
1951 snd_pcm_group_for_each_entry(s, substream) {
1952 if (s->pcm->card != substream->pcm->card)
1954 azx_dev = get_azx_dev(s);
1955 sbits |= 1 << azx_dev->index;
1957 snd_pcm_trigger_done(s, substream);
1960 spin_lock(&chip->reg_lock);
1962 /* first, set SYNC bits of corresponding streams */
1963 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1964 azx_writel(chip, OLD_SSYNC,
1965 azx_readl(chip, OLD_SSYNC) | sbits);
1967 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1969 snd_pcm_group_for_each_entry(s, substream) {
1970 if (s->pcm->card != substream->pcm->card)
1972 azx_dev = get_azx_dev(s);
1974 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1976 azx_dev->start_wallclk -=
1977 azx_dev->period_wallclk;
1978 azx_stream_start(chip, azx_dev);
1980 azx_stream_stop(chip, azx_dev);
1982 azx_dev->running = start;
1984 spin_unlock(&chip->reg_lock);
1988 /* wait until all FIFOs get ready */
1989 for (timeout = 5000; timeout; timeout--) {
1991 snd_pcm_group_for_each_entry(s, substream) {
1992 if (s->pcm->card != substream->pcm->card)
1994 azx_dev = get_azx_dev(s);
1995 if (!(azx_sd_readb(azx_dev, SD_STS) &
2004 /* wait until all RUN bits are cleared */
2005 for (timeout = 5000; timeout; timeout--) {
2007 snd_pcm_group_for_each_entry(s, substream) {
2008 if (s->pcm->card != substream->pcm->card)
2010 azx_dev = get_azx_dev(s);
2011 if (azx_sd_readb(azx_dev, SD_CTL) &
2021 spin_lock(&chip->reg_lock);
2022 /* reset SYNC bits */
2023 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2024 azx_writel(chip, OLD_SSYNC,
2025 azx_readl(chip, OLD_SSYNC) & ~sbits);
2027 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2028 spin_unlock(&chip->reg_lock);
2033 /* get the current DMA position with correction on VIA chips */
2034 static unsigned int azx_via_get_position(struct azx *chip,
2035 struct azx_dev *azx_dev)
2037 unsigned int link_pos, mini_pos, bound_pos;
2038 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2039 unsigned int fifo_size;
2041 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2042 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2043 /* Playback, no problem using link position */
2049 * use mod to get the DMA position just like old chipset
2051 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2052 mod_dma_pos %= azx_dev->period_bytes;
2054 /* azx_dev->fifo_size can't get FIFO size of in stream.
2055 * Get from base address + offset.
2057 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2059 if (azx_dev->insufficient) {
2060 /* Link position never gather than FIFO size */
2061 if (link_pos <= fifo_size)
2064 azx_dev->insufficient = 0;
2067 if (link_pos <= fifo_size)
2068 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2070 mini_pos = link_pos - fifo_size;
2072 /* Find nearest previous boudary */
2073 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2074 mod_link_pos = link_pos % azx_dev->period_bytes;
2075 if (mod_link_pos >= fifo_size)
2076 bound_pos = link_pos - mod_link_pos;
2077 else if (mod_dma_pos >= mod_mini_pos)
2078 bound_pos = mini_pos - mod_mini_pos;
2080 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2081 if (bound_pos >= azx_dev->bufsize)
2085 /* Calculate real DMA position we want */
2086 return bound_pos + mod_dma_pos;
2089 static unsigned int azx_get_position(struct azx *chip,
2090 struct azx_dev *azx_dev,
2094 int stream = azx_dev->substream->stream;
2096 switch (chip->position_fix[stream]) {
2099 pos = azx_sd_readl(azx_dev, SD_LPIB);
2101 case POS_FIX_VIACOMBO:
2102 pos = azx_via_get_position(chip, azx_dev);
2105 /* use the position buffer */
2106 pos = le32_to_cpu(*azx_dev->posbuf);
2107 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2108 if (!pos || pos == (u32)-1) {
2110 "hda-intel: Invalid position buffer, "
2111 "using LPIB read method instead.\n");
2112 chip->position_fix[stream] = POS_FIX_LPIB;
2113 pos = azx_sd_readl(azx_dev, SD_LPIB);
2115 chip->position_fix[stream] = POS_FIX_POSBUF;
2120 if (pos >= azx_dev->bufsize)
2125 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2127 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2128 struct azx *chip = apcm->chip;
2129 struct azx_dev *azx_dev = get_azx_dev(substream);
2130 return bytes_to_frames(substream->runtime,
2131 azx_get_position(chip, azx_dev, false));
2135 * Check whether the current DMA position is acceptable for updating
2136 * periods. Returns non-zero if it's OK.
2138 * Many HD-audio controllers appear pretty inaccurate about
2139 * the update-IRQ timing. The IRQ is issued before actually the
2140 * data is processed. So, we need to process it afterwords in a
2143 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2149 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2150 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2151 return -1; /* bogus (too early) interrupt */
2153 stream = azx_dev->substream->stream;
2154 pos = azx_get_position(chip, azx_dev, true);
2156 if (WARN_ONCE(!azx_dev->period_bytes,
2157 "hda-intel: zero azx_dev->period_bytes"))
2158 return -1; /* this shouldn't happen! */
2159 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2160 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2161 /* NG - it's below the first next period boundary */
2162 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2163 azx_dev->start_wallclk += wallclk;
2164 return 1; /* OK, it's fine */
2168 * The work for pending PCM period updates.
2170 static void azx_irq_pending_work(struct work_struct *work)
2172 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2175 if (!chip->irq_pending_warned) {
2177 "hda-intel: IRQ timing workaround is activated "
2178 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2179 chip->card->number);
2180 chip->irq_pending_warned = 1;
2185 spin_lock_irq(&chip->reg_lock);
2186 for (i = 0; i < chip->num_streams; i++) {
2187 struct azx_dev *azx_dev = &chip->azx_dev[i];
2188 if (!azx_dev->irq_pending ||
2189 !azx_dev->substream ||
2192 ok = azx_position_ok(chip, azx_dev);
2194 azx_dev->irq_pending = 0;
2195 spin_unlock(&chip->reg_lock);
2196 snd_pcm_period_elapsed(azx_dev->substream);
2197 spin_lock(&chip->reg_lock);
2198 } else if (ok < 0) {
2199 pending = 0; /* too early */
2203 spin_unlock_irq(&chip->reg_lock);
2210 /* clear irq_pending flags and assure no on-going workq */
2211 static void azx_clear_irq_pending(struct azx *chip)
2215 spin_lock_irq(&chip->reg_lock);
2216 for (i = 0; i < chip->num_streams; i++)
2217 chip->azx_dev[i].irq_pending = 0;
2218 spin_unlock_irq(&chip->reg_lock);
2222 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2223 struct vm_area_struct *area)
2225 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2226 struct azx *chip = apcm->chip;
2227 if (!azx_snoop(chip))
2228 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2229 return snd_pcm_lib_default_mmap(substream, area);
2232 #define azx_pcm_mmap NULL
2235 static struct snd_pcm_ops azx_pcm_ops = {
2236 .open = azx_pcm_open,
2237 .close = azx_pcm_close,
2238 .ioctl = snd_pcm_lib_ioctl,
2239 .hw_params = azx_pcm_hw_params,
2240 .hw_free = azx_pcm_hw_free,
2241 .prepare = azx_pcm_prepare,
2242 .trigger = azx_pcm_trigger,
2243 .pointer = azx_pcm_pointer,
2244 .mmap = azx_pcm_mmap,
2245 .page = snd_pcm_sgbuf_ops_page,
2248 static void azx_pcm_free(struct snd_pcm *pcm)
2250 struct azx_pcm *apcm = pcm->private_data;
2252 list_del(&apcm->list);
2257 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2260 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2261 struct hda_pcm *cpcm)
2263 struct azx *chip = bus->private_data;
2264 struct snd_pcm *pcm;
2265 struct azx_pcm *apcm;
2266 int pcm_dev = cpcm->device;
2270 list_for_each_entry(apcm, &chip->pcm_list, list) {
2271 if (apcm->pcm->device == pcm_dev) {
2272 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2276 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2277 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2278 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2282 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2283 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2288 apcm->codec = codec;
2289 pcm->private_data = apcm;
2290 pcm->private_free = azx_pcm_free;
2291 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2292 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2293 list_add_tail(&apcm->list, &chip->pcm_list);
2295 for (s = 0; s < 2; s++) {
2296 apcm->hinfo[s] = &cpcm->stream[s];
2297 if (cpcm->stream[s].substreams)
2298 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2300 /* buffer pre-allocation */
2301 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2302 if (size > MAX_PREALLOC_SIZE)
2303 size = MAX_PREALLOC_SIZE;
2304 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2305 snd_dma_pci_data(chip->pci),
2306 size, MAX_PREALLOC_SIZE);
2311 * mixer creation - all stuff is implemented in hda module
2313 static int __devinit azx_mixer_create(struct azx *chip)
2315 return snd_hda_build_controls(chip->bus);
2320 * initialize SD streams
2322 static int __devinit azx_init_stream(struct azx *chip)
2326 /* initialize each stream (aka device)
2327 * assign the starting bdl address to each stream (device)
2330 for (i = 0; i < chip->num_streams; i++) {
2331 struct azx_dev *azx_dev = &chip->azx_dev[i];
2332 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2333 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2334 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2335 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2336 azx_dev->sd_int_sta_mask = 1 << i;
2337 /* stream tag: must be non-zero and unique */
2339 azx_dev->stream_tag = i + 1;
2345 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2347 if (request_irq(chip->pci->irq, azx_interrupt,
2348 chip->msi ? 0 : IRQF_SHARED,
2349 KBUILD_MODNAME, chip)) {
2350 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2351 "disabling device\n", chip->pci->irq);
2353 snd_card_disconnect(chip->card);
2356 chip->irq = chip->pci->irq;
2357 pci_intx(chip->pci, !chip->msi);
2362 static void azx_stop_chip(struct azx *chip)
2364 if (!chip->initialized)
2367 /* disable interrupts */
2368 azx_int_disable(chip);
2369 azx_int_clear(chip);
2371 /* disable CORB/RIRB */
2372 azx_free_cmd_io(chip);
2374 /* disable position buffer */
2375 azx_writel(chip, DPLBASE, 0);
2376 azx_writel(chip, DPUBASE, 0);
2378 chip->initialized = 0;
2381 #ifdef CONFIG_SND_HDA_POWER_SAVE
2382 /* power-up/down the controller */
2383 static void azx_power_notify(struct hda_bus *bus)
2385 struct azx *chip = bus->private_data;
2386 struct hda_codec *c;
2389 list_for_each_entry(c, &bus->codec_list, list) {
2396 azx_init_chip(chip, 1);
2397 else if (chip->running && power_save_controller &&
2398 !bus->power_keep_link_on)
2399 azx_stop_chip(chip);
2401 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2408 static int azx_suspend(struct device *dev)
2410 struct pci_dev *pci = to_pci_dev(dev);
2411 struct snd_card *card = dev_get_drvdata(dev);
2412 struct azx *chip = card->private_data;
2415 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2416 azx_clear_irq_pending(chip);
2417 list_for_each_entry(p, &chip->pcm_list, list)
2418 snd_pcm_suspend_all(p->pcm);
2419 if (chip->initialized)
2420 snd_hda_suspend(chip->bus);
2421 azx_stop_chip(chip);
2422 if (chip->irq >= 0) {
2423 free_irq(chip->irq, chip);
2427 pci_disable_msi(chip->pci);
2428 pci_disable_device(pci);
2429 pci_save_state(pci);
2430 pci_set_power_state(pci, PCI_D3hot);
2434 static int azx_resume(struct device *dev)
2436 struct pci_dev *pci = to_pci_dev(dev);
2437 struct snd_card *card = dev_get_drvdata(dev);
2438 struct azx *chip = card->private_data;
2440 pci_set_power_state(pci, PCI_D0);
2441 pci_restore_state(pci);
2442 if (pci_enable_device(pci) < 0) {
2443 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2444 "disabling device\n");
2445 snd_card_disconnect(card);
2448 pci_set_master(pci);
2450 if (pci_enable_msi(pci) < 0)
2452 if (azx_acquire_irq(chip, 1) < 0)
2456 azx_init_chip(chip, 1);
2458 snd_hda_resume(chip->bus);
2459 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2462 static SIMPLE_DEV_PM_OPS(azx_pm, azx_suspend, azx_resume);
2463 #define AZX_PM_OPS &azx_pm
2465 #define azx_suspend(dev)
2466 #define azx_resume(dev)
2467 #define AZX_PM_OPS NULL
2468 #endif /* CONFIG_PM */
2472 * reboot notifier for hang-up problem at power-down
2474 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2476 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2477 snd_hda_bus_reboot_notify(chip->bus);
2478 azx_stop_chip(chip);
2482 static void azx_notifier_register(struct azx *chip)
2484 chip->reboot_notifier.notifier_call = azx_halt;
2485 register_reboot_notifier(&chip->reboot_notifier);
2488 static void azx_notifier_unregister(struct azx *chip)
2490 if (chip->reboot_notifier.notifier_call)
2491 unregister_reboot_notifier(&chip->reboot_notifier);
2494 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2495 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2497 #ifdef SUPPORT_VGA_SWITCHEROO
2498 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2500 static void azx_vs_set_state(struct pci_dev *pci,
2501 enum vga_switcheroo_state state)
2503 struct snd_card *card = pci_get_drvdata(pci);
2504 struct azx *chip = card->private_data;
2507 if (chip->init_failed)
2510 disabled = (state == VGA_SWITCHEROO_OFF);
2511 if (chip->disabled == disabled)
2515 chip->disabled = disabled;
2517 snd_printk(KERN_INFO SFX
2518 "%s: Start delayed initialization\n",
2519 pci_name(chip->pci));
2520 if (azx_first_init(chip) < 0 ||
2521 azx_probe_continue(chip) < 0) {
2522 snd_printk(KERN_ERR SFX
2523 "%s: initialization error\n",
2524 pci_name(chip->pci));
2525 chip->init_failed = true;
2529 snd_printk(KERN_INFO SFX
2530 "%s %s via VGA-switcheroo\n",
2531 disabled ? "Disabling" : "Enabling",
2532 pci_name(chip->pci));
2534 azx_suspend(&pci->dev);
2535 chip->disabled = true;
2536 snd_hda_lock_devices(chip->bus);
2538 snd_hda_unlock_devices(chip->bus);
2539 chip->disabled = false;
2540 azx_resume(&pci->dev);
2545 static bool azx_vs_can_switch(struct pci_dev *pci)
2547 struct snd_card *card = pci_get_drvdata(pci);
2548 struct azx *chip = card->private_data;
2550 if (chip->init_failed)
2552 if (chip->disabled || !chip->bus)
2554 if (snd_hda_lock_devices(chip->bus))
2556 snd_hda_unlock_devices(chip->bus);
2560 static void __devinit init_vga_switcheroo(struct azx *chip)
2562 struct pci_dev *p = get_bound_vga(chip->pci);
2564 snd_printk(KERN_INFO SFX
2565 "%s: Handle VGA-switcheroo audio client\n",
2566 pci_name(chip->pci));
2567 chip->use_vga_switcheroo = 1;
2572 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2573 .set_gpu_state = azx_vs_set_state,
2574 .can_switch = azx_vs_can_switch,
2577 static int __devinit register_vga_switcheroo(struct azx *chip)
2579 if (!chip->use_vga_switcheroo)
2581 /* FIXME: currently only handling DIS controller
2582 * is there any machine with two switchable HDMI audio controllers?
2584 return vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2589 #define init_vga_switcheroo(chip) /* NOP */
2590 #define register_vga_switcheroo(chip) 0
2591 #define check_hdmi_disabled(pci) false
2592 #endif /* SUPPORT_VGA_SWITCHER */
2597 static int azx_free(struct azx *chip)
2601 azx_notifier_unregister(chip);
2603 if (use_vga_switcheroo(chip)) {
2604 if (chip->disabled && chip->bus)
2605 snd_hda_unlock_devices(chip->bus);
2606 vga_switcheroo_unregister_client(chip->pci);
2609 if (chip->initialized) {
2610 azx_clear_irq_pending(chip);
2611 for (i = 0; i < chip->num_streams; i++)
2612 azx_stream_stop(chip, &chip->azx_dev[i]);
2613 azx_stop_chip(chip);
2617 free_irq(chip->irq, (void*)chip);
2619 pci_disable_msi(chip->pci);
2620 if (chip->remap_addr)
2621 iounmap(chip->remap_addr);
2623 if (chip->azx_dev) {
2624 for (i = 0; i < chip->num_streams; i++)
2625 if (chip->azx_dev[i].bdl.area) {
2626 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2627 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2630 if (chip->rb.area) {
2631 mark_pages_wc(chip, &chip->rb, false);
2632 snd_dma_free_pages(&chip->rb);
2634 if (chip->posbuf.area) {
2635 mark_pages_wc(chip, &chip->posbuf, false);
2636 snd_dma_free_pages(&chip->posbuf);
2638 if (chip->region_requested)
2639 pci_release_regions(chip->pci);
2640 pci_disable_device(chip->pci);
2641 kfree(chip->azx_dev);
2647 static int azx_dev_free(struct snd_device *device)
2649 return azx_free(device->device_data);
2652 #ifdef SUPPORT_VGA_SWITCHEROO
2654 * Check of disabled HDMI controller by vga-switcheroo
2656 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2660 /* check only discrete GPU */
2661 switch (pci->vendor) {
2662 case PCI_VENDOR_ID_ATI:
2663 case PCI_VENDOR_ID_AMD:
2664 case PCI_VENDOR_ID_NVIDIA:
2665 if (pci->devfn == 1) {
2666 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2667 pci->bus->number, 0);
2669 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2679 static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2681 bool vga_inactive = false;
2682 struct pci_dev *p = get_bound_vga(pci);
2685 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2686 vga_inactive = true;
2689 return vga_inactive;
2691 #endif /* SUPPORT_VGA_SWITCHEROO */
2694 * white/black-listing for position_fix
2696 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2697 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2698 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2699 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2700 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2701 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2702 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2703 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2704 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2705 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2706 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2707 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2708 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2709 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2710 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2714 static int __devinit check_position_fix(struct azx *chip, int fix)
2716 const struct snd_pci_quirk *q;
2720 case POS_FIX_POSBUF:
2721 case POS_FIX_VIACOMBO:
2726 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2729 "hda_intel: position_fix set to %d "
2730 "for device %04x:%04x\n",
2731 q->value, q->subvendor, q->subdevice);
2735 /* Check VIA/ATI HD Audio Controller exist */
2736 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2737 snd_printd(SFX "Using VIACOMBO position fix\n");
2738 return POS_FIX_VIACOMBO;
2740 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2741 snd_printd(SFX "Using LPIB position fix\n");
2742 return POS_FIX_LPIB;
2744 if (chip->driver_caps & AZX_DCAPS_POSFIX_COMBO) {
2745 snd_printd(SFX "Using COMBO position fix\n");
2746 return POS_FIX_COMBO;
2748 return POS_FIX_AUTO;
2752 * black-lists for probe_mask
2754 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2755 /* Thinkpad often breaks the controller communication when accessing
2756 * to the non-working (or non-existing) modem codec slot.
2758 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2759 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2760 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2762 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2763 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2764 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2765 /* forced codec slots */
2766 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2767 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2768 /* WinFast VP200 H (Teradici) user reported broken communication */
2769 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
2773 #define AZX_FORCE_CODEC_MASK 0x100
2775 static void __devinit check_probe_mask(struct azx *chip, int dev)
2777 const struct snd_pci_quirk *q;
2779 chip->codec_probe_mask = probe_mask[dev];
2780 if (chip->codec_probe_mask == -1) {
2781 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2784 "hda_intel: probe_mask set to 0x%x "
2785 "for device %04x:%04x\n",
2786 q->value, q->subvendor, q->subdevice);
2787 chip->codec_probe_mask = q->value;
2791 /* check forced option */
2792 if (chip->codec_probe_mask != -1 &&
2793 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2794 chip->codec_mask = chip->codec_probe_mask & 0xff;
2795 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2801 * white/black-list for enable_msi
2803 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2804 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2805 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2806 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2807 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2808 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2812 static void __devinit check_msi(struct azx *chip)
2814 const struct snd_pci_quirk *q;
2816 if (enable_msi >= 0) {
2817 chip->msi = !!enable_msi;
2820 chip->msi = 1; /* enable MSI as default */
2821 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2824 "hda_intel: msi for device %04x:%04x set to %d\n",
2825 q->subvendor, q->subdevice, q->value);
2826 chip->msi = q->value;
2830 /* NVidia chipsets seem to cause troubles with MSI */
2831 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2832 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2837 /* check the snoop mode availability */
2838 static void __devinit azx_check_snoop_available(struct azx *chip)
2840 bool snoop = chip->snoop;
2842 switch (chip->driver_type) {
2843 case AZX_DRIVER_VIA:
2844 /* force to non-snoop mode for a new VIA controller
2849 pci_read_config_byte(chip->pci, 0x42, &val);
2850 if (!(val & 0x80) && chip->pci->revision == 0x30)
2854 case AZX_DRIVER_ATIHDMI_NS:
2855 /* new ATI HDMI requires non-snoop */
2860 if (snoop != chip->snoop) {
2861 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2862 snoop ? "snoop" : "non-snoop");
2863 chip->snoop = snoop;
2870 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2871 int dev, unsigned int driver_caps,
2874 static struct snd_device_ops ops = {
2875 .dev_free = azx_dev_free,
2882 err = pci_enable_device(pci);
2886 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2888 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2889 pci_disable_device(pci);
2893 spin_lock_init(&chip->reg_lock);
2894 mutex_init(&chip->open_mutex);
2898 chip->driver_caps = driver_caps;
2899 chip->driver_type = driver_caps & 0xff;
2901 chip->dev_index = dev;
2902 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2903 INIT_LIST_HEAD(&chip->pcm_list);
2904 init_vga_switcheroo(chip);
2906 chip->position_fix[0] = chip->position_fix[1] =
2907 check_position_fix(chip, position_fix[dev]);
2908 /* combo mode uses LPIB for playback */
2909 if (chip->position_fix[0] == POS_FIX_COMBO) {
2910 chip->position_fix[0] = POS_FIX_LPIB;
2911 chip->position_fix[1] = POS_FIX_AUTO;
2914 check_probe_mask(chip, dev);
2916 chip->single_cmd = single_cmd;
2917 chip->snoop = hda_snoop;
2918 azx_check_snoop_available(chip);
2920 if (bdl_pos_adj[dev] < 0) {
2921 switch (chip->driver_type) {
2922 case AZX_DRIVER_ICH:
2923 case AZX_DRIVER_PCH:
2924 bdl_pos_adj[dev] = 1;
2927 bdl_pos_adj[dev] = 32;
2932 if (check_hdmi_disabled(pci)) {
2933 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
2935 if (use_vga_switcheroo(chip)) {
2936 snd_printk(KERN_INFO SFX "Delaying initialization\n");
2937 chip->disabled = true;
2941 pci_disable_device(pci);
2945 err = azx_first_init(chip);
2952 err = register_vga_switcheroo(chip);
2954 snd_printk(KERN_ERR SFX
2955 "Error registering VGA-switcheroo client\n");
2960 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2962 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2971 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
2973 int dev = chip->dev_index;
2974 struct pci_dev *pci = chip->pci;
2975 struct snd_card *card = chip->card;
2977 unsigned short gcap;
2979 #if BITS_PER_LONG != 64
2980 /* Fix up base address on ULI M5461 */
2981 if (chip->driver_type == AZX_DRIVER_ULI) {
2983 pci_read_config_word(pci, 0x40, &tmp3);
2984 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2985 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2989 err = pci_request_regions(pci, "ICH HD audio");
2992 chip->region_requested = 1;
2994 chip->addr = pci_resource_start(pci, 0);
2995 chip->remap_addr = pci_ioremap_bar(pci, 0);
2996 if (chip->remap_addr == NULL) {
2997 snd_printk(KERN_ERR SFX "ioremap error\n");
3002 if (pci_enable_msi(pci) < 0)
3005 if (azx_acquire_irq(chip, 0) < 0)
3008 pci_set_master(pci);
3009 synchronize_irq(chip->irq);
3011 gcap = azx_readw(chip, GCAP);
3012 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
3014 /* disable SB600 64bit support for safety */
3015 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3016 struct pci_dev *p_smbus;
3017 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3018 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3021 if (p_smbus->revision < 0x30)
3022 gcap &= ~ICH6_GCAP_64OK;
3023 pci_dev_put(p_smbus);
3027 /* disable 64bit DMA address on some devices */
3028 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3029 snd_printd(SFX "Disabling 64bit DMA\n");
3030 gcap &= ~ICH6_GCAP_64OK;
3033 /* disable buffer size rounding to 128-byte multiples if supported */
3034 if (align_buffer_size >= 0)
3035 chip->align_buffer_size = !!align_buffer_size;
3037 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3038 chip->align_buffer_size = 0;
3039 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3040 chip->align_buffer_size = 1;
3042 chip->align_buffer_size = 1;
3045 /* allow 64bit DMA address if supported by H/W */
3046 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3047 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3049 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3050 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3053 /* read number of streams from GCAP register instead of using
3056 chip->capture_streams = (gcap >> 8) & 0x0f;
3057 chip->playback_streams = (gcap >> 12) & 0x0f;
3058 if (!chip->playback_streams && !chip->capture_streams) {
3059 /* gcap didn't give any info, switching to old method */
3061 switch (chip->driver_type) {
3062 case AZX_DRIVER_ULI:
3063 chip->playback_streams = ULI_NUM_PLAYBACK;
3064 chip->capture_streams = ULI_NUM_CAPTURE;
3066 case AZX_DRIVER_ATIHDMI:
3067 case AZX_DRIVER_ATIHDMI_NS:
3068 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3069 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3071 case AZX_DRIVER_GENERIC:
3073 chip->playback_streams = ICH6_NUM_PLAYBACK;
3074 chip->capture_streams = ICH6_NUM_CAPTURE;
3078 chip->capture_index_offset = 0;
3079 chip->playback_index_offset = chip->capture_streams;
3080 chip->num_streams = chip->playback_streams + chip->capture_streams;
3081 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3083 if (!chip->azx_dev) {
3084 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3088 for (i = 0; i < chip->num_streams; i++) {
3089 /* allocate memory for the BDL for each stream */
3090 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3091 snd_dma_pci_data(chip->pci),
3092 BDL_SIZE, &chip->azx_dev[i].bdl);
3094 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
3097 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3099 /* allocate memory for the position buffer */
3100 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3101 snd_dma_pci_data(chip->pci),
3102 chip->num_streams * 8, &chip->posbuf);
3104 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
3107 mark_pages_wc(chip, &chip->posbuf, true);
3108 /* allocate CORB/RIRB */
3109 err = azx_alloc_cmd_io(chip);
3113 /* initialize streams */
3114 azx_init_stream(chip);
3116 /* initialize chip */
3118 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3120 /* codec detection */
3121 if (!chip->codec_mask) {
3122 snd_printk(KERN_ERR SFX "no codecs found!\n");
3126 strcpy(card->driver, "HDA-Intel");
3127 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3128 sizeof(card->shortname));
3129 snprintf(card->longname, sizeof(card->longname),
3130 "%s at 0x%lx irq %i",
3131 card->shortname, chip->addr, chip->irq);
3136 static void power_down_all_codecs(struct azx *chip)
3138 #ifdef CONFIG_SND_HDA_POWER_SAVE
3139 /* The codecs were powered up in snd_hda_codec_new().
3140 * Now all initialization done, so turn them down if possible
3142 struct hda_codec *codec;
3143 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3144 snd_hda_power_down(codec);
3149 static int __devinit azx_probe(struct pci_dev *pci,
3150 const struct pci_device_id *pci_id)
3153 struct snd_card *card;
3157 if (dev >= SNDRV_CARDS)
3164 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3166 snd_printk(KERN_ERR SFX "Error creating card!\n");
3170 /* set this here since it's referred in snd_hda_load_patch() */
3171 snd_card_set_dev(card, &pci->dev);
3173 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3176 card->private_data = chip;
3178 if (!chip->disabled) {
3179 err = azx_probe_continue(chip);
3184 pci_set_drvdata(pci, card);
3190 snd_card_free(card);
3194 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3196 int dev = chip->dev_index;
3199 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3200 chip->beep_mode = beep_mode[dev];
3203 /* create codec instances */
3204 err = azx_codec_create(chip, model[dev]);
3207 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3208 if (patch[dev] && *patch[dev]) {
3209 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3211 err = snd_hda_load_patch(chip->bus, patch[dev]);
3216 if ((probe_only[dev] & 1) == 0) {
3217 err = azx_codec_configure(chip);
3222 /* create PCM streams */
3223 err = snd_hda_build_pcms(chip->bus);
3227 /* create mixer controls */
3228 err = azx_mixer_create(chip);
3232 err = snd_card_register(chip->card);
3237 power_down_all_codecs(chip);
3238 azx_notifier_register(chip);
3243 chip->init_failed = 1;
3247 static void __devexit azx_remove(struct pci_dev *pci)
3249 struct snd_card *card = pci_get_drvdata(pci);
3251 snd_card_free(card);
3252 pci_set_drvdata(pci, NULL);
3256 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3258 { PCI_DEVICE(0x8086, 0x1c20),
3259 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3260 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3262 { PCI_DEVICE(0x8086, 0x1d20),
3263 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3266 { PCI_DEVICE(0x8086, 0x1e20),
3267 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3268 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3270 { PCI_DEVICE(0x8086, 0x8c20),
3271 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3272 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3274 { PCI_DEVICE(0x8086, 0x0c0c),
3275 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3276 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3278 { PCI_DEVICE(0x8086, 0x811b),
3279 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3280 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3281 { PCI_DEVICE(0x8086, 0x080a),
3282 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3283 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3285 { PCI_DEVICE(0x8086, 0x2668),
3286 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3287 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3288 { PCI_DEVICE(0x8086, 0x27d8),
3289 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3290 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3291 { PCI_DEVICE(0x8086, 0x269a),
3292 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3293 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3294 { PCI_DEVICE(0x8086, 0x284b),
3295 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3296 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3297 { PCI_DEVICE(0x8086, 0x293e),
3298 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3299 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3300 { PCI_DEVICE(0x8086, 0x293f),
3301 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3302 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3303 { PCI_DEVICE(0x8086, 0x3a3e),
3304 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3305 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3306 { PCI_DEVICE(0x8086, 0x3a6e),
3307 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3308 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3310 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3311 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3312 .class_mask = 0xffffff,
3313 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3314 /* ATI SB 450/600/700/800/900 */
3315 { PCI_DEVICE(0x1002, 0x437b),
3316 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3317 { PCI_DEVICE(0x1002, 0x4383),
3318 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3320 { PCI_DEVICE(0x1022, 0x780d),
3321 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3323 { PCI_DEVICE(0x1002, 0x793b),
3324 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3325 { PCI_DEVICE(0x1002, 0x7919),
3326 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3327 { PCI_DEVICE(0x1002, 0x960f),
3328 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3329 { PCI_DEVICE(0x1002, 0x970f),
3330 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3331 { PCI_DEVICE(0x1002, 0xaa00),
3332 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3333 { PCI_DEVICE(0x1002, 0xaa08),
3334 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3335 { PCI_DEVICE(0x1002, 0xaa10),
3336 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3337 { PCI_DEVICE(0x1002, 0xaa18),
3338 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3339 { PCI_DEVICE(0x1002, 0xaa20),
3340 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3341 { PCI_DEVICE(0x1002, 0xaa28),
3342 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3343 { PCI_DEVICE(0x1002, 0xaa30),
3344 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3345 { PCI_DEVICE(0x1002, 0xaa38),
3346 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3347 { PCI_DEVICE(0x1002, 0xaa40),
3348 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3349 { PCI_DEVICE(0x1002, 0xaa48),
3350 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3351 { PCI_DEVICE(0x1002, 0x9902),
3352 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3353 { PCI_DEVICE(0x1002, 0xaaa0),
3354 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3355 { PCI_DEVICE(0x1002, 0xaaa8),
3356 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3357 { PCI_DEVICE(0x1002, 0xaab0),
3358 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3359 /* VIA VT8251/VT8237A */
3360 { PCI_DEVICE(0x1106, 0x3288),
3361 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3362 /* VIA GFX VT7122/VX900 */
3363 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3364 /* VIA GFX VT6122/VX11 */
3365 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3367 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3369 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3371 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3372 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3373 .class_mask = 0xffffff,
3374 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3376 { PCI_DEVICE(0x6549, 0x1200),
3377 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3378 /* Creative X-Fi (CA0110-IBG) */
3380 { PCI_DEVICE(0x1102, 0x0010),
3381 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3382 { PCI_DEVICE(0x1102, 0x0012),
3383 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3384 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3385 /* the following entry conflicts with snd-ctxfi driver,
3386 * as ctxfi driver mutates from HD-audio to native mode with
3387 * a special command sequence.
3389 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3390 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3391 .class_mask = 0xffffff,
3392 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3393 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3395 /* this entry seems still valid -- i.e. without emu20kx chip */
3396 { PCI_DEVICE(0x1102, 0x0009),
3397 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3398 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3401 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3402 /* VMware HDAudio */
3403 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3404 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3405 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3406 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3407 .class_mask = 0xffffff,
3408 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3409 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3410 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3411 .class_mask = 0xffffff,
3412 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3415 MODULE_DEVICE_TABLE(pci, azx_ids);
3417 /* pci_driver definition */
3418 static struct pci_driver azx_driver = {
3419 .name = KBUILD_MODNAME,
3420 .id_table = azx_ids,
3422 .remove = __devexit_p(azx_remove),
3428 module_pci_driver(azx_driver);