sound/pci/hda/hda_tegra.c

   1 /*
   2  *
   3  * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  *
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/clocksource.h>
  21 #include <linux/completion.h>
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mutex.h>
  31 #include <linux/of_device.h>
  32 #include <linux/slab.h>
  33 #include <linux/time.h>
  34
  35 #include <sound/core.h>
  36 #include <sound/initval.h>
  37
  38 #include "hda_codec.h"
  39 #include "hda_controller.h"
  40
  41 /* Defines for Nvidia Tegra HDA support */
  42 #define HDA_BAR0           0x8000
  43
  44 #define HDA_CFG_CMD        0x1004
  45 #define HDA_CFG_BAR0       0x1010
  46
  47 #define HDA_ENABLE_IO_SPACE       (1 << 0)
  48 #define HDA_ENABLE_MEM_SPACE      (1 << 1)
  49 #define HDA_ENABLE_BUS_MASTER     (1 << 2)
  50 #define HDA_ENABLE_SERR           (1 << 8)
  51 #define HDA_DISABLE_INTR          (1 << 10)
  52 #define HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
  53 #define HDA_BAR0_FINAL_PROGRAM    (1 << 14)
  54
  55 /* IPFS */
  56 #define HDA_IPFS_CONFIG           0x180
  57 #define HDA_IPFS_EN_FPCI          0x1
  58
  59 #define HDA_IPFS_FPCI_BAR0        0x80
  60 #define HDA_FPCI_BAR0_START       0x40
  61
  62 #define HDA_IPFS_INTR_MASK        0x188
  63 #define HDA_IPFS_EN_INTR          (1 << 16)
  64
  65 /* max number of SDs */
  66 #define NUM_CAPTURE_SD 1
  67 #define NUM_PLAYBACK_SD 1
  68
  69 struct hda_tegra {
  70         struct azx chip;
  71         struct device *dev;
  72         struct clk *hda_clk;
  73         struct clk *hda2codec_2x_clk;
  74         struct clk *hda2hdmi_clk;
  75         void __iomem *regs;
  76 };
  77
  78 #ifdef CONFIG_PM
  79 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
  80 module_param(power_save, bint, 0644);
  81 MODULE_PARM_DESC(power_save,
  82                  "Automatic power-saving timeout (in seconds, 0 = disable).");
  83 #else
  84 #define power_save      0
  85 #endif
  86
  87 /*
  88  * DMA page allocation ops.
  89  */
  90 static int dma_alloc_pages(struct hdac_bus *bus, int type, size_t size,
  91                            struct snd_dma_buffer *buf)
  92 {
  93         return snd_dma_alloc_pages(type, bus->dev, size, buf);
  94 }
  95
  96 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
  97 {
  98         snd_dma_free_pages(buf);
  99 }
 100
 101 static int substream_alloc_pages(struct azx *chip,
 102                                  struct snd_pcm_substream *substream,
 103                                  size_t size)
 104 {
 105         struct azx_dev *azx_dev = get_azx_dev(substream);
 106
 107         azx_dev->core.bufsize = 0;
 108         azx_dev->core.period_bytes = 0;
 109         azx_dev->core.format_val = 0;
 110         return snd_pcm_lib_malloc_pages(substream, size);
 111 }
 112
 113 static int substream_free_pages(struct azx *chip,
 114                                 struct snd_pcm_substream *substream)
 115 {
 116         return snd_pcm_lib_free_pages(substream);
 117 }
 118
 119 /*
 120  * Register access ops. Tegra HDA register access is DWORD only.
 121  */
 122 static void hda_tegra_writel(u32 value, u32 *addr)
 123 {
 124         writel(value, addr);
 125 }
 126
 127 static u32 hda_tegra_readl(u32 *addr)
 128 {
 129         return readl(addr);
 130 }
 131
 132 static void hda_tegra_writew(u16 value, u16 *addr)
 133 {
 134         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
 135         void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
 136         u32 v;
 137
 138         v = readl(dword_addr);
 139         v &= ~(0xffff << shift);
 140         v |= value << shift;
 141         writel(v, dword_addr);
 142 }
 143
 144 static u16 hda_tegra_readw(u16 *addr)
 145 {
 146         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
 147         void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
 148         u32 v;
 149
 150         v = readl(dword_addr);
 151         return (v >> shift) & 0xffff;
 152 }
 153
 154 static void hda_tegra_writeb(u8 value, u8 *addr)
 155 {
 156         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
 157         void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
 158         u32 v;
 159
 160         v = readl(dword_addr);
 161         v &= ~(0xff << shift);
 162         v |= value << shift;
 163         writel(v, dword_addr);
 164 }
 165
 166 static u8 hda_tegra_readb(u8 *addr)
 167 {
 168         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
 169         void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
 170         u32 v;
 171
 172         v = readl(dword_addr);
 173         return (v >> shift) & 0xff;
 174 }
 175
 176 static const struct hdac_io_ops hda_tegra_io_ops = {
 177         .reg_writel = hda_tegra_writel,
 178         .reg_readl = hda_tegra_readl,
 179         .reg_writew = hda_tegra_writew,
 180         .reg_readw = hda_tegra_readw,
 181         .reg_writeb = hda_tegra_writeb,
 182         .reg_readb = hda_tegra_readb,
 183         .dma_alloc_pages = dma_alloc_pages,
 184         .dma_free_pages = dma_free_pages,
 185 };
 186
 187 static const struct hda_controller_ops hda_tegra_ops = {
 188         .substream_alloc_pages = substream_alloc_pages,
 189         .substream_free_pages = substream_free_pages,
 190 };
 191
 192 static void hda_tegra_init(struct hda_tegra *hda)
 193 {
 194         u32 v;
 195
 196         /* Enable PCI access */
 197         v = readl(hda->regs + HDA_IPFS_CONFIG);
 198         v |= HDA_IPFS_EN_FPCI;
 199         writel(v, hda->regs + HDA_IPFS_CONFIG);
 200
 201         /* Enable MEM/IO space and bus master */
 202         v = readl(hda->regs + HDA_CFG_CMD);
 203         v &= ~HDA_DISABLE_INTR;
 204         v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
 205                 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
 206         writel(v, hda->regs + HDA_CFG_CMD);
 207
 208         writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
 209         writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
 210         writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
 211
 212         v = readl(hda->regs + HDA_IPFS_INTR_MASK);
 213         v |= HDA_IPFS_EN_INTR;
 214         writel(v, hda->regs + HDA_IPFS_INTR_MASK);
 215 }
 216
 217 static int hda_tegra_enable_clocks(struct hda_tegra *data)
 218 {
 219         int rc;
 220
 221         rc = clk_prepare_enable(data->hda_clk);
 222         if (rc)
 223                 return rc;
 224         rc = clk_prepare_enable(data->hda2codec_2x_clk);
 225         if (rc)
 226                 goto disable_hda;
 227         rc = clk_prepare_enable(data->hda2hdmi_clk);
 228         if (rc)
 229                 goto disable_codec_2x;
 230
 231         return 0;
 232
 233 disable_codec_2x:
 234         clk_disable_unprepare(data->hda2codec_2x_clk);
 235 disable_hda:
 236         clk_disable_unprepare(data->hda_clk);
 237         return rc;
 238 }
 239
 240 #ifdef CONFIG_PM_SLEEP
 241 static void hda_tegra_disable_clocks(struct hda_tegra *data)
 242 {
 243         clk_disable_unprepare(data->hda2hdmi_clk);
 244         clk_disable_unprepare(data->hda2codec_2x_clk);
 245         clk_disable_unprepare(data->hda_clk);
 246 }
 247
 248 /*
 249  * power management
 250  */
 251 static int hda_tegra_suspend(struct device *dev)
 252 {
 253         struct snd_card *card = dev_get_drvdata(dev);
 254         struct azx *chip = card->private_data;
 255         struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
 256
 257         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 258
 259         azx_stop_chip(chip);
 260         azx_enter_link_reset(chip);
 261         hda_tegra_disable_clocks(hda);
 262
 263         return 0;
 264 }
 265
 266 static int hda_tegra_resume(struct device *dev)
 267 {
 268         struct snd_card *card = dev_get_drvdata(dev);
 269         struct azx *chip = card->private_data;
 270         struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
 271
 272         hda_tegra_enable_clocks(hda);
 273
 274         hda_tegra_init(hda);
 275
 276         azx_init_chip(chip, 1);
 277
 278         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 279
 280         return 0;
 281 }
 282 #endif /* CONFIG_PM_SLEEP */
 283
 284 static const struct dev_pm_ops hda_tegra_pm = {
 285         SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
 286 };
 287
 288 static int hda_tegra_dev_disconnect(struct snd_device *device)
 289 {
 290         struct azx *chip = device->device_data;
 291
 292         chip->bus.shutdown = 1;
 293         return 0;
 294 }
 295
 296 /*
 297  * destructor
 298  */
 299 static int hda_tegra_dev_free(struct snd_device *device)
 300 {
 301         struct azx *chip = device->device_data;
 302
 303         if (azx_bus(chip)->chip_init) {
 304                 azx_stop_all_streams(chip);
 305                 azx_stop_chip(chip);
 306         }
 307
 308         azx_free_stream_pages(chip);
 309         azx_free_streams(chip);
 310         snd_hdac_bus_exit(bus);
 311
 312         return 0;
 313 }
 314
 315 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
 316 {
 317         struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
 318         struct hdac_bus *bus = azx_bus(chip);
 319         struct device *dev = hda->dev;
 320         struct resource *res;
 321         int err;
 322
 323         hda->hda_clk = devm_clk_get(dev, "hda");
 324         if (IS_ERR(hda->hda_clk))
 325                 return PTR_ERR(hda->hda_clk);
 326         hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
 327         if (IS_ERR(hda->hda2codec_2x_clk))
 328                 return PTR_ERR(hda->hda2codec_2x_clk);
 329         hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
 330         if (IS_ERR(hda->hda2hdmi_clk))
 331                 return PTR_ERR(hda->hda2hdmi_clk);
 332
 333         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 334         hda->regs = devm_ioremap_resource(dev, res);
 335         if (IS_ERR(hda->regs))
 336                 return PTR_ERR(hda->regs);
 337
 338         bus->remap_addr = hda->regs + HDA_BAR0;
 339         bus->addr = res->start + HDA_BAR0;
 340
 341         err = hda_tegra_enable_clocks(hda);
 342         if (err)
 343                 return err;
 344
 345         hda_tegra_init(hda);
 346
 347         return 0;
 348 }
 349
 350 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
 351 {
 352         struct hdac_bus *bus = azx_bus(chip);
 353         struct snd_card *card = chip->card;
 354         int err;
 355         unsigned short gcap;
 356         int irq_id = platform_get_irq(pdev, 0);
 357
 358         err = hda_tegra_init_chip(chip, pdev);
 359         if (err)
 360                 return err;
 361
 362         err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
 363                              IRQF_SHARED, KBUILD_MODNAME, chip);
 364         if (err) {
 365                 dev_err(chip->card->dev,
 366                         "unable to request IRQ %d, disabling device\n",
 367                         irq_id);
 368                 return err;
 369         }
 370         bus->irq = irq_id;
 371
 372         synchronize_irq(bus->irq);
 373
 374         gcap = azx_readw(chip, GCAP);
 375         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
 376
 377         /* read number of streams from GCAP register instead of using
 378          * hardcoded value
 379          */
 380         chip->capture_streams = (gcap >> 8) & 0x0f;
 381         chip->playback_streams = (gcap >> 12) & 0x0f;
 382         if (!chip->playback_streams && !chip->capture_streams) {
 383                 /* gcap didn't give any info, switching to old method */
 384                 chip->playback_streams = NUM_PLAYBACK_SD;
 385                 chip->capture_streams = NUM_CAPTURE_SD;
 386         }
 387         chip->capture_index_offset = 0;
 388         chip->playback_index_offset = chip->capture_streams;
 389         chip->num_streams = chip->playback_streams + chip->capture_streams;
 390
 391         /* initialize streams */
 392         err = azx_init_streams(chip);
 393         if (err < 0)
 394                 return err;
 395
 396         err = azx_alloc_stream_pages(chip);
 397         if (err < 0)
 398                 return err;
 399
 400         /* initialize chip */
 401         azx_init_chip(chip, 1);
 402
 403         /* codec detection */
 404         if (!bus->codec_mask) {
 405                 dev_err(card->dev, "no codecs found!\n");
 406                 return -ENODEV;
 407         }
 408
 409         strcpy(card->driver, "tegra-hda");
 410         strcpy(card->shortname, "tegra-hda");
 411         snprintf(card->longname, sizeof(card->longname),
 412                  "%s at 0x%lx irq %i",
 413                  card->shortname, bus->addr, bus->irq);
 414
 415         return 0;
 416 }
 417
 418 /*
 419  * constructor
 420  */
 421 static int hda_tegra_create(struct snd_card *card,
 422                             unsigned int driver_caps,
 423                             struct hda_tegra *hda)
 424 {
 425         static struct snd_device_ops ops = {
 426                 .dev_disconnect = hda_tegra_dev_disconnect,
 427                 .dev_free = hda_tegra_dev_free,
 428         };
 429         struct azx *chip;
 430         int err;
 431
 432         chip = &hda->chip;
 433
 434         mutex_init(&chip->open_mutex);
 435         chip->card = card;
 436         chip->ops = &hda_tegra_ops;
 437         chip->driver_caps = driver_caps;
 438         chip->driver_type = driver_caps & 0xff;
 439         chip->dev_index = 0;
 440         INIT_LIST_HEAD(&chip->pcm_list);
 441
 442         chip->codec_probe_mask = -1;
 443
 444         chip->single_cmd = false;
 445         chip->snoop = true;
 446
 447         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
 448         if (err < 0) {
 449                 dev_err(card->dev, "Error creating device\n");
 450                 return err;
 451         }
 452
 453         return 0;
 454 }
 455
 456 static const struct of_device_id hda_tegra_match[] = {
 457         { .compatible = "nvidia,tegra30-hda" },
 458         {},
 459 };
 460 MODULE_DEVICE_TABLE(of, hda_tegra_match);
 461
 462 static int hda_tegra_probe(struct platform_device *pdev)
 463 {
 464         struct snd_card *card;
 465         struct azx *chip;
 466         struct hda_tegra *hda;
 467         int err;
 468         const unsigned int driver_flags = AZX_DCAPS_RIRB_DELAY;
 469
 470         hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
 471         if (!hda)
 472                 return -ENOMEM;
 473         hda->dev = &pdev->dev;
 474         chip = &hda->chip;
 475
 476         err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
 477                            THIS_MODULE, 0, &card);
 478         if (err < 0) {
 479                 dev_err(&pdev->dev, "Error creating card!\n");
 480                 return err;
 481         }
 482
 483         err = azx_bus_init(chip, NULL, &hda_tegra_io_ops);
 484         if (err < 0)
 485                 goto out_free;
 486
 487         err = hda_tegra_create(card, driver_flags, hda);
 488         if (err < 0)
 489                 goto out_free;
 490         card->private_data = chip;
 491
 492         dev_set_drvdata(&pdev->dev, card);
 493
 494         err = hda_tegra_first_init(chip, pdev);
 495         if (err < 0)
 496                 goto out_free;
 497
 498         /* create codec instances */
 499         err = azx_probe_codecs(chip, 0);
 500         if (err < 0)
 501                 goto out_free;
 502
 503         err = azx_codec_configure(chip);
 504         if (err < 0)
 505                 goto out_free;
 506
 507         err = snd_card_register(chip->card);
 508         if (err < 0)
 509                 goto out_free;
 510
 511         chip->running = 1;
 512         snd_hda_set_power_save(&chip->bus, power_save * 1000);
 513
 514         return 0;
 515
 516 out_free:
 517         snd_card_free(card);
 518         return err;
 519 }
 520
 521 static int hda_tegra_remove(struct platform_device *pdev)
 522 {
 523         return snd_card_free(dev_get_drvdata(&pdev->dev));
 524 }
 525
 526 static void hda_tegra_shutdown(struct platform_device *pdev)
 527 {
 528         struct snd_card *card = dev_get_drvdata(&pdev->dev);
 529         struct azx *chip;
 530
 531         if (!card)
 532                 return;
 533         chip = card->private_data;
 534         if (chip && chip->running)
 535                 azx_stop_chip(chip);
 536 }
 537
 538 static struct platform_driver tegra_platform_hda = {
 539         .driver = {
 540                 .name = "tegra-hda",
 541                 .pm = &hda_tegra_pm,
 542                 .of_match_table = hda_tegra_match,
 543         },
 544         .probe = hda_tegra_probe,
 545         .remove = hda_tegra_remove,
 546         .shutdown = hda_tegra_shutdown,
 547 };
 548 module_platform_driver(tegra_platform_hda);
 549
 550 MODULE_DESCRIPTION("Tegra HDA bus driver");
 551 MODULE_LICENSE("GPL v2");