sound/pci/hda/patch_ca0132.c

   1 /*
   2  * HD audio interface patch for Creative CA0132 chip
   3  *
   4  * Copyright (c) 2011, Creative Technology Ltd.
   5  *
   6  * Based on patch_ca0110.c
   7  * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
   8  *
   9  *  This driver is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License as published by
  11  *  the Free Software Foundation; either version 2 of the License, or
  12  *  (at your option) any later version.
  13  *
  14  *  This driver is distributed in the hope that it will be useful,
  15  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *  GNU General Public License for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License
  20  *  along with this program; if not, write to the Free Software
  21  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/mutex.h>
  28 #include <linux/module.h>
  29 #include <linux/firmware.h>
  30 #include <sound/core.h>
  31 #include "hda_codec.h"
  32 #include "hda_local.h"
  33 #include "hda_auto_parser.h"
  34 #include "hda_jack.h"
  35
  36 #include "ca0132_regs.h"
  37
  38 /* Enable this to see controls for tuning purpose. */
  39 /*#define ENABLE_TUNING_CONTROLS*/
  40
  41 #define FLOAT_ZERO      0x00000000
  42 #define FLOAT_ONE       0x3f800000
  43 #define FLOAT_TWO       0x40000000
  44 #define FLOAT_MINUS_5   0xc0a00000
  45
  46 #define UNSOL_TAG_DSP   0x16
  47
  48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
  49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
  50
  51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS          8
  52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS      32
  53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS           2
  54
  55 #define MASTERCONTROL                           0x80
  56 #define MASTERCONTROL_ALLOC_DMA_CHAN            10
  57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS  60
  58
  59 #define WIDGET_CHIP_CTRL      0x15
  60 #define WIDGET_DSP_CTRL       0x16
  61
  62 #define MEM_CONNID_MICIN1     3
  63 #define MEM_CONNID_MICIN2     5
  64 #define MEM_CONNID_MICOUT1    12
  65 #define MEM_CONNID_MICOUT2    14
  66 #define MEM_CONNID_WUH        10
  67 #define MEM_CONNID_DSP        16
  68 #define MEM_CONNID_DMIC       100
  69
  70 #define SCP_SET    0
  71 #define SCP_GET    1
  72
  73 #define EFX_FILE   "ctefx.bin"
  74
  75 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
  76 MODULE_FIRMWARE(EFX_FILE);
  77 #endif
  78
  79 static char *dirstr[2] = { "Playback", "Capture" };
  80
  81 enum {
  82         SPEAKER_OUT,
  83         HEADPHONE_OUT
  84 };
  85
  86 enum {
  87         DIGITAL_MIC,
  88         LINE_MIC_IN
  89 };
  90
  91 enum {
  92 #define VNODE_START_NID    0x80
  93         VNID_SPK = VNODE_START_NID,                     /* Speaker vnid */
  94         VNID_MIC,
  95         VNID_HP_SEL,
  96         VNID_AMIC1_SEL,
  97         VNID_HP_ASEL,
  98         VNID_AMIC1_ASEL,
  99         VNODE_END_NID,
 100 #define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
 101
 102 #define EFFECT_START_NID    0x90
 103 #define OUT_EFFECT_START_NID    EFFECT_START_NID
 104         SURROUND = OUT_EFFECT_START_NID,
 105         CRYSTALIZER,
 106         DIALOG_PLUS,
 107         SMART_VOLUME,
 108         X_BASS,
 109         EQUALIZER,
 110         OUT_EFFECT_END_NID,
 111 #define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
 112
 113 #define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
 114         ECHO_CANCELLATION = IN_EFFECT_START_NID,
 115         VOICE_FOCUS,
 116         MIC_SVM,
 117         NOISE_REDUCTION,
 118         IN_EFFECT_END_NID,
 119 #define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
 120
 121         VOICEFX = IN_EFFECT_END_NID,
 122         PLAY_ENHANCEMENT,
 123         CRYSTAL_VOICE,
 124         EFFECT_END_NID
 125 #define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
 126 };
 127
 128 /* Effects values size*/
 129 #define EFFECT_VALS_MAX_COUNT 12
 130
 131 /* Latency introduced by DSP blocks in milliseconds. */
 132 #define DSP_CAPTURE_INIT_LATENCY        0
 133 #define DSP_CRYSTAL_VOICE_LATENCY       124
 134 #define DSP_PLAYBACK_INIT_LATENCY       13
 135 #define DSP_PLAY_ENHANCEMENT_LATENCY    30
 136 #define DSP_SPEAKER_OUT_LATENCY         7
 137
 138 struct ct_effect {
 139         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 140         hda_nid_t nid;
 141         int mid; /*effect module ID*/
 142         int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
 143         int direct; /* 0:output; 1:input*/
 144         int params; /* number of default non-on/off params */
 145         /*effect default values, 1st is on/off. */
 146         unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
 147 };
 148
 149 #define EFX_DIR_OUT 0
 150 #define EFX_DIR_IN  1
 151
 152 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
 153         { .name = "Surround",
 154           .nid = SURROUND,
 155           .mid = 0x96,
 156           .reqs = {0, 1},
 157           .direct = EFX_DIR_OUT,
 158           .params = 1,
 159           .def_vals = {0x3F800000, 0x3F2B851F}
 160         },
 161         { .name = "Crystalizer",
 162           .nid = CRYSTALIZER,
 163           .mid = 0x96,
 164           .reqs = {7, 8},
 165           .direct = EFX_DIR_OUT,
 166           .params = 1,
 167           .def_vals = {0x3F800000, 0x3F266666}
 168         },
 169         { .name = "Dialog Plus",
 170           .nid = DIALOG_PLUS,
 171           .mid = 0x96,
 172           .reqs = {2, 3},
 173           .direct = EFX_DIR_OUT,
 174           .params = 1,
 175           .def_vals = {0x00000000, 0x3F000000}
 176         },
 177         { .name = "Smart Volume",
 178           .nid = SMART_VOLUME,
 179           .mid = 0x96,
 180           .reqs = {4, 5, 6},
 181           .direct = EFX_DIR_OUT,
 182           .params = 2,
 183           .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
 184         },
 185         { .name = "X-Bass",
 186           .nid = X_BASS,
 187           .mid = 0x96,
 188           .reqs = {24, 23, 25},
 189           .direct = EFX_DIR_OUT,
 190           .params = 2,
 191           .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
 192         },
 193         { .name = "Equalizer",
 194           .nid = EQUALIZER,
 195           .mid = 0x96,
 196           .reqs = {9, 10, 11, 12, 13, 14,
 197                         15, 16, 17, 18, 19, 20},
 198           .direct = EFX_DIR_OUT,
 199           .params = 11,
 200           .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
 201                        0x00000000, 0x00000000, 0x00000000, 0x00000000,
 202                        0x00000000, 0x00000000, 0x00000000, 0x00000000}
 203         },
 204         { .name = "Echo Cancellation",
 205           .nid = ECHO_CANCELLATION,
 206           .mid = 0x95,
 207           .reqs = {0, 1, 2, 3},
 208           .direct = EFX_DIR_IN,
 209           .params = 3,
 210           .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
 211         },
 212         { .name = "Voice Focus",
 213           .nid = VOICE_FOCUS,
 214           .mid = 0x95,
 215           .reqs = {6, 7, 8, 9},
 216           .direct = EFX_DIR_IN,
 217           .params = 3,
 218           .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
 219         },
 220         { .name = "Mic SVM",
 221           .nid = MIC_SVM,
 222           .mid = 0x95,
 223           .reqs = {44, 45},
 224           .direct = EFX_DIR_IN,
 225           .params = 1,
 226           .def_vals = {0x00000000, 0x3F3D70A4}
 227         },
 228         { .name = "Noise Reduction",
 229           .nid = NOISE_REDUCTION,
 230           .mid = 0x95,
 231           .reqs = {4, 5},
 232           .direct = EFX_DIR_IN,
 233           .params = 1,
 234           .def_vals = {0x3F800000, 0x3F000000}
 235         },
 236         { .name = "VoiceFX",
 237           .nid = VOICEFX,
 238           .mid = 0x95,
 239           .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
 240           .direct = EFX_DIR_IN,
 241           .params = 8,
 242           .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
 243                        0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
 244                        0x00000000}
 245         }
 246 };
 247
 248 /* Tuning controls */
 249 #ifdef ENABLE_TUNING_CONTROLS
 250
 251 enum {
 252 #define TUNING_CTL_START_NID  0xC0
 253         WEDGE_ANGLE = TUNING_CTL_START_NID,
 254         SVM_LEVEL,
 255         EQUALIZER_BAND_0,
 256         EQUALIZER_BAND_1,
 257         EQUALIZER_BAND_2,
 258         EQUALIZER_BAND_3,
 259         EQUALIZER_BAND_4,
 260         EQUALIZER_BAND_5,
 261         EQUALIZER_BAND_6,
 262         EQUALIZER_BAND_7,
 263         EQUALIZER_BAND_8,
 264         EQUALIZER_BAND_9,
 265         TUNING_CTL_END_NID
 266 #define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
 267 };
 268
 269 struct ct_tuning_ctl {
 270         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 271         hda_nid_t parent_nid;
 272         hda_nid_t nid;
 273         int mid; /*effect module ID*/
 274         int req; /*effect module request*/
 275         int direct; /* 0:output; 1:input*/
 276         unsigned int def_val;/*effect default values*/
 277 };
 278
 279 static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
 280         { .name = "Wedge Angle",
 281           .parent_nid = VOICE_FOCUS,
 282           .nid = WEDGE_ANGLE,
 283           .mid = 0x95,
 284           .req = 8,
 285           .direct = EFX_DIR_IN,
 286           .def_val = 0x41F00000
 287         },
 288         { .name = "SVM Level",
 289           .parent_nid = MIC_SVM,
 290           .nid = SVM_LEVEL,
 291           .mid = 0x95,
 292           .req = 45,
 293           .direct = EFX_DIR_IN,
 294           .def_val = 0x3F3D70A4
 295         },
 296         { .name = "EQ Band0",
 297           .parent_nid = EQUALIZER,
 298           .nid = EQUALIZER_BAND_0,
 299           .mid = 0x96,
 300           .req = 11,
 301           .direct = EFX_DIR_OUT,
 302           .def_val = 0x00000000
 303         },
 304         { .name = "EQ Band1",
 305           .parent_nid = EQUALIZER,
 306           .nid = EQUALIZER_BAND_1,
 307           .mid = 0x96,
 308           .req = 12,
 309           .direct = EFX_DIR_OUT,
 310           .def_val = 0x00000000
 311         },
 312         { .name = "EQ Band2",
 313           .parent_nid = EQUALIZER,
 314           .nid = EQUALIZER_BAND_2,
 315           .mid = 0x96,
 316           .req = 13,
 317           .direct = EFX_DIR_OUT,
 318           .def_val = 0x00000000
 319         },
 320         { .name = "EQ Band3",
 321           .parent_nid = EQUALIZER,
 322           .nid = EQUALIZER_BAND_3,
 323           .mid = 0x96,
 324           .req = 14,
 325           .direct = EFX_DIR_OUT,
 326           .def_val = 0x00000000
 327         },
 328         { .name = "EQ Band4",
 329           .parent_nid = EQUALIZER,
 330           .nid = EQUALIZER_BAND_4,
 331           .mid = 0x96,
 332           .req = 15,
 333           .direct = EFX_DIR_OUT,
 334           .def_val = 0x00000000
 335         },
 336         { .name = "EQ Band5",
 337           .parent_nid = EQUALIZER,
 338           .nid = EQUALIZER_BAND_5,
 339           .mid = 0x96,
 340           .req = 16,
 341           .direct = EFX_DIR_OUT,
 342           .def_val = 0x00000000
 343         },
 344         { .name = "EQ Band6",
 345           .parent_nid = EQUALIZER,
 346           .nid = EQUALIZER_BAND_6,
 347           .mid = 0x96,
 348           .req = 17,
 349           .direct = EFX_DIR_OUT,
 350           .def_val = 0x00000000
 351         },
 352         { .name = "EQ Band7",
 353           .parent_nid = EQUALIZER,
 354           .nid = EQUALIZER_BAND_7,
 355           .mid = 0x96,
 356           .req = 18,
 357           .direct = EFX_DIR_OUT,
 358           .def_val = 0x00000000
 359         },
 360         { .name = "EQ Band8",
 361           .parent_nid = EQUALIZER,
 362           .nid = EQUALIZER_BAND_8,
 363           .mid = 0x96,
 364           .req = 19,
 365           .direct = EFX_DIR_OUT,
 366           .def_val = 0x00000000
 367         },
 368         { .name = "EQ Band9",
 369           .parent_nid = EQUALIZER,
 370           .nid = EQUALIZER_BAND_9,
 371           .mid = 0x96,
 372           .req = 20,
 373           .direct = EFX_DIR_OUT,
 374           .def_val = 0x00000000
 375         }
 376 };
 377 #endif
 378
 379 /* Voice FX Presets */
 380 #define VOICEFX_MAX_PARAM_COUNT 9
 381
 382 struct ct_voicefx {
 383         char *name;
 384         hda_nid_t nid;
 385         int mid;
 386         int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
 387 };
 388
 389 struct ct_voicefx_preset {
 390         char *name; /*preset name*/
 391         unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
 392 };
 393
 394 static struct ct_voicefx ca0132_voicefx = {
 395         .name = "VoiceFX Capture Switch",
 396         .nid = VOICEFX,
 397         .mid = 0x95,
 398         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
 399 };
 400
 401 static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
 402         { .name = "Neutral",
 403           .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
 404                     0x44FA0000, 0x3F800000, 0x3F800000,
 405                     0x3F800000, 0x00000000, 0x00000000 }
 406         },
 407         { .name = "Female2Male",
 408           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 409                     0x44FA0000, 0x3F19999A, 0x3F866666,
 410                     0x3F800000, 0x00000000, 0x00000000 }
 411         },
 412         { .name = "Male2Female",
 413           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 414                     0x450AC000, 0x4017AE14, 0x3F6B851F,
 415                     0x3F800000, 0x00000000, 0x00000000 }
 416         },
 417         { .name = "ScrappyKid",
 418           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 419                     0x44FA0000, 0x40400000, 0x3F28F5C3,
 420                     0x3F800000, 0x00000000, 0x00000000 }
 421         },
 422         { .name = "Elderly",
 423           .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
 424                     0x44E10000, 0x3FB33333, 0x3FB9999A,
 425                     0x3F800000, 0x3E3A2E43, 0x00000000 }
 426         },
 427         { .name = "Orc",
 428           .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
 429                     0x45098000, 0x3F266666, 0x3FC00000,
 430                     0x3F800000, 0x00000000, 0x00000000 }
 431         },
 432         { .name = "Elf",
 433           .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
 434                     0x45193000, 0x3F8E147B, 0x3F75C28F,
 435                     0x3F800000, 0x00000000, 0x00000000 }
 436         },
 437         { .name = "Dwarf",
 438           .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
 439                     0x45007000, 0x3F451EB8, 0x3F7851EC,
 440                     0x3F800000, 0x00000000, 0x00000000 }
 441         },
 442         { .name = "AlienBrute",
 443           .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
 444                     0x451F6000, 0x3F266666, 0x3FA7D945,
 445                     0x3F800000, 0x3CF5C28F, 0x00000000 }
 446         },
 447         { .name = "Robot",
 448           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 449                     0x44FA0000, 0x3FB2718B, 0x3F800000,
 450                     0xBC07010E, 0x00000000, 0x00000000 }
 451         },
 452         { .name = "Marine",
 453           .vals = { 0x3F800000, 0x43C20000, 0x44906000,
 454                     0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
 455                     0x3F0A3D71, 0x00000000, 0x00000000 }
 456         },
 457         { .name = "Emo",
 458           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 459                     0x44FA0000, 0x3F800000, 0x3F800000,
 460                     0x3E4CCCCD, 0x00000000, 0x00000000 }
 461         },
 462         { .name = "DeepVoice",
 463           .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
 464                     0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
 465                     0x3F800000, 0x00000000, 0x00000000 }
 466         },
 467         { .name = "Munchkin",
 468           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 469                     0x44FA0000, 0x3F800000, 0x3F1A043C,
 470                     0x3F800000, 0x00000000, 0x00000000 }
 471         }
 472 };
 473
 474 enum hda_cmd_vendor_io {
 475         /* for DspIO node */
 476         VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
 477         VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
 478
 479         VENDOR_DSPIO_STATUS                  = 0xF01,
 480         VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
 481         VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
 482         VENDOR_DSPIO_DSP_INIT                = 0x703,
 483         VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
 484         VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
 485
 486         /* for ChipIO node */
 487         VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
 488         VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
 489         VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
 490         VENDOR_CHIPIO_DATA_LOW               = 0x300,
 491         VENDOR_CHIPIO_DATA_HIGH              = 0x400,
 492
 493         VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
 494         VENDOR_CHIPIO_STATUS                 = 0xF01,
 495         VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
 496         VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
 497
 498         VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
 499         VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
 500
 501         VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
 502         VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
 503
 504         VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
 505         VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
 506         VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
 507         VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
 508         VENDOR_CHIPIO_FLAG_SET               = 0x70F,
 509         VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
 510         VENDOR_CHIPIO_PARAM_SET              = 0x710,
 511         VENDOR_CHIPIO_PARAM_GET              = 0xF10,
 512
 513         VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
 514         VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
 515         VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
 516         VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
 517
 518         VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
 519         VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
 520         VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
 521         VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
 522
 523         VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
 524         VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
 525         VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
 526         VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
 527         VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
 528         VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
 529
 530         VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
 531 };
 532
 533 /*
 534  *  Control flag IDs
 535  */
 536 enum control_flag_id {
 537         /* Connection manager stream setup is bypassed/enabled */
 538         CONTROL_FLAG_C_MGR                  = 0,
 539         /* DSP DMA is bypassed/enabled */
 540         CONTROL_FLAG_DMA                    = 1,
 541         /* 8051 'idle' mode is disabled/enabled */
 542         CONTROL_FLAG_IDLE_ENABLE            = 2,
 543         /* Tracker for the SPDIF-in path is bypassed/enabled */
 544         CONTROL_FLAG_TRACKER                = 3,
 545         /* DigitalOut to Spdif2Out connection is disabled/enabled */
 546         CONTROL_FLAG_SPDIF2OUT              = 4,
 547         /* Digital Microphone is disabled/enabled */
 548         CONTROL_FLAG_DMIC                   = 5,
 549         /* ADC_B rate is 48 kHz/96 kHz */
 550         CONTROL_FLAG_ADC_B_96KHZ            = 6,
 551         /* ADC_C rate is 48 kHz/96 kHz */
 552         CONTROL_FLAG_ADC_C_96KHZ            = 7,
 553         /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
 554         CONTROL_FLAG_DAC_96KHZ              = 8,
 555         /* DSP rate is 48 kHz/96 kHz */
 556         CONTROL_FLAG_DSP_96KHZ              = 9,
 557         /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
 558         CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
 559         /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
 560         CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
 561         /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
 562         CONTROL_FLAG_DECODE_LOOP            = 12,
 563         /* De-emphasis filter on DAC-1 disabled/enabled */
 564         CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
 565         /* De-emphasis filter on DAC-2 disabled/enabled */
 566         CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
 567         /* De-emphasis filter on DAC-3 disabled/enabled */
 568         CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
 569         /* High-pass filter on ADC_B disabled/enabled */
 570         CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
 571         /* High-pass filter on ADC_C disabled/enabled */
 572         CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
 573         /* Common mode on Port_A disabled/enabled */
 574         CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
 575         /* Common mode on Port_D disabled/enabled */
 576         CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
 577         /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
 578         CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
 579         /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
 580         CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
 581         /* ASI rate is 48kHz/96kHz */
 582         CONTROL_FLAG_ASI_96KHZ              = 22,
 583         /* DAC power settings able to control attached ports no/yes */
 584         CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
 585         /* Clock Stop OK reporting is disabled/enabled */
 586         CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
 587         /* Number of control flags */
 588         CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
 589 };
 590
 591 /*
 592  * Control parameter IDs
 593  */
 594 enum control_param_id {
 595         /* 0: None, 1: Mic1In*/
 596         CONTROL_PARAM_VIP_SOURCE               = 1,
 597         /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
 598         CONTROL_PARAM_SPDIF1_SOURCE            = 2,
 599         /* Port A output stage gain setting to use when 16 Ohm output
 600          * impedance is selected*/
 601         CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
 602         /* Port D output stage gain setting to use when 16 Ohm output
 603          * impedance is selected*/
 604         CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
 605
 606         /* Stream Control */
 607
 608         /* Select stream with the given ID */
 609         CONTROL_PARAM_STREAM_ID                = 24,
 610         /* Source connection point for the selected stream */
 611         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
 612         /* Destination connection point for the selected stream */
 613         CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
 614         /* Number of audio channels in the selected stream */
 615         CONTROL_PARAM_STREAMS_CHANNELS         = 27,
 616         /*Enable control for the selected stream */
 617         CONTROL_PARAM_STREAM_CONTROL           = 28,
 618
 619         /* Connection Point Control */
 620
 621         /* Select connection point with the given ID */
 622         CONTROL_PARAM_CONN_POINT_ID            = 29,
 623         /* Connection point sample rate */
 624         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
 625
 626         /* Node Control */
 627
 628         /* Select HDA node with the given ID */
 629         CONTROL_PARAM_NODE_ID                  = 31
 630 };
 631
 632 /*
 633  *  Dsp Io Status codes
 634  */
 635 enum hda_vendor_status_dspio {
 636         /* Success */
 637         VENDOR_STATUS_DSPIO_OK                       = 0x00,
 638         /* Busy, unable to accept new command, the host must retry */
 639         VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
 640         /* SCP command queue is full */
 641         VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
 642         /* SCP response queue is empty */
 643         VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
 644 };
 645
 646 /*
 647  *  Chip Io Status codes
 648  */
 649 enum hda_vendor_status_chipio {
 650         /* Success */
 651         VENDOR_STATUS_CHIPIO_OK   = 0x00,
 652         /* Busy, unable to accept new command, the host must retry */
 653         VENDOR_STATUS_CHIPIO_BUSY = 0x01
 654 };
 655
 656 /*
 657  *  CA0132 sample rate
 658  */
 659 enum ca0132_sample_rate {
 660         SR_6_000        = 0x00,
 661         SR_8_000        = 0x01,
 662         SR_9_600        = 0x02,
 663         SR_11_025       = 0x03,
 664         SR_16_000       = 0x04,
 665         SR_22_050       = 0x05,
 666         SR_24_000       = 0x06,
 667         SR_32_000       = 0x07,
 668         SR_44_100       = 0x08,
 669         SR_48_000       = 0x09,
 670         SR_88_200       = 0x0A,
 671         SR_96_000       = 0x0B,
 672         SR_144_000      = 0x0C,
 673         SR_176_400      = 0x0D,
 674         SR_192_000      = 0x0E,
 675         SR_384_000      = 0x0F,
 676
 677         SR_COUNT        = 0x10,
 678
 679         SR_RATE_UNKNOWN = 0x1F
 680 };
 681
 682 enum dsp_download_state {
 683         DSP_DOWNLOAD_FAILED = -1,
 684         DSP_DOWNLOAD_INIT   = 0,
 685         DSP_DOWNLOADING     = 1,
 686         DSP_DOWNLOADED      = 2
 687 };
 688
 689 /* retrieve parameters from hda format */
 690 #define get_hdafmt_chs(fmt)     (fmt & 0xf)
 691 #define get_hdafmt_bits(fmt)    ((fmt >> 4) & 0x7)
 692 #define get_hdafmt_rate(fmt)    ((fmt >> 8) & 0x7f)
 693 #define get_hdafmt_type(fmt)    ((fmt >> 15) & 0x1)
 694
 695 /*
 696  * CA0132 specific
 697  */
 698
 699 struct ca0132_spec {
 700         struct snd_kcontrol_new *mixers[5];
 701         unsigned int num_mixers;
 702         const struct hda_verb *base_init_verbs;
 703         const struct hda_verb *base_exit_verbs;
 704         const struct hda_verb *chip_init_verbs;
 705         struct hda_verb *spec_init_verbs;
 706         struct auto_pin_cfg autocfg;
 707
 708         /* Nodes configurations */
 709         struct hda_multi_out multiout;
 710         hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
 711         hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
 712         unsigned int num_outputs;
 713         hda_nid_t input_pins[AUTO_PIN_LAST];
 714         hda_nid_t adcs[AUTO_PIN_LAST];
 715         hda_nid_t dig_out;
 716         hda_nid_t dig_in;
 717         unsigned int num_inputs;
 718         hda_nid_t shared_mic_nid;
 719         hda_nid_t shared_out_nid;
 720         hda_nid_t unsol_tag_hp;
 721         hda_nid_t unsol_tag_amic1;
 722
 723         /* chip access */
 724         struct mutex chipio_mutex; /* chip access mutex */
 725         u32 curr_chip_addx;
 726
 727         /* DSP download related */
 728         enum dsp_download_state dsp_state;
 729         unsigned int dsp_stream_id;
 730         unsigned int wait_scp;
 731         unsigned int wait_scp_header;
 732         unsigned int wait_num_data;
 733         unsigned int scp_resp_header;
 734         unsigned int scp_resp_data[4];
 735         unsigned int scp_resp_count;
 736
 737         /* mixer and effects related */
 738         unsigned char dmic_ctl;
 739         int cur_out_type;
 740         int cur_mic_type;
 741         long vnode_lvol[VNODES_COUNT];
 742         long vnode_rvol[VNODES_COUNT];
 743         long vnode_lswitch[VNODES_COUNT];
 744         long vnode_rswitch[VNODES_COUNT];
 745         long effects_switch[EFFECTS_COUNT];
 746         long voicefx_val;
 747         long cur_mic_boost;
 748
 749         struct hda_codec *codec;
 750         struct delayed_work unsol_hp_work;
 751         int quirk;
 752
 753 #ifdef ENABLE_TUNING_CONTROLS
 754         long cur_ctl_vals[TUNING_CTLS_COUNT];
 755 #endif
 756 };
 757
 758 /*
 759  * CA0132 quirks table
 760  */
 761 enum {
 762         QUIRK_NONE,
 763         QUIRK_ALIENWARE,
 764 };
 765
 766 static const struct snd_pci_quirk ca0132_quirks[] = {
 767         SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15", QUIRK_ALIENWARE),
 768         {}
 769 };
 770
 771 /*
 772  * CA0132 codec access
 773  */
 774 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
 775                 unsigned int verb, unsigned int parm, unsigned int *res)
 776 {
 777         unsigned int response;
 778         response = snd_hda_codec_read(codec, nid, 0, verb, parm);
 779         *res = response;
 780
 781         return ((response == -1) ? -1 : 0);
 782 }
 783
 784 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
 785                 unsigned short converter_format, unsigned int *res)
 786 {
 787         return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
 788                                 converter_format & 0xffff, res);
 789 }
 790
 791 static int codec_set_converter_stream_channel(struct hda_codec *codec,
 792                                 hda_nid_t nid, unsigned char stream,
 793                                 unsigned char channel, unsigned int *res)
 794 {
 795         unsigned char converter_stream_channel = 0;
 796
 797         converter_stream_channel = (stream << 4) | (channel & 0x0f);
 798         return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
 799                                 converter_stream_channel, res);
 800 }
 801
 802 /* Chip access helper function */
 803 static int chipio_send(struct hda_codec *codec,
 804                        unsigned int reg,
 805                        unsigned int data)
 806 {
 807         unsigned int res;
 808         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 809
 810         /* send bits of data specified by reg */
 811         do {
 812                 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
 813                                          reg, data);
 814                 if (res == VENDOR_STATUS_CHIPIO_OK)
 815                         return 0;
 816                 msleep(20);
 817         } while (time_before(jiffies, timeout));
 818
 819         return -EIO;
 820 }
 821
 822 /*
 823  * Write chip address through the vendor widget -- NOT protected by the Mutex!
 824  */
 825 static int chipio_write_address(struct hda_codec *codec,
 826                                 unsigned int chip_addx)
 827 {
 828         struct ca0132_spec *spec = codec->spec;
 829         int res;
 830
 831         if (spec->curr_chip_addx == chip_addx)
 832                         return 0;
 833
 834         /* send low 16 bits of the address */
 835         res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
 836                           chip_addx & 0xffff);
 837
 838         if (res != -EIO) {
 839                 /* send high 16 bits of the address */
 840                 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
 841                                   chip_addx >> 16);
 842         }
 843
 844         spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
 845
 846         return res;
 847 }
 848
 849 /*
 850  * Write data through the vendor widget -- NOT protected by the Mutex!
 851  */
 852 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
 853 {
 854         struct ca0132_spec *spec = codec->spec;
 855         int res;
 856
 857         /* send low 16 bits of the data */
 858         res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
 859
 860         if (res != -EIO) {
 861                 /* send high 16 bits of the data */
 862                 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
 863                                   data >> 16);
 864         }
 865
 866         /*If no error encountered, automatically increment the address
 867         as per chip behaviour*/
 868         spec->curr_chip_addx = (res != -EIO) ?
 869                                         (spec->curr_chip_addx + 4) : ~0UL;
 870         return res;
 871 }
 872
 873 /*
 874  * Write multiple data through the vendor widget -- NOT protected by the Mutex!
 875  */
 876 static int chipio_write_data_multiple(struct hda_codec *codec,
 877                                       const u32 *data,
 878                                       unsigned int count)
 879 {
 880         int status = 0;
 881
 882         if (data == NULL) {
 883                 codec_dbg(codec, "chipio_write_data null ptr\n");
 884                 return -EINVAL;
 885         }
 886
 887         while ((count-- != 0) && (status == 0))
 888                 status = chipio_write_data(codec, *data++);
 889
 890         return status;
 891 }
 892
 893
 894 /*
 895  * Read data through the vendor widget -- NOT protected by the Mutex!
 896  */
 897 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
 898 {
 899         struct ca0132_spec *spec = codec->spec;
 900         int res;
 901
 902         /* post read */
 903         res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
 904
 905         if (res != -EIO) {
 906                 /* read status */
 907                 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
 908         }
 909
 910         if (res != -EIO) {
 911                 /* read data */
 912                 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
 913                                            VENDOR_CHIPIO_HIC_READ_DATA,
 914                                            0);
 915         }
 916
 917         /*If no error encountered, automatically increment the address
 918         as per chip behaviour*/
 919         spec->curr_chip_addx = (res != -EIO) ?
 920                                         (spec->curr_chip_addx + 4) : ~0UL;
 921         return res;
 922 }
 923
 924 /*
 925  * Write given value to the given address through the chip I/O widget.
 926  * protected by the Mutex
 927  */
 928 static int chipio_write(struct hda_codec *codec,
 929                 unsigned int chip_addx, const unsigned int data)
 930 {
 931         struct ca0132_spec *spec = codec->spec;
 932         int err;
 933
 934         mutex_lock(&spec->chipio_mutex);
 935
 936         /* write the address, and if successful proceed to write data */
 937         err = chipio_write_address(codec, chip_addx);
 938         if (err < 0)
 939                 goto exit;
 940
 941         err = chipio_write_data(codec, data);
 942         if (err < 0)
 943                 goto exit;
 944
 945 exit:
 946         mutex_unlock(&spec->chipio_mutex);
 947         return err;
 948 }
 949
 950 /*
 951  * Write multiple values to the given address through the chip I/O widget.
 952  * protected by the Mutex
 953  */
 954 static int chipio_write_multiple(struct hda_codec *codec,
 955                                  u32 chip_addx,
 956                                  const u32 *data,
 957                                  unsigned int count)
 958 {
 959         struct ca0132_spec *spec = codec->spec;
 960         int status;
 961
 962         mutex_lock(&spec->chipio_mutex);
 963         status = chipio_write_address(codec, chip_addx);
 964         if (status < 0)
 965                 goto error;
 966
 967         status = chipio_write_data_multiple(codec, data, count);
 968 error:
 969         mutex_unlock(&spec->chipio_mutex);
 970
 971         return status;
 972 }
 973
 974 /*
 975  * Read the given address through the chip I/O widget
 976  * protected by the Mutex
 977  */
 978 static int chipio_read(struct hda_codec *codec,
 979                 unsigned int chip_addx, unsigned int *data)
 980 {
 981         struct ca0132_spec *spec = codec->spec;
 982         int err;
 983
 984         mutex_lock(&spec->chipio_mutex);
 985
 986         /* write the address, and if successful proceed to write data */
 987         err = chipio_write_address(codec, chip_addx);
 988         if (err < 0)
 989                 goto exit;
 990
 991         err = chipio_read_data(codec, data);
 992         if (err < 0)
 993                 goto exit;
 994
 995 exit:
 996         mutex_unlock(&spec->chipio_mutex);
 997         return err;
 998 }
 999
1000 /*
1001  * Set chip control flags through the chip I/O widget.
1002  */
1003 static void chipio_set_control_flag(struct hda_codec *codec,
1004                                     enum control_flag_id flag_id,
1005                                     bool flag_state)
1006 {
1007         unsigned int val;
1008         unsigned int flag_bit;
1009
1010         flag_bit = (flag_state ? 1 : 0);
1011         val = (flag_bit << 7) | (flag_id);
1012         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1013                             VENDOR_CHIPIO_FLAG_SET, val);
1014 }
1015
1016 /*
1017  * Set chip parameters through the chip I/O widget.
1018  */
1019 static void chipio_set_control_param(struct hda_codec *codec,
1020                 enum control_param_id param_id, int param_val)
1021 {
1022         struct ca0132_spec *spec = codec->spec;
1023         int val;
1024
1025         if ((param_id < 32) && (param_val < 8)) {
1026                 val = (param_val << 5) | (param_id);
1027                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1028                                     VENDOR_CHIPIO_PARAM_SET, val);
1029         } else {
1030                 mutex_lock(&spec->chipio_mutex);
1031                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1032                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1033                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1034                                             param_id);
1035                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1036                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1037                                             param_val);
1038                 }
1039                 mutex_unlock(&spec->chipio_mutex);
1040         }
1041 }
1042
1043 /*
1044  * Set sampling rate of the connection point.
1045  */
1046 static void chipio_set_conn_rate(struct hda_codec *codec,
1047                                 int connid, enum ca0132_sample_rate rate)
1048 {
1049         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1050         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1051                                  rate);
1052 }
1053
1054 /*
1055  * Enable clocks.
1056  */
1057 static void chipio_enable_clocks(struct hda_codec *codec)
1058 {
1059         struct ca0132_spec *spec = codec->spec;
1060
1061         mutex_lock(&spec->chipio_mutex);
1062         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1063                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1064         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1065                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1066         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1067                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1068         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1069                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1070         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1071                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1072         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1073                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1074         mutex_unlock(&spec->chipio_mutex);
1075 }
1076
1077 /*
1078  * CA0132 DSP IO stuffs
1079  */
1080 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1081                       unsigned int data)
1082 {
1083         int res;
1084         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1085
1086         /* send bits of data specified by reg to dsp */
1087         do {
1088                 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1089                 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1090                         return res;
1091                 msleep(20);
1092         } while (time_before(jiffies, timeout));
1093
1094         return -EIO;
1095 }
1096
1097 /*
1098  * Wait for DSP to be ready for commands
1099  */
1100 static void dspio_write_wait(struct hda_codec *codec)
1101 {
1102         int status;
1103         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1104
1105         do {
1106                 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1107                                                 VENDOR_DSPIO_STATUS, 0);
1108                 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1109                     (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1110                         break;
1111                 msleep(1);
1112         } while (time_before(jiffies, timeout));
1113 }
1114
1115 /*
1116  * Write SCP data to DSP
1117  */
1118 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1119 {
1120         struct ca0132_spec *spec = codec->spec;
1121         int status;
1122
1123         dspio_write_wait(codec);
1124
1125         mutex_lock(&spec->chipio_mutex);
1126         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1127                             scp_data & 0xffff);
1128         if (status < 0)
1129                 goto error;
1130
1131         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1132                                     scp_data >> 16);
1133         if (status < 0)
1134                 goto error;
1135
1136         /* OK, now check if the write itself has executed*/
1137         status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1138                                     VENDOR_DSPIO_STATUS, 0);
1139 error:
1140         mutex_unlock(&spec->chipio_mutex);
1141
1142         return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1143                         -EIO : 0;
1144 }
1145
1146 /*
1147  * Write multiple SCP data to DSP
1148  */
1149 static int dspio_write_multiple(struct hda_codec *codec,
1150                                 unsigned int *buffer, unsigned int size)
1151 {
1152         int status = 0;
1153         unsigned int count;
1154
1155         if ((buffer == NULL))
1156                 return -EINVAL;
1157
1158         count = 0;
1159         while (count < size) {
1160                 status = dspio_write(codec, *buffer++);
1161                 if (status != 0)
1162                         break;
1163                 count++;
1164         }
1165
1166         return status;
1167 }
1168
1169 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1170 {
1171         int status;
1172
1173         status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1174         if (status == -EIO)
1175                 return status;
1176
1177         status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1178         if (status == -EIO ||
1179             status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1180                 return -EIO;
1181
1182         *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1183                                    VENDOR_DSPIO_SCP_READ_DATA, 0);
1184
1185         return 0;
1186 }
1187
1188 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1189                                unsigned int *buf_size, unsigned int size_count)
1190 {
1191         int status = 0;
1192         unsigned int size = *buf_size;
1193         unsigned int count;
1194         unsigned int skip_count;
1195         unsigned int dummy;
1196
1197         if ((buffer == NULL))
1198                 return -1;
1199
1200         count = 0;
1201         while (count < size && count < size_count) {
1202                 status = dspio_read(codec, buffer++);
1203                 if (status != 0)
1204                         break;
1205                 count++;
1206         }
1207
1208         skip_count = count;
1209         if (status == 0) {
1210                 while (skip_count < size) {
1211                         status = dspio_read(codec, &dummy);
1212                         if (status != 0)
1213                                 break;
1214                         skip_count++;
1215                 }
1216         }
1217         *buf_size = count;
1218
1219         return status;
1220 }
1221
1222 /*
1223  * Construct the SCP header using corresponding fields
1224  */
1225 static inline unsigned int
1226 make_scp_header(unsigned int target_id, unsigned int source_id,
1227                 unsigned int get_flag, unsigned int req,
1228                 unsigned int device_flag, unsigned int resp_flag,
1229                 unsigned int error_flag, unsigned int data_size)
1230 {
1231         unsigned int header = 0;
1232
1233         header = (data_size & 0x1f) << 27;
1234         header |= (error_flag & 0x01) << 26;
1235         header |= (resp_flag & 0x01) << 25;
1236         header |= (device_flag & 0x01) << 24;
1237         header |= (req & 0x7f) << 17;
1238         header |= (get_flag & 0x01) << 16;
1239         header |= (source_id & 0xff) << 8;
1240         header |= target_id & 0xff;
1241
1242         return header;
1243 }
1244
1245 /*
1246  * Extract corresponding fields from SCP header
1247  */
1248 static inline void
1249 extract_scp_header(unsigned int header,
1250                    unsigned int *target_id, unsigned int *source_id,
1251                    unsigned int *get_flag, unsigned int *req,
1252                    unsigned int *device_flag, unsigned int *resp_flag,
1253                    unsigned int *error_flag, unsigned int *data_size)
1254 {
1255         if (data_size)
1256                 *data_size = (header >> 27) & 0x1f;
1257         if (error_flag)
1258                 *error_flag = (header >> 26) & 0x01;
1259         if (resp_flag)
1260                 *resp_flag = (header >> 25) & 0x01;
1261         if (device_flag)
1262                 *device_flag = (header >> 24) & 0x01;
1263         if (req)
1264                 *req = (header >> 17) & 0x7f;
1265         if (get_flag)
1266                 *get_flag = (header >> 16) & 0x01;
1267         if (source_id)
1268                 *source_id = (header >> 8) & 0xff;
1269         if (target_id)
1270                 *target_id = header & 0xff;
1271 }
1272
1273 #define SCP_MAX_DATA_WORDS  (16)
1274
1275 /* Structure to contain any SCP message */
1276 struct scp_msg {
1277         unsigned int hdr;
1278         unsigned int data[SCP_MAX_DATA_WORDS];
1279 };
1280
1281 static void dspio_clear_response_queue(struct hda_codec *codec)
1282 {
1283         unsigned int dummy = 0;
1284         int status = -1;
1285
1286         /* clear all from the response queue */
1287         do {
1288                 status = dspio_read(codec, &dummy);
1289         } while (status == 0);
1290 }
1291
1292 static int dspio_get_response_data(struct hda_codec *codec)
1293 {
1294         struct ca0132_spec *spec = codec->spec;
1295         unsigned int data = 0;
1296         unsigned int count;
1297
1298         if (dspio_read(codec, &data) < 0)
1299                 return -EIO;
1300
1301         if ((data & 0x00ffffff) == spec->wait_scp_header) {
1302                 spec->scp_resp_header = data;
1303                 spec->scp_resp_count = data >> 27;
1304                 count = spec->wait_num_data;
1305                 dspio_read_multiple(codec, spec->scp_resp_data,
1306                                     &spec->scp_resp_count, count);
1307                 return 0;
1308         }
1309
1310         return -EIO;
1311 }
1312
1313 /*
1314  * Send SCP message to DSP
1315  */
1316 static int dspio_send_scp_message(struct hda_codec *codec,
1317                                   unsigned char *send_buf,
1318                                   unsigned int send_buf_size,
1319                                   unsigned char *return_buf,
1320                                   unsigned int return_buf_size,
1321                                   unsigned int *bytes_returned)
1322 {
1323         struct ca0132_spec *spec = codec->spec;
1324         int status = -1;
1325         unsigned int scp_send_size = 0;
1326         unsigned int total_size;
1327         bool waiting_for_resp = false;
1328         unsigned int header;
1329         struct scp_msg *ret_msg;
1330         unsigned int resp_src_id, resp_target_id;
1331         unsigned int data_size, src_id, target_id, get_flag, device_flag;
1332
1333         if (bytes_returned)
1334                 *bytes_returned = 0;
1335
1336         /* get scp header from buffer */
1337         header = *((unsigned int *)send_buf);
1338         extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1339                            &device_flag, NULL, NULL, &data_size);
1340         scp_send_size = data_size + 1;
1341         total_size = (scp_send_size * 4);
1342
1343         if (send_buf_size < total_size)
1344                 return -EINVAL;
1345
1346         if (get_flag || device_flag) {
1347                 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1348                         return -EINVAL;
1349
1350                 spec->wait_scp_header = *((unsigned int *)send_buf);
1351
1352                 /* swap source id with target id */
1353                 resp_target_id = src_id;
1354                 resp_src_id = target_id;
1355                 spec->wait_scp_header &= 0xffff0000;
1356                 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1357                 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1358                 spec->wait_scp = 1;
1359                 waiting_for_resp = true;
1360         }
1361
1362         status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1363                                       scp_send_size);
1364         if (status < 0) {
1365                 spec->wait_scp = 0;
1366                 return status;
1367         }
1368
1369         if (waiting_for_resp) {
1370                 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1371                 memset(return_buf, 0, return_buf_size);
1372                 do {
1373                         msleep(20);
1374                 } while (spec->wait_scp && time_before(jiffies, timeout));
1375                 waiting_for_resp = false;
1376                 if (!spec->wait_scp) {
1377                         ret_msg = (struct scp_msg *)return_buf;
1378                         memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1379                         memcpy(&ret_msg->data, spec->scp_resp_data,
1380                                spec->wait_num_data);
1381                         *bytes_returned = (spec->scp_resp_count + 1) * 4;
1382                         status = 0;
1383                 } else {
1384                         status = -EIO;
1385                 }
1386                 spec->wait_scp = 0;
1387         }
1388
1389         return status;
1390 }
1391
1392 /**
1393  * Prepare and send the SCP message to DSP
1394  * @codec: the HDA codec
1395  * @mod_id: ID of the DSP module to send the command
1396  * @req: ID of request to send to the DSP module
1397  * @dir: SET or GET
1398  * @data: pointer to the data to send with the request, request specific
1399  * @len: length of the data, in bytes
1400  * @reply: point to the buffer to hold data returned for a reply
1401  * @reply_len: length of the reply buffer returned from GET
1402  *
1403  * Returns zero or a negative error code.
1404  */
1405 static int dspio_scp(struct hda_codec *codec,
1406                 int mod_id, int req, int dir, void *data, unsigned int len,
1407                 void *reply, unsigned int *reply_len)
1408 {
1409         int status = 0;
1410         struct scp_msg scp_send, scp_reply;
1411         unsigned int ret_bytes, send_size, ret_size;
1412         unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1413         unsigned int reply_data_size;
1414
1415         memset(&scp_send, 0, sizeof(scp_send));
1416         memset(&scp_reply, 0, sizeof(scp_reply));
1417
1418         if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1419                 return -EINVAL;
1420
1421         if (dir == SCP_GET && reply == NULL) {
1422                 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1423                 return -EINVAL;
1424         }
1425
1426         if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1427                 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1428                 return -EINVAL;
1429         }
1430
1431         scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1432                                        0, 0, 0, len/sizeof(unsigned int));
1433         if (data != NULL && len > 0) {
1434                 len = min((unsigned int)(sizeof(scp_send.data)), len);
1435                 memcpy(scp_send.data, data, len);
1436         }
1437
1438         ret_bytes = 0;
1439         send_size = sizeof(unsigned int) + len;
1440         status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1441                                         send_size, (unsigned char *)&scp_reply,
1442                                         sizeof(scp_reply), &ret_bytes);
1443
1444         if (status < 0) {
1445                 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1446                 return status;
1447         }
1448
1449         /* extract send and reply headers members */
1450         extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1451                            NULL, NULL, NULL, NULL, NULL);
1452         extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1453                            &reply_resp_flag, &reply_error_flag,
1454                            &reply_data_size);
1455
1456         if (!send_get_flag)
1457                 return 0;
1458
1459         if (reply_resp_flag && !reply_error_flag) {
1460                 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1461                                         / sizeof(unsigned int);
1462
1463                 if (*reply_len < ret_size*sizeof(unsigned int)) {
1464                         codec_dbg(codec, "reply too long for buf\n");
1465                         return -EINVAL;
1466                 } else if (ret_size != reply_data_size) {
1467                         codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1468                         return -EINVAL;
1469                 } else {
1470                         *reply_len = ret_size*sizeof(unsigned int);
1471                         memcpy(reply, scp_reply.data, *reply_len);
1472                 }
1473         } else {
1474                 codec_dbg(codec, "reply ill-formed or errflag set\n");
1475                 return -EIO;
1476         }
1477
1478         return status;
1479 }
1480
1481 /*
1482  * Set DSP parameters
1483  */
1484 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1485                         int req, void *data, unsigned int len)
1486 {
1487         return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1488 }
1489
1490 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1491                         int req, unsigned int data)
1492 {
1493         return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1494 }
1495
1496 /*
1497  * Allocate a DSP DMA channel via an SCP message
1498  */
1499 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1500 {
1501         int status = 0;
1502         unsigned int size = sizeof(dma_chan);
1503
1504         codec_dbg(codec, "     dspio_alloc_dma_chan() -- begin\n");
1505         status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1506                         SCP_GET, NULL, 0, dma_chan, &size);
1507
1508         if (status < 0) {
1509                 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1510                 return status;
1511         }
1512
1513         if ((*dma_chan + 1) == 0) {
1514                 codec_dbg(codec, "no free dma channels to allocate\n");
1515                 return -EBUSY;
1516         }
1517
1518         codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1519         codec_dbg(codec, "     dspio_alloc_dma_chan() -- complete\n");
1520
1521         return status;
1522 }
1523
1524 /*
1525  * Free a DSP DMA via an SCP message
1526  */
1527 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1528 {
1529         int status = 0;
1530         unsigned int dummy = 0;
1531
1532         codec_dbg(codec, "     dspio_free_dma_chan() -- begin\n");
1533         codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1534
1535         status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1536                            SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1537
1538         if (status < 0) {
1539                 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1540                 return status;
1541         }
1542
1543         codec_dbg(codec, "     dspio_free_dma_chan() -- complete\n");
1544
1545         return status;
1546 }
1547
1548 /*
1549  * (Re)start the DSP
1550  */
1551 static int dsp_set_run_state(struct hda_codec *codec)
1552 {
1553         unsigned int dbg_ctrl_reg;
1554         unsigned int halt_state;
1555         int err;
1556
1557         err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1558         if (err < 0)
1559                 return err;
1560
1561         halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1562                       DSP_DBGCNTL_STATE_LOBIT;
1563
1564         if (halt_state != 0) {
1565                 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1566                                   DSP_DBGCNTL_SS_MASK);
1567                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1568                                    dbg_ctrl_reg);
1569                 if (err < 0)
1570                         return err;
1571
1572                 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1573                                 DSP_DBGCNTL_EXEC_MASK;
1574                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1575                                    dbg_ctrl_reg);
1576                 if (err < 0)
1577                         return err;
1578         }
1579
1580         return 0;
1581 }
1582
1583 /*
1584  * Reset the DSP
1585  */
1586 static int dsp_reset(struct hda_codec *codec)
1587 {
1588         unsigned int res;
1589         int retry = 20;
1590
1591         codec_dbg(codec, "dsp_reset\n");
1592         do {
1593                 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1594                 retry--;
1595         } while (res == -EIO && retry);
1596
1597         if (!retry) {
1598                 codec_dbg(codec, "dsp_reset timeout\n");
1599                 return -EIO;
1600         }
1601
1602         return 0;
1603 }
1604
1605 /*
1606  * Convert chip address to DSP address
1607  */
1608 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1609                                         bool *code, bool *yram)
1610 {
1611         *code = *yram = false;
1612
1613         if (UC_RANGE(chip_addx, 1)) {
1614                 *code = true;
1615                 return UC_OFF(chip_addx);
1616         } else if (X_RANGE_ALL(chip_addx, 1)) {
1617                 return X_OFF(chip_addx);
1618         } else if (Y_RANGE_ALL(chip_addx, 1)) {
1619                 *yram = true;
1620                 return Y_OFF(chip_addx);
1621         }
1622
1623         return INVALID_CHIP_ADDRESS;
1624 }
1625
1626 /*
1627  * Check if the DSP DMA is active
1628  */
1629 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1630 {
1631         unsigned int dma_chnlstart_reg;
1632
1633         chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1634
1635         return ((dma_chnlstart_reg & (1 <<
1636                         (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1637 }
1638
1639 static int dsp_dma_setup_common(struct hda_codec *codec,
1640                                 unsigned int chip_addx,
1641                                 unsigned int dma_chan,
1642                                 unsigned int port_map_mask,
1643                                 bool ovly)
1644 {
1645         int status = 0;
1646         unsigned int chnl_prop;
1647         unsigned int dsp_addx;
1648         unsigned int active;
1649         bool code, yram;
1650
1651         codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
1652
1653         if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1654                 codec_dbg(codec, "dma chan num invalid\n");
1655                 return -EINVAL;
1656         }
1657
1658         if (dsp_is_dma_active(codec, dma_chan)) {
1659                 codec_dbg(codec, "dma already active\n");
1660                 return -EBUSY;
1661         }
1662
1663         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1664
1665         if (dsp_addx == INVALID_CHIP_ADDRESS) {
1666                 codec_dbg(codec, "invalid chip addr\n");
1667                 return -ENXIO;
1668         }
1669
1670         chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1671         active = 0;
1672
1673         codec_dbg(codec, "   dsp_dma_setup_common()    start reg pgm\n");
1674
1675         if (ovly) {
1676                 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1677                                      &chnl_prop);
1678
1679                 if (status < 0) {
1680                         codec_dbg(codec, "read CHNLPROP Reg fail\n");
1681                         return status;
1682                 }
1683                 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
1684         }
1685
1686         if (!code)
1687                 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1688         else
1689                 chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1690
1691         chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1692
1693         status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1694         if (status < 0) {
1695                 codec_dbg(codec, "write CHNLPROP Reg fail\n");
1696                 return status;
1697         }
1698         codec_dbg(codec, "   dsp_dma_setup_common()    Write CHNLPROP\n");
1699
1700         if (ovly) {
1701                 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1702                                      &active);
1703
1704                 if (status < 0) {
1705                         codec_dbg(codec, "read ACTIVE Reg fail\n");
1706                         return status;
1707                 }
1708                 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
1709         }
1710
1711         active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1712                 DSPDMAC_ACTIVE_AAR_MASK;
1713
1714         status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1715         if (status < 0) {
1716                 codec_dbg(codec, "write ACTIVE Reg fail\n");
1717                 return status;
1718         }
1719
1720         codec_dbg(codec, "   dsp_dma_setup_common()    Write ACTIVE\n");
1721
1722         status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1723                               port_map_mask);
1724         if (status < 0) {
1725                 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
1726                 return status;
1727         }
1728         codec_dbg(codec, "   dsp_dma_setup_common()    Write AUDCHSEL\n");
1729
1730         status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1731                         DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1732         if (status < 0) {
1733                 codec_dbg(codec, "write IRQCNT Reg fail\n");
1734                 return status;
1735         }
1736         codec_dbg(codec, "   dsp_dma_setup_common()    Write IRQCNT\n");
1737
1738         codec_dbg(codec,
1739                    "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1740                    "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1741                    chip_addx, dsp_addx, dma_chan,
1742                    port_map_mask, chnl_prop, active);
1743
1744         codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
1745
1746         return 0;
1747 }
1748
1749 /*
1750  * Setup the DSP DMA per-transfer-specific registers
1751  */
1752 static int dsp_dma_setup(struct hda_codec *codec,
1753                         unsigned int chip_addx,
1754                         unsigned int count,
1755                         unsigned int dma_chan)
1756 {
1757         int status = 0;
1758         bool code, yram;
1759         unsigned int dsp_addx;
1760         unsigned int addr_field;
1761         unsigned int incr_field;
1762         unsigned int base_cnt;
1763         unsigned int cur_cnt;
1764         unsigned int dma_cfg = 0;
1765         unsigned int adr_ofs = 0;
1766         unsigned int xfr_cnt = 0;
1767         const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1768                                                 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1769
1770         codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
1771
1772         if (count > max_dma_count) {
1773                 codec_dbg(codec, "count too big\n");
1774                 return -EINVAL;
1775         }
1776
1777         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1778         if (dsp_addx == INVALID_CHIP_ADDRESS) {
1779                 codec_dbg(codec, "invalid chip addr\n");
1780                 return -ENXIO;
1781         }
1782
1783         codec_dbg(codec, "   dsp_dma_setup()    start reg pgm\n");
1784
1785         addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1786         incr_field   = 0;
1787
1788         if (!code) {
1789                 addr_field <<= 1;
1790                 if (yram)
1791                         addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1792
1793                 incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1794         }
1795
1796         dma_cfg = addr_field + incr_field;
1797         status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1798                                 dma_cfg);
1799         if (status < 0) {
1800                 codec_dbg(codec, "write DMACFG Reg fail\n");
1801                 return status;
1802         }
1803         codec_dbg(codec, "   dsp_dma_setup()    Write DMACFG\n");
1804
1805         adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1806                                                         (code ? 0 : 1));
1807
1808         status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1809                                 adr_ofs);
1810         if (status < 0) {
1811                 codec_dbg(codec, "write DSPADROFS Reg fail\n");
1812                 return status;
1813         }
1814         codec_dbg(codec, "   dsp_dma_setup()    Write DSPADROFS\n");
1815
1816         base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1817
1818         cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1819
1820         xfr_cnt = base_cnt | cur_cnt;
1821
1822         status = chipio_write(codec,
1823                                 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1824         if (status < 0) {
1825                 codec_dbg(codec, "write XFRCNT Reg fail\n");
1826                 return status;
1827         }
1828         codec_dbg(codec, "   dsp_dma_setup()    Write XFRCNT\n");
1829
1830         codec_dbg(codec,
1831                    "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1832                    "ADROFS=0x%x, XFRCNT=0x%x\n",
1833                    chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1834
1835         codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
1836
1837         return 0;
1838 }
1839
1840 /*
1841  * Start the DSP DMA
1842  */
1843 static int dsp_dma_start(struct hda_codec *codec,
1844                          unsigned int dma_chan, bool ovly)
1845 {
1846         unsigned int reg = 0;
1847         int status = 0;
1848
1849         codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
1850
1851         if (ovly) {
1852                 status = chipio_read(codec,
1853                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1854
1855                 if (status < 0) {
1856                         codec_dbg(codec, "read CHNLSTART reg fail\n");
1857                         return status;
1858                 }
1859                 codec_dbg(codec, "-- dsp_dma_start()    Read CHNLSTART\n");
1860
1861                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1862                                 DSPDMAC_CHNLSTART_DIS_MASK);
1863         }
1864
1865         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1866                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1867         if (status < 0) {
1868                 codec_dbg(codec, "write CHNLSTART reg fail\n");
1869                 return status;
1870         }
1871         codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
1872
1873         return status;
1874 }
1875
1876 /*
1877  * Stop the DSP DMA
1878  */
1879 static int dsp_dma_stop(struct hda_codec *codec,
1880                         unsigned int dma_chan, bool ovly)
1881 {
1882         unsigned int reg = 0;
1883         int status = 0;
1884
1885         codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
1886
1887         if (ovly) {
1888                 status = chipio_read(codec,
1889                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1890
1891                 if (status < 0) {
1892                         codec_dbg(codec, "read CHNLSTART reg fail\n");
1893                         return status;
1894                 }
1895                 codec_dbg(codec, "-- dsp_dma_stop()    Read CHNLSTART\n");
1896                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1897                                 DSPDMAC_CHNLSTART_DIS_MASK);
1898         }
1899
1900         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1901                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1902         if (status < 0) {
1903                 codec_dbg(codec, "write CHNLSTART reg fail\n");
1904                 return status;
1905         }
1906         codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
1907
1908         return status;
1909 }
1910
1911 /**
1912  * Allocate router ports
1913  *
1914  * @codec: the HDA codec
1915  * @num_chans: number of channels in the stream
1916  * @ports_per_channel: number of ports per channel
1917  * @start_device: start device
1918  * @port_map: pointer to the port list to hold the allocated ports
1919  *
1920  * Returns zero or a negative error code.
1921  */
1922 static int dsp_allocate_router_ports(struct hda_codec *codec,
1923                                      unsigned int num_chans,
1924                                      unsigned int ports_per_channel,
1925                                      unsigned int start_device,
1926                                      unsigned int *port_map)
1927 {
1928         int status = 0;
1929         int res;
1930         u8 val;
1931
1932         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1933         if (status < 0)
1934                 return status;
1935
1936         val = start_device << 6;
1937         val |= (ports_per_channel - 1) << 4;
1938         val |= num_chans - 1;
1939
1940         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1941                             VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1942                             val);
1943
1944         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1945                             VENDOR_CHIPIO_PORT_ALLOC_SET,
1946                             MEM_CONNID_DSP);
1947
1948         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1949         if (status < 0)
1950                 return status;
1951
1952         res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1953                                 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1954
1955         *port_map = res;
1956
1957         return (res < 0) ? res : 0;
1958 }
1959
1960 /*
1961  * Free router ports
1962  */
1963 static int dsp_free_router_ports(struct hda_codec *codec)
1964 {
1965         int status = 0;
1966
1967         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1968         if (status < 0)
1969                 return status;
1970
1971         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1972                             VENDOR_CHIPIO_PORT_FREE_SET,
1973                             MEM_CONNID_DSP);
1974
1975         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1976
1977         return status;
1978 }
1979
1980 /*
1981  * Allocate DSP ports for the download stream
1982  */
1983 static int dsp_allocate_ports(struct hda_codec *codec,
1984                         unsigned int num_chans,
1985                         unsigned int rate_multi, unsigned int *port_map)
1986 {
1987         int status;
1988
1989         codec_dbg(codec, "     dsp_allocate_ports() -- begin\n");
1990
1991         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1992                 codec_dbg(codec, "bad rate multiple\n");
1993                 return -EINVAL;
1994         }
1995
1996         status = dsp_allocate_router_ports(codec, num_chans,
1997                                            rate_multi, 0, port_map);
1998
1999         codec_dbg(codec, "     dsp_allocate_ports() -- complete\n");
2000
2001         return status;
2002 }
2003
2004 static int dsp_allocate_ports_format(struct hda_codec *codec,
2005                         const unsigned short fmt,
2006                         unsigned int *port_map)
2007 {
2008         int status;
2009         unsigned int num_chans;
2010
2011         unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2012         unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2013         unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2014
2015         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2016                 codec_dbg(codec, "bad rate multiple\n");
2017                 return -EINVAL;
2018         }
2019
2020         num_chans = get_hdafmt_chs(fmt) + 1;
2021
2022         status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2023
2024         return status;
2025 }
2026
2027 /*
2028  * free DSP ports
2029  */
2030 static int dsp_free_ports(struct hda_codec *codec)
2031 {
2032         int status;
2033
2034         codec_dbg(codec, "     dsp_free_ports() -- begin\n");
2035
2036         status = dsp_free_router_ports(codec);
2037         if (status < 0) {
2038                 codec_dbg(codec, "free router ports fail\n");
2039                 return status;
2040         }
2041         codec_dbg(codec, "     dsp_free_ports() -- complete\n");
2042
2043         return status;
2044 }
2045
2046 /*
2047  *  HDA DMA engine stuffs for DSP code download
2048  */
2049 struct dma_engine {
2050         struct hda_codec *codec;
2051         unsigned short m_converter_format;
2052         struct snd_dma_buffer *dmab;
2053         unsigned int buf_size;
2054 };
2055
2056
2057 enum dma_state {
2058         DMA_STATE_STOP  = 0,
2059         DMA_STATE_RUN   = 1
2060 };
2061
2062 static int dma_convert_to_hda_format(struct hda_codec *codec,
2063                 unsigned int sample_rate,
2064                 unsigned short channels,
2065                 unsigned short *hda_format)
2066 {
2067         unsigned int format_val;
2068
2069         format_val = snd_hdac_calc_stream_format(sample_rate,
2070                                 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2071
2072         if (hda_format)
2073                 *hda_format = (unsigned short)format_val;
2074
2075         return 0;
2076 }
2077
2078 /*
2079  *  Reset DMA for DSP download
2080  */
2081 static int dma_reset(struct dma_engine *dma)
2082 {
2083         struct hda_codec *codec = dma->codec;
2084         struct ca0132_spec *spec = codec->spec;
2085         int status;
2086
2087         if (dma->dmab->area)
2088                 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2089
2090         status = snd_hda_codec_load_dsp_prepare(codec,
2091                         dma->m_converter_format,
2092                         dma->buf_size,
2093                         dma->dmab);
2094         if (status < 0)
2095                 return status;
2096         spec->dsp_stream_id = status;
2097         return 0;
2098 }
2099
2100 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2101 {
2102         bool cmd;
2103
2104         switch (state) {
2105         case DMA_STATE_STOP:
2106                 cmd = false;
2107                 break;
2108         case DMA_STATE_RUN:
2109                 cmd = true;
2110                 break;
2111         default:
2112                 return 0;
2113         }
2114
2115         snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2116         return 0;
2117 }
2118
2119 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2120 {
2121         return dma->dmab->bytes;
2122 }
2123
2124 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2125 {
2126         return dma->dmab->area;
2127 }
2128
2129 static int dma_xfer(struct dma_engine *dma,
2130                 const unsigned int *data,
2131                 unsigned int count)
2132 {
2133         memcpy(dma->dmab->area, data, count);
2134         return 0;
2135 }
2136
2137 static void dma_get_converter_format(
2138                 struct dma_engine *dma,
2139                 unsigned short *format)
2140 {
2141         if (format)
2142                 *format = dma->m_converter_format;
2143 }
2144
2145 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2146 {
2147         struct ca0132_spec *spec = dma->codec->spec;
2148
2149         return spec->dsp_stream_id;
2150 }
2151
2152 struct dsp_image_seg {
2153         u32 magic;
2154         u32 chip_addr;
2155         u32 count;
2156         u32 data[0];
2157 };
2158
2159 static const u32 g_magic_value = 0x4c46584d;
2160 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2161
2162 static bool is_valid(const struct dsp_image_seg *p)
2163 {
2164         return p->magic == g_magic_value;
2165 }
2166
2167 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2168 {
2169         return g_chip_addr_magic_value == p->chip_addr;
2170 }
2171
2172 static bool is_last(const struct dsp_image_seg *p)
2173 {
2174         return p->count == 0;
2175 }
2176
2177 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2178 {
2179         return sizeof(*p) + p->count*sizeof(u32);
2180 }
2181
2182 static const struct dsp_image_seg *get_next_seg_ptr(
2183                                 const struct dsp_image_seg *p)
2184 {
2185         return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2186 }
2187
2188 /*
2189  * CA0132 chip DSP transfer stuffs.  For DSP download.
2190  */
2191 #define INVALID_DMA_CHANNEL (~0U)
2192
2193 /*
2194  * Program a list of address/data pairs via the ChipIO widget.
2195  * The segment data is in the format of successive pairs of words.
2196  * These are repeated as indicated by the segment's count field.
2197  */
2198 static int dspxfr_hci_write(struct hda_codec *codec,
2199                         const struct dsp_image_seg *fls)
2200 {
2201         int status;
2202         const u32 *data;
2203         unsigned int count;
2204
2205         if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2206                 codec_dbg(codec, "hci_write invalid params\n");
2207                 return -EINVAL;
2208         }
2209
2210         count = fls->count;
2211         data = (u32 *)(fls->data);
2212         while (count >= 2) {
2213                 status = chipio_write(codec, data[0], data[1]);
2214                 if (status < 0) {
2215                         codec_dbg(codec, "hci_write chipio failed\n");
2216                         return status;
2217                 }
2218                 count -= 2;
2219                 data  += 2;
2220         }
2221         return 0;
2222 }
2223
2224 /**
2225  * Write a block of data into DSP code or data RAM using pre-allocated
2226  * DMA engine.
2227  *
2228  * @codec: the HDA codec
2229  * @fls: pointer to a fast load image
2230  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2231  *         no relocation
2232  * @dma_engine: pointer to DMA engine to be used for DSP download
2233  * @dma_chan: The number of DMA channels used for DSP download
2234  * @port_map_mask: port mapping
2235  * @ovly: TRUE if overlay format is required
2236  *
2237  * Returns zero or a negative error code.
2238  */
2239 static int dspxfr_one_seg(struct hda_codec *codec,
2240                         const struct dsp_image_seg *fls,
2241                         unsigned int reloc,
2242                         struct dma_engine *dma_engine,
2243                         unsigned int dma_chan,
2244                         unsigned int port_map_mask,
2245                         bool ovly)
2246 {
2247         int status = 0;
2248         bool comm_dma_setup_done = false;
2249         const unsigned int *data;
2250         unsigned int chip_addx;
2251         unsigned int words_to_write;
2252         unsigned int buffer_size_words;
2253         unsigned char *buffer_addx;
2254         unsigned short hda_format;
2255         unsigned int sample_rate_div;
2256         unsigned int sample_rate_mul;
2257         unsigned int num_chans;
2258         unsigned int hda_frame_size_words;
2259         unsigned int remainder_words;
2260         const u32 *data_remainder;
2261         u32 chip_addx_remainder;
2262         unsigned int run_size_words;
2263         const struct dsp_image_seg *hci_write = NULL;
2264         unsigned long timeout;
2265         bool dma_active;
2266
2267         if (fls == NULL)
2268                 return -EINVAL;
2269         if (is_hci_prog_list_seg(fls)) {
2270                 hci_write = fls;
2271                 fls = get_next_seg_ptr(fls);
2272         }
2273
2274         if (hci_write && (!fls || is_last(fls))) {
2275                 codec_dbg(codec, "hci_write\n");
2276                 return dspxfr_hci_write(codec, hci_write);
2277         }
2278
2279         if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2280                 codec_dbg(codec, "Invalid Params\n");
2281                 return -EINVAL;
2282         }
2283
2284         data = fls->data;
2285         chip_addx = fls->chip_addr,
2286         words_to_write = fls->count;
2287
2288         if (!words_to_write)
2289                 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2290         if (reloc)
2291                 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2292
2293         if (!UC_RANGE(chip_addx, words_to_write) &&
2294             !X_RANGE_ALL(chip_addx, words_to_write) &&
2295             !Y_RANGE_ALL(chip_addx, words_to_write)) {
2296                 codec_dbg(codec, "Invalid chip_addx Params\n");
2297                 return -EINVAL;
2298         }
2299
2300         buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2301                                         sizeof(u32);
2302
2303         buffer_addx = dma_get_buffer_addr(dma_engine);
2304
2305         if (buffer_addx == NULL) {
2306                 codec_dbg(codec, "dma_engine buffer NULL\n");
2307                 return -EINVAL;
2308         }
2309
2310         dma_get_converter_format(dma_engine, &hda_format);
2311         sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2312         sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2313         num_chans = get_hdafmt_chs(hda_format) + 1;
2314
2315         hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2316                         (num_chans * sample_rate_mul / sample_rate_div));
2317
2318         if (hda_frame_size_words == 0) {
2319                 codec_dbg(codec, "frmsz zero\n");
2320                 return -EINVAL;
2321         }
2322
2323         buffer_size_words = min(buffer_size_words,
2324                                 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2325                                 65536 : 32768));
2326         buffer_size_words -= buffer_size_words % hda_frame_size_words;
2327         codec_dbg(codec,
2328                    "chpadr=0x%08x frmsz=%u nchan=%u "
2329                    "rate_mul=%u div=%u bufsz=%u\n",
2330                    chip_addx, hda_frame_size_words, num_chans,
2331                    sample_rate_mul, sample_rate_div, buffer_size_words);
2332
2333         if (buffer_size_words < hda_frame_size_words) {
2334                 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2335                 return -EINVAL;
2336         }
2337
2338         remainder_words = words_to_write % hda_frame_size_words;
2339         data_remainder = data;
2340         chip_addx_remainder = chip_addx;
2341
2342         data += remainder_words;
2343         chip_addx += remainder_words*sizeof(u32);
2344         words_to_write -= remainder_words;
2345
2346         while (words_to_write != 0) {
2347                 run_size_words = min(buffer_size_words, words_to_write);
2348                 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2349                             words_to_write, run_size_words, remainder_words);
2350                 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2351                 if (!comm_dma_setup_done) {
2352                         status = dsp_dma_stop(codec, dma_chan, ovly);
2353                         if (status < 0)
2354                                 return status;
2355                         status = dsp_dma_setup_common(codec, chip_addx,
2356                                                 dma_chan, port_map_mask, ovly);
2357                         if (status < 0)
2358                                 return status;
2359                         comm_dma_setup_done = true;
2360                 }
2361
2362                 status = dsp_dma_setup(codec, chip_addx,
2363                                                 run_size_words, dma_chan);
2364                 if (status < 0)
2365                         return status;
2366                 status = dsp_dma_start(codec, dma_chan, ovly);
2367                 if (status < 0)
2368                         return status;
2369                 if (!dsp_is_dma_active(codec, dma_chan)) {
2370                         codec_dbg(codec, "dspxfr:DMA did not start\n");
2371                         return -EIO;
2372                 }
2373                 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2374                 if (status < 0)
2375                         return status;
2376                 if (remainder_words != 0) {
2377                         status = chipio_write_multiple(codec,
2378                                                 chip_addx_remainder,
2379                                                 data_remainder,
2380                                                 remainder_words);
2381                         if (status < 0)
2382                                 return status;
2383                         remainder_words = 0;
2384                 }
2385                 if (hci_write) {
2386                         status = dspxfr_hci_write(codec, hci_write);
2387                         if (status < 0)
2388                                 return status;
2389                         hci_write = NULL;
2390                 }
2391
2392                 timeout = jiffies + msecs_to_jiffies(2000);
2393                 do {
2394                         dma_active = dsp_is_dma_active(codec, dma_chan);
2395                         if (!dma_active)
2396                                 break;
2397                         msleep(20);
2398                 } while (time_before(jiffies, timeout));
2399                 if (dma_active)
2400                         break;
2401
2402                 codec_dbg(codec, "+++++ DMA complete\n");
2403                 dma_set_state(dma_engine, DMA_STATE_STOP);
2404                 status = dma_reset(dma_engine);
2405
2406                 if (status < 0)
2407                         return status;
2408
2409                 data += run_size_words;
2410                 chip_addx += run_size_words*sizeof(u32);
2411                 words_to_write -= run_size_words;
2412         }
2413
2414         if (remainder_words != 0) {
2415                 status = chipio_write_multiple(codec, chip_addx_remainder,
2416                                         data_remainder, remainder_words);
2417         }
2418
2419         return status;
2420 }
2421
2422 /**
2423  * Write the entire DSP image of a DSP code/data overlay to DSP memories
2424  *
2425  * @codec: the HDA codec
2426  * @fls_data: pointer to a fast load image
2427  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2428  *         no relocation
2429  * @sample_rate: sampling rate of the stream used for DSP download
2430  * @channels: channels of the stream used for DSP download
2431  * @ovly: TRUE if overlay format is required
2432  *
2433  * Returns zero or a negative error code.
2434  */
2435 static int dspxfr_image(struct hda_codec *codec,
2436                         const struct dsp_image_seg *fls_data,
2437                         unsigned int reloc,
2438                         unsigned int sample_rate,
2439                         unsigned short channels,
2440                         bool ovly)
2441 {
2442         struct ca0132_spec *spec = codec->spec;
2443         int status;
2444         unsigned short hda_format = 0;
2445         unsigned int response;
2446         unsigned char stream_id = 0;
2447         struct dma_engine *dma_engine;
2448         unsigned int dma_chan;
2449         unsigned int port_map_mask;
2450
2451         if (fls_data == NULL)
2452                 return -EINVAL;
2453
2454         dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2455         if (!dma_engine)
2456                 return -ENOMEM;
2457
2458         dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2459         if (!dma_engine->dmab) {
2460                 kfree(dma_engine);
2461                 return -ENOMEM;
2462         }
2463
2464         dma_engine->codec = codec;
2465         dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2466         dma_engine->m_converter_format = hda_format;
2467         dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2468                         DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2469
2470         dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2471
2472         status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2473                                         hda_format, &response);
2474
2475         if (status < 0) {
2476                 codec_dbg(codec, "set converter format fail\n");
2477                 goto exit;
2478         }
2479
2480         status = snd_hda_codec_load_dsp_prepare(codec,
2481                                 dma_engine->m_converter_format,
2482                                 dma_engine->buf_size,
2483                                 dma_engine->dmab);
2484         if (status < 0)
2485                 goto exit;
2486         spec->dsp_stream_id = status;
2487
2488         if (ovly) {
2489                 status = dspio_alloc_dma_chan(codec, &dma_chan);
2490                 if (status < 0) {
2491                         codec_dbg(codec, "alloc dmachan fail\n");
2492                         dma_chan = INVALID_DMA_CHANNEL;
2493                         goto exit;
2494                 }
2495         }
2496
2497         port_map_mask = 0;
2498         status = dsp_allocate_ports_format(codec, hda_format,
2499                                         &port_map_mask);
2500         if (status < 0) {
2501                 codec_dbg(codec, "alloc ports fail\n");
2502                 goto exit;
2503         }
2504
2505         stream_id = dma_get_stream_id(dma_engine);
2506         status = codec_set_converter_stream_channel(codec,
2507                         WIDGET_CHIP_CTRL, stream_id, 0, &response);
2508         if (status < 0) {
2509                 codec_dbg(codec, "set stream chan fail\n");
2510                 goto exit;
2511         }
2512
2513         while ((fls_data != NULL) && !is_last(fls_data)) {
2514                 if (!is_valid(fls_data)) {
2515                         codec_dbg(codec, "FLS check fail\n");
2516                         status = -EINVAL;
2517                         goto exit;
2518                 }
2519                 status = dspxfr_one_seg(codec, fls_data, reloc,
2520                                         dma_engine, dma_chan,
2521                                         port_map_mask, ovly);
2522                 if (status < 0)
2523                         break;
2524
2525                 if (is_hci_prog_list_seg(fls_data))
2526                         fls_data = get_next_seg_ptr(fls_data);
2527
2528                 if ((fls_data != NULL) && !is_last(fls_data))
2529                         fls_data = get_next_seg_ptr(fls_data);
2530         }
2531
2532         if (port_map_mask != 0)
2533                 status = dsp_free_ports(codec);
2534
2535         if (status < 0)
2536                 goto exit;
2537
2538         status = codec_set_converter_stream_channel(codec,
2539                                 WIDGET_CHIP_CTRL, 0, 0, &response);
2540
2541 exit:
2542         if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2543                 dspio_free_dma_chan(codec, dma_chan);
2544
2545         if (dma_engine->dmab->area)
2546                 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2547         kfree(dma_engine->dmab);
2548         kfree(dma_engine);
2549
2550         return status;
2551 }
2552
2553 /*
2554  * CA0132 DSP download stuffs.
2555  */
2556 static void dspload_post_setup(struct hda_codec *codec)
2557 {
2558         codec_dbg(codec, "---- dspload_post_setup ------\n");
2559
2560         /*set DSP speaker to 2.0 configuration*/
2561         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2562         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2563
2564         /*update write pointer*/
2565         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2566 }
2567
2568 /**
2569  * dspload_image - Download DSP from a DSP Image Fast Load structure.
2570  *
2571  * @codec: the HDA codec
2572  * @fls: pointer to a fast load image
2573  * @ovly: TRUE if overlay format is required
2574  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2575  *         no relocation
2576  * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2577  * @router_chans: number of audio router channels to be allocated (0 means use
2578  *                internal defaults; max is 32)
2579  *
2580  * Download DSP from a DSP Image Fast Load structure. This structure is a
2581  * linear, non-constant sized element array of structures, each of which
2582  * contain the count of the data to be loaded, the data itself, and the
2583  * corresponding starting chip address of the starting data location.
2584  * Returns zero or a negative error code.
2585  */
2586 static int dspload_image(struct hda_codec *codec,
2587                         const struct dsp_image_seg *fls,
2588                         bool ovly,
2589                         unsigned int reloc,
2590                         bool autostart,
2591                         int router_chans)
2592 {
2593         int status = 0;
2594         unsigned int sample_rate;
2595         unsigned short channels;
2596
2597         codec_dbg(codec, "---- dspload_image begin ------\n");
2598         if (router_chans == 0) {
2599                 if (!ovly)
2600                         router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2601                 else
2602                         router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2603         }
2604
2605         sample_rate = 48000;
2606         channels = (unsigned short)router_chans;
2607
2608         while (channels > 16) {
2609                 sample_rate *= 2;
2610                 channels /= 2;
2611         }
2612
2613         do {
2614                 codec_dbg(codec, "Ready to program DMA\n");
2615                 if (!ovly)
2616                         status = dsp_reset(codec);
2617
2618                 if (status < 0)
2619                         break;
2620
2621                 codec_dbg(codec, "dsp_reset() complete\n");
2622                 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2623                                       ovly);
2624
2625                 if (status < 0)
2626                         break;
2627
2628                 codec_dbg(codec, "dspxfr_image() complete\n");
2629                 if (autostart && !ovly) {
2630                         dspload_post_setup(codec);
2631                         status = dsp_set_run_state(codec);
2632                 }
2633
2634                 codec_dbg(codec, "LOAD FINISHED\n");
2635         } while (0);
2636
2637         return status;
2638 }
2639
2640 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
2641 static bool dspload_is_loaded(struct hda_codec *codec)
2642 {
2643         unsigned int data = 0;
2644         int status = 0;
2645
2646         status = chipio_read(codec, 0x40004, &data);
2647         if ((status < 0) || (data != 1))
2648                 return false;
2649
2650         return true;
2651 }
2652 #else
2653 #define dspload_is_loaded(codec)        false
2654 #endif
2655
2656 static bool dspload_wait_loaded(struct hda_codec *codec)
2657 {
2658         unsigned long timeout = jiffies + msecs_to_jiffies(2000);
2659
2660         do {
2661                 if (dspload_is_loaded(codec)) {
2662                         pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n");
2663                         return true;
2664                 }
2665                 msleep(20);
2666         } while (time_before(jiffies, timeout));
2667
2668         pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2669         return false;
2670 }
2671
2672 /*
2673  * PCM callbacks
2674  */
2675 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2676                         struct hda_codec *codec,
2677                         unsigned int stream_tag,
2678                         unsigned int format,
2679                         struct snd_pcm_substream *substream)
2680 {
2681         struct ca0132_spec *spec = codec->spec;
2682
2683         snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2684
2685         return 0;
2686 }
2687
2688 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2689                         struct hda_codec *codec,
2690                         struct snd_pcm_substream *substream)
2691 {
2692         struct ca0132_spec *spec = codec->spec;
2693
2694         if (spec->dsp_state == DSP_DOWNLOADING)
2695                 return 0;
2696
2697         /*If Playback effects are on, allow stream some time to flush
2698          *effects tail*/
2699         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2700                 msleep(50);
2701
2702         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
2703
2704         return 0;
2705 }
2706
2707 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2708                         struct hda_codec *codec,
2709                         struct snd_pcm_substream *substream)
2710 {
2711         struct ca0132_spec *spec = codec->spec;
2712         unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2713         struct snd_pcm_runtime *runtime = substream->runtime;
2714
2715         if (spec->dsp_state != DSP_DOWNLOADED)
2716                 return 0;
2717
2718         /* Add latency if playback enhancement and either effect is enabled. */
2719         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2720                 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2721                     (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2722                         latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2723         }
2724
2725         /* Applying Speaker EQ adds latency as well. */
2726         if (spec->cur_out_type == SPEAKER_OUT)
2727                 latency += DSP_SPEAKER_OUT_LATENCY;
2728
2729         return (latency * runtime->rate) / 1000;
2730 }
2731
2732 /*
2733  * Digital out
2734  */
2735 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2736                                         struct hda_codec *codec,
2737                                         struct snd_pcm_substream *substream)
2738 {
2739         struct ca0132_spec *spec = codec->spec;
2740         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2741 }
2742
2743 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2744                         struct hda_codec *codec,
2745                         unsigned int stream_tag,
2746                         unsigned int format,
2747                         struct snd_pcm_substream *substream)
2748 {
2749         struct ca0132_spec *spec = codec->spec;
2750         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2751                                              stream_tag, format, substream);
2752 }
2753
2754 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2755                         struct hda_codec *codec,
2756                         struct snd_pcm_substream *substream)
2757 {
2758         struct ca0132_spec *spec = codec->spec;
2759         return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
2760 }
2761
2762 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2763                                          struct hda_codec *codec,
2764                                          struct snd_pcm_substream *substream)
2765 {
2766         struct ca0132_spec *spec = codec->spec;
2767         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2768 }
2769
2770 /*
2771  * Analog capture
2772  */
2773 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2774                                         struct hda_codec *codec,
2775                                         unsigned int stream_tag,
2776                                         unsigned int format,
2777                                         struct snd_pcm_substream *substream)
2778 {
2779         snd_hda_codec_setup_stream(codec, hinfo->nid,
2780                                    stream_tag, 0, format);
2781
2782         return 0;
2783 }
2784
2785 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2786                         struct hda_codec *codec,
2787                         struct snd_pcm_substream *substream)
2788 {
2789         struct ca0132_spec *spec = codec->spec;
2790
2791         if (spec->dsp_state == DSP_DOWNLOADING)
2792                 return 0;
2793
2794         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2795         return 0;
2796 }
2797
2798 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2799                         struct hda_codec *codec,
2800                         struct snd_pcm_substream *substream)
2801 {
2802         struct ca0132_spec *spec = codec->spec;
2803         unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2804         struct snd_pcm_runtime *runtime = substream->runtime;
2805
2806         if (spec->dsp_state != DSP_DOWNLOADED)
2807                 return 0;
2808
2809         if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2810                 latency += DSP_CRYSTAL_VOICE_LATENCY;
2811
2812         return (latency * runtime->rate) / 1000;
2813 }
2814
2815 /*
2816  * Controls stuffs.
2817  */
2818
2819 /*
2820  * Mixer controls helpers.
2821  */
2822 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2823         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2824           .name = xname, \
2825           .subdevice = HDA_SUBDEV_AMP_FLAG, \
2826           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2827                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2828                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2829           .info = ca0132_volume_info, \
2830           .get = ca0132_volume_get, \
2831           .put = ca0132_volume_put, \
2832           .tlv = { .c = ca0132_volume_tlv }, \
2833           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2834
2835 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2836         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2837           .name = xname, \
2838           .subdevice = HDA_SUBDEV_AMP_FLAG, \
2839           .info = snd_hda_mixer_amp_switch_info, \
2840           .get = ca0132_switch_get, \
2841           .put = ca0132_switch_put, \
2842           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2843
2844 /* stereo */
2845 #define CA0132_CODEC_VOL(xname, nid, dir) \
2846         CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2847 #define CA0132_CODEC_MUTE(xname, nid, dir) \
2848         CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2849
2850 /* The followings are for tuning of products */
2851 #ifdef ENABLE_TUNING_CONTROLS
2852
2853 static unsigned int voice_focus_vals_lookup[] = {
2854 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
2855 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
2856 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
2857 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
2858 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
2859 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
2860 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
2861 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
2862 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
2863 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
2864 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
2865 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
2866 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
2867 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
2868 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
2869 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
2870 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
2871 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
2872 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
2873 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
2874 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
2875 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
2876 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
2877 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
2878 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
2879 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
2880 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2881 };
2882
2883 static unsigned int mic_svm_vals_lookup[] = {
2884 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
2885 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
2886 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
2887 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
2888 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
2889 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
2890 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
2891 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
2892 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
2893 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
2894 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
2895 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
2896 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
2897 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
2898 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
2899 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
2900 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2901 };
2902
2903 static unsigned int equalizer_vals_lookup[] = {
2904 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
2905 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
2906 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
2907 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
2908 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
2909 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
2910 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
2911 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
2912 0x41C00000
2913 };
2914
2915 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2916                           unsigned int *lookup, int idx)
2917 {
2918         int i = 0;
2919
2920         for (i = 0; i < TUNING_CTLS_COUNT; i++)
2921                 if (nid == ca0132_tuning_ctls[i].nid)
2922                         break;
2923
2924         snd_hda_power_up(codec);
2925         dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2926                         ca0132_tuning_ctls[i].req,
2927                         &(lookup[idx]), sizeof(unsigned int));
2928         snd_hda_power_down(codec);
2929
2930         return 1;
2931 }
2932
2933 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2934                           struct snd_ctl_elem_value *ucontrol)
2935 {
2936         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2937         struct ca0132_spec *spec = codec->spec;
2938         hda_nid_t nid = get_amp_nid(kcontrol);
2939         long *valp = ucontrol->value.integer.value;
2940         int idx = nid - TUNING_CTL_START_NID;
2941
2942         *valp = spec->cur_ctl_vals[idx];
2943         return 0;
2944 }
2945
2946 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2947                               struct snd_ctl_elem_info *uinfo)
2948 {
2949         int chs = get_amp_channels(kcontrol);
2950         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2951         uinfo->count = chs == 3 ? 2 : 1;
2952         uinfo->value.integer.min = 20;
2953         uinfo->value.integer.max = 180;
2954         uinfo->value.integer.step = 1;
2955
2956         return 0;
2957 }
2958
2959 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2960                                 struct snd_ctl_elem_value *ucontrol)
2961 {
2962         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2963         struct ca0132_spec *spec = codec->spec;
2964         hda_nid_t nid = get_amp_nid(kcontrol);
2965         long *valp = ucontrol->value.integer.value;
2966         int idx;
2967
2968         idx = nid - TUNING_CTL_START_NID;
2969         /* any change? */
2970         if (spec->cur_ctl_vals[idx] == *valp)
2971                 return 0;
2972
2973         spec->cur_ctl_vals[idx] = *valp;
2974
2975         idx = *valp - 20;
2976         tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2977
2978         return 1;
2979 }
2980
2981 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
2982                               struct snd_ctl_elem_info *uinfo)
2983 {
2984         int chs = get_amp_channels(kcontrol);
2985         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2986         uinfo->count = chs == 3 ? 2 : 1;
2987         uinfo->value.integer.min = 0;
2988         uinfo->value.integer.max = 100;
2989         uinfo->value.integer.step = 1;
2990
2991         return 0;
2992 }
2993
2994 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
2995                                 struct snd_ctl_elem_value *ucontrol)
2996 {
2997         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2998         struct ca0132_spec *spec = codec->spec;
2999         hda_nid_t nid = get_amp_nid(kcontrol);
3000         long *valp = ucontrol->value.integer.value;
3001         int idx;
3002
3003         idx = nid - TUNING_CTL_START_NID;
3004         /* any change? */
3005         if (spec->cur_ctl_vals[idx] == *valp)
3006                 return 0;
3007
3008         spec->cur_ctl_vals[idx] = *valp;
3009
3010         idx = *valp;
3011         tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3012
3013         return 0;
3014 }
3015
3016 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3017                               struct snd_ctl_elem_info *uinfo)
3018 {
3019         int chs = get_amp_channels(kcontrol);
3020         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3021         uinfo->count = chs == 3 ? 2 : 1;
3022         uinfo->value.integer.min = 0;
3023         uinfo->value.integer.max = 48;
3024         uinfo->value.integer.step = 1;
3025
3026         return 0;
3027 }
3028
3029 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3030                                 struct snd_ctl_elem_value *ucontrol)
3031 {
3032         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3033         struct ca0132_spec *spec = codec->spec;
3034         hda_nid_t nid = get_amp_nid(kcontrol);
3035         long *valp = ucontrol->value.integer.value;
3036         int idx;
3037
3038         idx = nid - TUNING_CTL_START_NID;
3039         /* any change? */
3040         if (spec->cur_ctl_vals[idx] == *valp)
3041                 return 0;
3042
3043         spec->cur_ctl_vals[idx] = *valp;
3044
3045         idx = *valp;
3046         tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3047
3048         return 1;
3049 }
3050
3051 static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3052 static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3053
3054 static int add_tuning_control(struct hda_codec *codec,
3055                                 hda_nid_t pnid, hda_nid_t nid,
3056                                 const char *name, int dir)
3057 {
3058         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3059         int type = dir ? HDA_INPUT : HDA_OUTPUT;
3060         struct snd_kcontrol_new knew =
3061                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3062
3063         knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3064                         SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3065         knew.tlv.c = 0;
3066         knew.tlv.p = 0;
3067         switch (pnid) {
3068         case VOICE_FOCUS:
3069                 knew.info = voice_focus_ctl_info;
3070                 knew.get = tuning_ctl_get;
3071                 knew.put = voice_focus_ctl_put;
3072                 knew.tlv.p = voice_focus_db_scale;
3073                 break;
3074         case MIC_SVM:
3075                 knew.info = mic_svm_ctl_info;
3076                 knew.get = tuning_ctl_get;
3077                 knew.put = mic_svm_ctl_put;
3078                 break;
3079         case EQUALIZER:
3080                 knew.info = equalizer_ctl_info;
3081                 knew.get = tuning_ctl_get;
3082                 knew.put = equalizer_ctl_put;
3083                 knew.tlv.p = eq_db_scale;
3084                 break;
3085         default:
3086                 return 0;
3087         }
3088         knew.private_value =
3089                 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3090         sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3091         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3092 }
3093
3094 static int add_tuning_ctls(struct hda_codec *codec)
3095 {
3096         int i;
3097         int err;
3098
3099         for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3100                 err = add_tuning_control(codec,
3101                                         ca0132_tuning_ctls[i].parent_nid,
3102                                         ca0132_tuning_ctls[i].nid,
3103                                         ca0132_tuning_ctls[i].name,
3104                                         ca0132_tuning_ctls[i].direct);
3105                 if (err < 0)
3106                         return err;
3107         }
3108
3109         return 0;
3110 }
3111
3112 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3113 {
3114         struct ca0132_spec *spec = codec->spec;
3115         int i;
3116
3117         /* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
3118         spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3119         /* SVM level defaults to 0.74. */
3120         spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3121
3122         /* EQ defaults to 0dB. */
3123         for (i = 2; i < TUNING_CTLS_COUNT; i++)
3124                 spec->cur_ctl_vals[i] = 24;
3125 }
3126 #endif /*ENABLE_TUNING_CONTROLS*/
3127
3128 /*
3129  * Select the active output.
3130  * If autodetect is enabled, output will be selected based on jack detection.
3131  * If jack inserted, headphone will be selected, else built-in speakers
3132  * If autodetect is disabled, output will be selected based on selection.
3133  */
3134 static int ca0132_select_out(struct hda_codec *codec)
3135 {
3136         struct ca0132_spec *spec = codec->spec;
3137         unsigned int pin_ctl;
3138         int jack_present;
3139         int auto_jack;
3140         unsigned int tmp;
3141         int err;
3142
3143         codec_dbg(codec, "ca0132_select_out\n");
3144
3145         snd_hda_power_up_pm(codec);
3146
3147         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3148
3149         if (auto_jack)
3150                 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]);
3151         else
3152                 jack_present =
3153                         spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3154
3155         if (jack_present)
3156                 spec->cur_out_type = HEADPHONE_OUT;
3157         else
3158                 spec->cur_out_type = SPEAKER_OUT;
3159
3160         if (spec->cur_out_type == SPEAKER_OUT) {
3161                 codec_dbg(codec, "ca0132_select_out speaker\n");
3162                 /*speaker out config*/
3163                 tmp = FLOAT_ONE;
3164                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3165                 if (err < 0)
3166                         goto exit;
3167                 /*enable speaker EQ*/
3168                 tmp = FLOAT_ONE;
3169                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3170                 if (err < 0)
3171                         goto exit;
3172
3173                 /* Setup EAPD */
3174                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3175                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3176                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3177                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3178                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3179                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3180                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3181                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3182
3183                 /* disable headphone node */
3184                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3185                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3186                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3187                                     pin_ctl & ~PIN_HP);
3188                 /* enable speaker node */
3189                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3190                                              AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3191                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3192                                     pin_ctl | PIN_OUT);
3193         } else {
3194                 codec_dbg(codec, "ca0132_select_out hp\n");
3195                 /*headphone out config*/
3196                 tmp = FLOAT_ZERO;
3197                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3198                 if (err < 0)
3199                         goto exit;
3200                 /*disable speaker EQ*/
3201                 tmp = FLOAT_ZERO;
3202                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3203                 if (err < 0)
3204                         goto exit;
3205
3206                 /* Setup EAPD */
3207                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3208                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3209                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3210                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3211                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3212                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3213                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3214                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3215
3216                 /* disable speaker*/
3217                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3218                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3219                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3220                                     pin_ctl & ~PIN_HP);
3221                 /* enable headphone*/
3222                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3223                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3224                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3225                                     pin_ctl | PIN_HP);
3226         }
3227
3228 exit:
3229         snd_hda_power_down_pm(codec);
3230
3231         return err < 0 ? err : 0;
3232 }
3233
3234 static void ca0132_unsol_hp_delayed(struct work_struct *work)
3235 {
3236         struct ca0132_spec *spec = container_of(
3237                 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
3238         struct hda_jack_tbl *jack;
3239
3240         ca0132_select_out(spec->codec);
3241         jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
3242         if (jack) {
3243                 jack->block_report = 0;
3244                 snd_hda_jack_report_sync(spec->codec);
3245         }
3246 }
3247
3248 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3249 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3250 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3251
3252 /*
3253  * Select the active VIP source
3254  */
3255 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3256 {
3257         struct ca0132_spec *spec = codec->spec;
3258         unsigned int tmp;
3259
3260         if (spec->dsp_state != DSP_DOWNLOADED)
3261                 return 0;
3262
3263         /* if CrystalVoice if off, vipsource should be 0 */
3264         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3265             (val == 0)) {
3266                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3267                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3268                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3269                 if (spec->cur_mic_type == DIGITAL_MIC)
3270                         tmp = FLOAT_TWO;
3271                 else
3272                         tmp = FLOAT_ONE;
3273                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3274                 tmp = FLOAT_ZERO;
3275                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3276         } else {
3277                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3278                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3279                 if (spec->cur_mic_type == DIGITAL_MIC)
3280                         tmp = FLOAT_TWO;
3281                 else
3282                         tmp = FLOAT_ONE;
3283                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3284                 tmp = FLOAT_ONE;
3285                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3286                 msleep(20);
3287                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3288         }
3289
3290         return 1;
3291 }
3292
3293 /*
3294  * Select the active microphone.
3295  * If autodetect is enabled, mic will be selected based on jack detection.
3296  * If jack inserted, ext.mic will be selected, else built-in mic
3297  * If autodetect is disabled, mic will be selected based on selection.
3298  */
3299 static int ca0132_select_mic(struct hda_codec *codec)
3300 {
3301         struct ca0132_spec *spec = codec->spec;
3302         int jack_present;
3303         int auto_jack;
3304
3305         codec_dbg(codec, "ca0132_select_mic\n");
3306
3307         snd_hda_power_up_pm(codec);
3308
3309         auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3310
3311         if (auto_jack)
3312                 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]);
3313         else
3314                 jack_present =
3315                         spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3316
3317         if (jack_present)
3318                 spec->cur_mic_type = LINE_MIC_IN;
3319         else
3320                 spec->cur_mic_type = DIGITAL_MIC;
3321
3322         if (spec->cur_mic_type == DIGITAL_MIC) {
3323                 /* enable digital Mic */
3324                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3325                 ca0132_set_dmic(codec, 1);
3326                 ca0132_mic_boost_set(codec, 0);
3327                 /* set voice focus */
3328                 ca0132_effects_set(codec, VOICE_FOCUS,
3329                                    spec->effects_switch
3330                                    [VOICE_FOCUS - EFFECT_START_NID]);
3331         } else {
3332                 /* disable digital Mic */
3333                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3334                 ca0132_set_dmic(codec, 0);
3335                 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3336                 /* disable voice focus */
3337                 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3338         }
3339
3340         snd_hda_power_down_pm(codec);
3341
3342         return 0;
3343 }
3344
3345 /*
3346  * Check if VNODE settings take effect immediately.
3347  */
3348 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3349                                      hda_nid_t vnid,
3350                                      hda_nid_t *shared_nid)
3351 {
3352         struct ca0132_spec *spec = codec->spec;
3353         hda_nid_t nid;
3354
3355         switch (vnid) {
3356         case VNID_SPK:
3357                 nid = spec->shared_out_nid;
3358                 break;
3359         case VNID_MIC:
3360                 nid = spec->shared_mic_nid;
3361                 break;
3362         default:
3363                 return false;
3364         }
3365
3366         if (shared_nid)
3367                 *shared_nid = nid;
3368
3369         return true;
3370 }
3371
3372 /*
3373 * The following functions are control change helpers.
3374 * They return 0 if no changed.  Return 1 if changed.
3375 */
3376 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3377 {
3378         struct ca0132_spec *spec = codec->spec;
3379         unsigned int tmp;
3380
3381         /* based on CrystalVoice state to enable VoiceFX. */
3382         if (enable) {
3383                 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3384                         FLOAT_ONE : FLOAT_ZERO;
3385         } else {
3386                 tmp = FLOAT_ZERO;
3387         }
3388
3389         dspio_set_uint_param(codec, ca0132_voicefx.mid,
3390                              ca0132_voicefx.reqs[0], tmp);
3391
3392         return 1;
3393 }
3394
3395 /*
3396  * Set the effects parameters
3397  */
3398 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3399 {
3400         struct ca0132_spec *spec = codec->spec;
3401         unsigned int on;
3402         int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3403         int err = 0;
3404         int idx = nid - EFFECT_START_NID;
3405
3406         if ((idx < 0) || (idx >= num_fx))
3407                 return 0; /* no changed */
3408
3409         /* for out effect, qualify with PE */
3410         if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3411                 /* if PE if off, turn off out effects. */
3412                 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3413                         val = 0;
3414         }
3415
3416         /* for in effect, qualify with CrystalVoice */
3417         if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3418                 /* if CrystalVoice if off, turn off in effects. */
3419                 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3420                         val = 0;
3421
3422                 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3423                 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3424                         val = 0;
3425         }
3426
3427         codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
3428                     nid, val);
3429
3430         on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3431         err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3432                                    ca0132_effects[idx].reqs[0], on);
3433
3434         if (err < 0)
3435                 return 0; /* no changed */
3436
3437         return 1;
3438 }
3439
3440 /*
3441  * Turn on/off Playback Enhancements
3442  */
3443 static int ca0132_pe_switch_set(struct hda_codec *codec)
3444 {
3445         struct ca0132_spec *spec = codec->spec;
3446         hda_nid_t nid;
3447         int i, ret = 0;
3448
3449         codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
3450                     spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3451
3452         i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3453         nid = OUT_EFFECT_START_NID;
3454         /* PE affects all out effects */
3455         for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3456                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3457
3458         return ret;
3459 }
3460
3461 /* Check if Mic1 is streaming, if so, stop streaming */
3462 static int stop_mic1(struct hda_codec *codec)
3463 {
3464         struct ca0132_spec *spec = codec->spec;
3465         unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3466                                                  AC_VERB_GET_CONV, 0);
3467         if (oldval != 0)
3468                 snd_hda_codec_write(codec, spec->adcs[0], 0,
3469                                     AC_VERB_SET_CHANNEL_STREAMID,
3470                                     0);
3471         return oldval;
3472 }
3473
3474 /* Resume Mic1 streaming if it was stopped. */
3475 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3476 {
3477         struct ca0132_spec *spec = codec->spec;
3478         /* Restore the previous stream and channel */
3479         if (oldval != 0)
3480                 snd_hda_codec_write(codec, spec->adcs[0], 0,
3481                                     AC_VERB_SET_CHANNEL_STREAMID,
3482                                     oldval);
3483 }
3484
3485 /*
3486  * Turn on/off CrystalVoice
3487  */
3488 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3489 {
3490         struct ca0132_spec *spec = codec->spec;
3491         hda_nid_t nid;
3492         int i, ret = 0;
3493         unsigned int oldval;
3494
3495         codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
3496                     spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3497
3498         i = IN_EFFECT_START_NID - EFFECT_START_NID;
3499         nid = IN_EFFECT_START_NID;
3500         /* CrystalVoice affects all in effects */
3501         for (; nid < IN_EFFECT_END_NID; nid++, i++)
3502                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3503
3504         /* including VoiceFX */
3505         ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3506
3507         /* set correct vipsource */
3508         oldval = stop_mic1(codec);
3509         ret |= ca0132_set_vipsource(codec, 1);
3510         resume_mic1(codec, oldval);
3511         return ret;
3512 }
3513
3514 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3515 {
3516         struct ca0132_spec *spec = codec->spec;
3517         int ret = 0;
3518
3519         if (val) /* on */
3520                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3521                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3522         else /* off */
3523                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3524                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3525
3526         return ret;
3527 }
3528
3529 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3530                                 struct snd_ctl_elem_value *ucontrol)
3531 {
3532         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3533         hda_nid_t nid = get_amp_nid(kcontrol);
3534         hda_nid_t shared_nid = 0;
3535         bool effective;
3536         int ret = 0;
3537         struct ca0132_spec *spec = codec->spec;
3538         int auto_jack;
3539
3540         if (nid == VNID_HP_SEL) {
3541                 auto_jack =
3542                         spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3543                 if (!auto_jack)
3544                         ca0132_select_out(codec);
3545                 return 1;
3546         }
3547
3548         if (nid == VNID_AMIC1_SEL) {
3549                 auto_jack =
3550                         spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3551                 if (!auto_jack)
3552                         ca0132_select_mic(codec);
3553                 return 1;
3554         }
3555
3556         if (nid == VNID_HP_ASEL) {
3557                 ca0132_select_out(codec);
3558                 return 1;
3559         }
3560
3561         if (nid == VNID_AMIC1_ASEL) {
3562                 ca0132_select_mic(codec);
3563                 return 1;
3564         }
3565
3566         /* if effective conditions, then update hw immediately. */
3567         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3568         if (effective) {
3569                 int dir = get_amp_direction(kcontrol);
3570                 int ch = get_amp_channels(kcontrol);
3571                 unsigned long pval;
3572
3573                 mutex_lock(&codec->control_mutex);
3574                 pval = kcontrol->private_value;
3575                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3576                                                                 0, dir);
3577                 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3578                 kcontrol->private_value = pval;
3579                 mutex_unlock(&codec->control_mutex);
3580         }
3581
3582         return ret;
3583 }
3584 /* End of control change helpers. */
3585
3586 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3587                                  struct snd_ctl_elem_info *uinfo)
3588 {
3589         unsigned int items = sizeof(ca0132_voicefx_presets)
3590                                 / sizeof(struct ct_voicefx_preset);
3591
3592         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3593         uinfo->count = 1;
3594         uinfo->value.enumerated.items = items;
3595         if (uinfo->value.enumerated.item >= items)
3596                 uinfo->value.enumerated.item = items - 1;
3597         strcpy(uinfo->value.enumerated.name,
3598                ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3599         return 0;
3600 }
3601
3602 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
3603                                 struct snd_ctl_elem_value *ucontrol)
3604 {
3605         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3606         struct ca0132_spec *spec = codec->spec;
3607
3608         ucontrol->value.enumerated.item[0] = spec->voicefx_val;
3609         return 0;
3610 }
3611
3612 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
3613                                 struct snd_ctl_elem_value *ucontrol)
3614 {
3615         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3616         struct ca0132_spec *spec = codec->spec;
3617         int i, err = 0;
3618         int sel = ucontrol->value.enumerated.item[0];
3619         unsigned int items = sizeof(ca0132_voicefx_presets)
3620                                 / sizeof(struct ct_voicefx_preset);
3621
3622         if (sel >= items)
3623                 return 0;
3624
3625         codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
3626                     sel, ca0132_voicefx_presets[sel].name);
3627
3628         /*
3629          * Idx 0 is default.
3630          * Default needs to qualify with CrystalVoice state.
3631          */
3632         for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3633                 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3634                                 ca0132_voicefx.reqs[i],
3635                                 ca0132_voicefx_presets[sel].vals[i]);
3636                 if (err < 0)
3637                         break;
3638         }
3639
3640         if (err >= 0) {
3641                 spec->voicefx_val = sel;
3642                 /* enable voice fx */
3643                 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3644         }
3645
3646         return 1;
3647 }
3648
3649 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3650                                 struct snd_ctl_elem_value *ucontrol)
3651 {
3652         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3653         struct ca0132_spec *spec = codec->spec;
3654         hda_nid_t nid = get_amp_nid(kcontrol);
3655         int ch = get_amp_channels(kcontrol);
3656         long *valp = ucontrol->value.integer.value;
3657
3658         /* vnode */
3659         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3660                 if (ch & 1) {
3661                         *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3662                         valp++;
3663                 }
3664                 if (ch & 2) {
3665                         *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3666                         valp++;
3667                 }
3668                 return 0;
3669         }
3670
3671         /* effects, include PE and CrystalVoice */
3672         if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3673                 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3674                 return 0;
3675         }
3676
3677         /* mic boost */
3678         if (nid == spec->input_pins[0]) {
3679                 *valp = spec->cur_mic_boost;
3680                 return 0;
3681         }
3682
3683         return 0;
3684 }
3685
3686 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3687                              struct snd_ctl_elem_value *ucontrol)
3688 {
3689         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3690         struct ca0132_spec *spec = codec->spec;
3691         hda_nid_t nid = get_amp_nid(kcontrol);
3692         int ch = get_amp_channels(kcontrol);
3693         long *valp = ucontrol->value.integer.value;
3694         int changed = 1;
3695
3696         codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
3697                     nid, *valp);
3698
3699         snd_hda_power_up(codec);
3700         /* vnode */
3701         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3702                 if (ch & 1) {
3703                         spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3704                         valp++;
3705                 }
3706                 if (ch & 2) {
3707                         spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3708                         valp++;
3709                 }
3710                 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3711                 goto exit;
3712         }
3713
3714         /* PE */
3715         if (nid == PLAY_ENHANCEMENT) {
3716                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3717                 changed = ca0132_pe_switch_set(codec);
3718                 goto exit;
3719         }
3720
3721         /* CrystalVoice */
3722         if (nid == CRYSTAL_VOICE) {
3723                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3724                 changed = ca0132_cvoice_switch_set(codec);
3725                 goto exit;
3726         }
3727
3728         /* out and in effects */
3729         if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3730             ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3731                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3732                 changed = ca0132_effects_set(codec, nid, *valp);
3733                 goto exit;
3734         }
3735
3736         /* mic boost */
3737         if (nid == spec->input_pins[0]) {
3738                 spec->cur_mic_boost = *valp;
3739
3740                 /* Mic boost does not apply to Digital Mic */
3741                 if (spec->cur_mic_type != DIGITAL_MIC)
3742                         changed = ca0132_mic_boost_set(codec, *valp);
3743                 goto exit;
3744         }
3745
3746 exit:
3747         snd_hda_power_down(codec);
3748         return changed;
3749 }
3750
3751 /*
3752  * Volume related
3753  */
3754 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3755                               struct snd_ctl_elem_info *uinfo)
3756 {
3757         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3758         struct ca0132_spec *spec = codec->spec;
3759         hda_nid_t nid = get_amp_nid(kcontrol);
3760         int ch = get_amp_channels(kcontrol);
3761         int dir = get_amp_direction(kcontrol);
3762         unsigned long pval;
3763         int err;
3764
3765         switch (nid) {
3766         case VNID_SPK:
3767                 /* follow shared_out info */
3768                 nid = spec->shared_out_nid;
3769                 mutex_lock(&codec->control_mutex);
3770                 pval = kcontrol->private_value;
3771                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3772                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3773                 kcontrol->private_value = pval;
3774                 mutex_unlock(&codec->control_mutex);
3775                 break;
3776         case VNID_MIC:
3777                 /* follow shared_mic info */
3778                 nid = spec->shared_mic_nid;
3779                 mutex_lock(&codec->control_mutex);
3780                 pval = kcontrol->private_value;
3781                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3782                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3783                 kcontrol->private_value = pval;
3784                 mutex_unlock(&codec->control_mutex);
3785                 break;
3786         default:
3787                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3788         }
3789         return err;
3790 }
3791
3792 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
3793                                 struct snd_ctl_elem_value *ucontrol)
3794 {
3795         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3796         struct ca0132_spec *spec = codec->spec;
3797         hda_nid_t nid = get_amp_nid(kcontrol);
3798         int ch = get_amp_channels(kcontrol);
3799         long *valp = ucontrol->value.integer.value;
3800
3801         /* store the left and right volume */
3802         if (ch & 1) {
3803                 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3804                 valp++;
3805         }
3806         if (ch & 2) {
3807                 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3808                 valp++;
3809         }
3810         return 0;
3811 }
3812
3813 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
3814                                 struct snd_ctl_elem_value *ucontrol)
3815 {
3816         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3817         struct ca0132_spec *spec = codec->spec;
3818         hda_nid_t nid = get_amp_nid(kcontrol);
3819         int ch = get_amp_channels(kcontrol);
3820         long *valp = ucontrol->value.integer.value;
3821         hda_nid_t shared_nid = 0;
3822         bool effective;
3823         int changed = 1;
3824
3825         /* store the left and right volume */
3826         if (ch & 1) {
3827                 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3828                 valp++;
3829         }
3830         if (ch & 2) {
3831                 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3832                 valp++;
3833         }
3834
3835         /* if effective conditions, then update hw immediately. */
3836         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3837         if (effective) {
3838                 int dir = get_amp_direction(kcontrol);
3839                 unsigned long pval;
3840
3841                 snd_hda_power_up(codec);
3842                 mutex_lock(&codec->control_mutex);
3843                 pval = kcontrol->private_value;
3844                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3845                                                                 0, dir);
3846                 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3847                 kcontrol->private_value = pval;
3848                 mutex_unlock(&codec->control_mutex);
3849                 snd_hda_power_down(codec);
3850         }
3851
3852         return changed;
3853 }
3854
3855 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3856                              unsigned int size, unsigned int __user *tlv)
3857 {
3858         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3859         struct ca0132_spec *spec = codec->spec;
3860         hda_nid_t nid = get_amp_nid(kcontrol);
3861         int ch = get_amp_channels(kcontrol);
3862         int dir = get_amp_direction(kcontrol);
3863         unsigned long pval;
3864         int err;
3865
3866         switch (nid) {
3867         case VNID_SPK:
3868                 /* follow shared_out tlv */
3869                 nid = spec->shared_out_nid;
3870                 mutex_lock(&codec->control_mutex);
3871                 pval = kcontrol->private_value;
3872                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3873                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3874                 kcontrol->private_value = pval;
3875                 mutex_unlock(&codec->control_mutex);
3876                 break;
3877         case VNID_MIC:
3878                 /* follow shared_mic tlv */
3879                 nid = spec->shared_mic_nid;
3880                 mutex_lock(&codec->control_mutex);
3881                 pval = kcontrol->private_value;
3882                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3883                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3884                 kcontrol->private_value = pval;
3885                 mutex_unlock(&codec->control_mutex);
3886                 break;
3887         default:
3888                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3889         }
3890         return err;
3891 }
3892
3893 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3894                          const char *pfx, int dir)
3895 {
3896         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3897         int type = dir ? HDA_INPUT : HDA_OUTPUT;
3898         struct snd_kcontrol_new knew =
3899                 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3900         sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
3901         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3902 }
3903
3904 static int add_voicefx(struct hda_codec *codec)
3905 {
3906         struct snd_kcontrol_new knew =
3907                 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3908                                     VOICEFX, 1, 0, HDA_INPUT);
3909         knew.info = ca0132_voicefx_info;
3910         knew.get = ca0132_voicefx_get;
3911         knew.put = ca0132_voicefx_put;
3912         return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
3913 }
3914
3915 /*
3916  * When changing Node IDs for Mixer Controls below, make sure to update
3917  * Node IDs in ca0132_config() as well.
3918  */
3919 static struct snd_kcontrol_new ca0132_mixer[] = {
3920         CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3921         CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3922         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3923         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3924         HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3925         HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3926         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3927         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3928         CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3929                                0x12, 1, HDA_INPUT),
3930         CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3931                                VNID_HP_SEL, 1, HDA_OUTPUT),
3932         CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3933                                VNID_AMIC1_SEL, 1, HDA_INPUT),
3934         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3935                                VNID_HP_ASEL, 1, HDA_OUTPUT),
3936         CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3937                                VNID_AMIC1_ASEL, 1, HDA_INPUT),
3938         { } /* end */
3939 };
3940
3941 static int ca0132_build_controls(struct hda_codec *codec)
3942 {
3943         struct ca0132_spec *spec = codec->spec;
3944         int i, num_fx;
3945         int err = 0;
3946
3947         /* Add Mixer controls */
3948         for (i = 0; i < spec->num_mixers; i++) {
3949                 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3950                 if (err < 0)
3951                         return err;
3952         }
3953
3954         /* Add in and out effects controls.
3955          * VoiceFX, PE and CrystalVoice are added separately.
3956          */
3957         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3958         for (i = 0; i < num_fx; i++) {
3959                 err = add_fx_switch(codec, ca0132_effects[i].nid,
3960                                     ca0132_effects[i].name,
3961                                     ca0132_effects[i].direct);
3962                 if (err < 0)
3963                         return err;
3964         }
3965
3966         err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3967         if (err < 0)
3968                 return err;
3969
3970         err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3971         if (err < 0)
3972                 return err;
3973
3974         add_voicefx(codec);
3975
3976 #ifdef ENABLE_TUNING_CONTROLS
3977         add_tuning_ctls(codec);
3978 #endif
3979
3980         err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3981         if (err < 0)
3982                 return err;
3983
3984         if (spec->dig_out) {
3985                 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
3986                                                     spec->dig_out);
3987                 if (err < 0)
3988                         return err;
3989                 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
3990                 if (err < 0)
3991                         return err;
3992                 /* spec->multiout.share_spdif = 1; */
3993         }
3994
3995         if (spec->dig_in) {
3996                 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
3997                 if (err < 0)
3998                         return err;
3999         }
4000         return 0;
4001 }
4002
4003 /*
4004  * PCM
4005  */
4006 static struct hda_pcm_stream ca0132_pcm_analog_playback = {
4007         .substreams = 1,
4008         .channels_min = 2,
4009         .channels_max = 6,
4010         .ops = {
4011                 .prepare = ca0132_playback_pcm_prepare,
4012                 .cleanup = ca0132_playback_pcm_cleanup,
4013                 .get_delay = ca0132_playback_pcm_delay,
4014         },
4015 };
4016
4017 static struct hda_pcm_stream ca0132_pcm_analog_capture = {
4018         .substreams = 1,
4019         .channels_min = 2,
4020         .channels_max = 2,
4021         .ops = {
4022                 .prepare = ca0132_capture_pcm_prepare,
4023                 .cleanup = ca0132_capture_pcm_cleanup,
4024                 .get_delay = ca0132_capture_pcm_delay,
4025         },
4026 };
4027
4028 static struct hda_pcm_stream ca0132_pcm_digital_playback = {
4029         .substreams = 1,
4030         .channels_min = 2,
4031         .channels_max = 2,
4032         .ops = {
4033                 .open = ca0132_dig_playback_pcm_open,
4034                 .close = ca0132_dig_playback_pcm_close,
4035                 .prepare = ca0132_dig_playback_pcm_prepare,
4036                 .cleanup = ca0132_dig_playback_pcm_cleanup
4037         },
4038 };
4039
4040 static struct hda_pcm_stream ca0132_pcm_digital_capture = {
4041         .substreams = 1,
4042         .channels_min = 2,
4043         .channels_max = 2,
4044 };
4045
4046 static int ca0132_build_pcms(struct hda_codec *codec)
4047 {
4048         struct ca0132_spec *spec = codec->spec;
4049         struct hda_pcm *info;
4050
4051         info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
4052         if (!info)
4053                 return -ENOMEM;
4054         info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4055         info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4056         info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4057                 spec->multiout.max_channels;
4058         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4059         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4060         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4061
4062         info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
4063         if (!info)
4064                 return -ENOMEM;
4065         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4066         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4067         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4068
4069         info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
4070         if (!info)
4071                 return -ENOMEM;
4072         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4073         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4074         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4075
4076         if (!spec->dig_out && !spec->dig_in)
4077                 return 0;
4078
4079         info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
4080         if (!info)
4081                 return -ENOMEM;
4082         info->pcm_type = HDA_PCM_TYPE_SPDIF;
4083         if (spec->dig_out) {
4084                 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4085                         ca0132_pcm_digital_playback;
4086                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4087         }
4088         if (spec->dig_in) {
4089                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4090                         ca0132_pcm_digital_capture;
4091                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4092         }
4093
4094         return 0;
4095 }
4096
4097 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4098 {
4099         if (pin) {
4100                 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
4101                 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4102                         snd_hda_codec_write(codec, pin, 0,
4103                                             AC_VERB_SET_AMP_GAIN_MUTE,
4104                                             AMP_OUT_UNMUTE);
4105         }
4106         if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4107                 snd_hda_codec_write(codec, dac, 0,
4108                                     AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4109 }
4110
4111 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4112 {
4113         if (pin) {
4114                 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
4115                 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4116                         snd_hda_codec_write(codec, pin, 0,
4117                                             AC_VERB_SET_AMP_GAIN_MUTE,
4118                                             AMP_IN_UNMUTE(0));
4119         }
4120         if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4121                 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4122                                     AMP_IN_UNMUTE(0));
4123
4124                 /* init to 0 dB and unmute. */
4125                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4126                                          HDA_AMP_VOLMASK, 0x5a);
4127                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4128                                          HDA_AMP_MUTE, 0);
4129         }
4130 }
4131
4132 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4133 {
4134         unsigned int caps;
4135
4136         caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4137                                   AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4138         snd_hda_override_amp_caps(codec, nid, dir, caps);
4139 }
4140
4141 /*
4142  * Switch between Digital built-in mic and analog mic.
4143  */
4144 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4145 {
4146         struct ca0132_spec *spec = codec->spec;
4147         unsigned int tmp;
4148         u8 val;
4149         unsigned int oldval;
4150
4151         codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
4152
4153         oldval = stop_mic1(codec);
4154         ca0132_set_vipsource(codec, 0);
4155         if (enable) {
4156                 /* set DMic input as 2-ch */
4157                 tmp = FLOAT_TWO;
4158                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4159
4160                 val = spec->dmic_ctl;
4161                 val |= 0x80;
4162                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4163                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
4164
4165                 if (!(spec->dmic_ctl & 0x20))
4166                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4167         } else {
4168                 /* set AMic input as mono */
4169                 tmp = FLOAT_ONE;
4170                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4171
4172                 val = spec->dmic_ctl;
4173                 /* clear bit7 and bit5 to disable dmic */
4174                 val &= 0x5f;
4175                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4176                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
4177
4178                 if (!(spec->dmic_ctl & 0x20))
4179                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4180         }
4181         ca0132_set_vipsource(codec, 1);
4182         resume_mic1(codec, oldval);
4183 }
4184
4185 /*
4186  * Initialization for Digital Mic.
4187  */
4188 static void ca0132_init_dmic(struct hda_codec *codec)
4189 {
4190         struct ca0132_spec *spec = codec->spec;
4191         u8 val;
4192
4193         /* Setup Digital Mic here, but don't enable.
4194          * Enable based on jack detect.
4195          */
4196
4197         /* MCLK uses MPIO1, set to enable.
4198          * Bit 2-0: MPIO select
4199          * Bit   3: set to disable
4200          * Bit 7-4: reserved
4201          */
4202         val = 0x01;
4203         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4204                             VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4205
4206         /* Data1 uses MPIO3. Data2 not use
4207          * Bit 2-0: Data1 MPIO select
4208          * Bit   3: set disable Data1
4209          * Bit 6-4: Data2 MPIO select
4210          * Bit   7: set disable Data2
4211          */
4212         val = 0x83;
4213         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4214                             VENDOR_CHIPIO_DMIC_PIN_SET, val);
4215
4216         /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4217          * Bit 3-0: Channel mask
4218          * Bit   4: set for 48KHz, clear for 32KHz
4219          * Bit   5: mode
4220          * Bit   6: set to select Data2, clear for Data1
4221          * Bit   7: set to enable DMic, clear for AMic
4222          */
4223         val = 0x23;
4224         /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4225         spec->dmic_ctl = val;
4226         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4227                             VENDOR_CHIPIO_DMIC_CTL_SET, val);
4228 }
4229
4230 /*
4231  * Initialization for Analog Mic 2
4232  */
4233 static void ca0132_init_analog_mic2(struct hda_codec *codec)
4234 {
4235         struct ca0132_spec *spec = codec->spec;
4236
4237         mutex_lock(&spec->chipio_mutex);
4238         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4239                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4240         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4241                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4242         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4243                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4244         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4245                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4246         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4247                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4248         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4249                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4250         mutex_unlock(&spec->chipio_mutex);
4251 }
4252
4253 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4254 {
4255         struct ca0132_spec *spec = codec->spec;
4256         int i;
4257
4258         codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
4259         snd_hda_codec_update_widgets(codec);
4260
4261         for (i = 0; i < spec->multiout.num_dacs; i++)
4262                 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4263
4264         for (i = 0; i < spec->num_outputs; i++)
4265                 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4266
4267         for (i = 0; i < spec->num_inputs; i++) {
4268                 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4269                 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4270         }
4271 }
4272
4273 /*
4274  * Setup default parameters for DSP
4275  */
4276 static void ca0132_setup_defaults(struct hda_codec *codec)
4277 {
4278         struct ca0132_spec *spec = codec->spec;
4279         unsigned int tmp;
4280         int num_fx;
4281         int idx, i;
4282
4283         if (spec->dsp_state != DSP_DOWNLOADED)
4284                 return;
4285
4286         /* out, in effects + voicefx */
4287         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4288         for (idx = 0; idx < num_fx; idx++) {
4289                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4290                         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4291                                              ca0132_effects[idx].reqs[i],
4292                                              ca0132_effects[idx].def_vals[i]);
4293                 }
4294         }
4295
4296         /*remove DSP headroom*/
4297         tmp = FLOAT_ZERO;
4298         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4299
4300         /*set speaker EQ bypass attenuation*/
4301         dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4302
4303         /* set AMic1 and AMic2 as mono mic */
4304         tmp = FLOAT_ONE;
4305         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4306         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4307
4308         /* set AMic1 as CrystalVoice input */
4309         tmp = FLOAT_ONE;
4310         dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4311
4312         /* set WUH source */
4313         tmp = FLOAT_TWO;
4314         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4315 }
4316
4317 /*
4318  * Initialization of flags in chip
4319  */
4320 static void ca0132_init_flags(struct hda_codec *codec)
4321 {
4322         chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4323         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4324         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4325         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4326         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4327         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4328 }
4329
4330 /*
4331  * Initialization of parameters in chip
4332  */
4333 static void ca0132_init_params(struct hda_codec *codec)
4334 {
4335         chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4336         chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4337 }
4338
4339 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4340 {
4341         chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4342         chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4343         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4344         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4345         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4346         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4347
4348         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4349         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4350         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4351 }
4352
4353 static bool ca0132_download_dsp_images(struct hda_codec *codec)
4354 {
4355         bool dsp_loaded = false;
4356         const struct dsp_image_seg *dsp_os_image;
4357         const struct firmware *fw_entry;
4358
4359         if (request_firmware(&fw_entry, EFX_FILE, codec->card->dev) != 0)
4360                 return false;
4361
4362         dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
4363         if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
4364                 pr_err("ca0132 dspload_image failed.\n");
4365                 goto exit_download;
4366         }
4367
4368         dsp_loaded = dspload_wait_loaded(codec);
4369
4370 exit_download:
4371         release_firmware(fw_entry);
4372
4373         return dsp_loaded;
4374 }
4375
4376 static void ca0132_download_dsp(struct hda_codec *codec)
4377 {
4378         struct ca0132_spec *spec = codec->spec;
4379
4380 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4381         return; /* NOP */
4382 #endif
4383
4384         if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
4385                 return; /* don't retry failures */
4386
4387         chipio_enable_clocks(codec);
4388         spec->dsp_state = DSP_DOWNLOADING;
4389         if (!ca0132_download_dsp_images(codec))
4390                 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4391         else
4392                 spec->dsp_state = DSP_DOWNLOADED;
4393
4394         if (spec->dsp_state == DSP_DOWNLOADED)
4395                 ca0132_set_dsp_msr(codec, true);
4396 }
4397
4398 static void ca0132_process_dsp_response(struct hda_codec *codec,
4399                                         struct hda_jack_callback *callback)
4400 {
4401         struct ca0132_spec *spec = codec->spec;
4402
4403         codec_dbg(codec, "ca0132_process_dsp_response\n");
4404         if (spec->wait_scp) {
4405                 if (dspio_get_response_data(codec) >= 0)
4406                         spec->wait_scp = 0;
4407         }
4408
4409         dspio_clear_response_queue(codec);
4410 }
4411
4412 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4413 {
4414         struct ca0132_spec *spec = codec->spec;
4415
4416         /* Delay enabling the HP amp, to let the mic-detection
4417          * state machine run.
4418          */
4419         cancel_delayed_work_sync(&spec->unsol_hp_work);
4420         schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
4421         cb->tbl->block_report = 1;
4422 }
4423
4424 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4425 {
4426         ca0132_select_mic(codec);
4427 }
4428
4429 static void ca0132_init_unsol(struct hda_codec *codec)
4430 {
4431         struct ca0132_spec *spec = codec->spec;
4432         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
4433         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
4434                                             amic_callback);
4435         snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
4436                                             ca0132_process_dsp_response);
4437 }
4438
4439 /*
4440  * Verbs tables.
4441  */
4442
4443 /* Sends before DSP download. */
4444 static struct hda_verb ca0132_base_init_verbs[] = {
4445         /*enable ct extension*/
4446         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4447         {}
4448 };
4449
4450 /* Send at exit. */
4451 static struct hda_verb ca0132_base_exit_verbs[] = {
4452         /*set afg to D3*/
4453         {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4454         /*disable ct extension*/
4455         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4456         {}
4457 };
4458
4459 /* Other verbs tables.  Sends after DSP download. */
4460 static struct hda_verb ca0132_init_verbs0[] = {
4461         /* chip init verbs */
4462         {0x15, 0x70D, 0xF0},
4463         {0x15, 0x70E, 0xFE},
4464         {0x15, 0x707, 0x75},
4465         {0x15, 0x707, 0xD3},
4466         {0x15, 0x707, 0x09},
4467         {0x15, 0x707, 0x53},
4468         {0x15, 0x707, 0xD4},
4469         {0x15, 0x707, 0xEF},
4470         {0x15, 0x707, 0x75},
4471         {0x15, 0x707, 0xD3},
4472         {0x15, 0x707, 0x09},
4473         {0x15, 0x707, 0x02},
4474         {0x15, 0x707, 0x37},
4475         {0x15, 0x707, 0x78},
4476         {0x15, 0x53C, 0xCE},
4477         {0x15, 0x575, 0xC9},
4478         {0x15, 0x53D, 0xCE},
4479         {0x15, 0x5B7, 0xC9},
4480         {0x15, 0x70D, 0xE8},
4481         {0x15, 0x70E, 0xFE},
4482         {0x15, 0x707, 0x02},
4483         {0x15, 0x707, 0x68},
4484         {0x15, 0x707, 0x62},
4485         {0x15, 0x53A, 0xCE},
4486         {0x15, 0x546, 0xC9},
4487         {0x15, 0x53B, 0xCE},
4488         {0x15, 0x5E8, 0xC9},
4489         {0x15, 0x717, 0x0D},
4490         {0x15, 0x718, 0x20},
4491         {}
4492 };
4493
4494 static void ca0132_init_chip(struct hda_codec *codec)
4495 {
4496         struct ca0132_spec *spec = codec->spec;
4497         int num_fx;
4498         int i;
4499         unsigned int on;
4500
4501         mutex_init(&spec->chipio_mutex);
4502
4503         spec->cur_out_type = SPEAKER_OUT;
4504         spec->cur_mic_type = DIGITAL_MIC;
4505         spec->cur_mic_boost = 0;
4506
4507         for (i = 0; i < VNODES_COUNT; i++) {
4508                 spec->vnode_lvol[i] = 0x5a;
4509                 spec->vnode_rvol[i] = 0x5a;
4510                 spec->vnode_lswitch[i] = 0;
4511                 spec->vnode_rswitch[i] = 0;
4512         }
4513
4514         /*
4515          * Default states for effects are in ca0132_effects[].
4516          */
4517         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4518         for (i = 0; i < num_fx; i++) {
4519                 on = (unsigned int)ca0132_effects[i].reqs[0];
4520                 spec->effects_switch[i] = on ? 1 : 0;
4521         }
4522
4523         spec->voicefx_val = 0;
4524         spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4525         spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4526
4527 #ifdef ENABLE_TUNING_CONTROLS
4528         ca0132_init_tuning_defaults(codec);
4529 #endif
4530 }
4531
4532 static void ca0132_exit_chip(struct hda_codec *codec)
4533 {
4534         /* put any chip cleanup stuffs here. */
4535
4536         if (dspload_is_loaded(codec))
4537                 dsp_reset(codec);
4538 }
4539
4540 static int ca0132_init(struct hda_codec *codec)
4541 {
4542         struct ca0132_spec *spec = codec->spec;
4543         struct auto_pin_cfg *cfg = &spec->autocfg;
4544         int i;
4545
4546         if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
4547                 spec->dsp_state = DSP_DOWNLOAD_INIT;
4548         spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
4549
4550         snd_hda_power_up_pm(codec);
4551
4552         ca0132_init_unsol(codec);
4553
4554         ca0132_init_params(codec);
4555         ca0132_init_flags(codec);
4556         snd_hda_sequence_write(codec, spec->base_init_verbs);
4557         ca0132_download_dsp(codec);
4558         ca0132_refresh_widget_caps(codec);
4559         ca0132_setup_defaults(codec);
4560         ca0132_init_analog_mic2(codec);
4561         ca0132_init_dmic(codec);
4562
4563         for (i = 0; i < spec->num_outputs; i++)
4564                 init_output(codec, spec->out_pins[i], spec->dacs[0]);
4565
4566         init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4567
4568         for (i = 0; i < spec->num_inputs; i++)
4569                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4570
4571         init_input(codec, cfg->dig_in_pin, spec->dig_in);
4572
4573         snd_hda_sequence_write(codec, spec->chip_init_verbs);
4574         snd_hda_sequence_write(codec, spec->spec_init_verbs);
4575
4576         ca0132_select_out(codec);
4577         ca0132_select_mic(codec);
4578
4579         snd_hda_jack_report_sync(codec);
4580
4581         snd_hda_power_down_pm(codec);
4582
4583         return 0;
4584 }
4585
4586 static void ca0132_free(struct hda_codec *codec)
4587 {
4588         struct ca0132_spec *spec = codec->spec;
4589
4590         cancel_delayed_work_sync(&spec->unsol_hp_work);
4591         snd_hda_power_up(codec);
4592         snd_hda_sequence_write(codec, spec->base_exit_verbs);
4593         ca0132_exit_chip(codec);
4594         snd_hda_power_down(codec);
4595         kfree(spec->spec_init_verbs);
4596         kfree(codec->spec);
4597 }
4598
4599 static struct hda_codec_ops ca0132_patch_ops = {
4600         .build_controls = ca0132_build_controls,
4601         .build_pcms = ca0132_build_pcms,
4602         .init = ca0132_init,
4603         .free = ca0132_free,
4604         .unsol_event = snd_hda_jack_unsol_event,
4605 };
4606
4607 static void ca0132_config(struct hda_codec *codec)
4608 {
4609         struct ca0132_spec *spec = codec->spec;
4610         struct auto_pin_cfg *cfg = &spec->autocfg;
4611
4612         spec->dacs[0] = 0x2;
4613         spec->dacs[1] = 0x3;
4614         spec->dacs[2] = 0x4;
4615
4616         spec->multiout.dac_nids = spec->dacs;
4617         spec->multiout.num_dacs = 3;
4618         spec->multiout.max_channels = 2;
4619
4620         spec->num_outputs = 2;
4621         spec->out_pins[0] = 0x0b; /* speaker out */
4622         if (spec->quirk == QUIRK_ALIENWARE) {
4623                 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
4624                 spec->out_pins[1] = 0x0f;
4625         } else{
4626                 spec->out_pins[1] = 0x10; /* headphone out */
4627         }
4628         spec->shared_out_nid = 0x2;
4629         spec->unsol_tag_hp = spec->out_pins[1];
4630
4631         spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4632         spec->adcs[1] = 0x8; /* analog mic2 */
4633         spec->adcs[2] = 0xa; /* what u hear */
4634
4635         spec->num_inputs = 3;
4636         spec->input_pins[0] = 0x12;
4637         spec->input_pins[1] = 0x11;
4638         spec->input_pins[2] = 0x13;
4639         spec->shared_mic_nid = 0x7;
4640         spec->unsol_tag_amic1 = spec->input_pins[0];
4641
4642         /* SPDIF I/O */
4643         spec->dig_out = 0x05;
4644         spec->multiout.dig_out_nid = spec->dig_out;
4645         cfg->dig_out_pins[0] = 0x0c;
4646         cfg->dig_outs = 1;
4647         cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4648         spec->dig_in = 0x09;
4649         cfg->dig_in_pin = 0x0e;
4650         cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4651 }
4652
4653 static int ca0132_prepare_verbs(struct hda_codec *codec)
4654 {
4655 /* Verbs + terminator (an empty element) */
4656 #define NUM_SPEC_VERBS 4
4657         struct ca0132_spec *spec = codec->spec;
4658
4659         spec->chip_init_verbs = ca0132_init_verbs0;
4660         spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL);
4661         if (!spec->spec_init_verbs)
4662                 return -ENOMEM;
4663
4664         /* HP jack autodetection */
4665         spec->spec_init_verbs[0].nid = spec->unsol_tag_hp;
4666         spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4667         spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp;
4668
4669         /* MIC1 jack autodetection */
4670         spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1;
4671         spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4672         spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1;
4673
4674         /* config EAPD */
4675         spec->spec_init_verbs[2].nid = 0x0b;
4676         spec->spec_init_verbs[2].param = 0x78D;
4677         spec->spec_init_verbs[2].verb = 0x00;
4678
4679         /* Previously commented configuration */
4680         /*
4681         spec->spec_init_verbs[3].nid = 0x0b;
4682         spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE;
4683         spec->spec_init_verbs[3].verb = 0x02;
4684
4685         spec->spec_init_verbs[4].nid = 0x10;
4686         spec->spec_init_verbs[4].param = 0x78D;
4687         spec->spec_init_verbs[4].verb = 0x02;
4688
4689         spec->spec_init_verbs[5].nid = 0x10;
4690         spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE;
4691         spec->spec_init_verbs[5].verb = 0x02;
4692         */
4693
4694         /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
4695         return 0;
4696 }
4697
4698 static int patch_ca0132(struct hda_codec *codec)
4699 {
4700         struct ca0132_spec *spec;
4701         int err;
4702         const struct snd_pci_quirk *quirk;
4703
4704         codec_dbg(codec, "patch_ca0132\n");
4705
4706         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4707         if (!spec)
4708                 return -ENOMEM;
4709         codec->spec = spec;
4710         spec->codec = codec;
4711
4712         codec->patch_ops = ca0132_patch_ops;
4713         codec->pcm_format_first = 1;
4714         codec->no_sticky_stream = 1;
4715
4716         /* Detect codec quirk */
4717         quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
4718         if (quirk)
4719                 spec->quirk = quirk->value;
4720         else
4721                 spec->quirk = QUIRK_NONE;
4722
4723         spec->dsp_state = DSP_DOWNLOAD_INIT;
4724         spec->num_mixers = 1;
4725         spec->mixers[0] = ca0132_mixer;
4726
4727         spec->base_init_verbs = ca0132_base_init_verbs;
4728         spec->base_exit_verbs = ca0132_base_exit_verbs;
4729
4730         INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4731
4732         ca0132_init_chip(codec);
4733
4734         ca0132_config(codec);
4735
4736         err = ca0132_prepare_verbs(codec);
4737         if (err < 0)
4738                 return err;
4739
4740         err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4741         if (err < 0)
4742                 return err;
4743
4744         return 0;
4745 }
4746
4747 /*
4748  * patch entries
4749  */
4750 static struct hda_codec_preset snd_hda_preset_ca0132[] = {
4751         { .id = 0x11020011, .name = "CA0132",     .patch = patch_ca0132 },
4752         {} /* terminator */
4753 };
4754
4755 MODULE_ALIAS("snd-hda-codec-id:11020011");
4756
4757 MODULE_LICENSE("GPL");
4758 MODULE_DESCRIPTION("Creative Sound Core3D codec");
4759
4760 static struct hda_codec_driver ca0132_driver = {
4761         .preset = snd_hda_preset_ca0132,
4762 };
4763
4764 module_hda_codec_driver(ca0132_driver);