2 * HD audio interface patch for Creative CA0132 chip
4 * Copyright (c) 2011, Creative Technology Ltd.
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/pci.h>
28 #include <linux/mutex.h>
29 #include <linux/module.h>
30 #include <linux/firmware.h>
31 #include <sound/core.h>
32 #include "hda_codec.h"
33 #include "hda_local.h"
34 #include "hda_auto_parser.h"
37 #include "ca0132_regs.h"
39 /* Enable this to see controls for tuning purpose. */
40 /*#define ENABLE_TUNING_CONTROLS*/
42 #define FLOAT_ZERO 0x00000000
43 #define FLOAT_ONE 0x3f800000
44 #define FLOAT_TWO 0x40000000
45 #define FLOAT_MINUS_5 0xc0a00000
47 #define UNSOL_TAG_HP 0x10
48 #define UNSOL_TAG_AMIC1 0x12
49 #define UNSOL_TAG_DSP 0x16
51 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
52 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
54 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
55 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
56 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
58 #define MASTERCONTROL 0x80
59 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
60 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
62 #define WIDGET_CHIP_CTRL 0x15
63 #define WIDGET_DSP_CTRL 0x16
65 #define MEM_CONNID_MICIN1 3
66 #define MEM_CONNID_MICIN2 5
67 #define MEM_CONNID_MICOUT1 12
68 #define MEM_CONNID_MICOUT2 14
69 #define MEM_CONNID_WUH 10
70 #define MEM_CONNID_DSP 16
71 #define MEM_CONNID_DMIC 100
76 #define EFX_FILE "ctefx.bin"
78 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
79 MODULE_FIRMWARE(EFX_FILE);
82 static char *dirstr[2] = { "Playback", "Capture" };
95 #define VNODE_START_NID 0x80
96 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
103 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
105 #define EFFECT_START_NID 0x90
106 #define OUT_EFFECT_START_NID EFFECT_START_NID
107 SURROUND = OUT_EFFECT_START_NID,
114 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
116 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
117 ECHO_CANCELLATION = IN_EFFECT_START_NID,
122 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
124 VOICEFX = IN_EFFECT_END_NID,
128 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
131 /* Effects values size*/
132 #define EFFECT_VALS_MAX_COUNT 12
137 int mid; /*effect module ID*/
138 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
139 int direct; /* 0:output; 1:input*/
140 int params; /* number of default non-on/off params */
141 /*effect default values, 1st is on/off. */
142 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
145 #define EFX_DIR_OUT 0
148 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
149 { .name = "Surround",
153 .direct = EFX_DIR_OUT,
155 .def_vals = {0x3F800000, 0x3F2B851F}
157 { .name = "Crystalizer",
161 .direct = EFX_DIR_OUT,
163 .def_vals = {0x3F800000, 0x3F266666}
165 { .name = "Dialog Plus",
169 .direct = EFX_DIR_OUT,
171 .def_vals = {0x00000000, 0x3F000000}
173 { .name = "Smart Volume",
177 .direct = EFX_DIR_OUT,
179 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
184 .reqs = {24, 23, 25},
185 .direct = EFX_DIR_OUT,
187 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
189 { .name = "Equalizer",
192 .reqs = {9, 10, 11, 12, 13, 14,
193 15, 16, 17, 18, 19, 20},
194 .direct = EFX_DIR_OUT,
196 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
197 0x00000000, 0x00000000, 0x00000000, 0x00000000,
198 0x00000000, 0x00000000, 0x00000000, 0x00000000}
200 { .name = "Echo Cancellation",
201 .nid = ECHO_CANCELLATION,
203 .reqs = {0, 1, 2, 3},
204 .direct = EFX_DIR_IN,
206 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
208 { .name = "Voice Focus",
211 .reqs = {6, 7, 8, 9},
212 .direct = EFX_DIR_IN,
214 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
220 .direct = EFX_DIR_IN,
222 .def_vals = {0x00000000, 0x3F3D70A4}
224 { .name = "Noise Reduction",
225 .nid = NOISE_REDUCTION,
228 .direct = EFX_DIR_IN,
230 .def_vals = {0x3F800000, 0x3F000000}
235 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
236 .direct = EFX_DIR_IN,
238 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
239 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
244 /* Tuning controls */
245 #ifdef ENABLE_TUNING_CONTROLS
248 #define TUNING_CTL_START_NID 0xC0
249 WEDGE_ANGLE = TUNING_CTL_START_NID,
262 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
265 struct ct_tuning_ctl {
267 hda_nid_t parent_nid;
269 int mid; /*effect module ID*/
270 int req; /*effect module request*/
271 int direct; /* 0:output; 1:input*/
272 unsigned int def_val;/*effect default values*/
275 static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
276 { .name = "Wedge Angle",
277 .parent_nid = VOICE_FOCUS,
281 .direct = EFX_DIR_IN,
282 .def_val = 0x41F00000
284 { .name = "SVM Level",
285 .parent_nid = MIC_SVM,
289 .direct = EFX_DIR_IN,
290 .def_val = 0x3F3D70A4
292 { .name = "EQ Band0",
293 .parent_nid = EQUALIZER,
294 .nid = EQUALIZER_BAND_0,
297 .direct = EFX_DIR_OUT,
298 .def_val = 0x00000000
300 { .name = "EQ Band1",
301 .parent_nid = EQUALIZER,
302 .nid = EQUALIZER_BAND_1,
305 .direct = EFX_DIR_OUT,
306 .def_val = 0x00000000
308 { .name = "EQ Band2",
309 .parent_nid = EQUALIZER,
310 .nid = EQUALIZER_BAND_2,
313 .direct = EFX_DIR_OUT,
314 .def_val = 0x00000000
316 { .name = "EQ Band3",
317 .parent_nid = EQUALIZER,
318 .nid = EQUALIZER_BAND_3,
321 .direct = EFX_DIR_OUT,
322 .def_val = 0x00000000
324 { .name = "EQ Band4",
325 .parent_nid = EQUALIZER,
326 .nid = EQUALIZER_BAND_4,
329 .direct = EFX_DIR_OUT,
330 .def_val = 0x00000000
332 { .name = "EQ Band5",
333 .parent_nid = EQUALIZER,
334 .nid = EQUALIZER_BAND_5,
337 .direct = EFX_DIR_OUT,
338 .def_val = 0x00000000
340 { .name = "EQ Band6",
341 .parent_nid = EQUALIZER,
342 .nid = EQUALIZER_BAND_6,
345 .direct = EFX_DIR_OUT,
346 .def_val = 0x00000000
348 { .name = "EQ Band7",
349 .parent_nid = EQUALIZER,
350 .nid = EQUALIZER_BAND_7,
353 .direct = EFX_DIR_OUT,
354 .def_val = 0x00000000
356 { .name = "EQ Band8",
357 .parent_nid = EQUALIZER,
358 .nid = EQUALIZER_BAND_8,
361 .direct = EFX_DIR_OUT,
362 .def_val = 0x00000000
364 { .name = "EQ Band9",
365 .parent_nid = EQUALIZER,
366 .nid = EQUALIZER_BAND_9,
369 .direct = EFX_DIR_OUT,
370 .def_val = 0x00000000
375 /* Voice FX Presets */
376 #define VOICEFX_MAX_PARAM_COUNT 9
382 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
385 struct ct_voicefx_preset {
386 char *name; /*preset name*/
387 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
390 static struct ct_voicefx ca0132_voicefx = {
391 .name = "VoiceFX Capture Switch",
394 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
397 static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
399 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
400 0x44FA0000, 0x3F800000, 0x3F800000,
401 0x3F800000, 0x00000000, 0x00000000 }
403 { .name = "Female2Male",
404 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
405 0x44FA0000, 0x3F19999A, 0x3F866666,
406 0x3F800000, 0x00000000, 0x00000000 }
408 { .name = "Male2Female",
409 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
410 0x450AC000, 0x4017AE14, 0x3F6B851F,
411 0x3F800000, 0x00000000, 0x00000000 }
413 { .name = "ScrappyKid",
414 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
415 0x44FA0000, 0x40400000, 0x3F28F5C3,
416 0x3F800000, 0x00000000, 0x00000000 }
419 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
420 0x44E10000, 0x3FB33333, 0x3FB9999A,
421 0x3F800000, 0x3E3A2E43, 0x00000000 }
424 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
425 0x45098000, 0x3F266666, 0x3FC00000,
426 0x3F800000, 0x00000000, 0x00000000 }
429 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
430 0x45193000, 0x3F8E147B, 0x3F75C28F,
431 0x3F800000, 0x00000000, 0x00000000 }
434 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
435 0x45007000, 0x3F451EB8, 0x3F7851EC,
436 0x3F800000, 0x00000000, 0x00000000 }
438 { .name = "AlienBrute",
439 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
440 0x451F6000, 0x3F266666, 0x3FA7D945,
441 0x3F800000, 0x3CF5C28F, 0x00000000 }
444 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
445 0x44FA0000, 0x3FB2718B, 0x3F800000,
446 0xBC07010E, 0x00000000, 0x00000000 }
449 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
450 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
451 0x3F0A3D71, 0x00000000, 0x00000000 }
454 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
455 0x44FA0000, 0x3F800000, 0x3F800000,
456 0x3E4CCCCD, 0x00000000, 0x00000000 }
458 { .name = "DeepVoice",
459 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
460 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
461 0x3F800000, 0x00000000, 0x00000000 }
463 { .name = "Munchkin",
464 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
465 0x44FA0000, 0x3F800000, 0x3F1A043C,
466 0x3F800000, 0x00000000, 0x00000000 }
470 enum hda_cmd_vendor_io {
472 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
473 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
475 VENDOR_DSPIO_STATUS = 0xF01,
476 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
477 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
478 VENDOR_DSPIO_DSP_INIT = 0x703,
479 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
480 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
482 /* for ChipIO node */
483 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
484 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
485 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
486 VENDOR_CHIPIO_DATA_LOW = 0x300,
487 VENDOR_CHIPIO_DATA_HIGH = 0x400,
489 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
490 VENDOR_CHIPIO_STATUS = 0xF01,
491 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
492 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
494 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
495 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
497 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
498 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
500 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
501 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
502 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
503 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
504 VENDOR_CHIPIO_FLAG_SET = 0x70F,
505 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
506 VENDOR_CHIPIO_PARAM_SET = 0x710,
507 VENDOR_CHIPIO_PARAM_GET = 0xF10,
509 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
510 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
511 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
512 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
514 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
515 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
516 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
517 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
519 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
520 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
521 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
522 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
523 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
524 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
526 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
532 enum control_flag_id {
533 /* Connection manager stream setup is bypassed/enabled */
534 CONTROL_FLAG_C_MGR = 0,
535 /* DSP DMA is bypassed/enabled */
536 CONTROL_FLAG_DMA = 1,
537 /* 8051 'idle' mode is disabled/enabled */
538 CONTROL_FLAG_IDLE_ENABLE = 2,
539 /* Tracker for the SPDIF-in path is bypassed/enabled */
540 CONTROL_FLAG_TRACKER = 3,
541 /* DigitalOut to Spdif2Out connection is disabled/enabled */
542 CONTROL_FLAG_SPDIF2OUT = 4,
543 /* Digital Microphone is disabled/enabled */
544 CONTROL_FLAG_DMIC = 5,
545 /* ADC_B rate is 48 kHz/96 kHz */
546 CONTROL_FLAG_ADC_B_96KHZ = 6,
547 /* ADC_C rate is 48 kHz/96 kHz */
548 CONTROL_FLAG_ADC_C_96KHZ = 7,
549 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
550 CONTROL_FLAG_DAC_96KHZ = 8,
551 /* DSP rate is 48 kHz/96 kHz */
552 CONTROL_FLAG_DSP_96KHZ = 9,
553 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
554 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
555 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
556 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
557 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
558 CONTROL_FLAG_DECODE_LOOP = 12,
559 /* De-emphasis filter on DAC-1 disabled/enabled */
560 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
561 /* De-emphasis filter on DAC-2 disabled/enabled */
562 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
563 /* De-emphasis filter on DAC-3 disabled/enabled */
564 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
565 /* High-pass filter on ADC_B disabled/enabled */
566 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
567 /* High-pass filter on ADC_C disabled/enabled */
568 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
569 /* Common mode on Port_A disabled/enabled */
570 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
571 /* Common mode on Port_D disabled/enabled */
572 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
573 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
574 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
575 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
576 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
577 /* ASI rate is 48kHz/96kHz */
578 CONTROL_FLAG_ASI_96KHZ = 22,
579 /* DAC power settings able to control attached ports no/yes */
580 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
581 /* Clock Stop OK reporting is disabled/enabled */
582 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
583 /* Number of control flags */
584 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
588 * Control parameter IDs
590 enum control_param_id {
591 /* 0: None, 1: Mic1In*/
592 CONTROL_PARAM_VIP_SOURCE = 1,
593 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
594 CONTROL_PARAM_SPDIF1_SOURCE = 2,
595 /* Port A output stage gain setting to use when 16 Ohm output
596 * impedance is selected*/
597 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
598 /* Port D output stage gain setting to use when 16 Ohm output
599 * impedance is selected*/
600 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
604 /* Select stream with the given ID */
605 CONTROL_PARAM_STREAM_ID = 24,
606 /* Source connection point for the selected stream */
607 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
608 /* Destination connection point for the selected stream */
609 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
610 /* Number of audio channels in the selected stream */
611 CONTROL_PARAM_STREAMS_CHANNELS = 27,
612 /*Enable control for the selected stream */
613 CONTROL_PARAM_STREAM_CONTROL = 28,
615 /* Connection Point Control */
617 /* Select connection point with the given ID */
618 CONTROL_PARAM_CONN_POINT_ID = 29,
619 /* Connection point sample rate */
620 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
624 /* Select HDA node with the given ID */
625 CONTROL_PARAM_NODE_ID = 31
629 * Dsp Io Status codes
631 enum hda_vendor_status_dspio {
633 VENDOR_STATUS_DSPIO_OK = 0x00,
634 /* Busy, unable to accept new command, the host must retry */
635 VENDOR_STATUS_DSPIO_BUSY = 0x01,
636 /* SCP command queue is full */
637 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
638 /* SCP response queue is empty */
639 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
643 * Chip Io Status codes
645 enum hda_vendor_status_chipio {
647 VENDOR_STATUS_CHIPIO_OK = 0x00,
648 /* Busy, unable to accept new command, the host must retry */
649 VENDOR_STATUS_CHIPIO_BUSY = 0x01
655 enum ca0132_sample_rate {
675 SR_RATE_UNKNOWN = 0x1F
678 enum dsp_download_state {
679 DSP_DOWNLOAD_FAILED = -1,
680 DSP_DOWNLOAD_INIT = 0,
685 /* retrieve parameters from hda format */
686 #define get_hdafmt_chs(fmt) (fmt & 0xf)
687 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
688 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
689 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
696 struct snd_kcontrol_new *mixers[5];
697 unsigned int num_mixers;
698 const struct hda_verb *base_init_verbs;
699 const struct hda_verb *base_exit_verbs;
700 const struct hda_verb *init_verbs[5];
701 unsigned int num_init_verbs; /* exclude base init verbs */
702 struct auto_pin_cfg autocfg;
704 /* Nodes configurations */
705 struct hda_multi_out multiout;
706 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
707 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
708 unsigned int num_outputs;
709 hda_nid_t input_pins[AUTO_PIN_LAST];
710 hda_nid_t adcs[AUTO_PIN_LAST];
713 unsigned int num_inputs;
714 hda_nid_t shared_mic_nid;
715 hda_nid_t shared_out_nid;
716 struct hda_pcm pcm_rec[5]; /* PCM information */
719 struct mutex chipio_mutex; /* chip access mutex */
722 /* DSP download related */
723 enum dsp_download_state dsp_state;
724 unsigned int dsp_stream_id;
725 unsigned int wait_scp;
726 unsigned int wait_scp_header;
727 unsigned int wait_num_data;
728 unsigned int scp_resp_header;
729 unsigned int scp_resp_data[4];
730 unsigned int scp_resp_count;
732 /* mixer and effects related */
733 unsigned char dmic_ctl;
736 long vnode_lvol[VNODES_COUNT];
737 long vnode_rvol[VNODES_COUNT];
738 long vnode_lswitch[VNODES_COUNT];
739 long vnode_rswitch[VNODES_COUNT];
740 long effects_switch[EFFECTS_COUNT];
744 #ifdef ENABLE_TUNING_CONTROLS
745 long cur_ctl_vals[TUNING_CTLS_COUNT];
750 * CA0132 codec access
752 unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
753 unsigned int verb, unsigned int parm, unsigned int *res)
755 unsigned int response;
756 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
759 return ((response == -1) ? -1 : 0);
762 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
763 unsigned short converter_format, unsigned int *res)
765 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
766 converter_format & 0xffff, res);
769 static int codec_set_converter_stream_channel(struct hda_codec *codec,
770 hda_nid_t nid, unsigned char stream,
771 unsigned char channel, unsigned int *res)
773 unsigned char converter_stream_channel = 0;
775 converter_stream_channel = (stream << 4) | (channel & 0x0f);
776 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
777 converter_stream_channel, res);
780 /* Chip access helper function */
781 static int chipio_send(struct hda_codec *codec,
788 /* send bits of data specified by reg */
790 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
792 if (res == VENDOR_STATUS_CHIPIO_OK)
799 * Write chip address through the vendor widget -- NOT protected by the Mutex!
801 static int chipio_write_address(struct hda_codec *codec,
802 unsigned int chip_addx)
804 struct ca0132_spec *spec = codec->spec;
807 if (spec->curr_chip_addx == chip_addx)
810 /* send low 16 bits of the address */
811 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
815 /* send high 16 bits of the address */
816 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
820 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
826 * Write data through the vendor widget -- NOT protected by the Mutex!
828 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
830 struct ca0132_spec *spec = codec->spec;
833 /* send low 16 bits of the data */
834 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
837 /* send high 16 bits of the data */
838 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
842 /*If no error encountered, automatically increment the address
843 as per chip behaviour*/
844 spec->curr_chip_addx = (res != -EIO) ?
845 (spec->curr_chip_addx + 4) : ~0UL;
850 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
852 static int chipio_write_data_multiple(struct hda_codec *codec,
859 snd_printdd(KERN_ERR "chipio_write_data null ptr");
863 while ((count-- != 0) && (status == 0))
864 status = chipio_write_data(codec, *data++);
871 * Read data through the vendor widget -- NOT protected by the Mutex!
873 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
875 struct ca0132_spec *spec = codec->spec;
879 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
883 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
888 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
889 VENDOR_CHIPIO_HIC_READ_DATA,
893 /*If no error encountered, automatically increment the address
894 as per chip behaviour*/
895 spec->curr_chip_addx = (res != -EIO) ?
896 (spec->curr_chip_addx + 4) : ~0UL;
901 * Write given value to the given address through the chip I/O widget.
902 * protected by the Mutex
904 static int chipio_write(struct hda_codec *codec,
905 unsigned int chip_addx, const unsigned int data)
907 struct ca0132_spec *spec = codec->spec;
910 mutex_lock(&spec->chipio_mutex);
912 /* write the address, and if successful proceed to write data */
913 err = chipio_write_address(codec, chip_addx);
917 err = chipio_write_data(codec, data);
922 mutex_unlock(&spec->chipio_mutex);
927 * Write multiple values to the given address through the chip I/O widget.
928 * protected by the Mutex
930 static int chipio_write_multiple(struct hda_codec *codec,
935 struct ca0132_spec *spec = codec->spec;
938 mutex_lock(&spec->chipio_mutex);
939 status = chipio_write_address(codec, chip_addx);
943 status = chipio_write_data_multiple(codec, data, count);
945 mutex_unlock(&spec->chipio_mutex);
951 * Read the given address through the chip I/O widget
952 * protected by the Mutex
954 static int chipio_read(struct hda_codec *codec,
955 unsigned int chip_addx, unsigned int *data)
957 struct ca0132_spec *spec = codec->spec;
960 mutex_lock(&spec->chipio_mutex);
962 /* write the address, and if successful proceed to write data */
963 err = chipio_write_address(codec, chip_addx);
967 err = chipio_read_data(codec, data);
972 mutex_unlock(&spec->chipio_mutex);
977 * Set chip control flags through the chip I/O widget.
979 static void chipio_set_control_flag(struct hda_codec *codec,
980 enum control_flag_id flag_id,
984 unsigned int flag_bit;
986 flag_bit = (flag_state ? 1 : 0);
987 val = (flag_bit << 7) | (flag_id);
988 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
989 VENDOR_CHIPIO_FLAG_SET, val);
993 * Set chip parameters through the chip I/O widget.
995 static void chipio_set_control_param(struct hda_codec *codec,
996 enum control_param_id param_id, int param_val)
998 struct ca0132_spec *spec = codec->spec;
1001 if ((param_id < 32) && (param_val < 8)) {
1002 val = (param_val << 5) | (param_id);
1003 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1004 VENDOR_CHIPIO_PARAM_SET, val);
1006 mutex_lock(&spec->chipio_mutex);
1007 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1008 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1009 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1011 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1012 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1015 mutex_unlock(&spec->chipio_mutex);
1020 * Set sampling rate of the connection point.
1022 static void chipio_set_conn_rate(struct hda_codec *codec,
1023 int connid, enum ca0132_sample_rate rate)
1025 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1026 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1033 static void chipio_enable_clocks(struct hda_codec *codec)
1035 struct ca0132_spec *spec = codec->spec;
1037 mutex_lock(&spec->chipio_mutex);
1038 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1039 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1040 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1041 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1042 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1043 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1044 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1045 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1046 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1047 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1048 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1049 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1050 mutex_unlock(&spec->chipio_mutex);
1054 * CA0132 DSP IO stuffs
1056 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1062 /* send bits of data specified by reg to dsp */
1064 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1065 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1073 * Wait for DSP to be ready for commands
1075 static void dspio_write_wait(struct hda_codec *codec)
1078 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1081 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1082 VENDOR_DSPIO_STATUS, 0);
1083 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1084 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1087 } while (time_before(jiffies, timeout));
1091 * Write SCP data to DSP
1093 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1095 struct ca0132_spec *spec = codec->spec;
1098 dspio_write_wait(codec);
1100 mutex_lock(&spec->chipio_mutex);
1101 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1106 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1111 /* OK, now check if the write itself has executed*/
1112 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1113 VENDOR_DSPIO_STATUS, 0);
1115 mutex_unlock(&spec->chipio_mutex);
1117 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1122 * Write multiple SCP data to DSP
1124 static int dspio_write_multiple(struct hda_codec *codec,
1125 unsigned int *buffer, unsigned int size)
1130 if ((buffer == NULL))
1134 while (count < size) {
1135 status = dspio_write(codec, *buffer++);
1144 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1148 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1152 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1153 if (status == -EIO ||
1154 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1157 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1158 VENDOR_DSPIO_SCP_READ_DATA, 0);
1163 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1164 unsigned int *buf_size, unsigned int size_count)
1167 unsigned int size = *buf_size;
1169 unsigned int skip_count;
1172 if ((buffer == NULL))
1176 while (count < size && count < size_count) {
1177 status = dspio_read(codec, buffer++);
1185 while (skip_count < size) {
1186 status = dspio_read(codec, &dummy);
1198 * Construct the SCP header using corresponding fields
1200 static inline unsigned int
1201 make_scp_header(unsigned int target_id, unsigned int source_id,
1202 unsigned int get_flag, unsigned int req,
1203 unsigned int device_flag, unsigned int resp_flag,
1204 unsigned int error_flag, unsigned int data_size)
1206 unsigned int header = 0;
1208 header = (data_size & 0x1f) << 27;
1209 header |= (error_flag & 0x01) << 26;
1210 header |= (resp_flag & 0x01) << 25;
1211 header |= (device_flag & 0x01) << 24;
1212 header |= (req & 0x7f) << 17;
1213 header |= (get_flag & 0x01) << 16;
1214 header |= (source_id & 0xff) << 8;
1215 header |= target_id & 0xff;
1221 * Extract corresponding fields from SCP header
1224 extract_scp_header(unsigned int header,
1225 unsigned int *target_id, unsigned int *source_id,
1226 unsigned int *get_flag, unsigned int *req,
1227 unsigned int *device_flag, unsigned int *resp_flag,
1228 unsigned int *error_flag, unsigned int *data_size)
1231 *data_size = (header >> 27) & 0x1f;
1233 *error_flag = (header >> 26) & 0x01;
1235 *resp_flag = (header >> 25) & 0x01;
1237 *device_flag = (header >> 24) & 0x01;
1239 *req = (header >> 17) & 0x7f;
1241 *get_flag = (header >> 16) & 0x01;
1243 *source_id = (header >> 8) & 0xff;
1245 *target_id = header & 0xff;
1248 #define SCP_MAX_DATA_WORDS (16)
1250 /* Structure to contain any SCP message */
1253 unsigned int data[SCP_MAX_DATA_WORDS];
1256 static void dspio_clear_response_queue(struct hda_codec *codec)
1258 unsigned int dummy = 0;
1261 /* clear all from the response queue */
1263 status = dspio_read(codec, &dummy);
1264 } while (status == 0);
1267 static int dspio_get_response_data(struct hda_codec *codec)
1269 struct ca0132_spec *spec = codec->spec;
1270 unsigned int data = 0;
1273 if (dspio_read(codec, &data) < 0)
1276 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1277 spec->scp_resp_header = data;
1278 spec->scp_resp_count = data >> 27;
1279 count = spec->wait_num_data;
1280 dspio_read_multiple(codec, spec->scp_resp_data,
1281 &spec->scp_resp_count, count);
1289 * Send SCP message to DSP
1291 static int dspio_send_scp_message(struct hda_codec *codec,
1292 unsigned char *send_buf,
1293 unsigned int send_buf_size,
1294 unsigned char *return_buf,
1295 unsigned int return_buf_size,
1296 unsigned int *bytes_returned)
1298 struct ca0132_spec *spec = codec->spec;
1301 unsigned int scp_send_size = 0;
1302 unsigned int total_size;
1303 bool waiting_for_resp = false;
1304 unsigned int header;
1305 struct scp_msg *ret_msg;
1306 unsigned int resp_src_id, resp_target_id;
1307 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1310 *bytes_returned = 0;
1312 /* get scp header from buffer */
1313 header = *((unsigned int *)send_buf);
1314 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1315 &device_flag, NULL, NULL, &data_size);
1316 scp_send_size = data_size + 1;
1317 total_size = (scp_send_size * 4);
1319 if (send_buf_size < total_size)
1322 if (get_flag || device_flag) {
1323 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1326 spec->wait_scp_header = *((unsigned int *)send_buf);
1328 /* swap source id with target id */
1329 resp_target_id = src_id;
1330 resp_src_id = target_id;
1331 spec->wait_scp_header &= 0xffff0000;
1332 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1333 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1335 waiting_for_resp = true;
1338 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1345 if (waiting_for_resp) {
1346 memset(return_buf, 0, return_buf_size);
1350 } while (spec->wait_scp && (--retry != 0));
1351 waiting_for_resp = false;
1353 ret_msg = (struct scp_msg *)return_buf;
1354 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1355 memcpy(&ret_msg->data, spec->scp_resp_data,
1356 spec->wait_num_data);
1357 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1369 * Prepare and send the SCP message to DSP
1370 * @codec: the HDA codec
1371 * @mod_id: ID of the DSP module to send the command
1372 * @req: ID of request to send to the DSP module
1374 * @data: pointer to the data to send with the request, request specific
1375 * @len: length of the data, in bytes
1376 * @reply: point to the buffer to hold data returned for a reply
1377 * @reply_len: length of the reply buffer returned from GET
1379 * Returns zero or a negative error code.
1381 static int dspio_scp(struct hda_codec *codec,
1382 int mod_id, int req, int dir, void *data, unsigned int len,
1383 void *reply, unsigned int *reply_len)
1386 struct scp_msg scp_send, scp_reply;
1387 unsigned int ret_bytes, send_size, ret_size;
1388 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1389 unsigned int reply_data_size;
1391 memset(&scp_send, 0, sizeof(scp_send));
1392 memset(&scp_reply, 0, sizeof(scp_reply));
1394 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1397 if (dir == SCP_GET && reply == NULL) {
1398 snd_printdd(KERN_ERR "dspio_scp get but has no buffer");
1402 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1403 snd_printdd(KERN_ERR "dspio_scp bad resp buf len parms");
1407 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1408 0, 0, 0, len/sizeof(unsigned int));
1409 if (data != NULL && len > 0) {
1410 len = min((unsigned int)(sizeof(scp_send.data)), len);
1411 memcpy(scp_send.data, data, len);
1415 send_size = sizeof(unsigned int) + len;
1416 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1417 send_size, (unsigned char *)&scp_reply,
1418 sizeof(scp_reply), &ret_bytes);
1421 snd_printdd(KERN_ERR "dspio_scp: send scp msg failed");
1425 /* extract send and reply headers members */
1426 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1427 NULL, NULL, NULL, NULL, NULL);
1428 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1429 &reply_resp_flag, &reply_error_flag,
1435 if (reply_resp_flag && !reply_error_flag) {
1436 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1437 / sizeof(unsigned int);
1439 if (*reply_len < ret_size*sizeof(unsigned int)) {
1440 snd_printdd(KERN_ERR "reply too long for buf");
1442 } else if (ret_size != reply_data_size) {
1443 snd_printdd(KERN_ERR "RetLen and HdrLen .NE.");
1446 *reply_len = ret_size*sizeof(unsigned int);
1447 memcpy(reply, scp_reply.data, *reply_len);
1450 snd_printdd(KERN_ERR "reply ill-formed or errflag set");
1458 * Set DSP parameters
1460 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1461 int req, void *data, unsigned int len)
1463 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1466 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1467 int req, unsigned int data)
1469 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1473 * Allocate a DSP DMA channel via an SCP message
1475 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1478 unsigned int size = sizeof(dma_chan);
1480 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- begin");
1481 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1482 SCP_GET, NULL, 0, dma_chan, &size);
1485 snd_printdd(KERN_INFO "dspio_alloc_dma_chan: SCP Failed");
1489 if ((*dma_chan + 1) == 0) {
1490 snd_printdd(KERN_INFO "no free dma channels to allocate");
1494 snd_printdd("dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1495 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- complete");
1501 * Free a DSP DMA via an SCP message
1503 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1506 unsigned int dummy = 0;
1508 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- begin");
1509 snd_printdd("dspio_free_dma_chan: chan=%d\n", dma_chan);
1511 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1512 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1515 snd_printdd(KERN_INFO "dspio_free_dma_chan: SCP Failed");
1519 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- complete");
1527 static int dsp_set_run_state(struct hda_codec *codec)
1529 unsigned int dbg_ctrl_reg;
1530 unsigned int halt_state;
1533 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1537 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1538 DSP_DBGCNTL_STATE_LOBIT;
1540 if (halt_state != 0) {
1541 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1542 DSP_DBGCNTL_SS_MASK);
1543 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1548 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1549 DSP_DBGCNTL_EXEC_MASK;
1550 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1562 static int dsp_reset(struct hda_codec *codec)
1567 snd_printdd("dsp_reset\n");
1569 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1571 } while (res == -EIO && retry);
1574 snd_printdd("dsp_reset timeout\n");
1582 * Convert chip address to DSP address
1584 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1585 bool *code, bool *yram)
1587 *code = *yram = false;
1589 if (UC_RANGE(chip_addx, 1)) {
1591 return UC_OFF(chip_addx);
1592 } else if (X_RANGE_ALL(chip_addx, 1)) {
1593 return X_OFF(chip_addx);
1594 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1596 return Y_OFF(chip_addx);
1599 return (unsigned int)INVALID_CHIP_ADDRESS;
1603 * Check if the DSP DMA is active
1605 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1607 unsigned int dma_chnlstart_reg;
1609 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1611 return ((dma_chnlstart_reg & (1 <<
1612 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1615 static int dsp_dma_setup_common(struct hda_codec *codec,
1616 unsigned int chip_addx,
1617 unsigned int dma_chan,
1618 unsigned int port_map_mask,
1622 unsigned int chnl_prop;
1623 unsigned int dsp_addx;
1624 unsigned int active;
1627 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Begin ---------");
1629 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1630 snd_printdd(KERN_ERR "dma chan num invalid");
1634 if (dsp_is_dma_active(codec, dma_chan)) {
1635 snd_printdd(KERN_ERR "dma already active");
1639 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1641 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1642 snd_printdd(KERN_ERR "invalid chip addr");
1646 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1649 snd_printdd(KERN_INFO " dsp_dma_setup_common() start reg pgm");
1652 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1656 snd_printdd(KERN_ERR "read CHNLPROP Reg fail");
1659 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read CHNLPROP");
1663 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1665 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1667 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1669 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1671 snd_printdd(KERN_ERR "write CHNLPROP Reg fail");
1674 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write CHNLPROP");
1677 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1681 snd_printdd(KERN_ERR "read ACTIVE Reg fail");
1684 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read ACTIVE");
1687 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1688 DSPDMAC_ACTIVE_AAR_MASK;
1690 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1692 snd_printdd(KERN_ERR "write ACTIVE Reg fail");
1696 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write ACTIVE");
1698 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1701 snd_printdd(KERN_ERR "write AUDCHSEL Reg fail");
1704 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write AUDCHSEL");
1706 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1707 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1709 snd_printdd(KERN_ERR "write IRQCNT Reg fail");
1712 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write IRQCNT");
1715 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1716 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1717 chip_addx, dsp_addx, dma_chan,
1718 port_map_mask, chnl_prop, active);
1720 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Complete ------");
1726 * Setup the DSP DMA per-transfer-specific registers
1728 static int dsp_dma_setup(struct hda_codec *codec,
1729 unsigned int chip_addx,
1731 unsigned int dma_chan)
1735 unsigned int dsp_addx;
1736 unsigned int addr_field;
1737 unsigned int incr_field;
1738 unsigned int base_cnt;
1739 unsigned int cur_cnt;
1740 unsigned int dma_cfg = 0;
1741 unsigned int adr_ofs = 0;
1742 unsigned int xfr_cnt = 0;
1743 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1744 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1746 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Begin ---------");
1748 if (count > max_dma_count) {
1749 snd_printdd(KERN_ERR "count too big");
1753 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1754 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1755 snd_printdd(KERN_ERR "invalid chip addr");
1759 snd_printdd(KERN_INFO " dsp_dma_setup() start reg pgm");
1761 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1767 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1769 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1772 dma_cfg = addr_field + incr_field;
1773 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1776 snd_printdd(KERN_ERR "write DMACFG Reg fail");
1779 snd_printdd(KERN_INFO " dsp_dma_setup() Write DMACFG");
1781 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1784 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1787 snd_printdd(KERN_ERR "write DSPADROFS Reg fail");
1790 snd_printdd(KERN_INFO " dsp_dma_setup() Write DSPADROFS");
1792 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1794 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1796 xfr_cnt = base_cnt | cur_cnt;
1798 status = chipio_write(codec,
1799 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1801 snd_printdd(KERN_ERR "write XFRCNT Reg fail");
1804 snd_printdd(KERN_INFO " dsp_dma_setup() Write XFRCNT");
1807 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1808 "ADROFS=0x%x, XFRCNT=0x%x\n",
1809 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1811 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Complete ---------");
1819 static int dsp_dma_start(struct hda_codec *codec,
1820 unsigned int dma_chan, bool ovly)
1822 unsigned int reg = 0;
1825 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Begin ---------");
1828 status = chipio_read(codec,
1829 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
1832 snd_printdd(KERN_ERR "read CHNLSTART reg fail");
1835 snd_printdd(KERN_INFO "-- dsp_dma_start() Read CHNLSTART");
1837 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1838 DSPDMAC_CHNLSTART_DIS_MASK);
1841 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1842 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1844 snd_printdd(KERN_ERR "write CHNLSTART reg fail");
1847 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Complete ---------");
1855 static int dsp_dma_stop(struct hda_codec *codec,
1856 unsigned int dma_chan, bool ovly)
1858 unsigned int reg = 0;
1861 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Begin ---------");
1864 status = chipio_read(codec,
1865 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
1868 snd_printdd(KERN_ERR "read CHNLSTART reg fail");
1871 snd_printdd(KERN_INFO "-- dsp_dma_stop() Read CHNLSTART");
1872 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1873 DSPDMAC_CHNLSTART_DIS_MASK);
1876 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1877 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1879 snd_printdd(KERN_ERR "write CHNLSTART reg fail");
1882 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Complete ---------");
1888 * Allocate router ports
1890 * @codec: the HDA codec
1891 * @num_chans: number of channels in the stream
1892 * @ports_per_channel: number of ports per channel
1893 * @start_device: start device
1894 * @port_map: pointer to the port list to hold the allocated ports
1896 * Returns zero or a negative error code.
1898 static int dsp_allocate_router_ports(struct hda_codec *codec,
1899 unsigned int num_chans,
1900 unsigned int ports_per_channel,
1901 unsigned int start_device,
1902 unsigned int *port_map)
1908 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1912 val = start_device << 6;
1913 val |= (ports_per_channel - 1) << 4;
1914 val |= num_chans - 1;
1916 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1917 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1920 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1921 VENDOR_CHIPIO_PORT_ALLOC_SET,
1924 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1928 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1929 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1933 return (res < 0) ? res : 0;
1939 static int dsp_free_router_ports(struct hda_codec *codec)
1943 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1947 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1948 VENDOR_CHIPIO_PORT_FREE_SET,
1951 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1957 * Allocate DSP ports for the download stream
1959 static int dsp_allocate_ports(struct hda_codec *codec,
1960 unsigned int num_chans,
1961 unsigned int rate_multi, unsigned int *port_map)
1965 snd_printdd(KERN_INFO " dsp_allocate_ports() -- begin");
1967 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1968 snd_printdd(KERN_ERR "bad rate multiple");
1972 status = dsp_allocate_router_ports(codec, num_chans,
1973 rate_multi, 0, port_map);
1975 snd_printdd(KERN_INFO " dsp_allocate_ports() -- complete");
1980 static int dsp_allocate_ports_format(struct hda_codec *codec,
1981 const unsigned short fmt,
1982 unsigned int *port_map)
1985 unsigned int num_chans;
1987 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
1988 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
1989 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
1991 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1992 snd_printdd(KERN_ERR "bad rate multiple");
1996 num_chans = get_hdafmt_chs(fmt) + 1;
1998 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2006 static int dsp_free_ports(struct hda_codec *codec)
2010 snd_printdd(KERN_INFO " dsp_free_ports() -- begin");
2012 status = dsp_free_router_ports(codec);
2014 snd_printdd(KERN_ERR "free router ports fail");
2017 snd_printdd(KERN_INFO " dsp_free_ports() -- complete");
2023 * HDA DMA engine stuffs for DSP code download
2026 struct hda_codec *codec;
2027 unsigned short m_converter_format;
2028 struct snd_dma_buffer *dmab;
2029 unsigned int buf_size;
2038 static int dma_convert_to_hda_format(
2039 unsigned int sample_rate,
2040 unsigned short channels,
2041 unsigned short *hda_format)
2043 unsigned int format_val;
2045 format_val = snd_hda_calc_stream_format(
2048 SNDRV_PCM_FORMAT_S32_LE,
2052 *hda_format = (unsigned short)format_val;
2058 * Reset DMA for DSP download
2060 static int dma_reset(struct dma_engine *dma)
2062 struct hda_codec *codec = dma->codec;
2063 struct ca0132_spec *spec = codec->spec;
2067 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2069 status = snd_hda_codec_load_dsp_prepare(codec,
2070 dma->m_converter_format,
2075 spec->dsp_stream_id = status;
2079 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2083 snd_printdd("dma_set_state state=%d\n", state);
2086 case DMA_STATE_STOP:
2096 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2100 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2102 return dma->dmab->bytes;
2105 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2107 return dma->dmab->area;
2110 static int dma_xfer(struct dma_engine *dma,
2111 const unsigned int *data,
2114 memcpy(dma->dmab->area, data, count);
2118 static void dma_get_converter_format(
2119 struct dma_engine *dma,
2120 unsigned short *format)
2123 *format = dma->m_converter_format;
2126 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2128 struct ca0132_spec *spec = dma->codec->spec;
2130 return spec->dsp_stream_id;
2133 struct dsp_image_seg {
2140 static const u32 g_magic_value = 0x4c46584d;
2141 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2143 static bool is_valid(const struct dsp_image_seg *p)
2145 return p->magic == g_magic_value;
2148 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2150 return g_chip_addr_magic_value == p->chip_addr;
2153 static bool is_last(const struct dsp_image_seg *p)
2155 return p->count == 0;
2158 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2160 return sizeof(*p) + p->count*sizeof(u32);
2163 static const struct dsp_image_seg *get_next_seg_ptr(
2164 const struct dsp_image_seg *p)
2166 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2170 * CA0132 chip DSP transfer stuffs. For DSP download.
2172 #define INVALID_DMA_CHANNEL (~0U)
2175 * Program a list of address/data pairs via the ChipIO widget.
2176 * The segment data is in the format of successive pairs of words.
2177 * These are repeated as indicated by the segment's count field.
2179 static int dspxfr_hci_write(struct hda_codec *codec,
2180 const struct dsp_image_seg *fls)
2186 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2187 snd_printdd(KERN_ERR "hci_write invalid params");
2192 data = (u32 *)(fls->data);
2193 while (count >= 2) {
2194 status = chipio_write(codec, data[0], data[1]);
2196 snd_printdd(KERN_ERR "hci_write chipio failed");
2206 * Write a block of data into DSP code or data RAM using pre-allocated
2209 * @codec: the HDA codec
2210 * @fls: pointer to a fast load image
2211 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2213 * @dma_engine: pointer to DMA engine to be used for DSP download
2214 * @dma_chan: The number of DMA channels used for DSP download
2215 * @port_map_mask: port mapping
2216 * @ovly: TRUE if overlay format is required
2218 * Returns zero or a negative error code.
2220 static int dspxfr_one_seg(struct hda_codec *codec,
2221 const struct dsp_image_seg *fls,
2223 struct dma_engine *dma_engine,
2224 unsigned int dma_chan,
2225 unsigned int port_map_mask,
2229 bool comm_dma_setup_done = false;
2230 const unsigned int *data;
2231 unsigned int chip_addx;
2232 unsigned int words_to_write;
2233 unsigned int buffer_size_words;
2234 unsigned char *buffer_addx;
2235 unsigned short hda_format;
2236 unsigned int sample_rate_div;
2237 unsigned int sample_rate_mul;
2238 unsigned int num_chans;
2239 unsigned int hda_frame_size_words;
2240 unsigned int remainder_words;
2241 const u32 *data_remainder;
2242 u32 chip_addx_remainder;
2243 unsigned int run_size_words;
2244 const struct dsp_image_seg *hci_write = NULL;
2249 if (is_hci_prog_list_seg(fls)) {
2251 fls = get_next_seg_ptr(fls);
2254 if (hci_write && (!fls || is_last(fls))) {
2255 snd_printdd("hci_write\n");
2256 return dspxfr_hci_write(codec, hci_write);
2259 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2260 snd_printdd("Invalid Params\n");
2265 chip_addx = fls->chip_addr,
2266 words_to_write = fls->count;
2268 if (!words_to_write)
2269 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2271 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2273 if (!UC_RANGE(chip_addx, words_to_write) &&
2274 !X_RANGE_ALL(chip_addx, words_to_write) &&
2275 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2276 snd_printdd("Invalid chip_addx Params\n");
2280 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2283 buffer_addx = dma_get_buffer_addr(dma_engine);
2285 if (buffer_addx == NULL) {
2286 snd_printdd(KERN_ERR "dma_engine buffer NULL\n");
2290 dma_get_converter_format(dma_engine, &hda_format);
2291 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2292 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2293 num_chans = get_hdafmt_chs(hda_format) + 1;
2295 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2296 (num_chans * sample_rate_mul / sample_rate_div));
2298 buffer_size_words = min(buffer_size_words,
2299 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2301 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2303 "chpadr=0x%08x frmsz=%u nchan=%u "
2304 "rate_mul=%u div=%u bufsz=%u\n",
2305 chip_addx, hda_frame_size_words, num_chans,
2306 sample_rate_mul, sample_rate_div, buffer_size_words);
2308 if ((buffer_addx == NULL) || (hda_frame_size_words == 0) ||
2309 (buffer_size_words < hda_frame_size_words)) {
2310 snd_printdd(KERN_ERR "dspxfr_one_seg:failed\n");
2314 remainder_words = words_to_write % hda_frame_size_words;
2315 data_remainder = data;
2316 chip_addx_remainder = chip_addx;
2318 data += remainder_words;
2319 chip_addx += remainder_words*sizeof(u32);
2320 words_to_write -= remainder_words;
2322 while (words_to_write != 0) {
2323 run_size_words = min(buffer_size_words, words_to_write);
2324 snd_printdd("dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2325 words_to_write, run_size_words, remainder_words);
2326 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2327 if (!comm_dma_setup_done) {
2328 status = dsp_dma_stop(codec, dma_chan, ovly);
2331 status = dsp_dma_setup_common(codec, chip_addx,
2332 dma_chan, port_map_mask, ovly);
2335 comm_dma_setup_done = true;
2338 status = dsp_dma_setup(codec, chip_addx,
2339 run_size_words, dma_chan);
2342 status = dsp_dma_start(codec, dma_chan, ovly);
2345 if (!dsp_is_dma_active(codec, dma_chan)) {
2346 snd_printdd(KERN_ERR "dspxfr:DMA did not start");
2349 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2352 if (remainder_words != 0) {
2353 status = chipio_write_multiple(codec,
2354 chip_addx_remainder,
2357 remainder_words = 0;
2360 status = dspxfr_hci_write(codec, hci_write);
2364 while (dsp_is_dma_active(codec, dma_chan)) {
2368 snd_printdd(KERN_INFO "+++++ DMA complete");
2369 dma_set_state(dma_engine, DMA_STATE_STOP);
2370 dma_reset(dma_engine);
2375 data += run_size_words;
2376 chip_addx += run_size_words*sizeof(u32);
2377 words_to_write -= run_size_words;
2380 if (remainder_words != 0) {
2381 status = chipio_write_multiple(codec, chip_addx_remainder,
2382 data_remainder, remainder_words);
2389 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2391 * @codec: the HDA codec
2392 * @fls_data: pointer to a fast load image
2393 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2395 * @sample_rate: sampling rate of the stream used for DSP download
2396 * @number_channels: channels of the stream used for DSP download
2397 * @ovly: TRUE if overlay format is required
2399 * Returns zero or a negative error code.
2401 static int dspxfr_image(struct hda_codec *codec,
2402 const struct dsp_image_seg *fls_data,
2404 unsigned int sample_rate,
2405 unsigned short channels,
2408 struct ca0132_spec *spec = codec->spec;
2410 unsigned short hda_format = 0;
2411 unsigned int response;
2412 unsigned char stream_id = 0;
2413 struct dma_engine *dma_engine;
2414 unsigned int dma_chan;
2415 unsigned int port_map_mask;
2417 if (fls_data == NULL)
2420 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2424 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2425 if (!dma_engine->dmab) {
2430 dma_engine->codec = codec;
2431 dma_convert_to_hda_format(sample_rate, channels, &hda_format);
2432 dma_engine->m_converter_format = hda_format;
2433 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2434 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2436 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2438 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2439 hda_format, &response);
2442 snd_printdd(KERN_ERR "set converter format fail");
2446 status = snd_hda_codec_load_dsp_prepare(codec,
2447 dma_engine->m_converter_format,
2448 dma_engine->buf_size,
2452 spec->dsp_stream_id = status;
2455 status = dspio_alloc_dma_chan(codec, &dma_chan);
2457 snd_printdd(KERN_ERR "alloc dmachan fail");
2458 dma_chan = INVALID_DMA_CHANNEL;
2464 status = dsp_allocate_ports_format(codec, hda_format,
2467 snd_printdd(KERN_ERR "alloc ports fail");
2471 stream_id = dma_get_stream_id(dma_engine);
2472 status = codec_set_converter_stream_channel(codec,
2473 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2475 snd_printdd(KERN_ERR "set stream chan fail");
2479 while ((fls_data != NULL) && !is_last(fls_data)) {
2480 if (!is_valid(fls_data)) {
2481 snd_printdd(KERN_ERR "FLS check fail");
2485 status = dspxfr_one_seg(codec, fls_data, reloc,
2486 dma_engine, dma_chan,
2487 port_map_mask, ovly);
2491 if (is_hci_prog_list_seg(fls_data))
2492 fls_data = get_next_seg_ptr(fls_data);
2494 if ((fls_data != NULL) && !is_last(fls_data))
2495 fls_data = get_next_seg_ptr(fls_data);
2498 if (port_map_mask != 0)
2499 status = dsp_free_ports(codec);
2504 status = codec_set_converter_stream_channel(codec,
2505 WIDGET_CHIP_CTRL, 0, 0, &response);
2508 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2509 dspio_free_dma_chan(codec, dma_chan);
2511 if (dma_engine->dmab)
2512 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2513 kfree(dma_engine->dmab);
2520 * CA0132 DSP download stuffs.
2522 static void dspload_post_setup(struct hda_codec *codec)
2524 snd_printdd(KERN_INFO "---- dspload_post_setup ------");
2526 /*set DSP speaker to 2.0 configuration*/
2527 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2528 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2530 /*update write pointer*/
2531 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2535 * Download DSP from a DSP Image Fast Load structure. This structure is a
2536 * linear, non-constant sized element array of structures, each of which
2537 * contain the count of the data to be loaded, the data itself, and the
2538 * corresponding starting chip address of the starting data location.
2540 * @codec: the HDA codec
2541 * @fls: pointer to a fast load image
2542 * @ovly: TRUE if overlay format is required
2543 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2545 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2546 * @router_chans: number of audio router channels to be allocated (0 means use
2547 * internal defaults; max is 32)
2549 * Returns zero or a negative error code.
2551 static int dspload_image(struct hda_codec *codec,
2552 const struct dsp_image_seg *fls,
2559 unsigned int sample_rate;
2560 unsigned short channels;
2562 snd_printdd(KERN_INFO "---- dspload_image begin ------");
2563 if (router_chans == 0) {
2565 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2567 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2570 sample_rate = 48000;
2571 channels = (unsigned short)router_chans;
2573 while (channels > 16) {
2579 snd_printdd(KERN_INFO "Ready to program DMA");
2581 status = dsp_reset(codec);
2586 snd_printdd(KERN_INFO "dsp_reset() complete");
2587 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2593 snd_printdd(KERN_INFO "dspxfr_image() complete");
2594 if (autostart && !ovly) {
2595 dspload_post_setup(codec);
2596 status = dsp_set_run_state(codec);
2599 snd_printdd(KERN_INFO "LOAD FINISHED");
2605 static bool dspload_is_loaded(struct hda_codec *codec)
2607 unsigned int data = 0;
2610 status = chipio_read(codec, 0x40004, &data);
2611 if ((status < 0) || (data != 1))
2617 static bool dspload_wait_loaded(struct hda_codec *codec)
2623 if (dspload_is_loaded(codec)) {
2624 pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n");
2629 pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2636 static void ca0132_setup_stream(struct hda_codec *codec, hda_nid_t nid,
2638 int channel_id, int format)
2640 unsigned int oldval, newval;
2646 "ca0132_setup_stream: NID=0x%x, stream=0x%x, "
2647 "channel=%d, format=0x%x\n",
2648 nid, stream_tag, channel_id, format);
2650 /* update the format-id if changed */
2651 oldval = snd_hda_codec_read(codec, nid, 0,
2652 AC_VERB_GET_STREAM_FORMAT,
2654 if (oldval != format) {
2656 snd_hda_codec_write(codec, nid, 0,
2657 AC_VERB_SET_STREAM_FORMAT,
2661 oldval = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
2662 newval = (stream_tag << 4) | channel_id;
2663 if (oldval != newval) {
2664 snd_hda_codec_write(codec, nid, 0,
2665 AC_VERB_SET_CHANNEL_STREAMID,
2670 static void ca0132_cleanup_stream(struct hda_codec *codec, hda_nid_t nid)
2677 snd_printdd(KERN_INFO "ca0132_cleanup_stream: NID=0x%x\n", nid);
2679 val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
2683 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_STREAM_FORMAT, 0);
2684 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2690 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2691 struct hda_codec *codec,
2692 unsigned int stream_tag,
2693 unsigned int format,
2694 struct snd_pcm_substream *substream)
2696 struct ca0132_spec *spec = codec->spec;
2698 ca0132_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2703 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2704 struct hda_codec *codec,
2705 struct snd_pcm_substream *substream)
2707 struct ca0132_spec *spec = codec->spec;
2709 if (spec->dsp_state == DSP_DOWNLOADING)
2712 /*If Playback effects are on, allow stream some time to flush
2714 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2717 ca0132_cleanup_stream(codec, spec->dacs[0]);
2725 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2726 struct hda_codec *codec,
2727 struct snd_pcm_substream *substream)
2729 struct ca0132_spec *spec = codec->spec;
2730 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2733 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2734 struct hda_codec *codec,
2735 unsigned int stream_tag,
2736 unsigned int format,
2737 struct snd_pcm_substream *substream)
2739 struct ca0132_spec *spec = codec->spec;
2740 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2741 stream_tag, format, substream);
2744 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2745 struct hda_codec *codec,
2746 struct snd_pcm_substream *substream)
2748 struct ca0132_spec *spec = codec->spec;
2749 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
2752 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2753 struct hda_codec *codec,
2754 struct snd_pcm_substream *substream)
2756 struct ca0132_spec *spec = codec->spec;
2757 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2763 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2764 struct hda_codec *codec,
2765 unsigned int stream_tag,
2766 unsigned int format,
2767 struct snd_pcm_substream *substream)
2769 struct ca0132_spec *spec = codec->spec;
2771 ca0132_setup_stream(codec, spec->adcs[substream->number],
2772 stream_tag, 0, format);
2777 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2778 struct hda_codec *codec,
2779 struct snd_pcm_substream *substream)
2781 struct ca0132_spec *spec = codec->spec;
2783 if (spec->dsp_state == DSP_DOWNLOADING)
2786 ca0132_cleanup_stream(codec, hinfo->nid);
2795 * Mixer controls helpers.
2797 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2798 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2800 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2801 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2802 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2803 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2804 .info = ca0132_volume_info, \
2805 .get = ca0132_volume_get, \
2806 .put = ca0132_volume_put, \
2807 .tlv = { .c = ca0132_volume_tlv }, \
2808 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2810 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2811 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2813 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2814 .info = snd_hda_mixer_amp_switch_info, \
2815 .get = ca0132_switch_get, \
2816 .put = ca0132_switch_put, \
2817 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2820 #define CA0132_CODEC_VOL(xname, nid, dir) \
2821 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2822 #define CA0132_CODEC_MUTE(xname, nid, dir) \
2823 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2825 /* The followings are for tuning of products */
2826 #ifdef ENABLE_TUNING_CONTROLS
2828 static unsigned int voice_focus_vals_lookup[] = {
2829 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
2830 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
2831 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
2832 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
2833 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
2834 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
2835 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
2836 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
2837 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
2838 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
2839 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
2840 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
2841 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
2842 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
2843 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
2844 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
2845 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
2846 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
2847 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
2848 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
2849 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
2850 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
2851 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
2852 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
2853 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
2854 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
2855 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2858 static unsigned int mic_svm_vals_lookup[] = {
2859 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
2860 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
2861 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
2862 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
2863 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
2864 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
2865 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
2866 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
2867 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
2868 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
2869 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
2870 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
2871 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
2872 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
2873 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
2874 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
2875 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2878 static unsigned int equalizer_vals_lookup[] = {
2879 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
2880 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
2881 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
2882 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
2883 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
2884 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
2885 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
2886 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
2890 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2891 unsigned int *lookup, int idx)
2895 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2896 if (nid == ca0132_tuning_ctls[i].nid)
2899 snd_hda_power_up(codec);
2900 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2901 ca0132_tuning_ctls[i].req,
2902 &(lookup[idx]), sizeof(unsigned int));
2903 snd_hda_power_down(codec);
2908 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2909 struct snd_ctl_elem_value *ucontrol)
2911 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2912 struct ca0132_spec *spec = codec->spec;
2913 hda_nid_t nid = get_amp_nid(kcontrol);
2914 long *valp = ucontrol->value.integer.value;
2915 int idx = nid - TUNING_CTL_START_NID;
2917 *valp = spec->cur_ctl_vals[idx];
2921 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2922 struct snd_ctl_elem_info *uinfo)
2924 int chs = get_amp_channels(kcontrol);
2925 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2926 uinfo->count = chs == 3 ? 2 : 1;
2927 uinfo->value.integer.min = 20;
2928 uinfo->value.integer.max = 180;
2929 uinfo->value.integer.step = 1;
2934 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2935 struct snd_ctl_elem_value *ucontrol)
2937 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2938 struct ca0132_spec *spec = codec->spec;
2939 hda_nid_t nid = get_amp_nid(kcontrol);
2940 long *valp = ucontrol->value.integer.value;
2943 idx = nid - TUNING_CTL_START_NID;
2945 if (spec->cur_ctl_vals[idx] == *valp)
2948 spec->cur_ctl_vals[idx] = *valp;
2951 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2956 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
2957 struct snd_ctl_elem_info *uinfo)
2959 int chs = get_amp_channels(kcontrol);
2960 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2961 uinfo->count = chs == 3 ? 2 : 1;
2962 uinfo->value.integer.min = 0;
2963 uinfo->value.integer.max = 100;
2964 uinfo->value.integer.step = 1;
2969 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
2970 struct snd_ctl_elem_value *ucontrol)
2972 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2973 struct ca0132_spec *spec = codec->spec;
2974 hda_nid_t nid = get_amp_nid(kcontrol);
2975 long *valp = ucontrol->value.integer.value;
2978 idx = nid - TUNING_CTL_START_NID;
2980 if (spec->cur_ctl_vals[idx] == *valp)
2983 spec->cur_ctl_vals[idx] = *valp;
2986 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
2991 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
2992 struct snd_ctl_elem_info *uinfo)
2994 int chs = get_amp_channels(kcontrol);
2995 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2996 uinfo->count = chs == 3 ? 2 : 1;
2997 uinfo->value.integer.min = 0;
2998 uinfo->value.integer.max = 48;
2999 uinfo->value.integer.step = 1;
3004 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3005 struct snd_ctl_elem_value *ucontrol)
3007 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3008 struct ca0132_spec *spec = codec->spec;
3009 hda_nid_t nid = get_amp_nid(kcontrol);
3010 long *valp = ucontrol->value.integer.value;
3013 idx = nid - TUNING_CTL_START_NID;
3015 if (spec->cur_ctl_vals[idx] == *valp)
3018 spec->cur_ctl_vals[idx] = *valp;
3021 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3026 static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3027 static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3029 static int add_tuning_control(struct hda_codec *codec,
3030 hda_nid_t pnid, hda_nid_t nid,
3031 const char *name, int dir)
3034 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3035 struct snd_kcontrol_new knew =
3036 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3038 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3039 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3044 knew.info = voice_focus_ctl_info;
3045 knew.get = tuning_ctl_get;
3046 knew.put = voice_focus_ctl_put;
3047 knew.tlv.p = voice_focus_db_scale;
3050 knew.info = mic_svm_ctl_info;
3051 knew.get = tuning_ctl_get;
3052 knew.put = mic_svm_ctl_put;
3055 knew.info = equalizer_ctl_info;
3056 knew.get = tuning_ctl_get;
3057 knew.put = equalizer_ctl_put;
3058 knew.tlv.p = eq_db_scale;
3063 knew.private_value =
3064 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3065 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3066 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3069 static int add_tuning_ctls(struct hda_codec *codec)
3074 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3075 err = add_tuning_control(codec,
3076 ca0132_tuning_ctls[i].parent_nid,
3077 ca0132_tuning_ctls[i].nid,
3078 ca0132_tuning_ctls[i].name,
3079 ca0132_tuning_ctls[i].direct);
3087 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3089 struct ca0132_spec *spec = codec->spec;
3092 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3093 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3094 /* SVM level defaults to 0.74. */
3095 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3097 /* EQ defaults to 0dB. */
3098 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3099 spec->cur_ctl_vals[i] = 24;
3101 #endif /*ENABLE_TUNING_CONTROLS*/
3104 * Select the active output.
3105 * If autodetect is enabled, output will be selected based on jack detection.
3106 * If jack inserted, headphone will be selected, else built-in speakers
3107 * If autodetect is disabled, output will be selected based on selection.
3109 static int ca0132_select_out(struct hda_codec *codec)
3111 struct ca0132_spec *spec = codec->spec;
3112 unsigned int pin_ctl;
3118 snd_printdd(KERN_INFO "ca0132_select_out\n");
3120 snd_hda_power_up(codec);
3122 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3125 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]);
3128 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3131 spec->cur_out_type = HEADPHONE_OUT;
3133 spec->cur_out_type = SPEAKER_OUT;
3135 if (spec->cur_out_type == SPEAKER_OUT) {
3136 snd_printdd(KERN_INFO "ca0132_select_out speaker\n");
3137 /*speaker out config*/
3139 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3142 /*enable speaker EQ*/
3144 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3149 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3150 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3151 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3152 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3153 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3154 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3155 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3156 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3158 /* disable headphone node */
3159 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3160 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3161 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3163 /* enable speaker node */
3164 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3165 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3166 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3169 snd_printdd(KERN_INFO "ca0132_select_out hp\n");
3170 /*headphone out config*/
3172 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3175 /*disable speaker EQ*/
3177 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3182 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3183 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3184 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3185 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3186 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3187 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3188 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3189 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3191 /* disable speaker*/
3192 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3193 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3194 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3196 /* enable headphone*/
3197 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3198 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3199 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3204 snd_hda_power_down(codec);
3206 return err < 0 ? err : 0;
3209 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3210 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3211 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3214 * Select the active VIP source
3216 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3218 struct ca0132_spec *spec = codec->spec;
3221 if (!dspload_is_loaded(codec))
3224 /* if CrystalVoice if off, vipsource should be 0 */
3225 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3227 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3228 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3229 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3230 if (spec->cur_mic_type == DIGITAL_MIC)
3234 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3236 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3238 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3239 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3240 if (spec->cur_mic_type == DIGITAL_MIC)
3244 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3246 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3248 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3255 * Select the active microphone.
3256 * If autodetect is enabled, mic will be selected based on jack detection.
3257 * If jack inserted, ext.mic will be selected, else built-in mic
3258 * If autodetect is disabled, mic will be selected based on selection.
3260 static int ca0132_select_mic(struct hda_codec *codec)
3262 struct ca0132_spec *spec = codec->spec;
3266 snd_printdd(KERN_INFO "ca0132_select_mic\n");
3268 snd_hda_power_up(codec);
3270 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3273 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]);
3276 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3279 spec->cur_mic_type = LINE_MIC_IN;
3281 spec->cur_mic_type = DIGITAL_MIC;
3283 if (spec->cur_mic_type == DIGITAL_MIC) {
3284 /* enable digital Mic */
3285 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3286 ca0132_set_dmic(codec, 1);
3287 ca0132_mic_boost_set(codec, 0);
3288 /* set voice focus */
3289 ca0132_effects_set(codec, VOICE_FOCUS,
3290 spec->effects_switch
3291 [VOICE_FOCUS - EFFECT_START_NID]);
3293 /* disable digital Mic */
3294 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3295 ca0132_set_dmic(codec, 0);
3296 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3297 /* disable voice focus */
3298 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3301 snd_hda_power_down(codec);
3307 * Check if VNODE settings take effect immediately.
3309 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3311 hda_nid_t *shared_nid)
3313 struct ca0132_spec *spec = codec->spec;
3315 bool effective = false;
3319 nid = spec->shared_out_nid;
3323 nid = spec->shared_mic_nid;
3330 if (effective && shared_nid)
3337 * The following functions are control change helpers.
3338 * They return 0 if no changed. Return 1 if changed.
3340 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3342 struct ca0132_spec *spec = codec->spec;
3345 /* based on CrystalVoice state to enable VoiceFX. */
3347 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3348 FLOAT_ONE : FLOAT_ZERO;
3353 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3354 ca0132_voicefx.reqs[0], tmp);
3360 * Set the effects parameters
3362 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3364 struct ca0132_spec *spec = codec->spec;
3366 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3368 int idx = nid - EFFECT_START_NID;
3370 if ((idx < 0) || (idx >= num_fx))
3371 return 0; /* no changed */
3373 /* for out effect, qualify with PE */
3374 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3375 /* if PE if off, turn off out effects. */
3376 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3380 /* for in effect, qualify with CrystalVoice */
3381 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3382 /* if CrystalVoice if off, turn off in effects. */
3383 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3386 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3387 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3391 snd_printdd(KERN_INFO "ca0132_effect_set: nid=0x%x, val=%ld\n",
3394 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3395 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3396 ca0132_effects[idx].reqs[0], on);
3399 return 0; /* no changed */
3405 * Turn on/off Playback Enhancements
3407 static int ca0132_pe_switch_set(struct hda_codec *codec)
3409 struct ca0132_spec *spec = codec->spec;
3413 snd_printdd(KERN_INFO "ca0132_pe_switch_set: val=%ld\n",
3414 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3416 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3417 nid = OUT_EFFECT_START_NID;
3418 /* PE affects all out effects */
3419 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3420 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3425 /* Check if Mic1 is streaming, if so, stop streaming */
3426 static int stop_mic1(struct hda_codec *codec)
3428 struct ca0132_spec *spec = codec->spec;
3429 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3430 AC_VERB_GET_CONV, 0);
3432 snd_hda_codec_write(codec, spec->adcs[0], 0,
3433 AC_VERB_SET_CHANNEL_STREAMID,
3438 /* Resume Mic1 streaming if it was stopped. */
3439 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3441 struct ca0132_spec *spec = codec->spec;
3442 /* Restore the previous stream and channel */
3444 snd_hda_codec_write(codec, spec->adcs[0], 0,
3445 AC_VERB_SET_CHANNEL_STREAMID,
3450 * Turn on/off CrystalVoice
3452 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3454 struct ca0132_spec *spec = codec->spec;
3457 unsigned int oldval;
3459 snd_printdd(KERN_INFO "ca0132_cvoice_switch_set: val=%ld\n",
3460 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3462 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3463 nid = IN_EFFECT_START_NID;
3464 /* CrystalVoice affects all in effects */
3465 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3466 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3468 /* including VoiceFX */
3469 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3471 /* set correct vipsource */
3472 oldval = stop_mic1(codec);
3473 ret |= ca0132_set_vipsource(codec, 1);
3474 resume_mic1(codec, oldval);
3478 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3480 struct ca0132_spec *spec = codec->spec;
3484 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3485 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3487 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3488 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3493 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3494 struct snd_ctl_elem_value *ucontrol)
3496 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3497 hda_nid_t nid = get_amp_nid(kcontrol);
3498 hda_nid_t shared_nid = 0;
3501 struct ca0132_spec *spec = codec->spec;
3504 if (nid == VNID_HP_SEL) {
3506 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3508 ca0132_select_out(codec);
3512 if (nid == VNID_AMIC1_SEL) {
3514 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3516 ca0132_select_mic(codec);
3520 if (nid == VNID_HP_ASEL) {
3521 ca0132_select_out(codec);
3525 if (nid == VNID_AMIC1_ASEL) {
3526 ca0132_select_mic(codec);
3530 /* if effective conditions, then update hw immediately. */
3531 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3533 int dir = get_amp_direction(kcontrol);
3534 int ch = get_amp_channels(kcontrol);
3537 mutex_lock(&codec->control_mutex);
3538 pval = kcontrol->private_value;
3539 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3541 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3542 kcontrol->private_value = pval;
3543 mutex_unlock(&codec->control_mutex);
3548 /* End of control change helpers. */
3550 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3551 struct snd_ctl_elem_info *uinfo)
3553 unsigned int items = sizeof(ca0132_voicefx_presets)
3554 / sizeof(struct ct_voicefx_preset);
3556 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3558 uinfo->value.enumerated.items = items;
3559 if (uinfo->value.enumerated.item >= items)
3560 uinfo->value.enumerated.item = items - 1;
3561 strcpy(uinfo->value.enumerated.name,
3562 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3566 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
3567 struct snd_ctl_elem_value *ucontrol)
3569 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3570 struct ca0132_spec *spec = codec->spec;
3572 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
3576 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
3577 struct snd_ctl_elem_value *ucontrol)
3579 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3580 struct ca0132_spec *spec = codec->spec;
3582 int sel = ucontrol->value.enumerated.item[0];
3583 unsigned int items = sizeof(ca0132_voicefx_presets)
3584 / sizeof(struct ct_voicefx_preset);
3589 snd_printdd(KERN_INFO "ca0132_voicefx_put: sel=%d, preset=%s\n",
3590 sel, ca0132_voicefx_presets[sel].name);
3594 * Default needs to qualify with CrystalVoice state.
3596 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3597 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3598 ca0132_voicefx.reqs[i],
3599 ca0132_voicefx_presets[sel].vals[i]);
3605 spec->voicefx_val = sel;
3606 /* enable voice fx */
3607 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3613 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3614 struct snd_ctl_elem_value *ucontrol)
3616 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3617 struct ca0132_spec *spec = codec->spec;
3618 hda_nid_t nid = get_amp_nid(kcontrol);
3619 int ch = get_amp_channels(kcontrol);
3620 long *valp = ucontrol->value.integer.value;
3623 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3625 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3629 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3635 /* effects, include PE and CrystalVoice */
3636 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3637 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3642 if (nid == spec->input_pins[0]) {
3643 *valp = spec->cur_mic_boost;
3650 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3651 struct snd_ctl_elem_value *ucontrol)
3653 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3654 struct ca0132_spec *spec = codec->spec;
3655 hda_nid_t nid = get_amp_nid(kcontrol);
3656 int ch = get_amp_channels(kcontrol);
3657 long *valp = ucontrol->value.integer.value;
3660 snd_printdd(KERN_INFO "ca0132_switch_put: nid=0x%x, val=%ld\n",
3663 snd_hda_power_up(codec);
3665 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3667 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3671 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3674 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3679 if (nid == PLAY_ENHANCEMENT) {
3680 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3681 changed = ca0132_pe_switch_set(codec);
3686 if (nid == CRYSTAL_VOICE) {
3687 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3688 changed = ca0132_cvoice_switch_set(codec);
3692 /* out and in effects */
3693 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3694 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3695 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3696 changed = ca0132_effects_set(codec, nid, *valp);
3701 if (nid == spec->input_pins[0]) {
3702 spec->cur_mic_boost = *valp;
3704 /* Mic boost does not apply to Digital Mic */
3705 if (spec->cur_mic_type != DIGITAL_MIC)
3706 changed = ca0132_mic_boost_set(codec, *valp);
3711 snd_hda_power_down(codec);
3718 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3719 struct snd_ctl_elem_info *uinfo)
3721 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3722 struct ca0132_spec *spec = codec->spec;
3723 hda_nid_t nid = get_amp_nid(kcontrol);
3724 int ch = get_amp_channels(kcontrol);
3725 int dir = get_amp_direction(kcontrol);
3731 /* follow shared_out info */
3732 nid = spec->shared_out_nid;
3733 mutex_lock(&codec->control_mutex);
3734 pval = kcontrol->private_value;
3735 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3736 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3737 kcontrol->private_value = pval;
3738 mutex_unlock(&codec->control_mutex);
3741 /* follow shared_mic info */
3742 nid = spec->shared_mic_nid;
3743 mutex_lock(&codec->control_mutex);
3744 pval = kcontrol->private_value;
3745 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3746 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3747 kcontrol->private_value = pval;
3748 mutex_unlock(&codec->control_mutex);
3751 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3756 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
3757 struct snd_ctl_elem_value *ucontrol)
3759 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3760 struct ca0132_spec *spec = codec->spec;
3761 hda_nid_t nid = get_amp_nid(kcontrol);
3762 int ch = get_amp_channels(kcontrol);
3763 long *valp = ucontrol->value.integer.value;
3765 /* store the left and right volume */
3767 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3771 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3777 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
3778 struct snd_ctl_elem_value *ucontrol)
3780 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3781 struct ca0132_spec *spec = codec->spec;
3782 hda_nid_t nid = get_amp_nid(kcontrol);
3783 int ch = get_amp_channels(kcontrol);
3784 long *valp = ucontrol->value.integer.value;
3785 hda_nid_t shared_nid = 0;
3789 /* store the left and right volume */
3791 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3795 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3799 /* if effective conditions, then update hw immediately. */
3800 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3802 int dir = get_amp_direction(kcontrol);
3805 snd_hda_power_up(codec);
3806 mutex_lock(&codec->control_mutex);
3807 pval = kcontrol->private_value;
3808 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3810 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3811 kcontrol->private_value = pval;
3812 mutex_unlock(&codec->control_mutex);
3813 snd_hda_power_down(codec);
3819 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3820 unsigned int size, unsigned int __user *tlv)
3822 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3823 struct ca0132_spec *spec = codec->spec;
3824 hda_nid_t nid = get_amp_nid(kcontrol);
3825 int ch = get_amp_channels(kcontrol);
3826 int dir = get_amp_direction(kcontrol);
3832 /* follow shared_out tlv */
3833 nid = spec->shared_out_nid;
3834 mutex_lock(&codec->control_mutex);
3835 pval = kcontrol->private_value;
3836 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3837 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3838 kcontrol->private_value = pval;
3839 mutex_unlock(&codec->control_mutex);
3842 /* follow shared_mic tlv */
3843 nid = spec->shared_mic_nid;
3844 mutex_lock(&codec->control_mutex);
3845 pval = kcontrol->private_value;
3846 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3847 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3848 kcontrol->private_value = pval;
3849 mutex_unlock(&codec->control_mutex);
3852 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3857 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3858 const char *pfx, int dir)
3861 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3862 struct snd_kcontrol_new knew =
3863 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3864 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
3865 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3868 static int add_voicefx(struct hda_codec *codec)
3870 struct snd_kcontrol_new knew =
3871 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3872 VOICEFX, 1, 0, HDA_INPUT);
3873 knew.info = ca0132_voicefx_info;
3874 knew.get = ca0132_voicefx_get;
3875 knew.put = ca0132_voicefx_put;
3876 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
3880 * When changing Node IDs for Mixer Controls below, make sure to update
3881 * Node IDs in ca0132_config() as well.
3883 static struct snd_kcontrol_new ca0132_mixer[] = {
3884 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3885 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3886 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3887 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3888 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3889 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3890 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3891 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3892 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3893 0x12, 1, HDA_INPUT),
3894 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3895 VNID_HP_SEL, 1, HDA_OUTPUT),
3896 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3897 VNID_AMIC1_SEL, 1, HDA_INPUT),
3898 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3899 VNID_HP_ASEL, 1, HDA_OUTPUT),
3900 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3901 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3905 static int ca0132_build_controls(struct hda_codec *codec)
3907 struct ca0132_spec *spec = codec->spec;
3911 /* Add Mixer controls */
3912 for (i = 0; i < spec->num_mixers; i++) {
3913 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3918 /* Add in and out effects controls.
3919 * VoiceFX, PE and CrystalVoice are added separately.
3921 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3922 for (i = 0; i < num_fx; i++) {
3923 err = add_fx_switch(codec, ca0132_effects[i].nid,
3924 ca0132_effects[i].name,
3925 ca0132_effects[i].direct);
3930 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3934 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3940 #ifdef ENABLE_TUNING_CONTROLS
3941 add_tuning_ctls(codec);
3944 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3948 if (spec->dig_out) {
3949 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
3953 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
3956 /* spec->multiout.share_spdif = 1; */
3960 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
3970 static struct hda_pcm_stream ca0132_pcm_analog_playback = {
3975 .prepare = ca0132_playback_pcm_prepare,
3976 .cleanup = ca0132_playback_pcm_cleanup
3980 static struct hda_pcm_stream ca0132_pcm_analog_capture = {
3985 .prepare = ca0132_capture_pcm_prepare,
3986 .cleanup = ca0132_capture_pcm_cleanup
3990 static struct hda_pcm_stream ca0132_pcm_digital_playback = {
3995 .open = ca0132_dig_playback_pcm_open,
3996 .close = ca0132_dig_playback_pcm_close,
3997 .prepare = ca0132_dig_playback_pcm_prepare,
3998 .cleanup = ca0132_dig_playback_pcm_cleanup
4002 static struct hda_pcm_stream ca0132_pcm_digital_capture = {
4008 static int ca0132_build_pcms(struct hda_codec *codec)
4010 struct ca0132_spec *spec = codec->spec;
4011 struct hda_pcm *info = spec->pcm_rec;
4013 codec->pcm_info = info;
4014 codec->num_pcms = 0;
4016 info->name = "CA0132 Analog";
4017 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4018 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4019 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4020 spec->multiout.max_channels;
4021 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4022 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4023 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4027 info->name = "CA0132 Analog Mic-In2";
4028 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4029 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4030 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4034 info->name = "CA0132 What U Hear";
4035 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4036 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4037 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4040 if (!spec->dig_out && !spec->dig_in)
4044 info->name = "CA0132 Digital";
4045 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4046 if (spec->dig_out) {
4047 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4048 ca0132_pcm_digital_playback;
4049 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4052 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4053 ca0132_pcm_digital_capture;
4054 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4061 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4064 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
4065 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4066 snd_hda_codec_write(codec, pin, 0,
4067 AC_VERB_SET_AMP_GAIN_MUTE,
4070 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4071 snd_hda_codec_write(codec, dac, 0,
4072 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4075 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4078 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
4079 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4080 snd_hda_codec_write(codec, pin, 0,
4081 AC_VERB_SET_AMP_GAIN_MUTE,
4084 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4085 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4088 /* init to 0 dB and unmute. */
4089 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4090 HDA_AMP_VOLMASK, 0x5a);
4091 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4096 static void ca0132_init_unsol(struct hda_codec *codec)
4098 snd_hda_jack_detect_enable(codec, UNSOL_TAG_HP, UNSOL_TAG_HP);
4099 snd_hda_jack_detect_enable(codec, UNSOL_TAG_AMIC1, UNSOL_TAG_AMIC1);
4102 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4106 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4107 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4108 snd_hda_override_amp_caps(codec, nid, dir, caps);
4112 * Switch between Digital built-in mic and analog mic.
4114 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4116 struct ca0132_spec *spec = codec->spec;
4119 unsigned int oldval;
4121 snd_printdd(KERN_INFO "ca0132_set_dmic: enable=%d\n", enable);
4123 oldval = stop_mic1(codec);
4124 ca0132_set_vipsource(codec, 0);
4126 /* set DMic input as 2-ch */
4128 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4130 val = spec->dmic_ctl;
4132 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4133 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4135 if (!(spec->dmic_ctl & 0x20))
4136 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4138 /* set AMic input as mono */
4140 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4142 val = spec->dmic_ctl;
4143 /* clear bit7 and bit5 to disable dmic */
4145 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4146 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4148 if (!(spec->dmic_ctl & 0x20))
4149 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4151 ca0132_set_vipsource(codec, 1);
4152 resume_mic1(codec, oldval);
4156 * Initialization for Digital Mic.
4158 static void ca0132_init_dmic(struct hda_codec *codec)
4160 struct ca0132_spec *spec = codec->spec;
4163 /* Setup Digital Mic here, but don't enable.
4164 * Enable based on jack detect.
4167 /* MCLK uses MPIO1, set to enable.
4168 * Bit 2-0: MPIO select
4169 * Bit 3: set to disable
4173 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4174 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4176 /* Data1 uses MPIO3. Data2 not use
4177 * Bit 2-0: Data1 MPIO select
4178 * Bit 3: set disable Data1
4179 * Bit 6-4: Data2 MPIO select
4180 * Bit 7: set disable Data2
4183 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4184 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4186 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4187 * Bit 3-0: Channel mask
4188 * Bit 4: set for 48KHz, clear for 32KHz
4190 * Bit 6: set to select Data2, clear for Data1
4191 * Bit 7: set to enable DMic, clear for AMic
4194 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4195 spec->dmic_ctl = val;
4196 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4197 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4201 * Initialization for Analog Mic 2
4203 static void ca0132_init_analog_mic2(struct hda_codec *codec)
4205 struct ca0132_spec *spec = codec->spec;
4207 mutex_lock(&spec->chipio_mutex);
4208 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4209 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4210 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4211 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4212 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4213 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4214 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4215 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4216 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4217 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4218 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4219 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4220 mutex_unlock(&spec->chipio_mutex);
4223 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4225 struct ca0132_spec *spec = codec->spec;
4229 snd_printdd(KERN_INFO "ca0132_refresh_widget_caps.\n");
4230 nid = codec->start_nid;
4231 for (i = 0; i < codec->num_nodes; i++, nid++)
4232 codec->wcaps[i] = snd_hda_param_read(codec, nid,
4233 AC_PAR_AUDIO_WIDGET_CAP);
4235 for (i = 0; i < spec->multiout.num_dacs; i++)
4236 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4238 for (i = 0; i < spec->num_outputs; i++)
4239 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4241 for (i = 0; i < spec->num_inputs; i++) {
4242 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4243 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4248 * Setup default parameters for DSP
4250 static void ca0132_setup_defaults(struct hda_codec *codec)
4256 if (!dspload_is_loaded(codec))
4259 /* out, in effects + voicefx */
4260 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4261 for (idx = 0; idx < num_fx; idx++) {
4262 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4263 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4264 ca0132_effects[idx].reqs[i],
4265 ca0132_effects[idx].def_vals[i]);
4269 /*remove DSP headroom*/
4271 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4273 /*set speaker EQ bypass attenuation*/
4274 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4276 /* set AMic1 and AMic2 as mono mic */
4278 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4279 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4281 /* set AMic1 as CrystalVoice input */
4283 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4285 /* set WUH source */
4287 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4291 * Initialization of flags in chip
4293 static void ca0132_init_flags(struct hda_codec *codec)
4295 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4296 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4297 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4298 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4299 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4300 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4304 * Initialization of parameters in chip
4306 static void ca0132_init_params(struct hda_codec *codec)
4308 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4309 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4312 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4314 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4315 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4316 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4317 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4318 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4319 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4321 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4322 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4323 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4326 static bool ca0132_download_dsp_images(struct hda_codec *codec)
4328 bool dsp_loaded = false;
4329 const struct dsp_image_seg *dsp_os_image;
4330 const struct firmware *fw_entry;
4332 if (request_firmware(&fw_entry, EFX_FILE, codec->bus->card->dev) != 0)
4335 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
4336 dspload_image(codec, dsp_os_image, 0, 0, true, 0);
4337 dsp_loaded = dspload_wait_loaded(codec);
4339 release_firmware(fw_entry);
4345 static void ca0132_download_dsp(struct hda_codec *codec)
4347 struct ca0132_spec *spec = codec->spec;
4349 spec->dsp_state = DSP_DOWNLOAD_INIT;
4351 if (spec->dsp_state == DSP_DOWNLOAD_INIT) {
4352 chipio_enable_clocks(codec);
4353 spec->dsp_state = DSP_DOWNLOADING;
4354 if (!ca0132_download_dsp_images(codec))
4355 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4357 spec->dsp_state = DSP_DOWNLOADED;
4360 if (spec->dsp_state == DSP_DOWNLOADED)
4361 ca0132_set_dsp_msr(codec, true);
4364 static void ca0132_process_dsp_response(struct hda_codec *codec)
4366 struct ca0132_spec *spec = codec->spec;
4368 snd_printdd(KERN_INFO "ca0132_process_dsp_response\n");
4369 if (spec->wait_scp) {
4370 if (dspio_get_response_data(codec) >= 0)
4374 dspio_clear_response_queue(codec);
4377 static void ca0132_unsol_event(struct hda_codec *codec, unsigned int res)
4379 snd_printdd(KERN_INFO "ca0132_unsol_event: 0x%x\n", res);
4382 if (((res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f) == UNSOL_TAG_DSP) {
4383 ca0132_process_dsp_response(codec);
4385 res = snd_hda_jack_get_action(codec,
4386 (res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f);
4388 snd_printdd(KERN_INFO "snd_hda_jack_get_action: 0x%x\n", res);
4392 ca0132_select_out(codec);
4393 snd_hda_jack_report_sync(codec);
4395 case UNSOL_TAG_AMIC1:
4396 ca0132_select_mic(codec);
4397 snd_hda_jack_report_sync(codec);
4409 /* Sends before DSP download. */
4410 static struct hda_verb ca0132_base_init_verbs[] = {
4411 /*enable ct extension*/
4412 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4413 /*enable DSP node unsol, needed for DSP download*/
4414 {0x16, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_DSP},
4419 static struct hda_verb ca0132_base_exit_verbs[] = {
4421 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4422 /*disable ct extension*/
4423 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4427 /* Other verbs tables. Sends after DSP download. */
4428 static struct hda_verb ca0132_init_verbs0[] = {
4429 /* chip init verbs */
4430 {0x15, 0x70D, 0xF0},
4431 {0x15, 0x70E, 0xFE},
4432 {0x15, 0x707, 0x75},
4433 {0x15, 0x707, 0xD3},
4434 {0x15, 0x707, 0x09},
4435 {0x15, 0x707, 0x53},
4436 {0x15, 0x707, 0xD4},
4437 {0x15, 0x707, 0xEF},
4438 {0x15, 0x707, 0x75},
4439 {0x15, 0x707, 0xD3},
4440 {0x15, 0x707, 0x09},
4441 {0x15, 0x707, 0x02},
4442 {0x15, 0x707, 0x37},
4443 {0x15, 0x707, 0x78},
4444 {0x15, 0x53C, 0xCE},
4445 {0x15, 0x575, 0xC9},
4446 {0x15, 0x53D, 0xCE},
4447 {0x15, 0x5B7, 0xC9},
4448 {0x15, 0x70D, 0xE8},
4449 {0x15, 0x70E, 0xFE},
4450 {0x15, 0x707, 0x02},
4451 {0x15, 0x707, 0x68},
4452 {0x15, 0x707, 0x62},
4453 {0x15, 0x53A, 0xCE},
4454 {0x15, 0x546, 0xC9},
4455 {0x15, 0x53B, 0xCE},
4456 {0x15, 0x5E8, 0xC9},
4457 {0x15, 0x717, 0x0D},
4458 {0x15, 0x718, 0x20},
4462 static struct hda_verb ca0132_init_verbs1[] = {
4463 {0x10, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_HP},
4464 {0x12, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_AMIC1},
4466 {0x0b, 0x78D, 0x00},
4467 /*{0x0b, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4468 /*{0x10, 0x78D, 0x02},*/
4469 /*{0x10, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4473 static void ca0132_init_chip(struct hda_codec *codec)
4475 struct ca0132_spec *spec = codec->spec;
4480 mutex_init(&spec->chipio_mutex);
4482 spec->cur_out_type = SPEAKER_OUT;
4483 spec->cur_mic_type = DIGITAL_MIC;
4484 spec->cur_mic_boost = 0;
4486 for (i = 0; i < VNODES_COUNT; i++) {
4487 spec->vnode_lvol[i] = 0x5a;
4488 spec->vnode_rvol[i] = 0x5a;
4489 spec->vnode_lswitch[i] = 0;
4490 spec->vnode_rswitch[i] = 0;
4494 * Default states for effects are in ca0132_effects[].
4496 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4497 for (i = 0; i < num_fx; i++) {
4498 on = (unsigned int)ca0132_effects[i].reqs[0];
4499 spec->effects_switch[i] = on ? 1 : 0;
4502 spec->voicefx_val = 0;
4503 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4504 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4506 #ifdef ENABLE_TUNING_CONTROLS
4507 ca0132_init_tuning_defaults(codec);
4511 static void ca0132_exit_chip(struct hda_codec *codec)
4513 /* put any chip cleanup stuffs here. */
4515 if (dspload_is_loaded(codec))
4519 static int ca0132_init(struct hda_codec *codec)
4521 struct ca0132_spec *spec = codec->spec;
4522 struct auto_pin_cfg *cfg = &spec->autocfg;
4525 spec->dsp_state = DSP_DOWNLOAD_INIT;
4526 spec->curr_chip_addx = (unsigned int)INVALID_CHIP_ADDRESS;
4528 snd_hda_power_up(codec);
4530 ca0132_init_params(codec);
4531 ca0132_init_flags(codec);
4532 snd_hda_sequence_write(codec, spec->base_init_verbs);
4533 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
4534 ca0132_download_dsp(codec);
4536 ca0132_refresh_widget_caps(codec);
4537 ca0132_setup_defaults(codec);
4538 ca0132_init_analog_mic2(codec);
4539 ca0132_init_dmic(codec);
4541 for (i = 0; i < spec->num_outputs; i++)
4542 init_output(codec, spec->out_pins[i], spec->dacs[0]);
4544 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4546 for (i = 0; i < spec->num_inputs; i++)
4547 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4549 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4551 for (i = 0; i < spec->num_init_verbs; i++)
4552 snd_hda_sequence_write(codec, spec->init_verbs[i]);
4554 ca0132_init_unsol(codec);
4556 ca0132_select_out(codec);
4557 ca0132_select_mic(codec);
4559 snd_hda_jack_report_sync(codec);
4561 snd_hda_power_down(codec);
4566 static void ca0132_free(struct hda_codec *codec)
4568 struct ca0132_spec *spec = codec->spec;
4570 snd_hda_power_up(codec);
4571 snd_hda_sequence_write(codec, spec->base_exit_verbs);
4572 ca0132_exit_chip(codec);
4573 snd_hda_power_down(codec);
4577 static struct hda_codec_ops ca0132_patch_ops = {
4578 .build_controls = ca0132_build_controls,
4579 .build_pcms = ca0132_build_pcms,
4580 .init = ca0132_init,
4581 .free = ca0132_free,
4582 .unsol_event = ca0132_unsol_event,
4585 static void ca0132_config(struct hda_codec *codec)
4587 struct ca0132_spec *spec = codec->spec;
4588 struct auto_pin_cfg *cfg = &spec->autocfg;
4590 spec->dacs[0] = 0x2;
4591 spec->dacs[1] = 0x3;
4592 spec->dacs[2] = 0x4;
4594 spec->multiout.dac_nids = spec->dacs;
4595 spec->multiout.num_dacs = 3;
4596 spec->multiout.max_channels = 2;
4598 spec->num_outputs = 2;
4599 spec->out_pins[0] = 0x0b; /* speaker out */
4600 spec->out_pins[1] = 0x10; /* headphone out */
4601 spec->shared_out_nid = 0x2;
4603 spec->num_inputs = 3;
4604 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4605 spec->adcs[1] = 0x8; /* analog mic2 */
4606 spec->adcs[2] = 0xa; /* what u hear */
4607 spec->shared_mic_nid = 0x7;
4609 spec->input_pins[0] = 0x12;
4610 spec->input_pins[1] = 0x11;
4611 spec->input_pins[2] = 0x13;
4614 spec->dig_out = 0x05;
4615 spec->multiout.dig_out_nid = spec->dig_out;
4616 cfg->dig_out_pins[0] = 0x0c;
4618 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4619 spec->dig_in = 0x09;
4620 cfg->dig_in_pin = 0x0e;
4621 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4624 static int patch_ca0132(struct hda_codec *codec)
4626 struct ca0132_spec *spec;
4629 snd_printdd("patch_ca0132\n");
4631 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4636 spec->num_mixers = 1;
4637 spec->mixers[0] = ca0132_mixer;
4639 spec->base_init_verbs = ca0132_base_init_verbs;
4640 spec->base_exit_verbs = ca0132_base_exit_verbs;
4641 spec->init_verbs[0] = ca0132_init_verbs0;
4642 spec->init_verbs[1] = ca0132_init_verbs1;
4643 spec->num_init_verbs = 2;
4645 ca0132_init_chip(codec);
4647 ca0132_config(codec);
4649 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4653 codec->patch_ops = ca0132_patch_ops;
4661 static struct hda_codec_preset snd_hda_preset_ca0132[] = {
4662 { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
4666 MODULE_ALIAS("snd-hda-codec-id:11020011");
4668 MODULE_LICENSE("GPL");
4669 MODULE_DESCRIPTION("Creative Sound Core3D codec");
4671 static struct hda_codec_preset_list ca0132_list = {
4672 .preset = snd_hda_preset_ca0132,
4673 .owner = THIS_MODULE,
4676 static int __init patch_ca0132_init(void)
4678 return snd_hda_add_codec_preset(&ca0132_list);
4681 static void __exit patch_ca0132_exit(void)
4683 snd_hda_delete_codec_preset(&ca0132_list);
4686 module_init(patch_ca0132_init)
4687 module_exit(patch_ca0132_exit)