3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
12 * Wu Fengguang <wfg@linux.intel.com>
15 * Wu Fengguang <wfg@linux.intel.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include <sound/hdaudio.h>
41 #include <sound/hda_i915.h>
42 #include "hda_codec.h"
43 #include "hda_local.h"
46 static bool static_hdmi_pcm;
47 module_param(static_hdmi_pcm, bool, 0644);
48 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
50 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
51 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
52 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
53 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
56 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
57 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
58 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
60 struct hdmi_spec_per_cvt {
63 unsigned int channels_min;
64 unsigned int channels_max;
70 /* max. connections to a widget */
71 #define HDA_MAX_CONNECTIONS 32
73 struct hdmi_spec_per_pin {
76 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
80 struct hda_codec *codec;
81 struct hdmi_eld sink_eld;
83 struct delayed_work work;
84 struct snd_kcontrol *eld_ctl;
86 bool setup; /* the stream has been set up by prepare callback */
87 int channels; /* current number of channels */
89 bool chmap_set; /* channel-map override by ALSA API? */
90 unsigned char chmap[8]; /* ALSA API channel-map */
91 #ifdef CONFIG_SND_PROC_FS
92 struct snd_info_entry *proc_entry;
96 struct cea_channel_speaker_allocation;
98 /* operations used by generic code that can be overridden by patches */
100 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
101 unsigned char *buf, int *eld_size);
103 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
104 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
106 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
107 int asp_slot, int channel);
109 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
110 int ca, int active_channels, int conn_type);
112 /* enable/disable HBR (HD passthrough) */
113 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
115 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
116 hda_nid_t pin_nid, u32 stream_tag, int format);
118 /* Helpers for producing the channel map TLVs. These can be overridden
119 * for devices that have non-standard mapping requirements. */
120 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
122 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
123 unsigned int *chmap, int channels);
125 /* check that the user-given chmap is supported */
126 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
131 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
132 hda_nid_t cvt_nids[4]; /* only for haswell fix */
135 struct snd_array pins; /* struct hdmi_spec_per_pin */
136 struct hda_pcm *pcm_rec[16];
137 unsigned int channels_max; /* max over all cvts */
139 struct hdmi_eld temp_eld;
145 * Non-generic VIA/NVIDIA specific
147 struct hda_multi_out multiout;
148 struct hda_pcm_stream pcm_playback;
150 /* i915/powerwell (Haswell+/Valleyview+) specific */
151 struct i915_audio_component_audio_ops i915_audio_ops;
155 struct hdmi_audio_infoframe {
162 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
166 u8 LFEPBL01_LSV36_DM_INH7;
169 struct dp_audio_infoframe {
172 u8 ver; /* 0x11 << 2 */
174 u8 CC02_CT47; /* match with HDMI infoframe from this on */
178 u8 LFEPBL01_LSV36_DM_INH7;
181 union audio_infoframe {
182 struct hdmi_audio_infoframe hdmi;
183 struct dp_audio_infoframe dp;
188 * CEA speaker placement:
191 * FLW FL FLC FC FRC FR FRW
198 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
199 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
201 enum cea_speaker_placement {
202 FL = (1 << 0), /* Front Left */
203 FC = (1 << 1), /* Front Center */
204 FR = (1 << 2), /* Front Right */
205 FLC = (1 << 3), /* Front Left Center */
206 FRC = (1 << 4), /* Front Right Center */
207 RL = (1 << 5), /* Rear Left */
208 RC = (1 << 6), /* Rear Center */
209 RR = (1 << 7), /* Rear Right */
210 RLC = (1 << 8), /* Rear Left Center */
211 RRC = (1 << 9), /* Rear Right Center */
212 LFE = (1 << 10), /* Low Frequency Effect */
213 FLW = (1 << 11), /* Front Left Wide */
214 FRW = (1 << 12), /* Front Right Wide */
215 FLH = (1 << 13), /* Front Left High */
216 FCH = (1 << 14), /* Front Center High */
217 FRH = (1 << 15), /* Front Right High */
218 TC = (1 << 16), /* Top Center */
222 * ELD SA bits in the CEA Speaker Allocation data block
224 static int eld_speaker_allocation_bits[] = {
232 /* the following are not defined in ELD yet */
239 struct cea_channel_speaker_allocation {
243 /* derived values, just for convenience */
251 * surround40 surround41 surround50 surround51 surround71
252 * ch0 front left = = = =
253 * ch1 front right = = = =
254 * ch2 rear left = = = =
255 * ch3 rear right = = = =
256 * ch4 LFE center center center
261 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
263 static int hdmi_channel_mapping[0x32][8] = {
265 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
267 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
269 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
271 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
273 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
275 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
277 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
279 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
281 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
285 * This is an ordered list!
287 * The preceding ones have better chances to be selected by
288 * hdmi_channel_allocation().
290 static struct cea_channel_speaker_allocation channel_allocations[] = {
291 /* channel: 7 6 5 4 3 2 1 0 */
292 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
294 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
296 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
298 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
300 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
302 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
304 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
306 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
308 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
310 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
311 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
312 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
313 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
314 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
315 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
316 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
317 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
318 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
319 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
320 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
321 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
322 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
323 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
324 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
325 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
326 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
327 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
328 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
329 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
330 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
331 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
332 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
333 { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
334 { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
335 { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
336 { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
337 { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
338 { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
339 { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
340 { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
341 { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
342 { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
343 { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
344 { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
345 { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
346 { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
347 { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
348 { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
349 { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
350 { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
358 #define get_pin(spec, idx) \
359 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
360 #define get_cvt(spec, idx) \
361 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
362 #define get_pcm_rec(spec, idx) ((spec)->pcm_rec[idx])
364 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
366 struct hdmi_spec *spec = codec->spec;
369 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
370 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
373 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
377 static int hinfo_to_pin_index(struct hda_codec *codec,
378 struct hda_pcm_stream *hinfo)
380 struct hdmi_spec *spec = codec->spec;
383 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
384 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
387 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
391 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
393 struct hdmi_spec *spec = codec->spec;
396 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
397 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
400 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
404 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
405 struct snd_ctl_elem_info *uinfo)
407 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
408 struct hdmi_spec *spec = codec->spec;
409 struct hdmi_spec_per_pin *per_pin;
410 struct hdmi_eld *eld;
413 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
415 pin_idx = kcontrol->private_value;
416 per_pin = get_pin(spec, pin_idx);
417 eld = &per_pin->sink_eld;
419 mutex_lock(&per_pin->lock);
420 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
421 mutex_unlock(&per_pin->lock);
426 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
427 struct snd_ctl_elem_value *ucontrol)
429 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
430 struct hdmi_spec *spec = codec->spec;
431 struct hdmi_spec_per_pin *per_pin;
432 struct hdmi_eld *eld;
435 pin_idx = kcontrol->private_value;
436 per_pin = get_pin(spec, pin_idx);
437 eld = &per_pin->sink_eld;
439 mutex_lock(&per_pin->lock);
440 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
441 mutex_unlock(&per_pin->lock);
446 memset(ucontrol->value.bytes.data, 0,
447 ARRAY_SIZE(ucontrol->value.bytes.data));
449 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
451 mutex_unlock(&per_pin->lock);
456 static struct snd_kcontrol_new eld_bytes_ctl = {
457 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
458 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
460 .info = hdmi_eld_ctl_info,
461 .get = hdmi_eld_ctl_get,
464 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
467 struct snd_kcontrol *kctl;
468 struct hdmi_spec *spec = codec->spec;
471 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
474 kctl->private_value = pin_idx;
475 kctl->id.device = device;
477 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
481 get_pin(spec, pin_idx)->eld_ctl = kctl;
486 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
487 int *packet_index, int *byte_index)
491 val = snd_hda_codec_read(codec, pin_nid, 0,
492 AC_VERB_GET_HDMI_DIP_INDEX, 0);
494 *packet_index = val >> 5;
495 *byte_index = val & 0x1f;
499 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
500 int packet_index, int byte_index)
504 val = (packet_index << 5) | (byte_index & 0x1f);
506 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
509 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
512 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
515 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
517 struct hdmi_spec *spec = codec->spec;
521 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
522 snd_hda_codec_write(codec, pin_nid, 0,
523 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
525 if (spec->dyn_pin_out)
526 /* Disable pin out until stream is active */
529 /* Enable pin out: some machines with GM965 gets broken output
530 * when the pin is disabled or changed while using with HDMI
534 snd_hda_codec_write(codec, pin_nid, 0,
535 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
538 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
540 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
541 AC_VERB_GET_CVT_CHAN_COUNT, 0);
544 static void hdmi_set_channel_count(struct hda_codec *codec,
545 hda_nid_t cvt_nid, int chs)
547 if (chs != hdmi_get_channel_count(codec, cvt_nid))
548 snd_hda_codec_write(codec, cvt_nid, 0,
549 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
556 #ifdef CONFIG_SND_PROC_FS
557 static void print_eld_info(struct snd_info_entry *entry,
558 struct snd_info_buffer *buffer)
560 struct hdmi_spec_per_pin *per_pin = entry->private_data;
562 mutex_lock(&per_pin->lock);
563 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
564 mutex_unlock(&per_pin->lock);
567 static void write_eld_info(struct snd_info_entry *entry,
568 struct snd_info_buffer *buffer)
570 struct hdmi_spec_per_pin *per_pin = entry->private_data;
572 mutex_lock(&per_pin->lock);
573 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
574 mutex_unlock(&per_pin->lock);
577 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
580 struct hda_codec *codec = per_pin->codec;
581 struct snd_info_entry *entry;
584 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
585 err = snd_card_proc_new(codec->card, name, &entry);
589 snd_info_set_text_ops(entry, per_pin, print_eld_info);
590 entry->c.text.write = write_eld_info;
591 entry->mode |= S_IWUSR;
592 per_pin->proc_entry = entry;
597 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
599 if (!per_pin->codec->bus->shutdown) {
600 snd_info_free_entry(per_pin->proc_entry);
601 per_pin->proc_entry = NULL;
605 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
610 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
616 * Channel mapping routines
620 * Compute derived values in channel_allocations[].
622 static void init_channel_allocations(void)
625 struct cea_channel_speaker_allocation *p;
627 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
628 p = channel_allocations + i;
631 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
632 if (p->speakers[j]) {
634 p->spk_mask |= p->speakers[j];
639 static int get_channel_allocation_order(int ca)
643 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
644 if (channel_allocations[i].ca_index == ca)
651 * The transformation takes two steps:
653 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
654 * spk_mask => (channel_allocations[]) => ai->CA
656 * TODO: it could select the wrong CA from multiple candidates.
658 static int hdmi_channel_allocation(struct hda_codec *codec,
659 struct hdmi_eld *eld, int channels)
664 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
667 * CA defaults to 0 for basic stereo audio
673 * expand ELD's speaker allocation mask
675 * ELD tells the speaker mask in a compact(paired) form,
676 * expand ELD's notions to match the ones used by Audio InfoFrame.
678 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
679 if (eld->info.spk_alloc & (1 << i))
680 spk_mask |= eld_speaker_allocation_bits[i];
683 /* search for the first working match in the CA table */
684 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
685 if (channels == channel_allocations[i].channels &&
686 (spk_mask & channel_allocations[i].spk_mask) ==
687 channel_allocations[i].spk_mask) {
688 ca = channel_allocations[i].ca_index;
694 /* if there was no match, select the regular ALSA channel
695 * allocation with the matching number of channels */
696 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
697 if (channels == channel_allocations[i].channels) {
698 ca = channel_allocations[i].ca_index;
704 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
705 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
711 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
714 #ifdef CONFIG_SND_DEBUG_VERBOSE
715 struct hdmi_spec *spec = codec->spec;
719 for (i = 0; i < 8; i++) {
720 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
721 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
727 static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
732 struct hdmi_spec *spec = codec->spec;
733 struct cea_channel_speaker_allocation *ch_alloc;
737 int non_pcm_mapping[8];
739 order = get_channel_allocation_order(ca);
740 ch_alloc = &channel_allocations[order];
742 if (hdmi_channel_mapping[ca][1] == 0) {
744 /* fill actual channel mappings in ALSA channel (i) order */
745 for (i = 0; i < ch_alloc->channels; i++) {
746 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
747 hdmi_slot++; /* skip zero slots */
749 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
751 /* fill the rest of the slots with ALSA channel 0xf */
752 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
753 if (!ch_alloc->speakers[7 - hdmi_slot])
754 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
758 for (i = 0; i < ch_alloc->channels; i++)
759 non_pcm_mapping[i] = (i << 4) | i;
761 non_pcm_mapping[i] = (0xf << 4) | i;
764 for (i = 0; i < 8; i++) {
765 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
766 int hdmi_slot = slotsetup & 0x0f;
767 int channel = (slotsetup & 0xf0) >> 4;
768 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
770 codec_dbg(codec, "HDMI: channel mapping failed\n");
776 struct channel_map_table {
777 unsigned char map; /* ALSA API channel map position */
778 int spk_mask; /* speaker position bit mask */
781 static struct channel_map_table map_tables[] = {
782 { SNDRV_CHMAP_FL, FL },
783 { SNDRV_CHMAP_FR, FR },
784 { SNDRV_CHMAP_RL, RL },
785 { SNDRV_CHMAP_RR, RR },
786 { SNDRV_CHMAP_LFE, LFE },
787 { SNDRV_CHMAP_FC, FC },
788 { SNDRV_CHMAP_RLC, RLC },
789 { SNDRV_CHMAP_RRC, RRC },
790 { SNDRV_CHMAP_RC, RC },
791 { SNDRV_CHMAP_FLC, FLC },
792 { SNDRV_CHMAP_FRC, FRC },
793 { SNDRV_CHMAP_TFL, FLH },
794 { SNDRV_CHMAP_TFR, FRH },
795 { SNDRV_CHMAP_FLW, FLW },
796 { SNDRV_CHMAP_FRW, FRW },
797 { SNDRV_CHMAP_TC, TC },
798 { SNDRV_CHMAP_TFC, FCH },
802 /* from ALSA API channel position to speaker bit mask */
803 static int to_spk_mask(unsigned char c)
805 struct channel_map_table *t = map_tables;
806 for (; t->map; t++) {
813 /* from ALSA API channel position to CEA slot */
814 static int to_cea_slot(int ordered_ca, unsigned char pos)
816 int mask = to_spk_mask(pos);
820 for (i = 0; i < 8; i++) {
821 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
829 /* from speaker bit mask to ALSA API channel position */
830 static int spk_to_chmap(int spk)
832 struct channel_map_table *t = map_tables;
833 for (; t->map; t++) {
834 if (t->spk_mask == spk)
840 /* from CEA slot to ALSA API channel position */
841 static int from_cea_slot(int ordered_ca, unsigned char slot)
843 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
845 return spk_to_chmap(mask);
848 /* get the CA index corresponding to the given ALSA API channel map */
849 static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
851 int i, spks = 0, spk_mask = 0;
853 for (i = 0; i < chs; i++) {
854 int mask = to_spk_mask(map[i]);
861 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
862 if ((chs == channel_allocations[i].channels ||
863 spks == channel_allocations[i].channels) &&
864 (spk_mask & channel_allocations[i].spk_mask) ==
865 channel_allocations[i].spk_mask)
866 return channel_allocations[i].ca_index;
871 /* set up the channel slots for the given ALSA API channel map */
872 static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
874 int chs, unsigned char *map,
877 struct hdmi_spec *spec = codec->spec;
878 int ordered_ca = get_channel_allocation_order(ca);
879 int alsa_pos, hdmi_slot;
880 int assignments[8] = {[0 ... 7] = 0xf};
882 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
884 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
887 continue; /* unassigned channel */
889 assignments[hdmi_slot] = alsa_pos;
892 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
895 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
896 assignments[hdmi_slot]);
903 /* store ALSA API channel map from the current default map */
904 static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
907 int ordered_ca = get_channel_allocation_order(ca);
908 for (i = 0; i < 8; i++) {
909 if (i < channel_allocations[ordered_ca].channels)
910 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
916 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
917 hda_nid_t pin_nid, bool non_pcm, int ca,
918 int channels, unsigned char *map,
921 if (!non_pcm && chmap_set) {
922 hdmi_manual_setup_channel_mapping(codec, pin_nid,
925 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
926 hdmi_setup_fake_chmap(map, ca);
929 hdmi_debug_channel_mapping(codec, pin_nid);
932 static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
933 int asp_slot, int channel)
935 return snd_hda_codec_write(codec, pin_nid, 0,
936 AC_VERB_SET_HDMI_CHAN_SLOT,
937 (channel << 4) | asp_slot);
940 static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
943 return (snd_hda_codec_read(codec, pin_nid, 0,
944 AC_VERB_GET_HDMI_CHAN_SLOT,
945 asp_slot) & 0xf0) >> 4;
949 * Audio InfoFrame routines
953 * Enable Audio InfoFrame Transmission
955 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
958 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
959 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
964 * Disable Audio InfoFrame Transmission
966 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
969 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
970 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
974 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
976 #ifdef CONFIG_SND_DEBUG_VERBOSE
980 size = snd_hdmi_get_eld_size(codec, pin_nid);
981 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
983 for (i = 0; i < 8; i++) {
984 size = snd_hda_codec_read(codec, pin_nid, 0,
985 AC_VERB_GET_HDMI_DIP_SIZE, i);
986 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
991 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
997 for (i = 0; i < 8; i++) {
998 size = snd_hda_codec_read(codec, pin_nid, 0,
999 AC_VERB_GET_HDMI_DIP_SIZE, i);
1003 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1004 for (j = 1; j < 1000; j++) {
1005 hdmi_write_dip_byte(codec, pin_nid, 0x0);
1006 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1008 codec_dbg(codec, "dip index %d: %d != %d\n",
1010 if (bi == 0) /* byte index wrapped around */
1014 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1020 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
1022 u8 *bytes = (u8 *)hdmi_ai;
1026 hdmi_ai->checksum = 0;
1028 for (i = 0; i < sizeof(*hdmi_ai); i++)
1031 hdmi_ai->checksum = -sum;
1034 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1040 hdmi_debug_dip_size(codec, pin_nid);
1041 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1043 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1044 for (i = 0; i < size; i++)
1045 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
1048 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
1054 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1058 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1059 for (i = 0; i < size; i++) {
1060 val = snd_hda_codec_read(codec, pin_nid, 0,
1061 AC_VERB_GET_HDMI_DIP_DATA, 0);
1069 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1071 int ca, int active_channels,
1074 union audio_infoframe ai;
1076 memset(&ai, 0, sizeof(ai));
1077 if (conn_type == 0) { /* HDMI */
1078 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1080 hdmi_ai->type = 0x84;
1081 hdmi_ai->ver = 0x01;
1082 hdmi_ai->len = 0x0a;
1083 hdmi_ai->CC02_CT47 = active_channels - 1;
1085 hdmi_checksum_audio_infoframe(hdmi_ai);
1086 } else if (conn_type == 1) { /* DisplayPort */
1087 struct dp_audio_infoframe *dp_ai = &ai.dp;
1091 dp_ai->ver = 0x11 << 2;
1092 dp_ai->CC02_CT47 = active_channels - 1;
1095 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
1101 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1102 * sizeof(*dp_ai) to avoid partial match/update problems when
1103 * the user switches between HDMI/DP monitors.
1105 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1108 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1110 active_channels, ca);
1111 hdmi_stop_infoframe_trans(codec, pin_nid);
1112 hdmi_fill_audio_infoframe(codec, pin_nid,
1113 ai.bytes, sizeof(ai));
1114 hdmi_start_infoframe_trans(codec, pin_nid);
1118 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1119 struct hdmi_spec_per_pin *per_pin,
1122 struct hdmi_spec *spec = codec->spec;
1123 hda_nid_t pin_nid = per_pin->pin_nid;
1124 int channels = per_pin->channels;
1125 int active_channels;
1126 struct hdmi_eld *eld;
1132 if (is_haswell_plus(codec))
1133 snd_hda_codec_write(codec, pin_nid, 0,
1134 AC_VERB_SET_AMP_GAIN_MUTE,
1137 eld = &per_pin->sink_eld;
1139 if (!non_pcm && per_pin->chmap_set)
1140 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1142 ca = hdmi_channel_allocation(codec, eld, channels);
1146 ordered_ca = get_channel_allocation_order(ca);
1147 active_channels = channel_allocations[ordered_ca].channels;
1149 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1152 * always configure channel mapping, it may have been changed by the
1153 * user in the meantime
1155 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1156 channels, per_pin->chmap,
1157 per_pin->chmap_set);
1159 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1160 eld->info.conn_type);
1162 per_pin->non_pcm = non_pcm;
1166 * Unsolicited events
1169 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1171 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
1173 struct hdmi_spec *spec = codec->spec;
1174 int pin_idx = pin_nid_to_pin_index(codec, nid);
1178 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1179 snd_hda_jack_report_sync(codec);
1182 static void jack_callback(struct hda_codec *codec,
1183 struct hda_jack_callback *jack)
1185 check_presence_and_report(codec, jack->tbl->nid);
1188 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1190 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1191 struct hda_jack_tbl *jack;
1192 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1194 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1197 jack->jack_dirty = 1;
1200 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1201 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1202 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1204 check_presence_and_report(codec, jack->nid);
1207 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1209 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1210 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1211 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1212 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1215 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1230 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1232 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1233 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1235 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
1236 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
1241 hdmi_intrinsic_event(codec, res);
1243 hdmi_non_intrinsic_event(codec, res);
1246 static void haswell_verify_D0(struct hda_codec *codec,
1247 hda_nid_t cvt_nid, hda_nid_t nid)
1251 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1252 * thus pins could only choose converter 0 for use. Make sure the
1253 * converters are in correct power state */
1254 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
1255 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1257 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
1258 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1261 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1262 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1263 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1271 /* HBR should be Non-PCM, 8 channels */
1272 #define is_hbr_format(format) \
1273 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1275 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1278 int pinctl, new_pinctl;
1280 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1281 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1282 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1285 return hbr ? -EINVAL : 0;
1287 new_pinctl = pinctl & ~AC_PINCTL_EPT;
1289 new_pinctl |= AC_PINCTL_EPT_HBR;
1291 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1294 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1296 pinctl == new_pinctl ? "" : "new-",
1299 if (pinctl != new_pinctl)
1300 snd_hda_codec_write(codec, pin_nid, 0,
1301 AC_VERB_SET_PIN_WIDGET_CONTROL,
1309 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1310 hda_nid_t pin_nid, u32 stream_tag, int format)
1312 struct hdmi_spec *spec = codec->spec;
1315 if (is_haswell_plus(codec))
1316 haswell_verify_D0(codec, cvt_nid, pin_nid);
1318 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1321 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
1325 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
1329 static int hdmi_choose_cvt(struct hda_codec *codec,
1330 int pin_idx, int *cvt_id, int *mux_id)
1332 struct hdmi_spec *spec = codec->spec;
1333 struct hdmi_spec_per_pin *per_pin;
1334 struct hdmi_spec_per_cvt *per_cvt = NULL;
1335 int cvt_idx, mux_idx = 0;
1337 per_pin = get_pin(spec, pin_idx);
1339 /* Dynamically assign converter to stream */
1340 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1341 per_cvt = get_cvt(spec, cvt_idx);
1343 /* Must not already be assigned */
1344 if (per_cvt->assigned)
1346 /* Must be in pin's mux's list of converters */
1347 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1348 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1350 /* Not in mux list */
1351 if (mux_idx == per_pin->num_mux_nids)
1356 /* No free converters */
1357 if (cvt_idx == spec->num_cvts)
1360 per_pin->mux_idx = mux_idx;
1370 /* Assure the pin select the right convetor */
1371 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1372 struct hdmi_spec_per_pin *per_pin)
1374 hda_nid_t pin_nid = per_pin->pin_nid;
1377 mux_idx = per_pin->mux_idx;
1378 curr = snd_hda_codec_read(codec, pin_nid, 0,
1379 AC_VERB_GET_CONNECT_SEL, 0);
1380 if (curr != mux_idx)
1381 snd_hda_codec_write_cache(codec, pin_nid, 0,
1382 AC_VERB_SET_CONNECT_SEL,
1386 /* Intel HDMI workaround to fix audio routing issue:
1387 * For some Intel display codecs, pins share the same connection list.
1388 * So a conveter can be selected by multiple pins and playback on any of these
1389 * pins will generate sound on the external display, because audio flows from
1390 * the same converter to the display pipeline. Also muting one pin may make
1391 * other pins have no sound output.
1392 * So this function assures that an assigned converter for a pin is not selected
1393 * by any other pins.
1395 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1396 hda_nid_t pin_nid, int mux_idx)
1398 struct hdmi_spec *spec = codec->spec;
1401 struct hdmi_spec_per_cvt *per_cvt;
1403 /* configure all pins, including "no physical connection" ones */
1404 for_each_hda_codec_node(nid, codec) {
1405 unsigned int wid_caps = get_wcaps(codec, nid);
1406 unsigned int wid_type = get_wcaps_type(wid_caps);
1408 if (wid_type != AC_WID_PIN)
1414 curr = snd_hda_codec_read(codec, nid, 0,
1415 AC_VERB_GET_CONNECT_SEL, 0);
1416 if (curr != mux_idx)
1419 /* choose an unassigned converter. The conveters in the
1420 * connection list are in the same order as in the codec.
1422 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1423 per_cvt = get_cvt(spec, cvt_idx);
1424 if (!per_cvt->assigned) {
1426 "choose cvt %d for pin nid %d\n",
1428 snd_hda_codec_write_cache(codec, nid, 0,
1429 AC_VERB_SET_CONNECT_SEL,
1440 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1441 struct hda_codec *codec,
1442 struct snd_pcm_substream *substream)
1444 struct hdmi_spec *spec = codec->spec;
1445 struct snd_pcm_runtime *runtime = substream->runtime;
1446 int pin_idx, cvt_idx, mux_idx = 0;
1447 struct hdmi_spec_per_pin *per_pin;
1448 struct hdmi_eld *eld;
1449 struct hdmi_spec_per_cvt *per_cvt = NULL;
1452 /* Validate hinfo */
1453 pin_idx = hinfo_to_pin_index(codec, hinfo);
1454 if (snd_BUG_ON(pin_idx < 0))
1456 per_pin = get_pin(spec, pin_idx);
1457 eld = &per_pin->sink_eld;
1459 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1463 per_cvt = get_cvt(spec, cvt_idx);
1464 /* Claim converter */
1465 per_cvt->assigned = 1;
1466 per_pin->cvt_nid = per_cvt->cvt_nid;
1467 hinfo->nid = per_cvt->cvt_nid;
1469 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1470 AC_VERB_SET_CONNECT_SEL,
1473 /* configure unused pins to choose other converters */
1474 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1475 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1477 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
1479 /* Initially set the converter's capabilities */
1480 hinfo->channels_min = per_cvt->channels_min;
1481 hinfo->channels_max = per_cvt->channels_max;
1482 hinfo->rates = per_cvt->rates;
1483 hinfo->formats = per_cvt->formats;
1484 hinfo->maxbps = per_cvt->maxbps;
1486 /* Restrict capabilities by ELD if this isn't disabled */
1487 if (!static_hdmi_pcm && eld->eld_valid) {
1488 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1489 if (hinfo->channels_min > hinfo->channels_max ||
1490 !hinfo->rates || !hinfo->formats) {
1491 per_cvt->assigned = 0;
1493 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1498 /* Store the updated parameters */
1499 runtime->hw.channels_min = hinfo->channels_min;
1500 runtime->hw.channels_max = hinfo->channels_max;
1501 runtime->hw.formats = hinfo->formats;
1502 runtime->hw.rates = hinfo->rates;
1504 snd_pcm_hw_constraint_step(substream->runtime, 0,
1505 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1510 * HDA/HDMI auto parsing
1512 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1514 struct hdmi_spec *spec = codec->spec;
1515 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1516 hda_nid_t pin_nid = per_pin->pin_nid;
1518 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1520 "HDMI: pin %d wcaps %#x does not support connection list\n",
1521 pin_nid, get_wcaps(codec, pin_nid));
1525 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1527 HDA_MAX_CONNECTIONS);
1532 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1534 struct hda_jack_tbl *jack;
1535 struct hda_codec *codec = per_pin->codec;
1536 struct hdmi_spec *spec = codec->spec;
1537 struct hdmi_eld *eld = &spec->temp_eld;
1538 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1539 hda_nid_t pin_nid = per_pin->pin_nid;
1541 * Always execute a GetPinSense verb here, even when called from
1542 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1543 * response's PD bit is not the real PD value, but indicates that
1544 * the real PD value changed. An older version of the HD-audio
1545 * specification worked this way. Hence, we just ignore the data in
1546 * the unsolicited response to avoid custom WARs.
1549 bool update_eld = false;
1550 bool eld_changed = false;
1553 snd_hda_power_up_pm(codec);
1554 present = snd_hda_pin_sense(codec, pin_nid);
1556 mutex_lock(&per_pin->lock);
1557 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1558 if (pin_eld->monitor_present)
1559 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1561 eld->eld_valid = false;
1564 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1565 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1567 if (eld->eld_valid) {
1568 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1569 &eld->eld_size) < 0)
1570 eld->eld_valid = false;
1572 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1573 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1575 eld->eld_valid = false;
1578 if (eld->eld_valid) {
1579 snd_hdmi_show_eld(codec, &eld->info);
1583 schedule_delayed_work(&per_pin->work,
1584 msecs_to_jiffies(300));
1589 if (pin_eld->eld_valid != eld->eld_valid)
1592 if (pin_eld->eld_valid && !eld->eld_valid)
1596 bool old_eld_valid = pin_eld->eld_valid;
1597 pin_eld->eld_valid = eld->eld_valid;
1598 if (pin_eld->eld_size != eld->eld_size ||
1599 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1600 eld->eld_size) != 0) {
1601 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1605 pin_eld->eld_size = eld->eld_size;
1606 pin_eld->info = eld->info;
1609 * Re-setup pin and infoframe. This is needed e.g. when
1610 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1611 * - transcoder can change during stream playback on Haswell
1612 * and this can make HW reset converter selection on a pin.
1614 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1615 if (is_haswell_plus(codec) ||
1616 is_valleyview_plus(codec)) {
1617 intel_verify_pin_cvt_connect(codec, per_pin);
1618 intel_not_share_assigned_cvt(codec, pin_nid,
1622 hdmi_setup_audio_infoframe(codec, per_pin,
1628 snd_ctl_notify(codec->card,
1629 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1630 &per_pin->eld_ctl->id);
1632 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1634 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1636 jack->block_report = !ret;
1638 mutex_unlock(&per_pin->lock);
1639 snd_hda_power_down_pm(codec);
1643 static void hdmi_repoll_eld(struct work_struct *work)
1645 struct hdmi_spec_per_pin *per_pin =
1646 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1648 if (per_pin->repoll_count++ > 6)
1649 per_pin->repoll_count = 0;
1651 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1652 snd_hda_jack_report_sync(per_pin->codec);
1655 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1658 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1660 struct hdmi_spec *spec = codec->spec;
1661 unsigned int caps, config;
1663 struct hdmi_spec_per_pin *per_pin;
1666 caps = snd_hda_query_pin_caps(codec, pin_nid);
1667 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1670 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1671 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1674 if (is_haswell_plus(codec))
1675 intel_haswell_fixup_connect_list(codec, pin_nid);
1677 pin_idx = spec->num_pins;
1678 per_pin = snd_array_new(&spec->pins);
1682 per_pin->pin_nid = pin_nid;
1683 per_pin->non_pcm = false;
1685 err = hdmi_read_pin_conn(codec, pin_idx);
1694 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1696 struct hdmi_spec *spec = codec->spec;
1697 struct hdmi_spec_per_cvt *per_cvt;
1701 chans = get_wcaps(codec, cvt_nid);
1702 chans = get_wcaps_channels(chans);
1704 per_cvt = snd_array_new(&spec->cvts);
1708 per_cvt->cvt_nid = cvt_nid;
1709 per_cvt->channels_min = 2;
1711 per_cvt->channels_max = chans;
1712 if (chans > spec->channels_max)
1713 spec->channels_max = chans;
1716 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1723 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1724 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1730 static int hdmi_parse_codec(struct hda_codec *codec)
1735 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1736 if (!nid || nodes < 0) {
1737 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1741 for (i = 0; i < nodes; i++, nid++) {
1745 caps = get_wcaps(codec, nid);
1746 type = get_wcaps_type(caps);
1748 if (!(caps & AC_WCAP_DIGITAL))
1752 case AC_WID_AUD_OUT:
1753 hdmi_add_cvt(codec, nid);
1756 hdmi_add_pin(codec, nid);
1766 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1768 struct hda_spdif_out *spdif;
1771 mutex_lock(&codec->spdif_mutex);
1772 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1773 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1774 mutex_unlock(&codec->spdif_mutex);
1783 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1784 struct hda_codec *codec,
1785 unsigned int stream_tag,
1786 unsigned int format,
1787 struct snd_pcm_substream *substream)
1789 hda_nid_t cvt_nid = hinfo->nid;
1790 struct hdmi_spec *spec = codec->spec;
1791 int pin_idx = hinfo_to_pin_index(codec, hinfo);
1792 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1793 hda_nid_t pin_nid = per_pin->pin_nid;
1797 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1798 /* Verify pin:cvt selections to avoid silent audio after S3.
1799 * After S3, the audio driver restores pin:cvt selections
1800 * but this can happen before gfx is ready and such selection
1801 * is overlooked by HW. Thus multiple pins can share a same
1802 * default convertor and mute control will affect each other,
1803 * which can cause a resumed audio playback become silent
1806 intel_verify_pin_cvt_connect(codec, per_pin);
1807 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1810 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1811 mutex_lock(&per_pin->lock);
1812 per_pin->channels = substream->runtime->channels;
1813 per_pin->setup = true;
1815 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1816 mutex_unlock(&per_pin->lock);
1818 if (spec->dyn_pin_out) {
1819 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1820 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1821 snd_hda_codec_write(codec, pin_nid, 0,
1822 AC_VERB_SET_PIN_WIDGET_CONTROL,
1826 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1829 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1830 struct hda_codec *codec,
1831 struct snd_pcm_substream *substream)
1833 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1837 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1838 struct hda_codec *codec,
1839 struct snd_pcm_substream *substream)
1841 struct hdmi_spec *spec = codec->spec;
1842 int cvt_idx, pin_idx;
1843 struct hdmi_spec_per_cvt *per_cvt;
1844 struct hdmi_spec_per_pin *per_pin;
1848 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1849 if (snd_BUG_ON(cvt_idx < 0))
1851 per_cvt = get_cvt(spec, cvt_idx);
1853 snd_BUG_ON(!per_cvt->assigned);
1854 per_cvt->assigned = 0;
1857 pin_idx = hinfo_to_pin_index(codec, hinfo);
1858 if (snd_BUG_ON(pin_idx < 0))
1860 per_pin = get_pin(spec, pin_idx);
1862 if (spec->dyn_pin_out) {
1863 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1864 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1865 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1866 AC_VERB_SET_PIN_WIDGET_CONTROL,
1870 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1872 mutex_lock(&per_pin->lock);
1873 per_pin->chmap_set = false;
1874 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1876 per_pin->setup = false;
1877 per_pin->channels = 0;
1878 mutex_unlock(&per_pin->lock);
1884 static const struct hda_pcm_ops generic_ops = {
1885 .open = hdmi_pcm_open,
1886 .close = hdmi_pcm_close,
1887 .prepare = generic_hdmi_playback_pcm_prepare,
1888 .cleanup = generic_hdmi_playback_pcm_cleanup,
1892 * ALSA API channel-map control callbacks
1894 static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1895 struct snd_ctl_elem_info *uinfo)
1897 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1898 struct hda_codec *codec = info->private_data;
1899 struct hdmi_spec *spec = codec->spec;
1900 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1901 uinfo->count = spec->channels_max;
1902 uinfo->value.integer.min = 0;
1903 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1907 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1910 /* If the speaker allocation matches the channel count, it is OK.*/
1911 if (cap->channels != channels)
1914 /* all channels are remappable freely */
1915 return SNDRV_CTL_TLVT_CHMAP_VAR;
1918 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1919 unsigned int *chmap, int channels)
1924 for (c = 7; c >= 0; c--) {
1925 int spk = cap->speakers[c];
1929 chmap[count++] = spk_to_chmap(spk);
1932 WARN_ON(count != channels);
1935 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1936 unsigned int size, unsigned int __user *tlv)
1938 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1939 struct hda_codec *codec = info->private_data;
1940 struct hdmi_spec *spec = codec->spec;
1941 unsigned int __user *dst;
1946 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1950 for (chs = 2; chs <= spec->channels_max; chs++) {
1952 struct cea_channel_speaker_allocation *cap;
1953 cap = channel_allocations;
1954 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1955 int chs_bytes = chs * 4;
1956 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1957 unsigned int tlv_chmap[8];
1963 if (put_user(type, dst) ||
1964 put_user(chs_bytes, dst + 1))
1969 if (size < chs_bytes)
1973 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1974 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1979 if (put_user(count, tlv + 1))
1984 static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1985 struct snd_ctl_elem_value *ucontrol)
1987 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1988 struct hda_codec *codec = info->private_data;
1989 struct hdmi_spec *spec = codec->spec;
1990 int pin_idx = kcontrol->private_value;
1991 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1994 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1995 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1999 static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2000 struct snd_ctl_elem_value *ucontrol)
2002 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2003 struct hda_codec *codec = info->private_data;
2004 struct hdmi_spec *spec = codec->spec;
2005 int pin_idx = kcontrol->private_value;
2006 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2007 unsigned int ctl_idx;
2008 struct snd_pcm_substream *substream;
2009 unsigned char chmap[8];
2010 int i, err, ca, prepared = 0;
2012 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2013 substream = snd_pcm_chmap_substream(info, ctl_idx);
2014 if (!substream || !substream->runtime)
2015 return 0; /* just for avoiding error from alsactl restore */
2016 switch (substream->runtime->status->state) {
2017 case SNDRV_PCM_STATE_OPEN:
2018 case SNDRV_PCM_STATE_SETUP:
2020 case SNDRV_PCM_STATE_PREPARED:
2026 memset(chmap, 0, sizeof(chmap));
2027 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2028 chmap[i] = ucontrol->value.integer.value[i];
2029 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2031 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2034 if (spec->ops.chmap_validate) {
2035 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2039 mutex_lock(&per_pin->lock);
2040 per_pin->chmap_set = true;
2041 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2043 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2044 mutex_unlock(&per_pin->lock);
2049 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2051 struct hdmi_spec *spec = codec->spec;
2054 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2055 struct hda_pcm *info;
2056 struct hda_pcm_stream *pstr;
2058 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
2061 spec->pcm_rec[pin_idx] = info;
2062 info->pcm_type = HDA_PCM_TYPE_HDMI;
2063 info->own_chmap = true;
2065 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2066 pstr->substreams = 1;
2067 pstr->ops = generic_ops;
2068 /* other pstr fields are set in open */
2074 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2076 char hdmi_str[32] = "HDMI/DP";
2077 struct hdmi_spec *spec = codec->spec;
2078 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2079 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
2082 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2083 if (!is_jack_detectable(codec, per_pin->pin_nid))
2084 strncat(hdmi_str, " Phantom",
2085 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2087 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str);
2090 static int generic_hdmi_build_controls(struct hda_codec *codec)
2092 struct hdmi_spec *spec = codec->spec;
2096 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2097 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2099 err = generic_hdmi_build_jack(codec, pin_idx);
2103 err = snd_hda_create_dig_out_ctls(codec,
2105 per_pin->mux_nids[0],
2109 snd_hda_spdif_ctls_unassign(codec, pin_idx);
2111 /* add control for ELD Bytes */
2112 err = hdmi_create_eld_ctl(codec, pin_idx,
2113 get_pcm_rec(spec, pin_idx)->device);
2118 hdmi_present_sense(per_pin, 0);
2121 /* add channel maps */
2122 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2123 struct hda_pcm *pcm;
2124 struct snd_pcm_chmap *chmap;
2125 struct snd_kcontrol *kctl;
2128 pcm = spec->pcm_rec[pin_idx];
2129 if (!pcm || !pcm->pcm)
2131 err = snd_pcm_add_chmap_ctls(pcm->pcm,
2132 SNDRV_PCM_STREAM_PLAYBACK,
2133 NULL, 0, pin_idx, &chmap);
2136 /* override handlers */
2137 chmap->private_data = codec;
2139 for (i = 0; i < kctl->count; i++)
2140 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2141 kctl->info = hdmi_chmap_ctl_info;
2142 kctl->get = hdmi_chmap_ctl_get;
2143 kctl->put = hdmi_chmap_ctl_put;
2144 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2150 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2152 struct hdmi_spec *spec = codec->spec;
2155 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2156 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2158 per_pin->codec = codec;
2159 mutex_init(&per_pin->lock);
2160 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2161 eld_proc_new(per_pin, pin_idx);
2166 static int generic_hdmi_init(struct hda_codec *codec)
2168 struct hdmi_spec *spec = codec->spec;
2171 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2172 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2173 hda_nid_t pin_nid = per_pin->pin_nid;
2175 hdmi_init_pin(codec, pin_nid);
2176 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2177 codec->jackpoll_interval > 0 ? jack_callback : NULL);
2182 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2184 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2185 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2188 static void hdmi_array_free(struct hdmi_spec *spec)
2190 snd_array_free(&spec->pins);
2191 snd_array_free(&spec->cvts);
2194 static void generic_hdmi_free(struct hda_codec *codec)
2196 struct hdmi_spec *spec = codec->spec;
2199 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2200 snd_hdac_i915_register_notifier(NULL);
2202 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2203 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2205 cancel_delayed_work_sync(&per_pin->work);
2206 eld_proc_free(per_pin);
2209 hdmi_array_free(spec);
2214 static int generic_hdmi_resume(struct hda_codec *codec)
2216 struct hdmi_spec *spec = codec->spec;
2219 codec->patch_ops.init(codec);
2220 regcache_sync(codec->core.regmap);
2222 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2223 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2224 hdmi_present_sense(per_pin, 1);
2230 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2231 .init = generic_hdmi_init,
2232 .free = generic_hdmi_free,
2233 .build_pcms = generic_hdmi_build_pcms,
2234 .build_controls = generic_hdmi_build_controls,
2235 .unsol_event = hdmi_unsol_event,
2237 .resume = generic_hdmi_resume,
2241 static const struct hdmi_ops generic_standard_hdmi_ops = {
2242 .pin_get_eld = snd_hdmi_get_eld,
2243 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2244 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2245 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2246 .pin_hbr_setup = hdmi_pin_hbr_setup,
2247 .setup_stream = hdmi_setup_stream,
2248 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2249 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2253 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2256 struct hdmi_spec *spec = codec->spec;
2260 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2261 if (nconns == spec->num_cvts &&
2262 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2265 /* override pins connection list */
2266 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2267 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2270 #define INTEL_VENDOR_NID 0x08
2271 #define INTEL_GET_VENDOR_VERB 0xf81
2272 #define INTEL_SET_VENDOR_VERB 0x781
2273 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2274 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2276 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2279 unsigned int vendor_param;
2281 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2282 INTEL_GET_VENDOR_VERB, 0);
2283 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2286 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2287 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2288 INTEL_SET_VENDOR_VERB, vendor_param);
2289 if (vendor_param == -1)
2293 snd_hda_codec_update_widgets(codec);
2296 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2298 unsigned int vendor_param;
2300 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2301 INTEL_GET_VENDOR_VERB, 0);
2302 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2305 /* enable DP1.2 mode */
2306 vendor_param |= INTEL_EN_DP12;
2307 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2308 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2309 INTEL_SET_VENDOR_VERB, vendor_param);
2312 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2313 * Otherwise you may get severe h/w communication errors.
2315 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2316 unsigned int power_state)
2318 if (power_state == AC_PWRST_D0) {
2319 intel_haswell_enable_all_pins(codec, false);
2320 intel_haswell_fixup_enable_dp12(codec);
2323 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2324 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2327 static void intel_pin_eld_notify(void *audio_ptr, int port)
2329 struct hda_codec *codec = audio_ptr;
2330 int pin_nid = port + 0x04;
2332 check_presence_and_report(codec, pin_nid);
2335 static int patch_generic_hdmi(struct hda_codec *codec)
2337 struct hdmi_spec *spec;
2339 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2343 spec->ops = generic_standard_hdmi_ops;
2345 hdmi_array_init(spec, 4);
2347 if (is_haswell_plus(codec)) {
2348 intel_haswell_enable_all_pins(codec, true);
2349 intel_haswell_fixup_enable_dp12(codec);
2352 /* For Valleyview/Cherryview, only the display codec is in the display
2353 * power well and can use link_power ops to request/release the power.
2354 * For Haswell/Broadwell, the controller is also in the power well and
2355 * can cover the codec power request, and so need not set this flag.
2356 * For previous platforms, there is no such power well feature.
2358 if (is_valleyview_plus(codec) || is_skylake(codec))
2359 codec->core.link_power_control = 1;
2361 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
2362 codec->depop_delay = 0;
2363 spec->i915_audio_ops.audio_ptr = codec;
2364 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2365 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2368 if (hdmi_parse_codec(codec) < 0) {
2373 codec->patch_ops = generic_hdmi_patch_ops;
2374 if (is_haswell_plus(codec)) {
2375 codec->patch_ops.set_power_state = haswell_set_power_state;
2376 codec->dp_mst = true;
2379 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2380 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2381 codec->auto_runtime_pm = 1;
2383 generic_hdmi_init_per_pins(codec);
2385 init_channel_allocations();
2391 * Shared non-generic implementations
2394 static int simple_playback_build_pcms(struct hda_codec *codec)
2396 struct hdmi_spec *spec = codec->spec;
2397 struct hda_pcm *info;
2399 struct hda_pcm_stream *pstr;
2400 struct hdmi_spec_per_cvt *per_cvt;
2402 per_cvt = get_cvt(spec, 0);
2403 chans = get_wcaps(codec, per_cvt->cvt_nid);
2404 chans = get_wcaps_channels(chans);
2406 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2409 spec->pcm_rec[0] = info;
2410 info->pcm_type = HDA_PCM_TYPE_HDMI;
2411 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2412 *pstr = spec->pcm_playback;
2413 pstr->nid = per_cvt->cvt_nid;
2414 if (pstr->channels_max <= 2 && chans && chans <= 16)
2415 pstr->channels_max = chans;
2420 /* unsolicited event for jack sensing */
2421 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2424 snd_hda_jack_set_dirty_all(codec);
2425 snd_hda_jack_report_sync(codec);
2428 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2429 * as long as spec->pins[] is set correctly
2431 #define simple_hdmi_build_jack generic_hdmi_build_jack
2433 static int simple_playback_build_controls(struct hda_codec *codec)
2435 struct hdmi_spec *spec = codec->spec;
2436 struct hdmi_spec_per_cvt *per_cvt;
2439 per_cvt = get_cvt(spec, 0);
2440 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2445 return simple_hdmi_build_jack(codec, 0);
2448 static int simple_playback_init(struct hda_codec *codec)
2450 struct hdmi_spec *spec = codec->spec;
2451 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2452 hda_nid_t pin = per_pin->pin_nid;
2454 snd_hda_codec_write(codec, pin, 0,
2455 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2456 /* some codecs require to unmute the pin */
2457 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2458 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2460 snd_hda_jack_detect_enable(codec, pin);
2464 static void simple_playback_free(struct hda_codec *codec)
2466 struct hdmi_spec *spec = codec->spec;
2468 hdmi_array_free(spec);
2473 * Nvidia specific implementations
2476 #define Nv_VERB_SET_Channel_Allocation 0xF79
2477 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2478 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2479 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2481 #define nvhdmi_master_con_nid_7x 0x04
2482 #define nvhdmi_master_pin_nid_7x 0x05
2484 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2485 /*front, rear, clfe, rear_surr */
2489 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2490 /* set audio protect on */
2491 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2492 /* enable digital output on pin widget */
2493 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2497 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2498 /* set audio protect on */
2499 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2500 /* enable digital output on pin widget */
2501 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2502 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2503 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2504 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2505 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2509 #ifdef LIMITED_RATE_FMT_SUPPORT
2510 /* support only the safe format and rate */
2511 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2512 #define SUPPORTED_MAXBPS 16
2513 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2515 /* support all rates and formats */
2516 #define SUPPORTED_RATES \
2517 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2518 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2519 SNDRV_PCM_RATE_192000)
2520 #define SUPPORTED_MAXBPS 24
2521 #define SUPPORTED_FORMATS \
2522 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2525 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2527 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2531 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2533 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2537 static unsigned int channels_2_6_8[] = {
2541 static unsigned int channels_2_8[] = {
2545 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2546 .count = ARRAY_SIZE(channels_2_6_8),
2547 .list = channels_2_6_8,
2551 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2552 .count = ARRAY_SIZE(channels_2_8),
2553 .list = channels_2_8,
2557 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2558 struct hda_codec *codec,
2559 struct snd_pcm_substream *substream)
2561 struct hdmi_spec *spec = codec->spec;
2562 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2564 switch (codec->preset->id) {
2569 hw_constraints_channels = &hw_constraints_2_8_channels;
2572 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2578 if (hw_constraints_channels != NULL) {
2579 snd_pcm_hw_constraint_list(substream->runtime, 0,
2580 SNDRV_PCM_HW_PARAM_CHANNELS,
2581 hw_constraints_channels);
2583 snd_pcm_hw_constraint_step(substream->runtime, 0,
2584 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2587 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2590 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2591 struct hda_codec *codec,
2592 struct snd_pcm_substream *substream)
2594 struct hdmi_spec *spec = codec->spec;
2595 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2598 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2599 struct hda_codec *codec,
2600 unsigned int stream_tag,
2601 unsigned int format,
2602 struct snd_pcm_substream *substream)
2604 struct hdmi_spec *spec = codec->spec;
2605 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2606 stream_tag, format, substream);
2609 static const struct hda_pcm_stream simple_pcm_playback = {
2614 .open = simple_playback_pcm_open,
2615 .close = simple_playback_pcm_close,
2616 .prepare = simple_playback_pcm_prepare
2620 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2621 .build_controls = simple_playback_build_controls,
2622 .build_pcms = simple_playback_build_pcms,
2623 .init = simple_playback_init,
2624 .free = simple_playback_free,
2625 .unsol_event = simple_hdmi_unsol_event,
2628 static int patch_simple_hdmi(struct hda_codec *codec,
2629 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2631 struct hdmi_spec *spec;
2632 struct hdmi_spec_per_cvt *per_cvt;
2633 struct hdmi_spec_per_pin *per_pin;
2635 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2640 hdmi_array_init(spec, 1);
2642 spec->multiout.num_dacs = 0; /* no analog */
2643 spec->multiout.max_channels = 2;
2644 spec->multiout.dig_out_nid = cvt_nid;
2647 per_pin = snd_array_new(&spec->pins);
2648 per_cvt = snd_array_new(&spec->cvts);
2649 if (!per_pin || !per_cvt) {
2650 simple_playback_free(codec);
2653 per_cvt->cvt_nid = cvt_nid;
2654 per_pin->pin_nid = pin_nid;
2655 spec->pcm_playback = simple_pcm_playback;
2657 codec->patch_ops = simple_hdmi_patch_ops;
2662 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2665 unsigned int chanmask;
2666 int chan = channels ? (channels - 1) : 1;
2685 /* Set the audio infoframe channel allocation and checksum fields. The
2686 * channel count is computed implicitly by the hardware. */
2687 snd_hda_codec_write(codec, 0x1, 0,
2688 Nv_VERB_SET_Channel_Allocation, chanmask);
2690 snd_hda_codec_write(codec, 0x1, 0,
2691 Nv_VERB_SET_Info_Frame_Checksum,
2692 (0x71 - chan - chanmask));
2695 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2696 struct hda_codec *codec,
2697 struct snd_pcm_substream *substream)
2699 struct hdmi_spec *spec = codec->spec;
2702 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2703 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2704 for (i = 0; i < 4; i++) {
2705 /* set the stream id */
2706 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2707 AC_VERB_SET_CHANNEL_STREAMID, 0);
2708 /* set the stream format */
2709 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2710 AC_VERB_SET_STREAM_FORMAT, 0);
2713 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2714 * streams are disabled. */
2715 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2717 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2720 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2721 struct hda_codec *codec,
2722 unsigned int stream_tag,
2723 unsigned int format,
2724 struct snd_pcm_substream *substream)
2727 unsigned int dataDCC2, channel_id;
2729 struct hdmi_spec *spec = codec->spec;
2730 struct hda_spdif_out *spdif;
2731 struct hdmi_spec_per_cvt *per_cvt;
2733 mutex_lock(&codec->spdif_mutex);
2734 per_cvt = get_cvt(spec, 0);
2735 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2737 chs = substream->runtime->channels;
2741 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2742 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2743 snd_hda_codec_write(codec,
2744 nvhdmi_master_con_nid_7x,
2746 AC_VERB_SET_DIGI_CONVERT_1,
2747 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2749 /* set the stream id */
2750 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2751 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2753 /* set the stream format */
2754 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2755 AC_VERB_SET_STREAM_FORMAT, format);
2757 /* turn on again (if needed) */
2758 /* enable and set the channel status audio/data flag */
2759 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2760 snd_hda_codec_write(codec,
2761 nvhdmi_master_con_nid_7x,
2763 AC_VERB_SET_DIGI_CONVERT_1,
2764 spdif->ctls & 0xff);
2765 snd_hda_codec_write(codec,
2766 nvhdmi_master_con_nid_7x,
2768 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2771 for (i = 0; i < 4; i++) {
2777 /* turn off SPDIF once;
2778 *otherwise the IEC958 bits won't be updated
2780 if (codec->spdif_status_reset &&
2781 (spdif->ctls & AC_DIG1_ENABLE))
2782 snd_hda_codec_write(codec,
2783 nvhdmi_con_nids_7x[i],
2785 AC_VERB_SET_DIGI_CONVERT_1,
2786 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2787 /* set the stream id */
2788 snd_hda_codec_write(codec,
2789 nvhdmi_con_nids_7x[i],
2791 AC_VERB_SET_CHANNEL_STREAMID,
2792 (stream_tag << 4) | channel_id);
2793 /* set the stream format */
2794 snd_hda_codec_write(codec,
2795 nvhdmi_con_nids_7x[i],
2797 AC_VERB_SET_STREAM_FORMAT,
2799 /* turn on again (if needed) */
2800 /* enable and set the channel status audio/data flag */
2801 if (codec->spdif_status_reset &&
2802 (spdif->ctls & AC_DIG1_ENABLE)) {
2803 snd_hda_codec_write(codec,
2804 nvhdmi_con_nids_7x[i],
2806 AC_VERB_SET_DIGI_CONVERT_1,
2807 spdif->ctls & 0xff);
2808 snd_hda_codec_write(codec,
2809 nvhdmi_con_nids_7x[i],
2811 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2815 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2817 mutex_unlock(&codec->spdif_mutex);
2821 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2825 .nid = nvhdmi_master_con_nid_7x,
2826 .rates = SUPPORTED_RATES,
2827 .maxbps = SUPPORTED_MAXBPS,
2828 .formats = SUPPORTED_FORMATS,
2830 .open = simple_playback_pcm_open,
2831 .close = nvhdmi_8ch_7x_pcm_close,
2832 .prepare = nvhdmi_8ch_7x_pcm_prepare
2836 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2838 struct hdmi_spec *spec;
2839 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2840 nvhdmi_master_pin_nid_7x);
2844 codec->patch_ops.init = nvhdmi_7x_init_2ch;
2845 /* override the PCM rates, etc, as the codec doesn't give full list */
2847 spec->pcm_playback.rates = SUPPORTED_RATES;
2848 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2849 spec->pcm_playback.formats = SUPPORTED_FORMATS;
2853 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2855 struct hdmi_spec *spec = codec->spec;
2856 int err = simple_playback_build_pcms(codec);
2858 struct hda_pcm *info = get_pcm_rec(spec, 0);
2859 info->own_chmap = true;
2864 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2866 struct hdmi_spec *spec = codec->spec;
2867 struct hda_pcm *info;
2868 struct snd_pcm_chmap *chmap;
2871 err = simple_playback_build_controls(codec);
2875 /* add channel maps */
2876 info = get_pcm_rec(spec, 0);
2877 err = snd_pcm_add_chmap_ctls(info->pcm,
2878 SNDRV_PCM_STREAM_PLAYBACK,
2879 snd_pcm_alt_chmaps, 8, 0, &chmap);
2882 switch (codec->preset->id) {
2887 chmap->channel_mask = (1U << 2) | (1U << 8);
2890 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2895 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2897 struct hdmi_spec *spec;
2898 int err = patch_nvhdmi_2ch(codec);
2902 spec->multiout.max_channels = 8;
2903 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2904 codec->patch_ops.init = nvhdmi_7x_init_8ch;
2905 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2906 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2908 /* Initialize the audio infoframe channel mask and checksum to something
2910 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2916 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2920 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2923 if (cap->ca_index == 0x00 && channels == 2)
2924 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2926 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2929 static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2931 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2937 static int patch_nvhdmi(struct hda_codec *codec)
2939 struct hdmi_spec *spec;
2942 err = patch_generic_hdmi(codec);
2947 spec->dyn_pin_out = true;
2949 spec->ops.chmap_cea_alloc_validate_get_type =
2950 nvhdmi_chmap_cea_alloc_validate_get_type;
2951 spec->ops.chmap_validate = nvhdmi_chmap_validate;
2957 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
2958 * accessed using vendor-defined verbs. These registers can be used for
2959 * interoperability between the HDA and HDMI drivers.
2962 /* Audio Function Group node */
2963 #define NVIDIA_AFG_NID 0x01
2966 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
2967 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
2968 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
2969 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
2970 * additional bit (at position 30) to signal the validity of the format.
2972 * | 31 | 30 | 29 16 | 15 0 |
2973 * +---------+-------+--------+--------+
2974 * | TRIGGER | VALID | UNUSED | FORMAT |
2975 * +-----------------------------------|
2977 * Note that for the trigger bit to take effect it needs to change value
2978 * (i.e. it needs to be toggled).
2980 #define NVIDIA_GET_SCRATCH0 0xfa6
2981 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
2982 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
2983 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
2984 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
2985 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
2986 #define NVIDIA_SCRATCH_VALID (1 << 6)
2988 #define NVIDIA_GET_SCRATCH1 0xfab
2989 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
2990 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
2991 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
2992 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
2995 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
2996 * the format is invalidated so that the HDMI codec can be disabled.
2998 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3002 /* bits [31:30] contain the trigger and valid bits */
3003 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3004 NVIDIA_GET_SCRATCH0, 0);
3005 value = (value >> 24) & 0xff;
3007 /* bits [15:0] are used to store the HDA format */
3008 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3009 NVIDIA_SET_SCRATCH0_BYTE0,
3010 (format >> 0) & 0xff);
3011 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3012 NVIDIA_SET_SCRATCH0_BYTE1,
3013 (format >> 8) & 0xff);
3015 /* bits [16:24] are unused */
3016 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3017 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3020 * Bit 30 signals that the data is valid and hence that HDMI audio can
3024 value &= ~NVIDIA_SCRATCH_VALID;
3026 value |= NVIDIA_SCRATCH_VALID;
3029 * Whenever the trigger bit is toggled, an interrupt is raised in the
3030 * HDMI codec. The HDMI driver will use that as trigger to update its
3033 value ^= NVIDIA_SCRATCH_TRIGGER;
3035 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3036 NVIDIA_SET_SCRATCH0_BYTE3, value);
3039 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3040 struct hda_codec *codec,
3041 unsigned int stream_tag,
3042 unsigned int format,
3043 struct snd_pcm_substream *substream)
3047 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3052 /* notify the HDMI codec of the format change */
3053 tegra_hdmi_set_format(codec, format);
3058 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3059 struct hda_codec *codec,
3060 struct snd_pcm_substream *substream)
3062 /* invalidate the format in the HDMI codec */
3063 tegra_hdmi_set_format(codec, 0);
3065 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3068 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3070 struct hdmi_spec *spec = codec->spec;
3073 for (i = 0; i < spec->num_pins; i++) {
3074 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3076 if (pcm->pcm_type == type)
3083 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3085 struct hda_pcm_stream *stream;
3086 struct hda_pcm *pcm;
3089 err = generic_hdmi_build_pcms(codec);
3093 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3098 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3099 * codec about format changes.
3101 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3102 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3103 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3108 static int patch_tegra_hdmi(struct hda_codec *codec)
3112 err = patch_generic_hdmi(codec);
3116 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3122 * ATI/AMD-specific implementations
3125 #define is_amdhdmi_rev3_or_later(codec) \
3126 ((codec)->core.vendor_id == 0x1002aa01 && \
3127 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3128 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3130 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3131 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3132 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3133 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3134 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3135 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3136 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3137 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3138 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3139 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3140 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3141 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3142 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3143 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3144 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3145 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3146 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3147 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3148 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3149 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3150 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3151 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3152 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3153 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3154 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3156 /* AMD specific HDA cvt verbs */
3157 #define ATI_VERB_SET_RAMP_RATE 0x770
3158 #define ATI_VERB_GET_RAMP_RATE 0xf70
3160 #define ATI_OUT_ENABLE 0x1
3162 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3163 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3165 #define ATI_HBR_CAPABLE 0x01
3166 #define ATI_HBR_ENABLE 0x10
3168 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3169 unsigned char *buf, int *eld_size)
3171 /* call hda_eld.c ATI/AMD-specific function */
3172 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3173 is_amdhdmi_rev3_or_later(codec));
3176 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3177 int active_channels, int conn_type)
3179 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3182 static int atihdmi_paired_swap_fc_lfe(int pos)
3185 * ATI/AMD have automatic FC/LFE swap built-in
3186 * when in pairwise mapping mode.
3190 /* see channel_allocations[].speakers[] */
3199 static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3201 struct cea_channel_speaker_allocation *cap;
3204 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3206 cap = &channel_allocations[get_channel_allocation_order(ca)];
3207 for (i = 0; i < chs; ++i) {
3208 int mask = to_spk_mask(map[i]);
3210 bool companion_ok = false;
3215 for (j = 0 + i % 2; j < 8; j += 2) {
3216 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3217 if (cap->speakers[chan_idx] == mask) {
3218 /* channel is in a supported position */
3221 if (i % 2 == 0 && i + 1 < chs) {
3222 /* even channel, check the odd companion */
3223 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3224 int comp_mask_req = to_spk_mask(map[i+1]);
3225 int comp_mask_act = cap->speakers[comp_chan_idx];
3227 if (comp_mask_req == comp_mask_act)
3228 companion_ok = true;
3240 i++; /* companion channel already checked */
3246 static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3247 int hdmi_slot, int stream_channel)
3250 int ati_channel_setup = 0;
3255 if (!has_amd_full_remap_support(codec)) {
3256 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3258 /* In case this is an odd slot but without stream channel, do not
3259 * disable the slot since the corresponding even slot could have a
3260 * channel. In case neither have a channel, the slot pair will be
3261 * disabled when this function is called for the even slot. */
3262 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3265 hdmi_slot -= hdmi_slot % 2;
3267 if (stream_channel != 0xf)
3268 stream_channel -= stream_channel % 2;
3271 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3273 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3275 if (stream_channel != 0xf)
3276 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3278 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3281 static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3284 bool was_odd = false;
3285 int ati_asp_slot = asp_slot;
3287 int ati_channel_setup;
3292 if (!has_amd_full_remap_support(codec)) {
3293 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3294 if (ati_asp_slot % 2 != 0) {
3300 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3302 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3304 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3307 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3310 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3316 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3317 * we need to take that into account (a single channel may take 2
3318 * channel slots if we need to carry a silent channel next to it).
3319 * On Rev3+ AMD codecs this function is not used.
3323 /* We only produce even-numbered channel count TLVs */
3324 if ((channels % 2) != 0)
3327 for (c = 0; c < 7; c += 2) {
3328 if (cap->speakers[c] || cap->speakers[c+1])
3332 if (chanpairs * 2 != channels)
3335 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3338 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3339 unsigned int *chmap, int channels)
3341 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3345 for (c = 7; c >= 0; c--) {
3346 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3347 int spk = cap->speakers[chan];
3349 /* add N/A channel if the companion channel is occupied */
3350 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3351 chmap[count++] = SNDRV_CHMAP_NA;
3356 chmap[count++] = spk_to_chmap(spk);
3359 WARN_ON(count != channels);
3362 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3365 int hbr_ctl, hbr_ctl_new;
3367 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3368 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3370 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3372 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3375 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3377 hbr_ctl == hbr_ctl_new ? "" : "new-",
3380 if (hbr_ctl != hbr_ctl_new)
3381 snd_hda_codec_write(codec, pin_nid, 0,
3382 ATI_VERB_SET_HBR_CONTROL,
3391 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3392 hda_nid_t pin_nid, u32 stream_tag, int format)
3395 if (is_amdhdmi_rev3_or_later(codec)) {
3396 int ramp_rate = 180; /* default as per AMD spec */
3397 /* disable ramp-up/down for non-pcm as per AMD spec */
3398 if (format & AC_FMT_TYPE_NON_PCM)
3401 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3404 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3408 static int atihdmi_init(struct hda_codec *codec)
3410 struct hdmi_spec *spec = codec->spec;
3413 err = generic_hdmi_init(codec);
3418 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3419 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3421 /* make sure downmix information in infoframe is zero */
3422 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3424 /* enable channel-wise remap mode if supported */
3425 if (has_amd_full_remap_support(codec))
3426 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3427 ATI_VERB_SET_MULTICHANNEL_MODE,
3428 ATI_MULTICHANNEL_MODE_SINGLE);
3434 static int patch_atihdmi(struct hda_codec *codec)
3436 struct hdmi_spec *spec;
3437 struct hdmi_spec_per_cvt *per_cvt;
3440 err = patch_generic_hdmi(codec);
3445 codec->patch_ops.init = atihdmi_init;
3449 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3450 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3451 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3452 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3453 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3454 spec->ops.setup_stream = atihdmi_setup_stream;
3456 if (!has_amd_full_remap_support(codec)) {
3457 /* override to ATI/AMD-specific versions with pairwise mapping */
3458 spec->ops.chmap_cea_alloc_validate_get_type =
3459 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3460 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3461 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3464 /* ATI/AMD converters do not advertise all of their capabilities */
3465 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3466 per_cvt = get_cvt(spec, cvt_idx);
3467 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3468 per_cvt->rates |= SUPPORTED_RATES;
3469 per_cvt->formats |= SUPPORTED_FORMATS;
3470 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3473 spec->channels_max = max(spec->channels_max, 8u);
3478 /* VIA HDMI Implementation */
3479 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3480 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3482 static int patch_via_hdmi(struct hda_codec *codec)
3484 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3490 static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
3491 { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
3492 { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
3493 { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
3494 { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
3495 { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
3496 { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
3497 { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
3498 { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3499 { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3500 { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3501 { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3502 { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
3503 { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
3504 { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
3505 { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi },
3506 { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
3507 { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
3508 { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
3509 { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
3510 { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
3511 { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
3512 { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
3513 { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
3514 /* 17 is known to be absent */
3515 { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
3516 { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
3517 { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
3518 { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
3519 { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
3520 { .id = 0x10de0020, .name = "Tegra30 HDMI", .patch = patch_tegra_hdmi },
3521 { .id = 0x10de0022, .name = "Tegra114 HDMI", .patch = patch_tegra_hdmi },
3522 { .id = 0x10de0028, .name = "Tegra124 HDMI", .patch = patch_tegra_hdmi },
3523 { .id = 0x10de0029, .name = "Tegra210 HDMI/DP", .patch = patch_tegra_hdmi },
3524 { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
3525 { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
3526 { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
3527 { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
3528 { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
3529 { .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
3530 { .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
3531 { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
3532 { .id = 0x10de0070, .name = "GPU 70 HDMI/DP", .patch = patch_nvhdmi },
3533 { .id = 0x10de0071, .name = "GPU 71 HDMI/DP", .patch = patch_nvhdmi },
3534 { .id = 0x10de0072, .name = "GPU 72 HDMI/DP", .patch = patch_nvhdmi },
3535 { .id = 0x10de007d, .name = "GPU 7d HDMI/DP", .patch = patch_nvhdmi },
3536 { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3537 { .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3538 { .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3539 { .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3540 { .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3541 { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3542 { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
3543 { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
3544 { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
3545 { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3546 { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
3547 { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
3548 { .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
3549 { .id = 0x80862808, .name = "Broadwell HDMI", .patch = patch_generic_hdmi },
3550 { .id = 0x80862809, .name = "Skylake HDMI", .patch = patch_generic_hdmi },
3551 { .id = 0x8086280a, .name = "Broxton HDMI", .patch = patch_generic_hdmi },
3552 { .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
3553 { .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
3554 { .id = 0x80862883, .name = "Braswell HDMI", .patch = patch_generic_hdmi },
3555 { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
3556 /* special ID for generic HDMI */
3557 { .id = HDA_CODEC_ID_GENERIC_HDMI, .patch = patch_generic_hdmi },
3561 MODULE_ALIAS("snd-hda-codec-id:1002793c");
3562 MODULE_ALIAS("snd-hda-codec-id:10027919");
3563 MODULE_ALIAS("snd-hda-codec-id:1002791a");
3564 MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3565 MODULE_ALIAS("snd-hda-codec-id:10951390");
3566 MODULE_ALIAS("snd-hda-codec-id:10951392");
3567 MODULE_ALIAS("snd-hda-codec-id:10de0002");
3568 MODULE_ALIAS("snd-hda-codec-id:10de0003");
3569 MODULE_ALIAS("snd-hda-codec-id:10de0005");
3570 MODULE_ALIAS("snd-hda-codec-id:10de0006");
3571 MODULE_ALIAS("snd-hda-codec-id:10de0007");
3572 MODULE_ALIAS("snd-hda-codec-id:10de000a");
3573 MODULE_ALIAS("snd-hda-codec-id:10de000b");
3574 MODULE_ALIAS("snd-hda-codec-id:10de000c");
3575 MODULE_ALIAS("snd-hda-codec-id:10de000d");
3576 MODULE_ALIAS("snd-hda-codec-id:10de0010");
3577 MODULE_ALIAS("snd-hda-codec-id:10de0011");
3578 MODULE_ALIAS("snd-hda-codec-id:10de0012");
3579 MODULE_ALIAS("snd-hda-codec-id:10de0013");
3580 MODULE_ALIAS("snd-hda-codec-id:10de0014");
3581 MODULE_ALIAS("snd-hda-codec-id:10de0015");
3582 MODULE_ALIAS("snd-hda-codec-id:10de0016");
3583 MODULE_ALIAS("snd-hda-codec-id:10de0018");
3584 MODULE_ALIAS("snd-hda-codec-id:10de0019");
3585 MODULE_ALIAS("snd-hda-codec-id:10de001a");
3586 MODULE_ALIAS("snd-hda-codec-id:10de001b");
3587 MODULE_ALIAS("snd-hda-codec-id:10de001c");
3588 MODULE_ALIAS("snd-hda-codec-id:10de0028");
3589 MODULE_ALIAS("snd-hda-codec-id:10de0040");
3590 MODULE_ALIAS("snd-hda-codec-id:10de0041");
3591 MODULE_ALIAS("snd-hda-codec-id:10de0042");
3592 MODULE_ALIAS("snd-hda-codec-id:10de0043");
3593 MODULE_ALIAS("snd-hda-codec-id:10de0044");
3594 MODULE_ALIAS("snd-hda-codec-id:10de0051");
3595 MODULE_ALIAS("snd-hda-codec-id:10de0060");
3596 MODULE_ALIAS("snd-hda-codec-id:10de0067");
3597 MODULE_ALIAS("snd-hda-codec-id:10de0070");
3598 MODULE_ALIAS("snd-hda-codec-id:10de0071");
3599 MODULE_ALIAS("snd-hda-codec-id:10de0072");
3600 MODULE_ALIAS("snd-hda-codec-id:10de007d");
3601 MODULE_ALIAS("snd-hda-codec-id:10de8001");
3602 MODULE_ALIAS("snd-hda-codec-id:11069f80");
3603 MODULE_ALIAS("snd-hda-codec-id:11069f81");
3604 MODULE_ALIAS("snd-hda-codec-id:11069f84");
3605 MODULE_ALIAS("snd-hda-codec-id:11069f85");
3606 MODULE_ALIAS("snd-hda-codec-id:17e80047");
3607 MODULE_ALIAS("snd-hda-codec-id:80860054");
3608 MODULE_ALIAS("snd-hda-codec-id:80862801");
3609 MODULE_ALIAS("snd-hda-codec-id:80862802");
3610 MODULE_ALIAS("snd-hda-codec-id:80862803");
3611 MODULE_ALIAS("snd-hda-codec-id:80862804");
3612 MODULE_ALIAS("snd-hda-codec-id:80862805");
3613 MODULE_ALIAS("snd-hda-codec-id:80862806");
3614 MODULE_ALIAS("snd-hda-codec-id:80862807");
3615 MODULE_ALIAS("snd-hda-codec-id:80862808");
3616 MODULE_ALIAS("snd-hda-codec-id:80862809");
3617 MODULE_ALIAS("snd-hda-codec-id:8086280a");
3618 MODULE_ALIAS("snd-hda-codec-id:80862880");
3619 MODULE_ALIAS("snd-hda-codec-id:80862882");
3620 MODULE_ALIAS("snd-hda-codec-id:80862883");
3621 MODULE_ALIAS("snd-hda-codec-id:808629fb");
3623 MODULE_LICENSE("GPL");
3624 MODULE_DESCRIPTION("HDMI HD-audio codec");
3625 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3626 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3627 MODULE_ALIAS("snd-hda-codec-atihdmi");
3629 static struct hda_codec_driver hdmi_driver = {
3630 .preset = snd_hda_preset_hdmi,
3633 module_hda_codec_driver(hdmi_driver);