sound/pci/maestro3.c

   1 /*
   2  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
   3  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
   4  *                       Takashi Iwai <tiwai@suse.de>
   5  *
   6  * Most of the hardware init stuffs are based on maestro3 driver for
   7  * OSS/Free by Zach Brown.  Many thanks to Zach!
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of the GNU General Public License as published by
  11  *   the Free Software Foundation; either version 2 of the License, or
  12  *   (at your option) any later version.
  13  *
  14  *   This program is distributed in the hope that it will be useful,
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *   GNU General Public License for more details.
  18  *
  19  *   You should have received a copy of the GNU General Public License
  20  *   along with this program; if not, write to the Free Software
  21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  *
  23  *
  24  * ChangeLog:
  25  * Aug. 27, 2001
  26  *     - Fixed deadlock on capture
  27  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  28  *
  29  */
  30
  31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  32 #define DRIVER_NAME "Maestro3"
  33
  34 #include <sound/driver.h>
  35 #include <asm/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/init.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/vmalloc.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/firmware.h>
  45 #include <sound/core.h>
  46 #include <sound/info.h>
  47 #include <sound/control.h>
  48 #include <sound/pcm.h>
  49 #include <sound/mpu401.h>
  50 #include <sound/ac97_codec.h>
  51 #include <sound/initval.h>
  52 #include <asm/byteorder.h>
  53
  54 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  55 MODULE_DESCRIPTION("ESS Maestro3 PCI");
  56 MODULE_LICENSE("GPL");
  57 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
  58                 "{ESS,ES1988},"
  59                 "{ESS,Allegro PCI},"
  60                 "{ESS,Allegro-1 PCI},"
  61                 "{ESS,Canyon3D-2/LE PCI}}");
  62
  63 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  64 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  65 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  66 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  67 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  68
  69 module_param_array(index, int, NULL, 0444);
  70 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  71 module_param_array(id, charp, NULL, 0444);
  72 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  73 module_param_array(enable, bool, NULL, 0444);
  74 MODULE_PARM_DESC(enable, "Enable this soundcard.");
  75 module_param_array(external_amp, bool, NULL, 0444);
  76 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  77 module_param_array(amp_gpio, int, NULL, 0444);
  78 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  79
  80 #define MAX_PLAYBACKS   2
  81 #define MAX_CAPTURES    1
  82 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
  83
  84
  85 /*
  86  * maestro3 registers
  87  */
  88
  89 /* Allegro PCI configuration registers */
  90 #define PCI_LEGACY_AUDIO_CTRL   0x40
  91 #define SOUND_BLASTER_ENABLE    0x00000001
  92 #define FM_SYNTHESIS_ENABLE     0x00000002
  93 #define GAME_PORT_ENABLE        0x00000004
  94 #define MPU401_IO_ENABLE        0x00000008
  95 #define MPU401_IRQ_ENABLE       0x00000010
  96 #define ALIAS_10BIT_IO          0x00000020
  97 #define SB_DMA_MASK             0x000000C0
  98 #define SB_DMA_0                0x00000040
  99 #define SB_DMA_1                0x00000040
 100 #define SB_DMA_R                0x00000080
 101 #define SB_DMA_3                0x000000C0
 102 #define SB_IRQ_MASK             0x00000700
 103 #define SB_IRQ_5                0x00000000
 104 #define SB_IRQ_7                0x00000100
 105 #define SB_IRQ_9                0x00000200
 106 #define SB_IRQ_10               0x00000300
 107 #define MIDI_IRQ_MASK           0x00003800
 108 #define SERIAL_IRQ_ENABLE       0x00004000
 109 #define DISABLE_LEGACY          0x00008000
 110
 111 #define PCI_ALLEGRO_CONFIG      0x50
 112 #define SB_ADDR_240             0x00000004
 113 #define MPU_ADDR_MASK           0x00000018
 114 #define MPU_ADDR_330            0x00000000
 115 #define MPU_ADDR_300            0x00000008
 116 #define MPU_ADDR_320            0x00000010
 117 #define MPU_ADDR_340            0x00000018
 118 #define USE_PCI_TIMING          0x00000040
 119 #define POSTED_WRITE_ENABLE     0x00000080
 120 #define DMA_POLICY_MASK         0x00000700
 121 #define DMA_DDMA                0x00000000
 122 #define DMA_TDMA                0x00000100
 123 #define DMA_PCPCI               0x00000200
 124 #define DMA_WBDMA16             0x00000400
 125 #define DMA_WBDMA4              0x00000500
 126 #define DMA_WBDMA2              0x00000600
 127 #define DMA_WBDMA1              0x00000700
 128 #define DMA_SAFE_GUARD          0x00000800
 129 #define HI_PERF_GP_ENABLE       0x00001000
 130 #define PIC_SNOOP_MODE_0        0x00002000
 131 #define PIC_SNOOP_MODE_1        0x00004000
 132 #define SOUNDBLASTER_IRQ_MASK   0x00008000
 133 #define RING_IN_ENABLE          0x00010000
 134 #define SPDIF_TEST_MODE         0x00020000
 135 #define CLK_MULT_MODE_SELECT_2  0x00040000
 136 #define EEPROM_WRITE_ENABLE     0x00080000
 137 #define CODEC_DIR_IN            0x00100000
 138 #define HV_BUTTON_FROM_GD       0x00200000
 139 #define REDUCED_DEBOUNCE        0x00400000
 140 #define HV_CTRL_ENABLE          0x00800000
 141 #define SPDIF_ENABLE            0x01000000
 142 #define CLK_DIV_SELECT          0x06000000
 143 #define CLK_DIV_BY_48           0x00000000
 144 #define CLK_DIV_BY_49           0x02000000
 145 #define CLK_DIV_BY_50           0x04000000
 146 #define CLK_DIV_RESERVED        0x06000000
 147 #define PM_CTRL_ENABLE          0x08000000
 148 #define CLK_MULT_MODE_SELECT    0x30000000
 149 #define CLK_MULT_MODE_SHIFT     28
 150 #define CLK_MULT_MODE_0         0x00000000
 151 #define CLK_MULT_MODE_1         0x10000000
 152 #define CLK_MULT_MODE_2         0x20000000
 153 #define CLK_MULT_MODE_3         0x30000000
 154 #define INT_CLK_SELECT          0x40000000
 155 #define INT_CLK_MULT_RESET      0x80000000
 156
 157 /* M3 */
 158 #define INT_CLK_SRC_NOT_PCI     0x00100000
 159 #define INT_CLK_MULT_ENABLE     0x80000000
 160
 161 #define PCI_ACPI_CONTROL        0x54
 162 #define PCI_ACPI_D0             0x00000000
 163 #define PCI_ACPI_D1             0xB4F70000
 164 #define PCI_ACPI_D2             0xB4F7B4F7
 165
 166 #define PCI_USER_CONFIG         0x58
 167 #define EXT_PCI_MASTER_ENABLE   0x00000001
 168 #define SPDIF_OUT_SELECT        0x00000002
 169 #define TEST_PIN_DIR_CTRL       0x00000004
 170 #define AC97_CODEC_TEST         0x00000020
 171 #define TRI_STATE_BUFFER        0x00000080
 172 #define IN_CLK_12MHZ_SELECT     0x00000100
 173 #define MULTI_FUNC_DISABLE      0x00000200
 174 #define EXT_MASTER_PAIR_SEL     0x00000400
 175 #define PCI_MASTER_SUPPORT      0x00000800
 176 #define STOP_CLOCK_ENABLE       0x00001000
 177 #define EAPD_DRIVE_ENABLE       0x00002000
 178 #define REQ_TRI_STATE_ENABLE    0x00004000
 179 #define REQ_LOW_ENABLE          0x00008000
 180 #define MIDI_1_ENABLE           0x00010000
 181 #define MIDI_2_ENABLE           0x00020000
 182 #define SB_AUDIO_SYNC           0x00040000
 183 #define HV_CTRL_TEST            0x00100000
 184 #define SOUNDBLASTER_TEST       0x00400000
 185
 186 #define PCI_USER_CONFIG_C       0x5C
 187
 188 #define PCI_DDMA_CTRL           0x60
 189 #define DDMA_ENABLE             0x00000001
 190
 191
 192 /* Allegro registers */
 193 #define HOST_INT_CTRL           0x18
 194 #define SB_INT_ENABLE           0x0001
 195 #define MPU401_INT_ENABLE       0x0002
 196 #define ASSP_INT_ENABLE         0x0010
 197 #define RING_INT_ENABLE         0x0020
 198 #define HV_INT_ENABLE           0x0040
 199 #define CLKRUN_GEN_ENABLE       0x0100
 200 #define HV_CTRL_TO_PME          0x0400
 201 #define SOFTWARE_RESET_ENABLE   0x8000
 202
 203 /*
 204  * should be using the above defines, probably.
 205  */
 206 #define REGB_ENABLE_RESET               0x01
 207 #define REGB_STOP_CLOCK                 0x10
 208
 209 #define HOST_INT_STATUS         0x1A
 210 #define SB_INT_PENDING          0x01
 211 #define MPU401_INT_PENDING      0x02
 212 #define ASSP_INT_PENDING        0x10
 213 #define RING_INT_PENDING        0x20
 214 #define HV_INT_PENDING          0x40
 215
 216 #define HARDWARE_VOL_CTRL       0x1B
 217 #define SHADOW_MIX_REG_VOICE    0x1C
 218 #define HW_VOL_COUNTER_VOICE    0x1D
 219 #define SHADOW_MIX_REG_MASTER   0x1E
 220 #define HW_VOL_COUNTER_MASTER   0x1F
 221
 222 #define CODEC_COMMAND           0x30
 223 #define CODEC_READ_B            0x80
 224
 225 #define CODEC_STATUS            0x30
 226 #define CODEC_BUSY_B            0x01
 227
 228 #define CODEC_DATA              0x32
 229
 230 #define RING_BUS_CTRL_A         0x36
 231 #define RAC_PME_ENABLE          0x0100
 232 #define RAC_SDFS_ENABLE         0x0200
 233 #define LAC_PME_ENABLE          0x0400
 234 #define LAC_SDFS_ENABLE         0x0800
 235 #define SERIAL_AC_LINK_ENABLE   0x1000
 236 #define IO_SRAM_ENABLE          0x2000
 237 #define IIS_INPUT_ENABLE        0x8000
 238
 239 #define RING_BUS_CTRL_B         0x38
 240 #define SECOND_CODEC_ID_MASK    0x0003
 241 #define SPDIF_FUNC_ENABLE       0x0010
 242 #define SECOND_AC_ENABLE        0x0020
 243 #define SB_MODULE_INTF_ENABLE   0x0040
 244 #define SSPE_ENABLE             0x0040
 245 #define M3I_DOCK_ENABLE         0x0080
 246
 247 #define SDO_OUT_DEST_CTRL       0x3A
 248 #define COMMAND_ADDR_OUT        0x0003
 249 #define PCM_LR_OUT_LOCAL        0x0000
 250 #define PCM_LR_OUT_REMOTE       0x0004
 251 #define PCM_LR_OUT_MUTE         0x0008
 252 #define PCM_LR_OUT_BOTH         0x000C
 253 #define LINE1_DAC_OUT_LOCAL     0x0000
 254 #define LINE1_DAC_OUT_REMOTE    0x0010
 255 #define LINE1_DAC_OUT_MUTE      0x0020
 256 #define LINE1_DAC_OUT_BOTH      0x0030
 257 #define PCM_CLS_OUT_LOCAL       0x0000
 258 #define PCM_CLS_OUT_REMOTE      0x0040
 259 #define PCM_CLS_OUT_MUTE        0x0080
 260 #define PCM_CLS_OUT_BOTH        0x00C0
 261 #define PCM_RLF_OUT_LOCAL       0x0000
 262 #define PCM_RLF_OUT_REMOTE      0x0100
 263 #define PCM_RLF_OUT_MUTE        0x0200
 264 #define PCM_RLF_OUT_BOTH        0x0300
 265 #define LINE2_DAC_OUT_LOCAL     0x0000
 266 #define LINE2_DAC_OUT_REMOTE    0x0400
 267 #define LINE2_DAC_OUT_MUTE      0x0800
 268 #define LINE2_DAC_OUT_BOTH      0x0C00
 269 #define HANDSET_OUT_LOCAL       0x0000
 270 #define HANDSET_OUT_REMOTE      0x1000
 271 #define HANDSET_OUT_MUTE        0x2000
 272 #define HANDSET_OUT_BOTH        0x3000
 273 #define IO_CTRL_OUT_LOCAL       0x0000
 274 #define IO_CTRL_OUT_REMOTE      0x4000
 275 #define IO_CTRL_OUT_MUTE        0x8000
 276 #define IO_CTRL_OUT_BOTH        0xC000
 277
 278 #define SDO_IN_DEST_CTRL        0x3C
 279 #define STATUS_ADDR_IN          0x0003
 280 #define PCM_LR_IN_LOCAL         0x0000
 281 #define PCM_LR_IN_REMOTE        0x0004
 282 #define PCM_LR_RESERVED         0x0008
 283 #define PCM_LR_IN_BOTH          0x000C
 284 #define LINE1_ADC_IN_LOCAL      0x0000
 285 #define LINE1_ADC_IN_REMOTE     0x0010
 286 #define LINE1_ADC_IN_MUTE       0x0020
 287 #define MIC_ADC_IN_LOCAL        0x0000
 288 #define MIC_ADC_IN_REMOTE       0x0040
 289 #define MIC_ADC_IN_MUTE         0x0080
 290 #define LINE2_DAC_IN_LOCAL      0x0000
 291 #define LINE2_DAC_IN_REMOTE     0x0400
 292 #define LINE2_DAC_IN_MUTE       0x0800
 293 #define HANDSET_IN_LOCAL        0x0000
 294 #define HANDSET_IN_REMOTE       0x1000
 295 #define HANDSET_IN_MUTE         0x2000
 296 #define IO_STATUS_IN_LOCAL      0x0000
 297 #define IO_STATUS_IN_REMOTE     0x4000
 298
 299 #define SPDIF_IN_CTRL           0x3E
 300 #define SPDIF_IN_ENABLE         0x0001
 301
 302 #define GPIO_DATA               0x60
 303 #define GPIO_DATA_MASK          0x0FFF
 304 #define GPIO_HV_STATUS          0x3000
 305 #define GPIO_PME_STATUS         0x4000
 306
 307 #define GPIO_MASK               0x64
 308 #define GPIO_DIRECTION          0x68
 309 #define GPO_PRIMARY_AC97        0x0001
 310 #define GPI_LINEOUT_SENSE       0x0004
 311 #define GPO_SECONDARY_AC97      0x0008
 312 #define GPI_VOL_DOWN            0x0010
 313 #define GPI_VOL_UP              0x0020
 314 #define GPI_IIS_CLK             0x0040
 315 #define GPI_IIS_LRCLK           0x0080
 316 #define GPI_IIS_DATA            0x0100
 317 #define GPI_DOCKING_STATUS      0x0100
 318 #define GPI_HEADPHONE_SENSE     0x0200
 319 #define GPO_EXT_AMP_SHUTDOWN    0x1000
 320
 321 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
 322 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
 323
 324 /* M3 */
 325 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
 326
 327 #define ASSP_INDEX_PORT         0x80
 328 #define ASSP_MEMORY_PORT        0x82
 329 #define ASSP_DATA_PORT          0x84
 330
 331 #define MPU401_DATA_PORT        0x98
 332 #define MPU401_STATUS_PORT      0x99
 333
 334 #define CLK_MULT_DATA_PORT      0x9C
 335
 336 #define ASSP_CONTROL_A          0xA2
 337 #define ASSP_0_WS_ENABLE        0x01
 338 #define ASSP_CTRL_A_RESERVED1   0x02
 339 #define ASSP_CTRL_A_RESERVED2   0x04
 340 #define ASSP_CLK_49MHZ_SELECT   0x08
 341 #define FAST_PLU_ENABLE         0x10
 342 #define ASSP_CTRL_A_RESERVED3   0x20
 343 #define DSP_CLK_36MHZ_SELECT    0x40
 344
 345 #define ASSP_CONTROL_B          0xA4
 346 #define RESET_ASSP              0x00
 347 #define RUN_ASSP                0x01
 348 #define ENABLE_ASSP_CLOCK       0x00
 349 #define STOP_ASSP_CLOCK         0x10
 350 #define RESET_TOGGLE            0x40
 351
 352 #define ASSP_CONTROL_C          0xA6
 353 #define ASSP_HOST_INT_ENABLE    0x01
 354 #define FM_ADDR_REMAP_DISABLE   0x02
 355 #define HOST_WRITE_PORT_ENABLE  0x08
 356
 357 #define ASSP_HOST_INT_STATUS    0xAC
 358 #define DSP2HOST_REQ_PIORECORD  0x01
 359 #define DSP2HOST_REQ_I2SRATE    0x02
 360 #define DSP2HOST_REQ_TIMER      0x04
 361
 362 /* AC97 registers */
 363 /* XXX fix this crap up */
 364 /*#define AC97_RESET              0x00*/
 365
 366 #define AC97_VOL_MUTE_B         0x8000
 367 #define AC97_VOL_M              0x1F
 368 #define AC97_LEFT_VOL_S         8
 369
 370 #define AC97_MASTER_VOL         0x02
 371 #define AC97_LINE_LEVEL_VOL     0x04
 372 #define AC97_MASTER_MONO_VOL    0x06
 373 #define AC97_PC_BEEP_VOL        0x0A
 374 #define AC97_PC_BEEP_VOL_M      0x0F
 375 #define AC97_SROUND_MASTER_VOL  0x38
 376 #define AC97_PC_BEEP_VOL_S      1
 377
 378 /*#define AC97_PHONE_VOL          0x0C
 379 #define AC97_MIC_VOL            0x0E*/
 380 #define AC97_MIC_20DB_ENABLE    0x40
 381
 382 /*#define AC97_LINEIN_VOL         0x10
 383 #define AC97_CD_VOL             0x12
 384 #define AC97_VIDEO_VOL          0x14
 385 #define AC97_AUX_VOL            0x16*/
 386 #define AC97_PCM_OUT_VOL        0x18
 387 /*#define AC97_RECORD_SELECT      0x1A*/
 388 #define AC97_RECORD_MIC         0x00
 389 #define AC97_RECORD_CD          0x01
 390 #define AC97_RECORD_VIDEO       0x02
 391 #define AC97_RECORD_AUX         0x03
 392 #define AC97_RECORD_MONO_MUX    0x02
 393 #define AC97_RECORD_DIGITAL     0x03
 394 #define AC97_RECORD_LINE        0x04
 395 #define AC97_RECORD_STEREO      0x05
 396 #define AC97_RECORD_MONO        0x06
 397 #define AC97_RECORD_PHONE       0x07
 398
 399 /*#define AC97_RECORD_GAIN        0x1C*/
 400 #define AC97_RECORD_VOL_M       0x0F
 401
 402 /*#define AC97_GENERAL_PURPOSE    0x20*/
 403 #define AC97_POWER_DOWN_CTRL    0x26
 404 #define AC97_ADC_READY          0x0001
 405 #define AC97_DAC_READY          0x0002
 406 #define AC97_ANALOG_READY       0x0004
 407 #define AC97_VREF_ON            0x0008
 408 #define AC97_PR0                0x0100
 409 #define AC97_PR1                0x0200
 410 #define AC97_PR2                0x0400
 411 #define AC97_PR3                0x0800
 412 #define AC97_PR4                0x1000
 413
 414 #define AC97_RESERVED1          0x28
 415
 416 #define AC97_VENDOR_TEST        0x5A
 417
 418 #define AC97_CLOCK_DELAY        0x5C
 419 #define AC97_LINEOUT_MUX_SEL    0x0001
 420 #define AC97_MONO_MUX_SEL       0x0002
 421 #define AC97_CLOCK_DELAY_SEL    0x1F
 422 #define AC97_DAC_CDS_SHIFT      6
 423 #define AC97_ADC_CDS_SHIFT      11
 424
 425 #define AC97_MULTI_CHANNEL_SEL  0x74
 426
 427 /*#define AC97_VENDOR_ID1         0x7C
 428 #define AC97_VENDOR_ID2         0x7E*/
 429
 430 /*
 431  * ASSP control regs
 432  */
 433 #define DSP_PORT_TIMER_COUNT    0x06
 434
 435 #define DSP_PORT_MEMORY_INDEX   0x80
 436
 437 #define DSP_PORT_MEMORY_TYPE    0x82
 438 #define MEMTYPE_INTERNAL_CODE   0x0002
 439 #define MEMTYPE_INTERNAL_DATA   0x0003
 440 #define MEMTYPE_MASK            0x0003
 441
 442 #define DSP_PORT_MEMORY_DATA    0x84
 443
 444 #define DSP_PORT_CONTROL_REG_A  0xA2
 445 #define DSP_PORT_CONTROL_REG_B  0xA4
 446 #define DSP_PORT_CONTROL_REG_C  0xA6
 447
 448 #define REV_A_CODE_MEMORY_BEGIN         0x0000
 449 #define REV_A_CODE_MEMORY_END           0x0FFF
 450 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
 451 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
 452
 453 #define REV_B_CODE_MEMORY_BEGIN         0x0000
 454 #define REV_B_CODE_MEMORY_END           0x0BFF
 455 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
 456 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
 457
 458 #define REV_A_DATA_MEMORY_BEGIN         0x1000
 459 #define REV_A_DATA_MEMORY_END           0x2FFF
 460 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
 461 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
 462
 463 #define REV_B_DATA_MEMORY_BEGIN         0x1000
 464 #define REV_B_DATA_MEMORY_END           0x2BFF
 465 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
 466 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
 467
 468
 469 #define NUM_UNITS_KERNEL_CODE          16
 470 #define NUM_UNITS_KERNEL_DATA           2
 471
 472 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
 473 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
 474
 475 /*
 476  * Kernel data layout
 477  */
 478
 479 #define DP_SHIFT_COUNT                  7
 480
 481 #define KDATA_BASE_ADDR                 0x1000
 482 #define KDATA_BASE_ADDR2                0x1080
 483
 484 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
 485 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
 486 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
 487 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
 488 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
 489 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
 490 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
 491 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
 492 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
 493
 494 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
 495 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
 496
 497 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
 498 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
 499 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
 500 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
 501 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
 502 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
 503 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
 504 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
 505 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
 506 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
 507
 508 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
 509 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
 510
 511 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
 512 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
 513
 514 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
 515 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
 516
 517 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
 518 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
 519 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
 520
 521 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
 522 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
 523 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
 524 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
 525 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
 526
 527 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
 528 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
 529 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
 530
 531 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
 532 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
 533 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
 534
 535 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
 536 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
 537 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
 538 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
 539 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
 540 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
 541 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
 542 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
 543 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
 544 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
 545
 546 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
 547 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
 548 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
 549
 550 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
 551 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
 552
 553 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
 554 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
 555 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
 556
 557 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
 558 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
 559 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
 560 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
 561 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
 562 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
 563
 564 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
 565 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
 566 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
 567 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
 568 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
 569 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
 570
 571 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)
 572 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
 573 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
 574 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
 575 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
 576 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
 577
 578 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
 579 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
 580 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
 581 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
 582
 583 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
 584 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
 585
 586 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
 587 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
 588
 589 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
 590 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
 591 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
 592 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
 593 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
 594
 595 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
 596 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
 597
 598 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
 599 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
 600 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
 601
 602 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
 603 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
 604
 605 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
 606
 607 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
 608 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
 609 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
 610 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
 611 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
 612 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
 613 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
 614 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
 615 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
 616 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
 617 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
 618 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
 619
 620 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
 621 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
 622 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
 623 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
 624
 625 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
 626 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
 627
 628 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
 629 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
 630 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
 631 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
 632
 633 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
 634 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
 635 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
 636 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
 637 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
 638
 639 /*
 640  * second 'segment' (?) reserved for mixer
 641  * buffers..
 642  */
 643
 644 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
 645 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
 646 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
 647 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
 648 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
 649 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
 650 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
 651 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
 652 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
 653 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
 654 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
 655 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
 656 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
 657 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
 658 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
 659 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
 660
 661 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
 662 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
 663 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
 664 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
 665 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
 666 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
 667 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
 668 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
 669 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
 670 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
 671 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
 672
 673 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
 674 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
 675 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
 676 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
 677 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
 678 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
 679
 680 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
 681 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
 682 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
 683 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
 684
 685 /*
 686  * client data area offsets
 687  */
 688 #define CDATA_INSTANCE_READY            0x00
 689
 690 #define CDATA_HOST_SRC_ADDRL            0x01
 691 #define CDATA_HOST_SRC_ADDRH            0x02
 692 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
 693 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
 694 #define CDATA_HOST_SRC_CURRENTL         0x05
 695 #define CDATA_HOST_SRC_CURRENTH         0x06
 696
 697 #define CDATA_IN_BUF_CONNECT            0x07
 698 #define CDATA_OUT_BUF_CONNECT           0x08
 699
 700 #define CDATA_IN_BUF_BEGIN              0x09
 701 #define CDATA_IN_BUF_END_PLUS_1         0x0A
 702 #define CDATA_IN_BUF_HEAD               0x0B
 703 #define CDATA_IN_BUF_TAIL               0x0C
 704 #define CDATA_OUT_BUF_BEGIN             0x0D
 705 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
 706 #define CDATA_OUT_BUF_HEAD              0x0F
 707 #define CDATA_OUT_BUF_TAIL              0x10
 708
 709 #define CDATA_DMA_CONTROL               0x11
 710 #define CDATA_RESERVED                  0x12
 711
 712 #define CDATA_FREQUENCY                 0x13
 713 #define CDATA_LEFT_VOLUME               0x14
 714 #define CDATA_RIGHT_VOLUME              0x15
 715 #define CDATA_LEFT_SUR_VOL              0x16
 716 #define CDATA_RIGHT_SUR_VOL             0x17
 717
 718 #define CDATA_HEADER_LEN                0x18
 719
 720 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
 721 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
 722 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
 723 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
 724 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
 725 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
 726 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
 727 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
 728
 729 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
 730 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 731 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 732 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
 733 #define MINISRC_BIQUAD_STAGE    2
 734 #define MINISRC_COEF_LOC          0x175
 735
 736 #define DMACONTROL_BLOCK_MASK           0x000F
 737 #define  DMAC_BLOCK0_SELECTOR           0x0000
 738 #define  DMAC_BLOCK1_SELECTOR           0x0001
 739 #define  DMAC_BLOCK2_SELECTOR           0x0002
 740 #define  DMAC_BLOCK3_SELECTOR           0x0003
 741 #define  DMAC_BLOCK4_SELECTOR           0x0004
 742 #define  DMAC_BLOCK5_SELECTOR           0x0005
 743 #define  DMAC_BLOCK6_SELECTOR           0x0006
 744 #define  DMAC_BLOCK7_SELECTOR           0x0007
 745 #define  DMAC_BLOCK8_SELECTOR           0x0008
 746 #define  DMAC_BLOCK9_SELECTOR           0x0009
 747 #define  DMAC_BLOCKA_SELECTOR           0x000A
 748 #define  DMAC_BLOCKB_SELECTOR           0x000B
 749 #define  DMAC_BLOCKC_SELECTOR           0x000C
 750 #define  DMAC_BLOCKD_SELECTOR           0x000D
 751 #define  DMAC_BLOCKE_SELECTOR           0x000E
 752 #define  DMAC_BLOCKF_SELECTOR           0x000F
 753 #define DMACONTROL_PAGE_MASK            0x00F0
 754 #define  DMAC_PAGE0_SELECTOR            0x0030
 755 #define  DMAC_PAGE1_SELECTOR            0x0020
 756 #define  DMAC_PAGE2_SELECTOR            0x0010
 757 #define  DMAC_PAGE3_SELECTOR            0x0000
 758 #define DMACONTROL_AUTOREPEAT           0x1000
 759 #define DMACONTROL_STOPPED              0x2000
 760 #define DMACONTROL_DIRECTION            0x0100
 761
 762 /*
 763  * an arbitrary volume we set the internal
 764  * volume settings to so that the ac97 volume
 765  * range is a little less insane.  0x7fff is
 766  * max.
 767  */
 768 #define ARB_VOLUME ( 0x6800 )
 769
 770 /*
 771  */
 772
 773 /* quirk lists */
 774 struct m3_quirk {
 775         const char *name;       /* device name */
 776         u16 vendor, device;     /* subsystem ids */
 777         int amp_gpio;           /* gpio pin #  for external amp, -1 = default */
 778         int irda_workaround;    /* non-zero if avoid to touch 0x10 on GPIO_DIRECTION
 779                                    (e.g. for IrDA on Dell Inspirons) */
 780 };
 781
 782 struct m3_hv_quirk {
 783         u16 vendor, device, subsystem_vendor, subsystem_device;
 784         u32 config;             /* ALLEGRO_CONFIG hardware volume bits */
 785         int is_omnibook;        /* Do HP OmniBook GPIO magic? */
 786 };
 787
 788 struct m3_list {
 789         int curlen;
 790         int mem_addr;
 791         int max;
 792 };
 793
 794 struct m3_dma {
 795
 796         int number;
 797         struct snd_pcm_substream *substream;
 798
 799         struct assp_instance {
 800                 unsigned short code, data;
 801         } inst;
 802
 803         int running;
 804         int opened;
 805
 806         unsigned long buffer_addr;
 807         int dma_size;
 808         int period_size;
 809         unsigned int hwptr;
 810         int count;
 811
 812         int index[3];
 813         struct m3_list *index_list[3];
 814
 815         int in_lists;
 816
 817         struct list_head list;
 818
 819 };
 820
 821 struct snd_m3 {
 822
 823         struct snd_card *card;
 824
 825         unsigned long iobase;
 826
 827         int irq;
 828         unsigned int allegro_flag : 1;
 829
 830         struct snd_ac97 *ac97;
 831
 832         struct snd_pcm *pcm;
 833
 834         struct pci_dev *pci;
 835         const struct m3_quirk *quirk;
 836         const struct m3_hv_quirk *hv_quirk;
 837
 838         int dacs_active;
 839         int timer_users;
 840
 841         struct m3_list  msrc_list;
 842         struct m3_list  mixer_list;
 843         struct m3_list  adc1_list;
 844         struct m3_list  dma_list;
 845
 846         /* for storing reset state..*/
 847         u8 reset_state;
 848
 849         int external_amp;
 850         int amp_gpio;
 851
 852         /* midi */
 853         struct snd_rawmidi *rmidi;
 854
 855         /* pcm streams */
 856         int num_substreams;
 857         struct m3_dma *substreams;
 858
 859         spinlock_t reg_lock;
 860         spinlock_t ac97_lock;
 861
 862         struct snd_kcontrol *master_switch;
 863         struct snd_kcontrol *master_volume;
 864         struct tasklet_struct hwvol_tq;
 865
 866 #ifdef CONFIG_PM
 867         u16 *suspend_mem;
 868 #endif
 869
 870         const struct firmware *assp_kernel_image;
 871         const struct firmware *assp_minisrc_image;
 872 };
 873
 874 /*
 875  * pci ids
 876  */
 877 static struct pci_device_id snd_m3_ids[] = {
 878         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
 879          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 880         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
 881          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 882         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
 883          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 884         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
 885          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 886         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
 887          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 888         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
 889          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 890         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
 891          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 892         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
 893          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 894         {0,},
 895 };
 896
 897 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
 898
 899 static const struct m3_quirk m3_quirk_list[] = {
 900         /* panasonic CF-28 "toughbook" */
 901         {
 902                 .name = "Panasonic CF-28",
 903                 .vendor = 0x10f7,
 904                 .device = 0x833e,
 905                 .amp_gpio = 0x0d,
 906         },
 907         /* panasonic CF-72 "toughbook" */
 908         {
 909                 .name = "Panasonic CF-72",
 910                 .vendor = 0x10f7,
 911                 .device = 0x833d,
 912                 .amp_gpio = 0x0d,
 913         },
 914         /* Dell Inspiron 4000 */
 915         {
 916                 .name = "Dell Inspiron 4000",
 917                 .vendor = 0x1028,
 918                 .device = 0x00b0,
 919                 .amp_gpio = -1,
 920                 .irda_workaround = 1,
 921         },
 922         /* Dell Inspiron 8000 */
 923         {
 924                 .name = "Dell Inspiron 8000",
 925                 .vendor = 0x1028,
 926                 .device = 0x00a4,
 927                 .amp_gpio = -1,
 928                 .irda_workaround = 1,
 929         },
 930         /* Dell Inspiron 8100 */
 931         {
 932                 .name = "Dell Inspiron 8100",
 933                 .vendor = 0x1028,
 934                 .device = 0x00e6,
 935                 .amp_gpio = -1,
 936                 .irda_workaround = 1,
 937         },
 938         /* NEC LM800J/7 */
 939         {
 940                 .name = "NEC LM800J/7",
 941                 .vendor = 0x1033,
 942                 .device = 0x80f1,
 943                 .amp_gpio = 0x03,
 944         },
 945         /* LEGEND ZhaoYang 3100CF */
 946         {
 947                 .name = "LEGEND ZhaoYang 3100CF",
 948                 .vendor = 0x1509,
 949                 .device = 0x1740,
 950                 .amp_gpio = 0x03,
 951         },
 952         /* END */
 953         { NULL }
 954 };
 955
 956 /* These values came from the Windows driver. */
 957 static const struct m3_hv_quirk m3_hv_quirk_list[] = {
 958         /* Allegro chips */
 959         { 0x125D, 0x1988, 0x0E11, 0x002E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 960         { 0x125D, 0x1988, 0x0E11, 0x0094, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 961         { 0x125D, 0x1988, 0x0E11, 0xB112, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 962         { 0x125D, 0x1988, 0x0E11, 0xB114, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 963         { 0x125D, 0x1988, 0x103C, 0x0012, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 964         { 0x125D, 0x1988, 0x103C, 0x0018, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 965         { 0x125D, 0x1988, 0x103C, 0x001C, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 966         { 0x125D, 0x1988, 0x103C, 0x001D, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 967         { 0x125D, 0x1988, 0x103C, 0x001E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 968         { 0x125D, 0x1988, 0x107B, 0x3350, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 969         { 0x125D, 0x1988, 0x10F7, 0x8338, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 970         { 0x125D, 0x1988, 0x10F7, 0x833C, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 971         { 0x125D, 0x1988, 0x10F7, 0x833D, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 972         { 0x125D, 0x1988, 0x10F7, 0x833E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 973         { 0x125D, 0x1988, 0x10F7, 0x833F, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 974         { 0x125D, 0x1988, 0x13BD, 0x1018, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 975         { 0x125D, 0x1988, 0x13BD, 0x1019, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 976         { 0x125D, 0x1988, 0x13BD, 0x101A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 977         { 0x125D, 0x1988, 0x14FF, 0x0F03, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 978         { 0x125D, 0x1988, 0x14FF, 0x0F04, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 979         { 0x125D, 0x1988, 0x14FF, 0x0F05, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 980         { 0x125D, 0x1988, 0x156D, 0xB400, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 981         { 0x125D, 0x1988, 0x156D, 0xB795, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 982         { 0x125D, 0x1988, 0x156D, 0xB797, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 983         { 0x125D, 0x1988, 0x156D, 0xC700, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 984         { 0x125D, 0x1988, 0x1033, 0x80F1, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 985         { 0x125D, 0x1988, 0x103C, 0x001A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, /* HP OmniBook 6100 */
 986         { 0x125D, 0x1988, 0x107B, 0x340A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 987         { 0x125D, 0x1988, 0x107B, 0x3450, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 988         { 0x125D, 0x1988, 0x109F, 0x3134, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 989         { 0x125D, 0x1988, 0x109F, 0x3161, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 990         { 0x125D, 0x1988, 0x144D, 0x3280, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 991         { 0x125D, 0x1988, 0x144D, 0x3281, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 992         { 0x125D, 0x1988, 0x144D, 0xC002, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 993         { 0x125D, 0x1988, 0x144D, 0xC003, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 994         { 0x125D, 0x1988, 0x1509, 0x1740, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 995         { 0x125D, 0x1988, 0x1610, 0x0010, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 996         { 0x125D, 0x1988, 0x1042, 0x1042, HV_CTRL_ENABLE, 0 },
 997         { 0x125D, 0x1988, 0x107B, 0x9500, HV_CTRL_ENABLE, 0 },
 998         { 0x125D, 0x1988, 0x14FF, 0x0F06, HV_CTRL_ENABLE, 0 },
 999         { 0x125D, 0x1988, 0x1558, 0x8586, HV_CTRL_ENABLE, 0 },
1000         { 0x125D, 0x1988, 0x161F, 0x2011, HV_CTRL_ENABLE, 0 },
1001         /* Maestro3 chips */
1002         { 0x125D, 0x1998, 0x103C, 0x000E, HV_CTRL_ENABLE, 0 },
1003         { 0x125D, 0x1998, 0x103C, 0x0010, HV_CTRL_ENABLE, 1 }, /* HP OmniBook 6000 */
1004         { 0x125D, 0x1998, 0x103C, 0x0011, HV_CTRL_ENABLE, 1 }, /* HP OmniBook 500 */
1005         { 0x125D, 0x1998, 0x103C, 0x001B, HV_CTRL_ENABLE, 0 },
1006         { 0x125D, 0x1998, 0x104D, 0x80A6, HV_CTRL_ENABLE, 0 },
1007         { 0x125D, 0x1998, 0x104D, 0x80AA, HV_CTRL_ENABLE, 0 },
1008         { 0x125D, 0x1998, 0x107B, 0x5300, HV_CTRL_ENABLE, 0 },
1009         { 0x125D, 0x1998, 0x110A, 0x1998, HV_CTRL_ENABLE, 0 },
1010         { 0x125D, 0x1998, 0x13BD, 0x1015, HV_CTRL_ENABLE, 0 },
1011         { 0x125D, 0x1998, 0x13BD, 0x101C, HV_CTRL_ENABLE, 0 },
1012         { 0x125D, 0x1998, 0x13BD, 0x1802, HV_CTRL_ENABLE, 0 },
1013         { 0x125D, 0x1998, 0x1599, 0x0715, HV_CTRL_ENABLE, 0 },
1014         { 0x125D, 0x1998, 0x5643, 0x5643, HV_CTRL_ENABLE, 0 },
1015         { 0x125D, 0x199A, 0x144D, 0x3260, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1016         { 0x125D, 0x199A, 0x144D, 0x3261, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1017         { 0x125D, 0x199A, 0x144D, 0xC000, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1018         { 0x125D, 0x199A, 0x144D, 0xC001, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1019         { 0 }
1020 };
1021
1022 /*
1023  * lowlevel functions
1024  */
1025
1026 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
1027 {
1028         outw(value, chip->iobase + reg);
1029 }
1030
1031 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
1032 {
1033         return inw(chip->iobase + reg);
1034 }
1035
1036 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
1037 {
1038         outb(value, chip->iobase + reg);
1039 }
1040
1041 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
1042 {
1043         return inb(chip->iobase + reg);
1044 }
1045
1046 /*
1047  * access 16bit words to the code or data regions of the dsp's memory.
1048  * index addresses 16bit words.
1049  */
1050 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
1051 {
1052         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1053         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1054         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1055 }
1056
1057 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
1058 {
1059         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1060         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1061         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1062 }
1063
1064 static void snd_m3_assp_halt(struct snd_m3 *chip)
1065 {
1066         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1067         msleep(10);
1068         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1069 }
1070
1071 static void snd_m3_assp_continue(struct snd_m3 *chip)
1072 {
1073         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1074 }
1075
1076
1077 /*
1078  * This makes me sad. the maestro3 has lists
1079  * internally that must be packed.. 0 terminates,
1080  * apparently, or maybe all unused entries have
1081  * to be 0, the lists have static lengths set
1082  * by the binary code images.
1083  */
1084
1085 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
1086 {
1087         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1088                           list->mem_addr + list->curlen,
1089                           val);
1090         return list->curlen++;
1091 }
1092
1093 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
1094 {
1095         u16  val;
1096         int lastindex = list->curlen - 1;
1097
1098         if (index != lastindex) {
1099                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1100                                        list->mem_addr + lastindex);
1101                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1102                                   list->mem_addr + index,
1103                                   val);
1104         }
1105
1106         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1107                           list->mem_addr + lastindex,
1108                           0);
1109
1110         list->curlen--;
1111 }
1112
1113 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1114 {
1115         chip->timer_users++;
1116         if (chip->timer_users != 1)
1117                 return;
1118
1119         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1120                           KDATA_TIMER_COUNT_RELOAD,
1121                           240);
1122
1123         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1124                           KDATA_TIMER_COUNT_CURRENT,
1125                           240);
1126
1127         snd_m3_outw(chip,
1128                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1129                     HOST_INT_CTRL);
1130 }
1131
1132 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1133 {
1134         chip->timer_users--;
1135         if (chip->timer_users > 0)
1136                 return;
1137
1138         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1139                           KDATA_TIMER_COUNT_RELOAD,
1140                           0);
1141
1142         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1143                           KDATA_TIMER_COUNT_CURRENT,
1144                           0);
1145
1146         snd_m3_outw(chip,
1147                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1148                     HOST_INT_CTRL);
1149 }
1150
1151 /*
1152  * start/stop
1153  */
1154
1155 /* spinlock held! */
1156 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1157                             struct snd_pcm_substream *subs)
1158 {
1159         if (! s || ! subs)
1160                 return -EINVAL;
1161
1162         snd_m3_inc_timer_users(chip);
1163         switch (subs->stream) {
1164         case SNDRV_PCM_STREAM_PLAYBACK:
1165                 chip->dacs_active++;
1166                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1167                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1168                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1169                                   KDATA_MIXER_TASK_NUMBER,
1170                                   chip->dacs_active);
1171                 break;
1172         case SNDRV_PCM_STREAM_CAPTURE:
1173                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1174                                   KDATA_ADC1_REQUEST, 1);
1175                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1176                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1177                 break;
1178         }
1179         return 0;
1180 }
1181
1182 /* spinlock held! */
1183 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1184                            struct snd_pcm_substream *subs)
1185 {
1186         if (! s || ! subs)
1187                 return -EINVAL;
1188
1189         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1190                           s->inst.data + CDATA_INSTANCE_READY, 0);
1191         snd_m3_dec_timer_users(chip);
1192         switch (subs->stream) {
1193         case SNDRV_PCM_STREAM_PLAYBACK:
1194                 chip->dacs_active--;
1195                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1196                                   KDATA_MIXER_TASK_NUMBER,
1197                                   chip->dacs_active);
1198                 break;
1199         case SNDRV_PCM_STREAM_CAPTURE:
1200                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1201                                   KDATA_ADC1_REQUEST, 0);
1202                 break;
1203         }
1204         return 0;
1205 }
1206
1207 static int
1208 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1209 {
1210         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1211         struct m3_dma *s = subs->runtime->private_data;
1212         int err = -EINVAL;
1213
1214         snd_assert(s != NULL, return -ENXIO);
1215
1216         spin_lock(&chip->reg_lock);
1217         switch (cmd) {
1218         case SNDRV_PCM_TRIGGER_START:
1219         case SNDRV_PCM_TRIGGER_RESUME:
1220                 if (s->running)
1221                         err = -EBUSY;
1222                 else {
1223                         s->running = 1;
1224                         err = snd_m3_pcm_start(chip, s, subs);
1225                 }
1226                 break;
1227         case SNDRV_PCM_TRIGGER_STOP:
1228         case SNDRV_PCM_TRIGGER_SUSPEND:
1229                 if (! s->running)
1230                         err = 0; /* should return error? */
1231                 else {
1232                         s->running = 0;
1233                         err = snd_m3_pcm_stop(chip, s, subs);
1234                 }
1235                 break;
1236         }
1237         spin_unlock(&chip->reg_lock);
1238         return err;
1239 }
1240
1241 /*
1242  * setup
1243  */
1244 static void
1245 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1246 {
1247         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1248         struct snd_pcm_runtime *runtime = subs->runtime;
1249
1250         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1251                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1252                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1253         } else {
1254                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1255                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1256         }
1257         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1258         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1259
1260         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1261         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1262         s->hwptr = 0;
1263         s->count = 0;
1264
1265 #define LO(x) ((x) & 0xffff)
1266 #define HI(x) LO((x) >> 16)
1267
1268         /* host dma buffer pointers */
1269         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1270                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1271                           LO(s->buffer_addr));
1272
1273         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1274                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1275                           HI(s->buffer_addr));
1276
1277         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1278                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1279                           LO(s->buffer_addr + s->dma_size));
1280
1281         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1282                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1283                           HI(s->buffer_addr + s->dma_size));
1284
1285         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1286                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1287                           LO(s->buffer_addr));
1288
1289         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1290                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1291                           HI(s->buffer_addr));
1292 #undef LO
1293 #undef HI
1294
1295         /* dsp buffers */
1296
1297         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1298                           s->inst.data + CDATA_IN_BUF_BEGIN,
1299                           dsp_in_buffer);
1300
1301         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1302                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1303                           dsp_in_buffer + (dsp_in_size / 2));
1304
1305         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1306                           s->inst.data + CDATA_IN_BUF_HEAD,
1307                           dsp_in_buffer);
1308
1309         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1310                           s->inst.data + CDATA_IN_BUF_TAIL,
1311                           dsp_in_buffer);
1312
1313         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1314                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1315                           dsp_out_buffer);
1316
1317         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1318                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1319                           dsp_out_buffer + (dsp_out_size / 2));
1320
1321         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1322                           s->inst.data + CDATA_OUT_BUF_HEAD,
1323                           dsp_out_buffer);
1324
1325         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1326                           s->inst.data + CDATA_OUT_BUF_TAIL,
1327                           dsp_out_buffer);
1328 }
1329
1330 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1331                               struct snd_pcm_runtime *runtime)
1332 {
1333         u32 freq;
1334
1335         /*
1336          * put us in the lists if we're not already there
1337          */
1338         if (! s->in_lists) {
1339                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1340                                               s->inst.data >> DP_SHIFT_COUNT);
1341                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1342                                               s->inst.data >> DP_SHIFT_COUNT);
1343                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1344                                               s->inst.data >> DP_SHIFT_COUNT);
1345                 s->in_lists = 1;
1346         }
1347
1348         /* write to 'mono' word */
1349         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1350                           s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1351                           runtime->channels == 2 ? 0 : 1);
1352         /* write to '8bit' word */
1353         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1354                           s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1355                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1356
1357         /* set up dac/adc rate */
1358         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1359         if (freq)
1360                 freq--;
1361
1362         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1363                           s->inst.data + CDATA_FREQUENCY,
1364                           freq);
1365 }
1366
1367
1368 static const struct play_vals {
1369         u16 addr, val;
1370 } pv[] = {
1371         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1372         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1373         {SRC3_DIRECTION_OFFSET, 0} ,
1374         /* +1, +2 are stereo/16 bit */
1375         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1376         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1377         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1378         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1379         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1380         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1381         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1382         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1383         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1384         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1385         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1386         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1387         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1388         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1389         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1390         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1391         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1392 };
1393
1394
1395 /* the mode passed should be already shifted and masked */
1396 static void
1397 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1398                       struct snd_pcm_substream *subs)
1399 {
1400         unsigned int i;
1401
1402         /*
1403          * some per client initializers
1404          */
1405
1406         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1407                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1408                           s->inst.data + 40 + 8);
1409
1410         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1411                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1412                           s->inst.code + MINISRC_COEF_LOC);
1413
1414         /* enable or disable low pass filter? */
1415         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1416                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1417                           subs->runtime->rate > 45000 ? 0xff : 0);
1418
1419         /* tell it which way dma is going? */
1420         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1421                           s->inst.data + CDATA_DMA_CONTROL,
1422                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1423
1424         /*
1425          * set an armload of static initializers
1426          */
1427         for (i = 0; i < ARRAY_SIZE(pv); i++)
1428                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1429                                   s->inst.data + pv[i].addr, pv[i].val);
1430 }
1431
1432 /*
1433  *    Native record driver
1434  */
1435 static const struct rec_vals {
1436         u16 addr, val;
1437 } rv[] = {
1438         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1439         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1440         {SRC3_DIRECTION_OFFSET, 1} ,
1441         /* +1, +2 are stereo/16 bit */
1442         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1443         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1444         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1445         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1446         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1447         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1448         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1449         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1450         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1451         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1452         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1453         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1454         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1455         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1456         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1457         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1458         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1459         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1460         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1461 };
1462
1463 static void
1464 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1465 {
1466         unsigned int i;
1467
1468         /*
1469          * some per client initializers
1470          */
1471
1472         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1473                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1474                           s->inst.data + 40 + 8);
1475
1476         /* tell it which way dma is going? */
1477         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1478                           s->inst.data + CDATA_DMA_CONTROL,
1479                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1480                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1481
1482         /*
1483          * set an armload of static initializers
1484          */
1485         for (i = 0; i < ARRAY_SIZE(rv); i++)
1486                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1487                                   s->inst.data + rv[i].addr, rv[i].val);
1488 }
1489
1490 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1491                                 struct snd_pcm_hw_params *hw_params)
1492 {
1493         struct m3_dma *s = substream->runtime->private_data;
1494         int err;
1495
1496         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1497                 return err;
1498         /* set buffer address */
1499         s->buffer_addr = substream->runtime->dma_addr;
1500         if (s->buffer_addr & 0x3) {
1501                 snd_printk(KERN_ERR "oh my, not aligned\n");
1502                 s->buffer_addr = s->buffer_addr & ~0x3;
1503         }
1504         return 0;
1505 }
1506
1507 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1508 {
1509         struct m3_dma *s;
1510
1511         if (substream->runtime->private_data == NULL)
1512                 return 0;
1513         s = substream->runtime->private_data;
1514         snd_pcm_lib_free_pages(substream);
1515         s->buffer_addr = 0;
1516         return 0;
1517 }
1518
1519 static int
1520 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1521 {
1522         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1523         struct snd_pcm_runtime *runtime = subs->runtime;
1524         struct m3_dma *s = runtime->private_data;
1525
1526         snd_assert(s != NULL, return -ENXIO);
1527
1528         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1529             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1530                 return -EINVAL;
1531         if (runtime->rate > 48000 ||
1532             runtime->rate < 8000)
1533                 return -EINVAL;
1534
1535         spin_lock_irq(&chip->reg_lock);
1536
1537         snd_m3_pcm_setup1(chip, s, subs);
1538
1539         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1540                 snd_m3_playback_setup(chip, s, subs);
1541         else
1542                 snd_m3_capture_setup(chip, s, subs);
1543
1544         snd_m3_pcm_setup2(chip, s, runtime);
1545
1546         spin_unlock_irq(&chip->reg_lock);
1547
1548         return 0;
1549 }
1550
1551 /*
1552  * get current pointer
1553  */
1554 static unsigned int
1555 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1556 {
1557         u16 hi = 0, lo = 0;
1558         int retry = 10;
1559         u32 addr;
1560
1561         /*
1562          * try and get a valid answer
1563          */
1564         while (retry--) {
1565                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1566                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1567
1568                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1569                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1570
1571                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1572                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1573                         break;
1574         }
1575         addr = lo | ((u32)hi<<16);
1576         return (unsigned int)(addr - s->buffer_addr);
1577 }
1578
1579 static snd_pcm_uframes_t
1580 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1581 {
1582         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1583         unsigned int ptr;
1584         struct m3_dma *s = subs->runtime->private_data;
1585         snd_assert(s != NULL, return 0);
1586
1587         spin_lock(&chip->reg_lock);
1588         ptr = snd_m3_get_pointer(chip, s, subs);
1589         spin_unlock(&chip->reg_lock);
1590         return bytes_to_frames(subs->runtime, ptr);
1591 }
1592
1593
1594 /* update pointer */
1595 /* spinlock held! */
1596 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1597 {
1598         struct snd_pcm_substream *subs = s->substream;
1599         unsigned int hwptr;
1600         int diff;
1601
1602         if (! s->running)
1603                 return;
1604
1605         hwptr = snd_m3_get_pointer(chip, s, subs);
1606
1607         /* try to avoid expensive modulo divisions */
1608         if (hwptr >= s->dma_size)
1609                 hwptr %= s->dma_size;
1610
1611         diff = s->dma_size + hwptr - s->hwptr;
1612         if (diff >= s->dma_size)
1613                 diff %= s->dma_size;
1614
1615         s->hwptr = hwptr;
1616         s->count += diff;
1617
1618         if (s->count >= (signed)s->period_size) {
1619
1620                 if (s->count < 2 * (signed)s->period_size)
1621                         s->count -= (signed)s->period_size;
1622                 else
1623                         s->count %= s->period_size;
1624
1625                 spin_unlock(&chip->reg_lock);
1626                 snd_pcm_period_elapsed(subs);
1627                 spin_lock(&chip->reg_lock);
1628         }
1629 }
1630
1631 static void snd_m3_update_hw_volume(unsigned long private_data)
1632 {
1633         struct snd_m3 *chip = (struct snd_m3 *) private_data;
1634         int x, val;
1635         unsigned long flags;
1636
1637         /* Figure out which volume control button was pushed,
1638            based on differences from the default register
1639            values. */
1640         x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1641
1642         /* Reset the volume control registers. */
1643         outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1644         outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1645         outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1646         outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1647
1648         if (!chip->master_switch || !chip->master_volume)
1649                 return;
1650
1651         /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1652         spin_lock_irqsave(&chip->ac97_lock, flags);
1653
1654         val = chip->ac97->regs[AC97_MASTER_VOL];
1655         switch (x) {
1656         case 0x88:
1657                 /* mute */
1658                 val ^= 0x8000;
1659                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1660                 outw(val, chip->iobase + CODEC_DATA);
1661                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1662                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1663                                &chip->master_switch->id);
1664                 break;
1665         case 0xaa:
1666                 /* volume up */
1667                 if ((val & 0x7f) > 0)
1668                         val--;
1669                 if ((val & 0x7f00) > 0)
1670                         val -= 0x0100;
1671                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1672                 outw(val, chip->iobase + CODEC_DATA);
1673                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1674                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1675                                &chip->master_volume->id);
1676                 break;
1677         case 0x66:
1678                 /* volume down */
1679                 if ((val & 0x7f) < 0x1f)
1680                         val++;
1681                 if ((val & 0x7f00) < 0x1f00)
1682                         val += 0x0100;
1683                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1684                 outw(val, chip->iobase + CODEC_DATA);
1685                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1686                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1687                                &chip->master_volume->id);
1688                 break;
1689         }
1690         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1691 }
1692
1693 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1694 {
1695         struct snd_m3 *chip = dev_id;
1696         u8 status;
1697         int i;
1698
1699         status = inb(chip->iobase + HOST_INT_STATUS);
1700
1701         if (status == 0xff)
1702                 return IRQ_NONE;
1703
1704         if (status & HV_INT_PENDING)
1705                 tasklet_hi_schedule(&chip->hwvol_tq);
1706
1707         /*
1708          * ack an assp int if its running
1709          * and has an int pending
1710          */
1711         if (status & ASSP_INT_PENDING) {
1712                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1713                 if (!(ctl & STOP_ASSP_CLOCK)) {
1714                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1715                         if (ctl & DSP2HOST_REQ_TIMER) {
1716                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1717                                 /* update adc/dac info if it was a timer int */
1718                                 spin_lock(&chip->reg_lock);
1719                                 for (i = 0; i < chip->num_substreams; i++) {
1720                                         struct m3_dma *s = &chip->substreams[i];
1721                                         if (s->running)
1722                                                 snd_m3_update_ptr(chip, s);
1723                                 }
1724                                 spin_unlock(&chip->reg_lock);
1725                         }
1726                 }
1727         }
1728
1729 #if 0 /* TODO: not supported yet */
1730         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1731                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1732 #endif
1733
1734         /* ack ints */
1735         outb(status, chip->iobase + HOST_INT_STATUS);
1736
1737         return IRQ_HANDLED;
1738 }
1739
1740
1741 /*
1742  */
1743
1744 static struct snd_pcm_hardware snd_m3_playback =
1745 {
1746         .info =                 (SNDRV_PCM_INFO_MMAP |
1747                                  SNDRV_PCM_INFO_INTERLEAVED |
1748                                  SNDRV_PCM_INFO_MMAP_VALID |
1749                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1750                                  /*SNDRV_PCM_INFO_PAUSE |*/
1751                                  SNDRV_PCM_INFO_RESUME),
1752         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1753         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1754         .rate_min =             8000,
1755         .rate_max =             48000,
1756         .channels_min =         1,
1757         .channels_max =         2,
1758         .buffer_bytes_max =     (512*1024),
1759         .period_bytes_min =     64,
1760         .period_bytes_max =     (512*1024),
1761         .periods_min =          1,
1762         .periods_max =          1024,
1763 };
1764
1765 static struct snd_pcm_hardware snd_m3_capture =
1766 {
1767         .info =                 (SNDRV_PCM_INFO_MMAP |
1768                                  SNDRV_PCM_INFO_INTERLEAVED |
1769                                  SNDRV_PCM_INFO_MMAP_VALID |
1770                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1771                                  /*SNDRV_PCM_INFO_PAUSE |*/
1772                                  SNDRV_PCM_INFO_RESUME),
1773         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1774         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1775         .rate_min =             8000,
1776         .rate_max =             48000,
1777         .channels_min =         1,
1778         .channels_max =         2,
1779         .buffer_bytes_max =     (512*1024),
1780         .period_bytes_min =     64,
1781         .period_bytes_max =     (512*1024),
1782         .periods_min =          1,
1783         .periods_max =          1024,
1784 };
1785
1786
1787 /*
1788  */
1789
1790 static int
1791 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1792 {
1793         int i;
1794         struct m3_dma *s;
1795
1796         spin_lock_irq(&chip->reg_lock);
1797         for (i = 0; i < chip->num_substreams; i++) {
1798                 s = &chip->substreams[i];
1799                 if (! s->opened)
1800                         goto __found;
1801         }
1802         spin_unlock_irq(&chip->reg_lock);
1803         return -ENOMEM;
1804 __found:
1805         s->opened = 1;
1806         s->running = 0;
1807         spin_unlock_irq(&chip->reg_lock);
1808
1809         subs->runtime->private_data = s;
1810         s->substream = subs;
1811
1812         /* set list owners */
1813         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1814                 s->index_list[0] = &chip->mixer_list;
1815         } else
1816                 s->index_list[0] = &chip->adc1_list;
1817         s->index_list[1] = &chip->msrc_list;
1818         s->index_list[2] = &chip->dma_list;
1819
1820         return 0;
1821 }
1822
1823 static void
1824 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1825 {
1826         struct m3_dma *s = subs->runtime->private_data;
1827
1828         if (s == NULL)
1829                 return; /* not opened properly */
1830
1831         spin_lock_irq(&chip->reg_lock);
1832         if (s->substream && s->running)
1833                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1834         if (s->in_lists) {
1835                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1836                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1837                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1838                 s->in_lists = 0;
1839         }
1840         s->running = 0;
1841         s->opened = 0;
1842         spin_unlock_irq(&chip->reg_lock);
1843 }
1844
1845 static int
1846 snd_m3_playback_open(struct snd_pcm_substream *subs)
1847 {
1848         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1849         struct snd_pcm_runtime *runtime = subs->runtime;
1850         int err;
1851
1852         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1853                 return err;
1854
1855         runtime->hw = snd_m3_playback;
1856         snd_pcm_set_sync(subs);
1857
1858         return 0;
1859 }
1860
1861 static int
1862 snd_m3_playback_close(struct snd_pcm_substream *subs)
1863 {
1864         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1865
1866         snd_m3_substream_close(chip, subs);
1867         return 0;
1868 }
1869
1870 static int
1871 snd_m3_capture_open(struct snd_pcm_substream *subs)
1872 {
1873         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1874         struct snd_pcm_runtime *runtime = subs->runtime;
1875         int err;
1876
1877         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1878                 return err;
1879
1880         runtime->hw = snd_m3_capture;
1881         snd_pcm_set_sync(subs);
1882
1883         return 0;
1884 }
1885
1886 static int
1887 snd_m3_capture_close(struct snd_pcm_substream *subs)
1888 {
1889         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1890
1891         snd_m3_substream_close(chip, subs);
1892         return 0;
1893 }
1894
1895 /*
1896  * create pcm instance
1897  */
1898
1899 static struct snd_pcm_ops snd_m3_playback_ops = {
1900         .open =         snd_m3_playback_open,
1901         .close =        snd_m3_playback_close,
1902         .ioctl =        snd_pcm_lib_ioctl,
1903         .hw_params =    snd_m3_pcm_hw_params,
1904         .hw_free =      snd_m3_pcm_hw_free,
1905         .prepare =      snd_m3_pcm_prepare,
1906         .trigger =      snd_m3_pcm_trigger,
1907         .pointer =      snd_m3_pcm_pointer,
1908 };
1909
1910 static struct snd_pcm_ops snd_m3_capture_ops = {
1911         .open =         snd_m3_capture_open,
1912         .close =        snd_m3_capture_close,
1913         .ioctl =        snd_pcm_lib_ioctl,
1914         .hw_params =    snd_m3_pcm_hw_params,
1915         .hw_free =      snd_m3_pcm_hw_free,
1916         .prepare =      snd_m3_pcm_prepare,
1917         .trigger =      snd_m3_pcm_trigger,
1918         .pointer =      snd_m3_pcm_pointer,
1919 };
1920
1921 static int __devinit
1922 snd_m3_pcm(struct snd_m3 * chip, int device)
1923 {
1924         struct snd_pcm *pcm;
1925         int err;
1926
1927         err = snd_pcm_new(chip->card, chip->card->driver, device,
1928                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1929         if (err < 0)
1930                 return err;
1931
1932         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1933         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1934
1935         pcm->private_data = chip;
1936         pcm->info_flags = 0;
1937         strcpy(pcm->name, chip->card->driver);
1938         chip->pcm = pcm;
1939
1940         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1941                                               snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1942
1943         return 0;
1944 }
1945
1946
1947 /*
1948  * ac97 interface
1949  */
1950
1951 /*
1952  * Wait for the ac97 serial bus to be free.
1953  * return nonzero if the bus is still busy.
1954  */
1955 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1956 {
1957         int i = 10000;
1958
1959         do {
1960                 if (! (snd_m3_inb(chip, 0x30) & 1))
1961                         return 0;
1962                 cpu_relax();
1963         } while (i-- > 0);
1964
1965         snd_printk(KERN_ERR "ac97 serial bus busy\n");
1966         return 1;
1967 }
1968
1969 static unsigned short
1970 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1971 {
1972         struct snd_m3 *chip = ac97->private_data;
1973         unsigned long flags;
1974         unsigned short data = 0xffff;
1975
1976         if (snd_m3_ac97_wait(chip))
1977                 goto fail;
1978         spin_lock_irqsave(&chip->ac97_lock, flags);
1979         snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1980         if (snd_m3_ac97_wait(chip))
1981                 goto fail_unlock;
1982         data = snd_m3_inw(chip, CODEC_DATA);
1983 fail_unlock:
1984         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1985 fail:
1986         return data;
1987 }
1988
1989 static void
1990 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1991 {
1992         struct snd_m3 *chip = ac97->private_data;
1993         unsigned long flags;
1994
1995         if (snd_m3_ac97_wait(chip))
1996                 return;
1997         spin_lock_irqsave(&chip->ac97_lock, flags);
1998         snd_m3_outw(chip, val, CODEC_DATA);
1999         snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
2000         spin_unlock_irqrestore(&chip->ac97_lock, flags);
2001 }
2002
2003
2004 static void snd_m3_remote_codec_config(int io, int isremote)
2005 {
2006         isremote = isremote ? 1 : 0;
2007
2008         outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
2009              io + RING_BUS_CTRL_B);
2010         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
2011              io + SDO_OUT_DEST_CTRL);
2012         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
2013              io + SDO_IN_DEST_CTRL);
2014 }
2015
2016 /*
2017  * hack, returns non zero on err
2018  */
2019 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
2020 {
2021         u16 ret;
2022
2023         if (snd_m3_ac97_wait(chip))
2024                 return 1;
2025
2026         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
2027
2028         if (snd_m3_ac97_wait(chip))
2029                 return 1;
2030
2031         ret = snd_m3_inw(chip, 0x32);
2032
2033         return (ret == 0) || (ret == 0xffff);
2034 }
2035
2036 static void snd_m3_ac97_reset(struct snd_m3 *chip)
2037 {
2038         u16 dir;
2039         int delay1 = 0, delay2 = 0, i;
2040         int io = chip->iobase;
2041
2042         if (chip->allegro_flag) {
2043                 /*
2044                  * the onboard codec on the allegro seems
2045                  * to want to wait a very long time before
2046                  * coming back to life
2047                  */
2048                 delay1 = 50;
2049                 delay2 = 800;
2050         } else {
2051                 /* maestro3 */
2052                 delay1 = 20;
2053                 delay2 = 500;
2054         }
2055
2056         for (i = 0; i < 5; i++) {
2057                 dir = inw(io + GPIO_DIRECTION);
2058                 if (! chip->quirk || ! chip->quirk->irda_workaround)
2059                         dir |= 0x10; /* assuming pci bus master? */
2060
2061                 snd_m3_remote_codec_config(io, 0);
2062
2063                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2064                 udelay(20);
2065
2066                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2067                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2068                 outw(0, io + GPIO_DATA);
2069                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2070
2071                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2072
2073                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2074                 udelay(5);
2075                 /* ok, bring back the ac-link */
2076                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2077                 outw(~0, io + GPIO_MASK);
2078
2079                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2080
2081                 if (! snd_m3_try_read_vendor(chip))
2082                         break;
2083
2084                 delay1 += 10;
2085                 delay2 += 100;
2086
2087                 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2088                            delay1, delay2);
2089         }
2090
2091 #if 0
2092         /* more gung-ho reset that doesn't
2093          * seem to work anywhere :)
2094          */
2095         tmp = inw(io + RING_BUS_CTRL_A);
2096         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2097         msleep(20);
2098         outw(tmp, io + RING_BUS_CTRL_A);
2099         msleep(50);
2100 #endif
2101 }
2102
2103 static int __devinit snd_m3_mixer(struct snd_m3 *chip)
2104 {
2105         struct snd_ac97_bus *pbus;
2106         struct snd_ac97_template ac97;
2107         struct snd_ctl_elem_id id;
2108         int err;
2109         static struct snd_ac97_bus_ops ops = {
2110                 .write = snd_m3_ac97_write,
2111                 .read = snd_m3_ac97_read,
2112         };
2113
2114         if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2115                 return err;
2116
2117         memset(&ac97, 0, sizeof(ac97));
2118         ac97.private_data = chip;
2119         if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2120                 return err;
2121
2122         /* seems ac97 PCM needs initialization.. hack hack.. */
2123         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2124         schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2125         snd_ac97_write(chip->ac97, AC97_PCM, 0);
2126
2127         memset(&id, 0, sizeof(id));
2128         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2129         strcpy(id.name, "Master Playback Switch");
2130         chip->master_switch = snd_ctl_find_id(chip->card, &id);
2131         memset(&id, 0, sizeof(id));
2132         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2133         strcpy(id.name, "Master Playback Volume");
2134         chip->master_volume = snd_ctl_find_id(chip->card, &id);
2135
2136         return 0;
2137 }
2138
2139
2140 #define FIRMWARE_IN_THE_KERNEL
2141
2142 #ifdef FIRMWARE_IN_THE_KERNEL
2143
2144 /*
2145  * DSP Code images
2146  */
2147
2148 static const u16 assp_kernel_image[] = {
2149     0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
2150     0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2151     0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2152     0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
2153     0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
2154     0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
2155     0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2156     0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2157     0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2158     0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2159     0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2160     0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2161     0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2162     0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2163     0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2164     0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2165     0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2166     0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2167     0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2168     0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2169     0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2170     0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2171     0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2172     0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2173     0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2174     0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2175     0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2176     0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2177     0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2178     0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2179     0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2180     0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2181     0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2182     0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2183     0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2184     0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2185     0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2186     0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2187     0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2188     0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2189     0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2190     0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2191     0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2192     0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2193     0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2194     0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2195     0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2196     0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2197     0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2198     0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2199     0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2200     0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2201     0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2202     0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2203     0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2204     0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2205     0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2206     0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2207     0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2208     0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2209     0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2210     0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2211     0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2212     0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2213     0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2214     0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2215     0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2216     0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2217     0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2218     0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2219     0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2220     0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2221     0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2222     0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2223     0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2224     0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2225     0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2226     0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2227     0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2228     0xBE3A,
2229 };
2230
2231 /*
2232  * Mini sample rate converter code image
2233  * that is to be loaded at 0x400 on the DSP.
2234  */
2235 static const u16 assp_minisrc_image[] = {
2236
2237     0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2238     0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2239     0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2240     0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2241     0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2242     0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2243     0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2244     0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2245     0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2246     0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2247     0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2248     0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2249     0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2250     0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2251     0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2252     0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2253     0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2254     0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2255     0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2256     0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2257     0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2258     0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2259     0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2260     0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2261     0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2262     0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2263     0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2264     0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2265     0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2266     0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2267     0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2268     0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2269     0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2270 };
2271
2272 static const struct firmware assp_kernel = {
2273         .data = (u8 *)assp_kernel_image,
2274         .size = sizeof assp_kernel_image
2275 };
2276 static const struct firmware assp_minisrc = {
2277         .data = (u8 *)assp_minisrc_image,
2278         .size = sizeof assp_minisrc_image
2279 };
2280
2281 #endif /* FIRMWARE_IN_THE_KERNEL */
2282
2283 #ifdef __LITTLE_ENDIAN
2284 static inline void snd_m3_convert_from_le(const struct firmware *fw) { }
2285 #else
2286 static void snd_m3_convert_from_le(const struct firmware *fw)
2287 {
2288         int i;
2289         u16 *data = (u16 *)fw->data;
2290
2291         for (i = 0; i < fw->size / 2; ++i)
2292                 le16_to_cpus(&data[i]);
2293 }
2294 #endif
2295
2296
2297 /*
2298  * initialize ASSP
2299  */
2300
2301 #define MINISRC_LPF_LEN 10
2302 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2303         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2304         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2305 };
2306
2307 static void snd_m3_assp_init(struct snd_m3 *chip)
2308 {
2309         unsigned int i;
2310         u16 *data;
2311
2312         /* zero kernel data */
2313         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2314                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2315                                   KDATA_BASE_ADDR + i, 0);
2316
2317         /* zero mixer data? */
2318         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2319                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2320                                   KDATA_BASE_ADDR2 + i, 0);
2321
2322         /* init dma pointer */
2323         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2324                           KDATA_CURRENT_DMA,
2325                           KDATA_DMA_XFER0);
2326
2327         /* write kernel into code memory.. */
2328         data = (u16 *)chip->assp_kernel_image->data;
2329         for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2330                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2331                                   REV_B_CODE_MEMORY_BEGIN + i, data[i]);
2332         }
2333
2334         /*
2335          * We only have this one client and we know that 0x400
2336          * is free in our kernel's mem map, so lets just
2337          * drop it there.  It seems that the minisrc doesn't
2338          * need vectors, so we won't bother with them..
2339          */
2340         data = (u16 *)chip->assp_minisrc_image->data;
2341         for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2342                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2343                                   0x400 + i, data[i]);
2344         }
2345
2346         /*
2347          * write the coefficients for the low pass filter?
2348          */
2349         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2350                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2351                                   0x400 + MINISRC_COEF_LOC + i,
2352                                   minisrc_lpf[i]);
2353         }
2354
2355         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2356                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2357                           0x8000);
2358
2359         /*
2360          * the minisrc is the only thing on
2361          * our task list..
2362          */
2363         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2364                           KDATA_TASK0,
2365                           0x400);
2366
2367         /*
2368          * init the mixer number..
2369          */
2370
2371         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2372                           KDATA_MIXER_TASK_NUMBER,0);
2373
2374         /*
2375          * EXTREME KERNEL MASTER VOLUME
2376          */
2377         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2378                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2379         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2380                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2381
2382         chip->mixer_list.curlen = 0;
2383         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2384         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2385         chip->adc1_list.curlen = 0;
2386         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2387         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2388         chip->dma_list.curlen = 0;
2389         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2390         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2391         chip->msrc_list.curlen = 0;
2392         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2393         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2394 }
2395
2396
2397 static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2398 {
2399         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2400                                MINISRC_IN_BUFFER_SIZE / 2 +
2401                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2402         int address, i;
2403
2404         /*
2405          * the revb memory map has 0x1100 through 0x1c00
2406          * free.
2407          */
2408
2409         /*
2410          * align instance address to 256 bytes so that its
2411          * shifted list address is aligned.
2412          * list address = (mem address >> 1) >> 7;
2413          */
2414         data_bytes = ALIGN(data_bytes, 256);
2415         address = 0x1100 + ((data_bytes/2) * index);
2416
2417         if ((address + (data_bytes/2)) >= 0x1c00) {
2418                 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2419                            data_bytes, index, address);
2420                 return -ENOMEM;
2421         }
2422
2423         s->number = index;
2424         s->inst.code = 0x400;
2425         s->inst.data = address;
2426
2427         for (i = data_bytes / 2; i > 0; address++, i--) {
2428                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2429                                   address, 0);
2430         }
2431
2432         return 0;
2433 }
2434
2435
2436 /*
2437  * this works for the reference board, have to find
2438  * out about others
2439  *
2440  * this needs more magic for 4 speaker, but..
2441  */
2442 static void
2443 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2444 {
2445         int io = chip->iobase;
2446         u16 gpo, polarity;
2447
2448         if (! chip->external_amp)
2449                 return;
2450
2451         polarity = enable ? 0 : 1;
2452         polarity = polarity << chip->amp_gpio;
2453         gpo = 1 << chip->amp_gpio;
2454
2455         outw(~gpo, io + GPIO_MASK);
2456
2457         outw(inw(io + GPIO_DIRECTION) | gpo,
2458              io + GPIO_DIRECTION);
2459
2460         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2461              io + GPIO_DATA);
2462
2463         outw(0xffff, io + GPIO_MASK);
2464 }
2465
2466 static int
2467 snd_m3_chip_init(struct snd_m3 *chip)
2468 {
2469         struct pci_dev *pcidev = chip->pci;
2470         unsigned long io = chip->iobase;
2471         u32 n;
2472         u16 w;
2473         u8 t; /* makes as much sense as 'n', no? */
2474
2475         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2476         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2477                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2478                DISABLE_LEGACY);
2479         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2480
2481         if (chip->hv_quirk && chip->hv_quirk->is_omnibook) {
2482                 /*
2483                  * Volume buttons on some HP OmniBook laptops don't work
2484                  * correctly. This makes them work for the most part.
2485                  *
2486                  * Volume up and down buttons on the laptop side work.
2487                  * Fn+cursor_up (volme up) works.
2488                  * Fn+cursor_down (volume down) doesn't work.
2489                  * Fn+F7 (mute) works acts as volume up.
2490                  */
2491                 outw(~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_MASK);
2492                 outw(inw(io + GPIO_DIRECTION) & ~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DIRECTION);
2493                 outw((GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DATA);
2494                 outw(0xffff, io + GPIO_MASK);
2495         }
2496         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2497         n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2498         if (chip->hv_quirk)
2499                 n |= chip->hv_quirk->config;
2500         /* For some reason we must always use reduced debounce. */
2501         n |= REDUCED_DEBOUNCE;
2502         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2503         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2504
2505         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2506         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2507         n &= ~INT_CLK_SELECT;
2508         if (!chip->allegro_flag) {
2509                 n &= ~INT_CLK_MULT_ENABLE;
2510                 n |= INT_CLK_SRC_NOT_PCI;
2511         }
2512         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2513         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2514
2515         if (chip->allegro_flag) {
2516                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2517                 n |= IN_CLK_12MHZ_SELECT;
2518                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2519         }
2520
2521         t = inb(chip->iobase + ASSP_CONTROL_A);
2522         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2523         t |= ASSP_CLK_49MHZ_SELECT;
2524         t |= ASSP_0_WS_ENABLE;
2525         outb(t, chip->iobase + ASSP_CONTROL_A);
2526
2527         snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2528         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2529
2530         outb(0x00, io + HARDWARE_VOL_CTRL);
2531         outb(0x88, io + SHADOW_MIX_REG_VOICE);
2532         outb(0x88, io + HW_VOL_COUNTER_VOICE);
2533         outb(0x88, io + SHADOW_MIX_REG_MASTER);
2534         outb(0x88, io + HW_VOL_COUNTER_MASTER);
2535
2536         return 0;
2537 }
2538
2539 static void
2540 snd_m3_enable_ints(struct snd_m3 *chip)
2541 {
2542         unsigned long io = chip->iobase;
2543         unsigned short val;
2544
2545         /* TODO: MPU401 not supported yet */
2546         val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2547         if (chip->hv_quirk && (chip->hv_quirk->config & HV_CTRL_ENABLE))
2548                 val |= HV_INT_ENABLE;
2549         outw(val, io + HOST_INT_CTRL);
2550         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2551              io + ASSP_CONTROL_C);
2552 }
2553
2554
2555 /*
2556  */
2557
2558 static int snd_m3_free(struct snd_m3 *chip)
2559 {
2560         struct m3_dma *s;
2561         int i;
2562
2563         if (chip->substreams) {
2564                 spin_lock_irq(&chip->reg_lock);
2565                 for (i = 0; i < chip->num_substreams; i++) {
2566                         s = &chip->substreams[i];
2567                         /* check surviving pcms; this should not happen though.. */
2568                         if (s->substream && s->running)
2569                                 snd_m3_pcm_stop(chip, s, s->substream);
2570                 }
2571                 spin_unlock_irq(&chip->reg_lock);
2572                 kfree(chip->substreams);
2573         }
2574         if (chip->iobase) {
2575                 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2576         }
2577
2578 #ifdef CONFIG_PM
2579         vfree(chip->suspend_mem);
2580 #endif
2581
2582         if (chip->irq >= 0) {
2583                 synchronize_irq(chip->irq);
2584                 free_irq(chip->irq, chip);
2585         }
2586
2587         if (chip->iobase)
2588                 pci_release_regions(chip->pci);
2589
2590 #ifdef FIRMWARE_IN_THE_KERNEL
2591         if (chip->assp_kernel_image != &assp_kernel)
2592 #endif
2593                 release_firmware(chip->assp_kernel_image);
2594 #ifdef FIRMWARE_IN_THE_KERNEL
2595         if (chip->assp_minisrc_image != &assp_minisrc)
2596 #endif
2597                 release_firmware(chip->assp_minisrc_image);
2598
2599         pci_disable_device(chip->pci);
2600         kfree(chip);
2601         return 0;
2602 }
2603
2604
2605 /*
2606  * APM support
2607  */
2608 #ifdef CONFIG_PM
2609 static int m3_suspend(struct pci_dev *pci, pm_message_t state)
2610 {
2611         struct snd_card *card = pci_get_drvdata(pci);
2612         struct snd_m3 *chip = card->private_data;
2613         int i, index;
2614
2615         if (chip->suspend_mem == NULL)
2616                 return 0;
2617
2618         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2619         snd_pcm_suspend_all(chip->pcm);
2620         snd_ac97_suspend(chip->ac97);
2621
2622         msleep(10); /* give the assp a chance to idle.. */
2623
2624         snd_m3_assp_halt(chip);
2625
2626         /* save dsp image */
2627         index = 0;
2628         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2629                 chip->suspend_mem[index++] =
2630                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2631         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2632                 chip->suspend_mem[index++] =
2633                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2634
2635         pci_disable_device(pci);
2636         pci_save_state(pci);
2637         pci_set_power_state(pci, pci_choose_state(pci, state));
2638         return 0;
2639 }
2640
2641 static int m3_resume(struct pci_dev *pci)
2642 {
2643         struct snd_card *card = pci_get_drvdata(pci);
2644         struct snd_m3 *chip = card->private_data;
2645         int i, index;
2646
2647         if (chip->suspend_mem == NULL)
2648                 return 0;
2649
2650         pci_set_power_state(pci, PCI_D0);
2651         pci_restore_state(pci);
2652         if (pci_enable_device(pci) < 0) {
2653                 printk(KERN_ERR "maestor3: pci_enable_device failed, "
2654                        "disabling device\n");
2655                 snd_card_disconnect(card);
2656                 return -EIO;
2657         }
2658         pci_set_master(pci);
2659
2660         /* first lets just bring everything back. .*/
2661         snd_m3_outw(chip, 0, 0x54);
2662         snd_m3_outw(chip, 0, 0x56);
2663
2664         snd_m3_chip_init(chip);
2665         snd_m3_assp_halt(chip);
2666         snd_m3_ac97_reset(chip);
2667
2668         /* restore dsp image */
2669         index = 0;
2670         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2671                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2672                                   chip->suspend_mem[index++]);
2673         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2674                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2675                                   chip->suspend_mem[index++]);
2676
2677         /* tell the dma engine to restart itself */
2678         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2679                           KDATA_DMA_ACTIVE, 0);
2680
2681         /* restore ac97 registers */
2682         snd_ac97_resume(chip->ac97);
2683
2684         snd_m3_assp_continue(chip);
2685         snd_m3_enable_ints(chip);
2686         snd_m3_amp_enable(chip, 1);
2687
2688         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2689         return 0;
2690 }
2691 #endif /* CONFIG_PM */
2692
2693
2694 /*
2695  */
2696
2697 static int snd_m3_dev_free(struct snd_device *device)
2698 {
2699         struct snd_m3 *chip = device->device_data;
2700         return snd_m3_free(chip);
2701 }
2702
2703 static int __devinit
2704 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2705               int enable_amp,
2706               int amp_gpio,
2707               struct snd_m3 **chip_ret)
2708 {
2709         struct snd_m3 *chip;
2710         int i, err;
2711         const struct m3_quirk *quirk;
2712         const struct m3_hv_quirk *hv_quirk;
2713         static struct snd_device_ops ops = {
2714                 .dev_free =     snd_m3_dev_free,
2715         };
2716
2717         *chip_ret = NULL;
2718
2719         if (pci_enable_device(pci))
2720                 return -EIO;
2721
2722         /* check, if we can restrict PCI DMA transfers to 28 bits */
2723         if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
2724             pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
2725                 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2726                 pci_disable_device(pci);
2727                 return -ENXIO;
2728         }
2729
2730         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2731         if (chip == NULL) {
2732                 pci_disable_device(pci);
2733                 return -ENOMEM;
2734         }
2735
2736         spin_lock_init(&chip->reg_lock);
2737         spin_lock_init(&chip->ac97_lock);
2738
2739         switch (pci->device) {
2740         case PCI_DEVICE_ID_ESS_ALLEGRO:
2741         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2742         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2743         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2744                 chip->allegro_flag = 1;
2745                 break;
2746         }
2747
2748         chip->card = card;
2749         chip->pci = pci;
2750         chip->irq = -1;
2751
2752         for (quirk = m3_quirk_list; quirk->vendor; quirk++) {
2753                 if (pci->subsystem_vendor == quirk->vendor &&
2754                     pci->subsystem_device == quirk->device) {
2755                         printk(KERN_INFO "maestro3: enabled hack for '%s'\n", quirk->name);
2756                         chip->quirk = quirk;
2757                         break;
2758                 }
2759         }
2760
2761         for (hv_quirk = m3_hv_quirk_list; hv_quirk->vendor; hv_quirk++) {
2762                 if (pci->vendor == hv_quirk->vendor &&
2763                     pci->device == hv_quirk->device &&
2764                     pci->subsystem_vendor == hv_quirk->subsystem_vendor &&
2765                     pci->subsystem_device == hv_quirk->subsystem_device) {
2766                         chip->hv_quirk = hv_quirk;
2767                         break;
2768                 }
2769         }
2770
2771         chip->external_amp = enable_amp;
2772         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2773                 chip->amp_gpio = amp_gpio;
2774         else if (chip->quirk && chip->quirk->amp_gpio >= 0)
2775                 chip->amp_gpio = chip->quirk->amp_gpio;
2776         else if (chip->allegro_flag)
2777                 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2778         else /* presumably this is for all 'maestro3's.. */
2779                 chip->amp_gpio = GPO_EXT_AMP_M3;
2780
2781         chip->num_substreams = NR_DSPS;
2782         chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2783                                    GFP_KERNEL);
2784         if (chip->substreams == NULL) {
2785                 kfree(chip);
2786                 pci_disable_device(pci);
2787                 return -ENOMEM;
2788         }
2789
2790         err = request_firmware(&chip->assp_kernel_image,
2791                                "ess/maestro3_assp_kernel.fw", &pci->dev);
2792         if (err < 0) {
2793 #ifdef FIRMWARE_IN_THE_KERNEL
2794                 chip->assp_kernel_image = &assp_kernel;
2795 #else
2796                 snd_m3_free(chip);
2797                 return err;
2798 #endif
2799         } else
2800                 snd_m3_convert_from_le(chip->assp_kernel_image);
2801
2802         err = request_firmware(&chip->assp_minisrc_image,
2803                                "ess/maestro3_assp_minisrc.fw", &pci->dev);
2804         if (err < 0) {
2805 #ifdef FIRMWARE_IN_THE_KERNEL
2806                 chip->assp_minisrc_image = &assp_minisrc;
2807 #else
2808                 snd_m3_free(chip);
2809                 return err;
2810 #endif
2811         } else
2812                 snd_m3_convert_from_le(chip->assp_minisrc_image);
2813
2814         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2815                 snd_m3_free(chip);
2816                 return err;
2817         }
2818         chip->iobase = pci_resource_start(pci, 0);
2819
2820         /* just to be sure */
2821         pci_set_master(pci);
2822
2823         snd_m3_chip_init(chip);
2824         snd_m3_assp_halt(chip);
2825
2826         snd_m3_ac97_reset(chip);
2827
2828         snd_m3_amp_enable(chip, 1);
2829
2830         tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2831
2832         if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2833                         card->driver, chip)) {
2834                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2835                 snd_m3_free(chip);
2836                 return -ENOMEM;
2837         }
2838         chip->irq = pci->irq;
2839
2840 #ifdef CONFIG_PM
2841         chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2842         if (chip->suspend_mem == NULL)
2843                 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2844 #endif
2845
2846         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2847                 snd_m3_free(chip);
2848                 return err;
2849         }
2850
2851         if ((err = snd_m3_mixer(chip)) < 0)
2852                 return err;
2853
2854         for (i = 0; i < chip->num_substreams; i++) {
2855                 struct m3_dma *s = &chip->substreams[i];
2856                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2857                         return err;
2858         }
2859
2860         if ((err = snd_m3_pcm(chip, 0)) < 0)
2861                 return err;
2862
2863         snd_m3_enable_ints(chip);
2864         snd_m3_assp_continue(chip);
2865
2866         snd_card_set_dev(card, &pci->dev);
2867
2868         *chip_ret = chip;
2869
2870         return 0;
2871 }
2872
2873 /*
2874  */
2875 static int __devinit
2876 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2877 {
2878         static int dev;
2879         struct snd_card *card;
2880         struct snd_m3 *chip;
2881         int err;
2882
2883         /* don't pick up modems */
2884         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2885                 return -ENODEV;
2886
2887         if (dev >= SNDRV_CARDS)
2888                 return -ENODEV;
2889         if (!enable[dev]) {
2890                 dev++;
2891                 return -ENOENT;
2892         }
2893
2894         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2895         if (card == NULL)
2896                 return -ENOMEM;
2897
2898         switch (pci->device) {
2899         case PCI_DEVICE_ID_ESS_ALLEGRO:
2900         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2901                 strcpy(card->driver, "Allegro");
2902                 break;
2903         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2904         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2905                 strcpy(card->driver, "Canyon3D-2");
2906                 break;
2907         default:
2908                 strcpy(card->driver, "Maestro3");
2909                 break;
2910         }
2911
2912         if ((err = snd_m3_create(card, pci,
2913                                  external_amp[dev],
2914                                  amp_gpio[dev],
2915                                  &chip)) < 0) {
2916                 snd_card_free(card);
2917                 return err;
2918         }
2919         card->private_data = chip;
2920
2921         sprintf(card->shortname, "ESS %s PCI", card->driver);
2922         sprintf(card->longname, "%s at 0x%lx, irq %d",
2923                 card->shortname, chip->iobase, chip->irq);
2924
2925         if ((err = snd_card_register(card)) < 0) {
2926                 snd_card_free(card);
2927                 return err;
2928         }
2929
2930 #if 0 /* TODO: not supported yet */
2931         /* TODO enable MIDI IRQ and I/O */
2932         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2933                                   chip->iobase + MPU401_DATA_PORT,
2934                                   MPU401_INFO_INTEGRATED,
2935                                   chip->irq, 0, &chip->rmidi);
2936         if (err < 0)
2937                 printk(KERN_WARNING "maestro3: no MIDI support.\n");
2938 #endif
2939
2940         pci_set_drvdata(pci, card);
2941         dev++;
2942         return 0;
2943 }
2944
2945 static void __devexit snd_m3_remove(struct pci_dev *pci)
2946 {
2947         snd_card_free(pci_get_drvdata(pci));
2948         pci_set_drvdata(pci, NULL);
2949 }
2950
2951 static struct pci_driver driver = {
2952         .name = "Maestro3",
2953         .id_table = snd_m3_ids,
2954         .probe = snd_m3_probe,
2955         .remove = __devexit_p(snd_m3_remove),
2956 #ifdef CONFIG_PM
2957         .suspend = m3_suspend,
2958         .resume = m3_resume,
2959 #endif
2960 };
2961
2962 static int __init alsa_card_m3_init(void)
2963 {
2964         return pci_register_driver(&driver);
2965 }
2966
2967 static void __exit alsa_card_m3_exit(void)
2968 {
2969         pci_unregister_driver(&driver);
2970 }
2971
2972 module_init(alsa_card_m3_init)
2973 module_exit(alsa_card_m3_exit)