sound/pci/rme96.c

   1 /*
   2  *   ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
   3  *   interfaces
   4  *
   5  *      Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
   6  *
   7  *      Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
   8  *      code.
   9  *
  10  *   This program is free software; you can redistribute it and/or modify
  11  *   it under the terms of the GNU General Public License as published by
  12  *   the Free Software Foundation; either version 2 of the License, or
  13  *   (at your option) any later version.
  14  *
  15  *   This program is distributed in the hope that it will be useful,
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *   GNU General Public License for more details.
  19  *
  20  *   You should have received a copy of the GNU General Public License
  21  *   along with this program; if not, write to the Free Software
  22  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/module.h>
  31
  32 #include <sound/core.h>
  33 #include <sound/info.h>
  34 #include <sound/control.h>
  35 #include <sound/pcm.h>
  36 #include <sound/pcm_params.h>
  37 #include <sound/asoundef.h>
  38 #include <sound/initval.h>
  39
  40 #include <asm/io.h>
  41
  42 /* note, two last pcis should be equal, it is not a bug */
  43
  44 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
  45 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
  46                    "Digi96/8 PAD");
  47 MODULE_LICENSE("GPL");
  48 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
  49                 "{RME,Digi96/8},"
  50                 "{RME,Digi96/8 PRO},"
  51                 "{RME,Digi96/8 PST},"
  52                 "{RME,Digi96/8 PAD}}");
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  56 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
  57
  58 module_param_array(index, int, NULL, 0444);
  59 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
  60 module_param_array(id, charp, NULL, 0444);
  61 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
  62 module_param_array(enable, bool, NULL, 0444);
  63 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
  64
  65 /*
  66  * Defines for RME Digi96 series, from internal RME reference documents
  67  * dated 12.01.00
  68  */
  69
  70 #define RME96_SPDIF_NCHANNELS 2
  71
  72 /* Playback and capture buffer size */
  73 #define RME96_BUFFER_SIZE 0x10000
  74
  75 /* IO area size */
  76 #define RME96_IO_SIZE 0x60000
  77
  78 /* IO area offsets */
  79 #define RME96_IO_PLAY_BUFFER      0x0
  80 #define RME96_IO_REC_BUFFER       0x10000
  81 #define RME96_IO_CONTROL_REGISTER 0x20000
  82 #define RME96_IO_ADDITIONAL_REG   0x20004
  83 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
  84 #define RME96_IO_CONFIRM_REC_IRQ  0x2000C
  85 #define RME96_IO_SET_PLAY_POS     0x40000
  86 #define RME96_IO_RESET_PLAY_POS   0x4FFFC
  87 #define RME96_IO_SET_REC_POS      0x50000
  88 #define RME96_IO_RESET_REC_POS    0x5FFFC
  89 #define RME96_IO_GET_PLAY_POS     0x20000
  90 #define RME96_IO_GET_REC_POS      0x30000
  91
  92 /* Write control register bits */
  93 #define RME96_WCR_START     (1 << 0)
  94 #define RME96_WCR_START_2   (1 << 1)
  95 #define RME96_WCR_GAIN_0    (1 << 2)
  96 #define RME96_WCR_GAIN_1    (1 << 3)
  97 #define RME96_WCR_MODE24    (1 << 4)
  98 #define RME96_WCR_MODE24_2  (1 << 5)
  99 #define RME96_WCR_BM        (1 << 6)
 100 #define RME96_WCR_BM_2      (1 << 7)
 101 #define RME96_WCR_ADAT      (1 << 8)
 102 #define RME96_WCR_FREQ_0    (1 << 9)
 103 #define RME96_WCR_FREQ_1    (1 << 10)
 104 #define RME96_WCR_DS        (1 << 11)
 105 #define RME96_WCR_PRO       (1 << 12)
 106 #define RME96_WCR_EMP       (1 << 13)
 107 #define RME96_WCR_SEL       (1 << 14)
 108 #define RME96_WCR_MASTER    (1 << 15)
 109 #define RME96_WCR_PD        (1 << 16)
 110 #define RME96_WCR_INP_0     (1 << 17)
 111 #define RME96_WCR_INP_1     (1 << 18)
 112 #define RME96_WCR_THRU_0    (1 << 19)
 113 #define RME96_WCR_THRU_1    (1 << 20)
 114 #define RME96_WCR_THRU_2    (1 << 21)
 115 #define RME96_WCR_THRU_3    (1 << 22)
 116 #define RME96_WCR_THRU_4    (1 << 23)
 117 #define RME96_WCR_THRU_5    (1 << 24)
 118 #define RME96_WCR_THRU_6    (1 << 25)
 119 #define RME96_WCR_THRU_7    (1 << 26)
 120 #define RME96_WCR_DOLBY     (1 << 27)
 121 #define RME96_WCR_MONITOR_0 (1 << 28)
 122 #define RME96_WCR_MONITOR_1 (1 << 29)
 123 #define RME96_WCR_ISEL      (1 << 30)
 124 #define RME96_WCR_IDIS      (1 << 31)
 125
 126 #define RME96_WCR_BITPOS_GAIN_0 2
 127 #define RME96_WCR_BITPOS_GAIN_1 3
 128 #define RME96_WCR_BITPOS_FREQ_0 9
 129 #define RME96_WCR_BITPOS_FREQ_1 10
 130 #define RME96_WCR_BITPOS_INP_0 17
 131 #define RME96_WCR_BITPOS_INP_1 18
 132 #define RME96_WCR_BITPOS_MONITOR_0 28
 133 #define RME96_WCR_BITPOS_MONITOR_1 29
 134
 135 /* Read control register bits */
 136 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
 137 #define RME96_RCR_IRQ_2     (1 << 16)
 138 #define RME96_RCR_T_OUT     (1 << 17)
 139 #define RME96_RCR_DEV_ID_0  (1 << 21)
 140 #define RME96_RCR_DEV_ID_1  (1 << 22)
 141 #define RME96_RCR_LOCK      (1 << 23)
 142 #define RME96_RCR_VERF      (1 << 26)
 143 #define RME96_RCR_F0        (1 << 27)
 144 #define RME96_RCR_F1        (1 << 28)
 145 #define RME96_RCR_F2        (1 << 29)
 146 #define RME96_RCR_AUTOSYNC  (1 << 30)
 147 #define RME96_RCR_IRQ       (1 << 31)
 148
 149 #define RME96_RCR_BITPOS_F0 27
 150 #define RME96_RCR_BITPOS_F1 28
 151 #define RME96_RCR_BITPOS_F2 29
 152
 153 /* Additional register bits */
 154 #define RME96_AR_WSEL       (1 << 0)
 155 #define RME96_AR_ANALOG     (1 << 1)
 156 #define RME96_AR_FREQPAD_0  (1 << 2)
 157 #define RME96_AR_FREQPAD_1  (1 << 3)
 158 #define RME96_AR_FREQPAD_2  (1 << 4)
 159 #define RME96_AR_PD2        (1 << 5)
 160 #define RME96_AR_DAC_EN     (1 << 6)
 161 #define RME96_AR_CLATCH     (1 << 7)
 162 #define RME96_AR_CCLK       (1 << 8)
 163 #define RME96_AR_CDATA      (1 << 9)
 164
 165 #define RME96_AR_BITPOS_F0 2
 166 #define RME96_AR_BITPOS_F1 3
 167 #define RME96_AR_BITPOS_F2 4
 168
 169 /* Monitor tracks */
 170 #define RME96_MONITOR_TRACKS_1_2 0
 171 #define RME96_MONITOR_TRACKS_3_4 1
 172 #define RME96_MONITOR_TRACKS_5_6 2
 173 #define RME96_MONITOR_TRACKS_7_8 3
 174
 175 /* Attenuation */
 176 #define RME96_ATTENUATION_0 0
 177 #define RME96_ATTENUATION_6 1
 178 #define RME96_ATTENUATION_12 2
 179 #define RME96_ATTENUATION_18 3
 180
 181 /* Input types */
 182 #define RME96_INPUT_OPTICAL 0
 183 #define RME96_INPUT_COAXIAL 1
 184 #define RME96_INPUT_INTERNAL 2
 185 #define RME96_INPUT_XLR 3
 186 #define RME96_INPUT_ANALOG 4
 187
 188 /* Clock modes */
 189 #define RME96_CLOCKMODE_SLAVE 0
 190 #define RME96_CLOCKMODE_MASTER 1
 191 #define RME96_CLOCKMODE_WORDCLOCK 2
 192
 193 /* Block sizes in bytes */
 194 #define RME96_SMALL_BLOCK_SIZE 2048
 195 #define RME96_LARGE_BLOCK_SIZE 8192
 196
 197 /* Volume control */
 198 #define RME96_AD1852_VOL_BITS 14
 199 #define RME96_AD1855_VOL_BITS 10
 200
 201 /* Defines for snd_rme96_trigger */
 202 #define RME96_TB_START_PLAYBACK 1
 203 #define RME96_TB_START_CAPTURE 2
 204 #define RME96_TB_STOP_PLAYBACK 4
 205 #define RME96_TB_STOP_CAPTURE 8
 206 #define RME96_TB_RESET_PLAYPOS 16
 207 #define RME96_TB_RESET_CAPTUREPOS 32
 208 #define RME96_TB_CLEAR_PLAYBACK_IRQ 64
 209 #define RME96_TB_CLEAR_CAPTURE_IRQ 128
 210 #define RME96_RESUME_PLAYBACK   (RME96_TB_START_PLAYBACK)
 211 #define RME96_RESUME_CAPTURE    (RME96_TB_START_CAPTURE)
 212 #define RME96_RESUME_BOTH       (RME96_RESUME_PLAYBACK \
 213                                 | RME96_RESUME_CAPTURE)
 214 #define RME96_START_PLAYBACK    (RME96_TB_START_PLAYBACK \
 215                                 | RME96_TB_RESET_PLAYPOS)
 216 #define RME96_START_CAPTURE     (RME96_TB_START_CAPTURE \
 217                                 | RME96_TB_RESET_CAPTUREPOS)
 218 #define RME96_START_BOTH        (RME96_START_PLAYBACK \
 219                                 | RME96_START_CAPTURE)
 220 #define RME96_STOP_PLAYBACK     (RME96_TB_STOP_PLAYBACK \
 221                                 | RME96_TB_CLEAR_PLAYBACK_IRQ)
 222 #define RME96_STOP_CAPTURE      (RME96_TB_STOP_CAPTURE \
 223                                 | RME96_TB_CLEAR_CAPTURE_IRQ)
 224 #define RME96_STOP_BOTH         (RME96_STOP_PLAYBACK \
 225                                 | RME96_STOP_CAPTURE)
 226
 227 struct rme96 {
 228         spinlock_t    lock;
 229         int irq;
 230         unsigned long port;
 231         void __iomem *iobase;
 232
 233         u32 wcreg;    /* cached write control register value */
 234         u32 wcreg_spdif;                /* S/PDIF setup */
 235         u32 wcreg_spdif_stream;         /* S/PDIF setup (temporary) */
 236         u32 rcreg;    /* cached read control register value */
 237         u32 areg;     /* cached additional register value */
 238         u16 vol[2]; /* cached volume of analog output */
 239
 240         u8 rev; /* card revision number */
 241
 242         struct snd_pcm_substream *playback_substream;
 243         struct snd_pcm_substream *capture_substream;
 244
 245         int playback_frlog; /* log2 of framesize */
 246         int capture_frlog;
 247
 248         size_t playback_periodsize; /* in bytes, zero if not used */
 249         size_t capture_periodsize; /* in bytes, zero if not used */
 250
 251         struct snd_card *card;
 252         struct snd_pcm *spdif_pcm;
 253         struct snd_pcm *adat_pcm;
 254         struct pci_dev     *pci;
 255         struct snd_kcontrol   *spdif_ctl;
 256 };
 257
 258 static DEFINE_PCI_DEVICE_TABLE(snd_rme96_ids) = {
 259         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
 260         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
 261         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
 262         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
 263         { 0, }
 264 };
 265
 266 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
 267
 268 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
 269 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
 270 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
 271 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
 272                                      (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
 273 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
 274 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
 275                                   ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
 276 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
 277
 278 static int
 279 snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
 280
 281 static int
 282 snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
 283
 284 static int
 285 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
 286                            int cmd);
 287
 288 static int
 289 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
 290                           int cmd);
 291
 292 static snd_pcm_uframes_t
 293 snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
 294
 295 static snd_pcm_uframes_t
 296 snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
 297
 298 static void snd_rme96_proc_init(struct rme96 *rme96);
 299
 300 static int
 301 snd_rme96_create_switches(struct snd_card *card,
 302                           struct rme96 *rme96);
 303
 304 static int
 305 snd_rme96_getinputtype(struct rme96 *rme96);
 306
 307 static inline unsigned int
 308 snd_rme96_playback_ptr(struct rme96 *rme96)
 309 {
 310         return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
 311                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
 312 }
 313
 314 static inline unsigned int
 315 snd_rme96_capture_ptr(struct rme96 *rme96)
 316 {
 317         return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
 318                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
 319 }
 320
 321 static int
 322 snd_rme96_playback_silence(struct snd_pcm_substream *substream,
 323                            int channel, /* not used (interleaved data) */
 324                            snd_pcm_uframes_t pos,
 325                            snd_pcm_uframes_t count)
 326 {
 327         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 328         count <<= rme96->playback_frlog;
 329         pos <<= rme96->playback_frlog;
 330         memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
 331                   0, count);
 332         return 0;
 333 }
 334
 335 static int
 336 snd_rme96_playback_copy(struct snd_pcm_substream *substream,
 337                         int channel, /* not used (interleaved data) */
 338                         snd_pcm_uframes_t pos,
 339                         void __user *src,
 340                         snd_pcm_uframes_t count)
 341 {
 342         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 343         count <<= rme96->playback_frlog;
 344         pos <<= rme96->playback_frlog;
 345         copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
 346                             count);
 347         return 0;
 348 }
 349
 350 static int
 351 snd_rme96_capture_copy(struct snd_pcm_substream *substream,
 352                        int channel, /* not used (interleaved data) */
 353                        snd_pcm_uframes_t pos,
 354                        void __user *dst,
 355                        snd_pcm_uframes_t count)
 356 {
 357         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 358         count <<= rme96->capture_frlog;
 359         pos <<= rme96->capture_frlog;
 360         copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
 361                             count);
 362         return 0;
 363 }
 364
 365 /*
 366  * Digital output capabilities (S/PDIF)
 367  */
 368 static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
 369 {
 370         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 371                               SNDRV_PCM_INFO_MMAP_VALID |
 372                               SNDRV_PCM_INFO_SYNC_START |
 373                               SNDRV_PCM_INFO_INTERLEAVED |
 374                               SNDRV_PCM_INFO_PAUSE),
 375         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 376                               SNDRV_PCM_FMTBIT_S32_LE),
 377         .rates =             (SNDRV_PCM_RATE_32000 |
 378                               SNDRV_PCM_RATE_44100 |
 379                               SNDRV_PCM_RATE_48000 |
 380                               SNDRV_PCM_RATE_64000 |
 381                               SNDRV_PCM_RATE_88200 |
 382                               SNDRV_PCM_RATE_96000),
 383         .rate_min =          32000,
 384         .rate_max =          96000,
 385         .channels_min =      2,
 386         .channels_max =      2,
 387         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 388         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 389         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 390         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 391         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 392         .fifo_size =         0,
 393 };
 394
 395 /*
 396  * Digital input capabilities (S/PDIF)
 397  */
 398 static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
 399 {
 400         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 401                               SNDRV_PCM_INFO_MMAP_VALID |
 402                               SNDRV_PCM_INFO_SYNC_START |
 403                               SNDRV_PCM_INFO_INTERLEAVED |
 404                               SNDRV_PCM_INFO_PAUSE),
 405         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 406                               SNDRV_PCM_FMTBIT_S32_LE),
 407         .rates =             (SNDRV_PCM_RATE_32000 |
 408                               SNDRV_PCM_RATE_44100 |
 409                               SNDRV_PCM_RATE_48000 |
 410                               SNDRV_PCM_RATE_64000 |
 411                               SNDRV_PCM_RATE_88200 |
 412                               SNDRV_PCM_RATE_96000),
 413         .rate_min =          32000,
 414         .rate_max =          96000,
 415         .channels_min =      2,
 416         .channels_max =      2,
 417         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 418         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 419         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 420         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 421         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 422         .fifo_size =         0,
 423 };
 424
 425 /*
 426  * Digital output capabilities (ADAT)
 427  */
 428 static struct snd_pcm_hardware snd_rme96_playback_adat_info =
 429 {
 430         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 431                               SNDRV_PCM_INFO_MMAP_VALID |
 432                               SNDRV_PCM_INFO_SYNC_START |
 433                               SNDRV_PCM_INFO_INTERLEAVED |
 434                               SNDRV_PCM_INFO_PAUSE),
 435         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 436                               SNDRV_PCM_FMTBIT_S32_LE),
 437         .rates =             (SNDRV_PCM_RATE_44100 |
 438                               SNDRV_PCM_RATE_48000),
 439         .rate_min =          44100,
 440         .rate_max =          48000,
 441         .channels_min =      8,
 442         .channels_max =      8,
 443         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 444         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 445         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 446         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 447         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 448         .fifo_size =         0,
 449 };
 450
 451 /*
 452  * Digital input capabilities (ADAT)
 453  */
 454 static struct snd_pcm_hardware snd_rme96_capture_adat_info =
 455 {
 456         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 457                               SNDRV_PCM_INFO_MMAP_VALID |
 458                               SNDRV_PCM_INFO_SYNC_START |
 459                               SNDRV_PCM_INFO_INTERLEAVED |
 460                               SNDRV_PCM_INFO_PAUSE),
 461         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 462                               SNDRV_PCM_FMTBIT_S32_LE),
 463         .rates =             (SNDRV_PCM_RATE_44100 |
 464                               SNDRV_PCM_RATE_48000),
 465         .rate_min =          44100,
 466         .rate_max =          48000,
 467         .channels_min =      8,
 468         .channels_max =      8,
 469         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 470         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 471         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 472         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 473         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 474         .fifo_size =         0,
 475 };
 476
 477 /*
 478  * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
 479  * of the AD1852 or AD1852 D/A converter on the board.  CDATA must be set up
 480  * on the falling edge of CCLK and be stable on the rising edge.  The rising
 481  * edge of CLATCH after the last data bit clocks in the whole data word.
 482  * A fast processor could probably drive the SPI interface faster than the
 483  * DAC can handle (3MHz for the 1855, unknown for the 1852).  The udelay(1)
 484  * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
 485  *
 486  * NOTE: increased delay from 1 to 10, since there where problems setting
 487  * the volume.
 488  */
 489 static void
 490 snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
 491 {
 492         int i;
 493
 494         for (i = 0; i < 16; i++) {
 495                 if (val & 0x8000) {
 496                         rme96->areg |= RME96_AR_CDATA;
 497                 } else {
 498                         rme96->areg &= ~RME96_AR_CDATA;
 499                 }
 500                 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
 501                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 502                 udelay(10);
 503                 rme96->areg |= RME96_AR_CCLK;
 504                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 505                 udelay(10);
 506                 val <<= 1;
 507         }
 508         rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
 509         rme96->areg |= RME96_AR_CLATCH;
 510         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 511         udelay(10);
 512         rme96->areg &= ~RME96_AR_CLATCH;
 513         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 514 }
 515
 516 static void
 517 snd_rme96_apply_dac_volume(struct rme96 *rme96)
 518 {
 519         if (RME96_DAC_IS_1852(rme96)) {
 520                 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
 521                 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
 522         } else if (RME96_DAC_IS_1855(rme96)) {
 523                 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
 524                 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
 525         }
 526 }
 527
 528 static void
 529 snd_rme96_reset_dac(struct rme96 *rme96)
 530 {
 531         writel(rme96->wcreg | RME96_WCR_PD,
 532                rme96->iobase + RME96_IO_CONTROL_REGISTER);
 533         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 534 }
 535
 536 static int
 537 snd_rme96_getmontracks(struct rme96 *rme96)
 538 {
 539         return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
 540                 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
 541 }
 542
 543 static int
 544 snd_rme96_setmontracks(struct rme96 *rme96,
 545                        int montracks)
 546 {
 547         if (montracks & 1) {
 548                 rme96->wcreg |= RME96_WCR_MONITOR_0;
 549         } else {
 550                 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
 551         }
 552         if (montracks & 2) {
 553                 rme96->wcreg |= RME96_WCR_MONITOR_1;
 554         } else {
 555                 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
 556         }
 557         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 558         return 0;
 559 }
 560
 561 static int
 562 snd_rme96_getattenuation(struct rme96 *rme96)
 563 {
 564         return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
 565                 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
 566 }
 567
 568 static int
 569 snd_rme96_setattenuation(struct rme96 *rme96,
 570                          int attenuation)
 571 {
 572         switch (attenuation) {
 573         case 0:
 574                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
 575                         ~RME96_WCR_GAIN_1;
 576                 break;
 577         case 1:
 578                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
 579                         ~RME96_WCR_GAIN_1;
 580                 break;
 581         case 2:
 582                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
 583                         RME96_WCR_GAIN_1;
 584                 break;
 585         case 3:
 586                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
 587                         RME96_WCR_GAIN_1;
 588                 break;
 589         default:
 590                 return -EINVAL;
 591         }
 592         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 593         return 0;
 594 }
 595
 596 static int
 597 snd_rme96_capture_getrate(struct rme96 *rme96,
 598                           int *is_adat)
 599 {
 600         int n, rate;
 601
 602         *is_adat = 0;
 603         if (rme96->areg & RME96_AR_ANALOG) {
 604                 /* Analog input, overrides S/PDIF setting */
 605                 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
 606                         (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
 607                 switch (n) {
 608                 case 1:
 609                         rate = 32000;
 610                         break;
 611                 case 2:
 612                         rate = 44100;
 613                         break;
 614                 case 3:
 615                         rate = 48000;
 616                         break;
 617                 default:
 618                         return -1;
 619                 }
 620                 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
 621         }
 622
 623         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
 624         if (rme96->rcreg & RME96_RCR_LOCK) {
 625                 /* ADAT rate */
 626                 *is_adat = 1;
 627                 if (rme96->rcreg & RME96_RCR_T_OUT) {
 628                         return 48000;
 629                 }
 630                 return 44100;
 631         }
 632
 633         if (rme96->rcreg & RME96_RCR_VERF) {
 634                 return -1;
 635         }
 636
 637         /* S/PDIF rate */
 638         n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
 639                 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
 640                 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
 641
 642         switch (n) {
 643         case 0:
 644                 if (rme96->rcreg & RME96_RCR_T_OUT) {
 645                         return 64000;
 646                 }
 647                 return -1;
 648         case 3: return 96000;
 649         case 4: return 88200;
 650         case 5: return 48000;
 651         case 6: return 44100;
 652         case 7: return 32000;
 653         default:
 654                 break;
 655         }
 656         return -1;
 657 }
 658
 659 static int
 660 snd_rme96_playback_getrate(struct rme96 *rme96)
 661 {
 662         int rate, dummy;
 663
 664         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
 665             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
 666             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
 667         {
 668                 /* slave clock */
 669                 return rate;
 670         }
 671         rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
 672                 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
 673         switch (rate) {
 674         case 1:
 675                 rate = 32000;
 676                 break;
 677         case 2:
 678                 rate = 44100;
 679                 break;
 680         case 3:
 681                 rate = 48000;
 682                 break;
 683         default:
 684                 return -1;
 685         }
 686         return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
 687 }
 688
 689 static int
 690 snd_rme96_playback_setrate(struct rme96 *rme96,
 691                            int rate)
 692 {
 693         int ds;
 694
 695         ds = rme96->wcreg & RME96_WCR_DS;
 696         switch (rate) {
 697         case 32000:
 698                 rme96->wcreg &= ~RME96_WCR_DS;
 699                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
 700                         ~RME96_WCR_FREQ_1;
 701                 break;
 702         case 44100:
 703                 rme96->wcreg &= ~RME96_WCR_DS;
 704                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
 705                         ~RME96_WCR_FREQ_0;
 706                 break;
 707         case 48000:
 708                 rme96->wcreg &= ~RME96_WCR_DS;
 709                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
 710                         RME96_WCR_FREQ_1;
 711                 break;
 712         case 64000:
 713                 rme96->wcreg |= RME96_WCR_DS;
 714                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
 715                         ~RME96_WCR_FREQ_1;
 716                 break;
 717         case 88200:
 718                 rme96->wcreg |= RME96_WCR_DS;
 719                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
 720                         ~RME96_WCR_FREQ_0;
 721                 break;
 722         case 96000:
 723                 rme96->wcreg |= RME96_WCR_DS;
 724                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
 725                         RME96_WCR_FREQ_1;
 726                 break;
 727         default:
 728                 return -EINVAL;
 729         }
 730         if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
 731             (ds && !(rme96->wcreg & RME96_WCR_DS)))
 732         {
 733                 /* change to/from double-speed: reset the DAC (if available) */
 734                 snd_rme96_reset_dac(rme96);
 735         } else {
 736                 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 737         }
 738         return 0;
 739 }
 740
 741 static int
 742 snd_rme96_capture_analog_setrate(struct rme96 *rme96,
 743                                  int rate)
 744 {
 745         switch (rate) {
 746         case 32000:
 747                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
 748                                ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 749                 break;
 750         case 44100:
 751                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
 752                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 753                 break;
 754         case 48000:
 755                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
 756                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 757                 break;
 758         case 64000:
 759                 if (rme96->rev < 4) {
 760                         return -EINVAL;
 761                 }
 762                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
 763                                ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 764                 break;
 765         case 88200:
 766                 if (rme96->rev < 4) {
 767                         return -EINVAL;
 768                 }
 769                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
 770                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 771                 break;
 772         case 96000:
 773                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
 774                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 775                 break;
 776         default:
 777                 return -EINVAL;
 778         }
 779         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 780         return 0;
 781 }
 782
 783 static int
 784 snd_rme96_setclockmode(struct rme96 *rme96,
 785                        int mode)
 786 {
 787         switch (mode) {
 788         case RME96_CLOCKMODE_SLAVE:
 789                 /* AutoSync */
 790                 rme96->wcreg &= ~RME96_WCR_MASTER;
 791                 rme96->areg &= ~RME96_AR_WSEL;
 792                 break;
 793         case RME96_CLOCKMODE_MASTER:
 794                 /* Internal */
 795                 rme96->wcreg |= RME96_WCR_MASTER;
 796                 rme96->areg &= ~RME96_AR_WSEL;
 797                 break;
 798         case RME96_CLOCKMODE_WORDCLOCK:
 799                 /* Word clock is a master mode */
 800                 rme96->wcreg |= RME96_WCR_MASTER;
 801                 rme96->areg |= RME96_AR_WSEL;
 802                 break;
 803         default:
 804                 return -EINVAL;
 805         }
 806         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 807         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 808         return 0;
 809 }
 810
 811 static int
 812 snd_rme96_getclockmode(struct rme96 *rme96)
 813 {
 814         if (rme96->areg & RME96_AR_WSEL) {
 815                 return RME96_CLOCKMODE_WORDCLOCK;
 816         }
 817         return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
 818                 RME96_CLOCKMODE_SLAVE;
 819 }
 820
 821 static int
 822 snd_rme96_setinputtype(struct rme96 *rme96,
 823                        int type)
 824 {
 825         int n;
 826
 827         switch (type) {
 828         case RME96_INPUT_OPTICAL:
 829                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
 830                         ~RME96_WCR_INP_1;
 831                 break;
 832         case RME96_INPUT_COAXIAL:
 833                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
 834                         ~RME96_WCR_INP_1;
 835                 break;
 836         case RME96_INPUT_INTERNAL:
 837                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
 838                         RME96_WCR_INP_1;
 839                 break;
 840         case RME96_INPUT_XLR:
 841                 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
 842                      rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
 843                     (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
 844                      rme96->rev > 4))
 845                 {
 846                         /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
 847                         return -EINVAL;
 848                 }
 849                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
 850                         RME96_WCR_INP_1;
 851                 break;
 852         case RME96_INPUT_ANALOG:
 853                 if (!RME96_HAS_ANALOG_IN(rme96)) {
 854                         return -EINVAL;
 855                 }
 856                 rme96->areg |= RME96_AR_ANALOG;
 857                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 858                 if (rme96->rev < 4) {
 859                         /*
 860                          * Revision less than 004 does not support 64 and
 861                          * 88.2 kHz
 862                          */
 863                         if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
 864                                 snd_rme96_capture_analog_setrate(rme96, 44100);
 865                         }
 866                         if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
 867                                 snd_rme96_capture_analog_setrate(rme96, 32000);
 868                         }
 869                 }
 870                 return 0;
 871         default:
 872                 return -EINVAL;
 873         }
 874         if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
 875                 rme96->areg &= ~RME96_AR_ANALOG;
 876                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 877         }
 878         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 879         return 0;
 880 }
 881
 882 static int
 883 snd_rme96_getinputtype(struct rme96 *rme96)
 884 {
 885         if (rme96->areg & RME96_AR_ANALOG) {
 886                 return RME96_INPUT_ANALOG;
 887         }
 888         return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
 889                 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
 890 }
 891
 892 static void
 893 snd_rme96_setframelog(struct rme96 *rme96,
 894                       int n_channels,
 895                       int is_playback)
 896 {
 897         int frlog;
 898
 899         if (n_channels == 2) {
 900                 frlog = 1;
 901         } else {
 902                 /* assume 8 channels */
 903                 frlog = 3;
 904         }
 905         if (is_playback) {
 906                 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
 907                 rme96->playback_frlog = frlog;
 908         } else {
 909                 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
 910                 rme96->capture_frlog = frlog;
 911         }
 912 }
 913
 914 static int
 915 snd_rme96_playback_setformat(struct rme96 *rme96,
 916                              int format)
 917 {
 918         switch (format) {
 919         case SNDRV_PCM_FORMAT_S16_LE:
 920                 rme96->wcreg &= ~RME96_WCR_MODE24;
 921                 break;
 922         case SNDRV_PCM_FORMAT_S32_LE:
 923                 rme96->wcreg |= RME96_WCR_MODE24;
 924                 break;
 925         default:
 926                 return -EINVAL;
 927         }
 928         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 929         return 0;
 930 }
 931
 932 static int
 933 snd_rme96_capture_setformat(struct rme96 *rme96,
 934                             int format)
 935 {
 936         switch (format) {
 937         case SNDRV_PCM_FORMAT_S16_LE:
 938                 rme96->wcreg &= ~RME96_WCR_MODE24_2;
 939                 break;
 940         case SNDRV_PCM_FORMAT_S32_LE:
 941                 rme96->wcreg |= RME96_WCR_MODE24_2;
 942                 break;
 943         default:
 944                 return -EINVAL;
 945         }
 946         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 947         return 0;
 948 }
 949
 950 static void
 951 snd_rme96_set_period_properties(struct rme96 *rme96,
 952                                 size_t period_bytes)
 953 {
 954         switch (period_bytes) {
 955         case RME96_LARGE_BLOCK_SIZE:
 956                 rme96->wcreg &= ~RME96_WCR_ISEL;
 957                 break;
 958         case RME96_SMALL_BLOCK_SIZE:
 959                 rme96->wcreg |= RME96_WCR_ISEL;
 960                 break;
 961         default:
 962                 snd_BUG();
 963                 break;
 964         }
 965         rme96->wcreg &= ~RME96_WCR_IDIS;
 966         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 967 }
 968
 969 static int
 970 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
 971                              struct snd_pcm_hw_params *params)
 972 {
 973         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 974         struct snd_pcm_runtime *runtime = substream->runtime;
 975         int err, rate, dummy;
 976
 977         runtime->dma_area = (void __force *)(rme96->iobase +
 978                                              RME96_IO_PLAY_BUFFER);
 979         runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
 980         runtime->dma_bytes = RME96_BUFFER_SIZE;
 981
 982         spin_lock_irq(&rme96->lock);
 983         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
 984             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
 985             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
 986         {
 987                 /* slave clock */
 988                 if ((int)params_rate(params) != rate) {
 989                         spin_unlock_irq(&rme96->lock);
 990                         return -EIO;
 991                 }
 992         } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
 993                 spin_unlock_irq(&rme96->lock);
 994                 return err;
 995         }
 996         if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
 997                 spin_unlock_irq(&rme96->lock);
 998                 return err;
 999         }
1000         snd_rme96_setframelog(rme96, params_channels(params), 1);
1001         if (rme96->capture_periodsize != 0) {
1002                 if (params_period_size(params) << rme96->playback_frlog !=
1003                     rme96->capture_periodsize)
1004                 {
1005                         spin_unlock_irq(&rme96->lock);
1006                         return -EBUSY;
1007                 }
1008         }
1009         rme96->playback_periodsize =
1010                 params_period_size(params) << rme96->playback_frlog;
1011         snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1012         /* S/PDIF setup */
1013         if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1014                 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1015                 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1016         }
1017         spin_unlock_irq(&rme96->lock);
1018
1019         return 0;
1020 }
1021
1022 static int
1023 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1024                             struct snd_pcm_hw_params *params)
1025 {
1026         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1027         struct snd_pcm_runtime *runtime = substream->runtime;
1028         int err, isadat, rate;
1029
1030         runtime->dma_area = (void __force *)(rme96->iobase +
1031                                              RME96_IO_REC_BUFFER);
1032         runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1033         runtime->dma_bytes = RME96_BUFFER_SIZE;
1034
1035         spin_lock_irq(&rme96->lock);
1036         if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1037                 spin_unlock_irq(&rme96->lock);
1038                 return err;
1039         }
1040         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1041                 if ((err = snd_rme96_capture_analog_setrate(rme96,
1042                                                             params_rate(params))) < 0)
1043                 {
1044                         spin_unlock_irq(&rme96->lock);
1045                         return err;
1046                 }
1047         } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1048                 if ((int)params_rate(params) != rate) {
1049                         spin_unlock_irq(&rme96->lock);
1050                         return -EIO;
1051                 }
1052                 if ((isadat && runtime->hw.channels_min == 2) ||
1053                     (!isadat && runtime->hw.channels_min == 8))
1054                 {
1055                         spin_unlock_irq(&rme96->lock);
1056                         return -EIO;
1057                 }
1058         }
1059         snd_rme96_setframelog(rme96, params_channels(params), 0);
1060         if (rme96->playback_periodsize != 0) {
1061                 if (params_period_size(params) << rme96->capture_frlog !=
1062                     rme96->playback_periodsize)
1063                 {
1064                         spin_unlock_irq(&rme96->lock);
1065                         return -EBUSY;
1066                 }
1067         }
1068         rme96->capture_periodsize =
1069                 params_period_size(params) << rme96->capture_frlog;
1070         snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1071         spin_unlock_irq(&rme96->lock);
1072
1073         return 0;
1074 }
1075
1076 static void
1077 snd_rme96_trigger(struct rme96 *rme96,
1078                   int op)
1079 {
1080         if (op & RME96_TB_RESET_PLAYPOS)
1081                 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1082         if (op & RME96_TB_RESET_CAPTUREPOS)
1083                 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1084         if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) {
1085                 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1086                 if (rme96->rcreg & RME96_RCR_IRQ)
1087                         writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1088         }
1089         if (op & RME96_TB_CLEAR_CAPTURE_IRQ) {
1090                 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1091                 if (rme96->rcreg & RME96_RCR_IRQ_2)
1092                         writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1093         }
1094         if (op & RME96_TB_START_PLAYBACK)
1095                 rme96->wcreg |= RME96_WCR_START;
1096         if (op & RME96_TB_STOP_PLAYBACK)
1097                 rme96->wcreg &= ~RME96_WCR_START;
1098         if (op & RME96_TB_START_CAPTURE)
1099                 rme96->wcreg |= RME96_WCR_START_2;
1100         if (op & RME96_TB_STOP_CAPTURE)
1101                 rme96->wcreg &= ~RME96_WCR_START_2;
1102         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1103 }
1104
1105
1106
1107 static irqreturn_t
1108 snd_rme96_interrupt(int irq,
1109                     void *dev_id)
1110 {
1111         struct rme96 *rme96 = (struct rme96 *)dev_id;
1112
1113         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1114         /* fastpath out, to ease interrupt sharing */
1115         if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1116               (rme96->rcreg & RME96_RCR_IRQ_2)))
1117         {
1118                 return IRQ_NONE;
1119         }
1120
1121         if (rme96->rcreg & RME96_RCR_IRQ) {
1122                 /* playback */
1123                 snd_pcm_period_elapsed(rme96->playback_substream);
1124                 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1125         }
1126         if (rme96->rcreg & RME96_RCR_IRQ_2) {
1127                 /* capture */
1128                 snd_pcm_period_elapsed(rme96->capture_substream);
1129                 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1130         }
1131         return IRQ_HANDLED;
1132 }
1133
1134 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1135
1136 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1137         .count = ARRAY_SIZE(period_bytes),
1138         .list = period_bytes,
1139         .mask = 0
1140 };
1141
1142 static void
1143 rme96_set_buffer_size_constraint(struct rme96 *rme96,
1144                                  struct snd_pcm_runtime *runtime)
1145 {
1146         unsigned int size;
1147
1148         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1149                                      RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1150         if ((size = rme96->playback_periodsize) != 0 ||
1151             (size = rme96->capture_periodsize) != 0)
1152                 snd_pcm_hw_constraint_minmax(runtime,
1153                                              SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1154                                              size, size);
1155         else
1156                 snd_pcm_hw_constraint_list(runtime, 0,
1157                                            SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1158                                            &hw_constraints_period_bytes);
1159 }
1160
1161 static int
1162 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1163 {
1164         int rate, dummy;
1165         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1166         struct snd_pcm_runtime *runtime = substream->runtime;
1167
1168         snd_pcm_set_sync(substream);
1169         spin_lock_irq(&rme96->lock);
1170         if (rme96->playback_substream != NULL) {
1171                 spin_unlock_irq(&rme96->lock);
1172                 return -EBUSY;
1173         }
1174         rme96->wcreg &= ~RME96_WCR_ADAT;
1175         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1176         rme96->playback_substream = substream;
1177         spin_unlock_irq(&rme96->lock);
1178
1179         runtime->hw = snd_rme96_playback_spdif_info;
1180         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1181             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1182             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1183         {
1184                 /* slave clock */
1185                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1186                 runtime->hw.rate_min = rate;
1187                 runtime->hw.rate_max = rate;
1188         }
1189         rme96_set_buffer_size_constraint(rme96, runtime);
1190
1191         rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1192         rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1193         snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1194                        SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1195         return 0;
1196 }
1197
1198 static int
1199 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1200 {
1201         int isadat, rate;
1202         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1203         struct snd_pcm_runtime *runtime = substream->runtime;
1204
1205         snd_pcm_set_sync(substream);
1206         runtime->hw = snd_rme96_capture_spdif_info;
1207         if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1208             (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1209         {
1210                 if (isadat) {
1211                         return -EIO;
1212                 }
1213                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1214                 runtime->hw.rate_min = rate;
1215                 runtime->hw.rate_max = rate;
1216         }
1217
1218         spin_lock_irq(&rme96->lock);
1219         if (rme96->capture_substream != NULL) {
1220                 spin_unlock_irq(&rme96->lock);
1221                 return -EBUSY;
1222         }
1223         rme96->capture_substream = substream;
1224         spin_unlock_irq(&rme96->lock);
1225
1226         rme96_set_buffer_size_constraint(rme96, runtime);
1227         return 0;
1228 }
1229
1230 static int
1231 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1232 {
1233         int rate, dummy;
1234         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1235         struct snd_pcm_runtime *runtime = substream->runtime;
1236
1237         snd_pcm_set_sync(substream);
1238         spin_lock_irq(&rme96->lock);
1239         if (rme96->playback_substream != NULL) {
1240                 spin_unlock_irq(&rme96->lock);
1241                 return -EBUSY;
1242         }
1243         rme96->wcreg |= RME96_WCR_ADAT;
1244         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1245         rme96->playback_substream = substream;
1246         spin_unlock_irq(&rme96->lock);
1247
1248         runtime->hw = snd_rme96_playback_adat_info;
1249         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1250             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1251             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1252         {
1253                 /* slave clock */
1254                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1255                 runtime->hw.rate_min = rate;
1256                 runtime->hw.rate_max = rate;
1257         }
1258         rme96_set_buffer_size_constraint(rme96, runtime);
1259         return 0;
1260 }
1261
1262 static int
1263 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1264 {
1265         int isadat, rate;
1266         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1267         struct snd_pcm_runtime *runtime = substream->runtime;
1268
1269         snd_pcm_set_sync(substream);
1270         runtime->hw = snd_rme96_capture_adat_info;
1271         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1272                 /* makes no sense to use analog input. Note that analog
1273                    expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1274                 return -EIO;
1275         }
1276         if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1277                 if (!isadat) {
1278                         return -EIO;
1279                 }
1280                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1281                 runtime->hw.rate_min = rate;
1282                 runtime->hw.rate_max = rate;
1283         }
1284
1285         spin_lock_irq(&rme96->lock);
1286         if (rme96->capture_substream != NULL) {
1287                 spin_unlock_irq(&rme96->lock);
1288                 return -EBUSY;
1289         }
1290         rme96->capture_substream = substream;
1291         spin_unlock_irq(&rme96->lock);
1292
1293         rme96_set_buffer_size_constraint(rme96, runtime);
1294         return 0;
1295 }
1296
1297 static int
1298 snd_rme96_playback_close(struct snd_pcm_substream *substream)
1299 {
1300         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1301         int spdif = 0;
1302
1303         spin_lock_irq(&rme96->lock);
1304         if (RME96_ISPLAYING(rme96)) {
1305                 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1306         }
1307         rme96->playback_substream = NULL;
1308         rme96->playback_periodsize = 0;
1309         spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1310         spin_unlock_irq(&rme96->lock);
1311         if (spdif) {
1312                 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1313                 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1314                                SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1315         }
1316         return 0;
1317 }
1318
1319 static int
1320 snd_rme96_capture_close(struct snd_pcm_substream *substream)
1321 {
1322         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1323
1324         spin_lock_irq(&rme96->lock);
1325         if (RME96_ISRECORDING(rme96)) {
1326                 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1327         }
1328         rme96->capture_substream = NULL;
1329         rme96->capture_periodsize = 0;
1330         spin_unlock_irq(&rme96->lock);
1331         return 0;
1332 }
1333
1334 static int
1335 snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1336 {
1337         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1338
1339         spin_lock_irq(&rme96->lock);
1340         if (RME96_ISPLAYING(rme96)) {
1341                 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1342         }
1343         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1344         spin_unlock_irq(&rme96->lock);
1345         return 0;
1346 }
1347
1348 static int
1349 snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1350 {
1351         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1352
1353         spin_lock_irq(&rme96->lock);
1354         if (RME96_ISRECORDING(rme96)) {
1355                 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1356         }
1357         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1358         spin_unlock_irq(&rme96->lock);
1359         return 0;
1360 }
1361
1362 static int
1363 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1364                            int cmd)
1365 {
1366         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1367         struct snd_pcm_substream *s;
1368         bool sync;
1369
1370         snd_pcm_group_for_each_entry(s, substream) {
1371                 if (snd_pcm_substream_chip(s) == rme96)
1372                         snd_pcm_trigger_done(s, substream);
1373         }
1374
1375         sync = (rme96->playback_substream && rme96->capture_substream) &&
1376                (rme96->playback_substream->group ==
1377                 rme96->capture_substream->group);
1378
1379         switch (cmd) {
1380         case SNDRV_PCM_TRIGGER_START:
1381                 if (!RME96_ISPLAYING(rme96)) {
1382                         if (substream != rme96->playback_substream)
1383                                 return -EBUSY;
1384                         snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1385                                                  : RME96_START_PLAYBACK);
1386                 }
1387                 break;
1388
1389         case SNDRV_PCM_TRIGGER_STOP:
1390                 if (RME96_ISPLAYING(rme96)) {
1391                         if (substream != rme96->playback_substream)
1392                                 return -EBUSY;
1393                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1394                                                  :  RME96_STOP_PLAYBACK);
1395                 }
1396                 break;
1397
1398         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1399                 if (RME96_ISPLAYING(rme96))
1400                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1401                                                  : RME96_STOP_PLAYBACK);
1402                 break;
1403
1404         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1405                 if (!RME96_ISPLAYING(rme96))
1406                         snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1407                                                  : RME96_RESUME_PLAYBACK);
1408                 break;
1409
1410         default:
1411                 return -EINVAL;
1412         }
1413
1414         return 0;
1415 }
1416
1417 static int
1418 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1419                           int cmd)
1420 {
1421         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1422         struct snd_pcm_substream *s;
1423         bool sync;
1424
1425         snd_pcm_group_for_each_entry(s, substream) {
1426                 if (snd_pcm_substream_chip(s) == rme96)
1427                         snd_pcm_trigger_done(s, substream);
1428         }
1429
1430         sync = (rme96->playback_substream && rme96->capture_substream) &&
1431                (rme96->playback_substream->group ==
1432                 rme96->capture_substream->group);
1433
1434         switch (cmd) {
1435         case SNDRV_PCM_TRIGGER_START:
1436                 if (!RME96_ISRECORDING(rme96)) {
1437                         if (substream != rme96->capture_substream)
1438                                 return -EBUSY;
1439                         snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1440                                                  : RME96_START_CAPTURE);
1441                 }
1442                 break;
1443
1444         case SNDRV_PCM_TRIGGER_STOP:
1445                 if (RME96_ISRECORDING(rme96)) {
1446                         if (substream != rme96->capture_substream)
1447                                 return -EBUSY;
1448                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1449                                                  : RME96_STOP_CAPTURE);
1450                 }
1451                 break;
1452
1453         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1454                 if (RME96_ISRECORDING(rme96))
1455                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1456                                                  : RME96_STOP_CAPTURE);
1457                 break;
1458
1459         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1460                 if (!RME96_ISRECORDING(rme96))
1461                         snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1462                                                  : RME96_RESUME_CAPTURE);
1463                 break;
1464
1465         default:
1466                 return -EINVAL;
1467         }
1468
1469         return 0;
1470 }
1471
1472 static snd_pcm_uframes_t
1473 snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1474 {
1475         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1476         return snd_rme96_playback_ptr(rme96);
1477 }
1478
1479 static snd_pcm_uframes_t
1480 snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1481 {
1482         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1483         return snd_rme96_capture_ptr(rme96);
1484 }
1485
1486 static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1487         .open =         snd_rme96_playback_spdif_open,
1488         .close =        snd_rme96_playback_close,
1489         .ioctl =        snd_pcm_lib_ioctl,
1490         .hw_params =    snd_rme96_playback_hw_params,
1491         .prepare =      snd_rme96_playback_prepare,
1492         .trigger =      snd_rme96_playback_trigger,
1493         .pointer =      snd_rme96_playback_pointer,
1494         .copy =         snd_rme96_playback_copy,
1495         .silence =      snd_rme96_playback_silence,
1496         .mmap =         snd_pcm_lib_mmap_iomem,
1497 };
1498
1499 static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1500         .open =         snd_rme96_capture_spdif_open,
1501         .close =        snd_rme96_capture_close,
1502         .ioctl =        snd_pcm_lib_ioctl,
1503         .hw_params =    snd_rme96_capture_hw_params,
1504         .prepare =      snd_rme96_capture_prepare,
1505         .trigger =      snd_rme96_capture_trigger,
1506         .pointer =      snd_rme96_capture_pointer,
1507         .copy =         snd_rme96_capture_copy,
1508         .mmap =         snd_pcm_lib_mmap_iomem,
1509 };
1510
1511 static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1512         .open =         snd_rme96_playback_adat_open,
1513         .close =        snd_rme96_playback_close,
1514         .ioctl =        snd_pcm_lib_ioctl,
1515         .hw_params =    snd_rme96_playback_hw_params,
1516         .prepare =      snd_rme96_playback_prepare,
1517         .trigger =      snd_rme96_playback_trigger,
1518         .pointer =      snd_rme96_playback_pointer,
1519         .copy =         snd_rme96_playback_copy,
1520         .silence =      snd_rme96_playback_silence,
1521         .mmap =         snd_pcm_lib_mmap_iomem,
1522 };
1523
1524 static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1525         .open =         snd_rme96_capture_adat_open,
1526         .close =        snd_rme96_capture_close,
1527         .ioctl =        snd_pcm_lib_ioctl,
1528         .hw_params =    snd_rme96_capture_hw_params,
1529         .prepare =      snd_rme96_capture_prepare,
1530         .trigger =      snd_rme96_capture_trigger,
1531         .pointer =      snd_rme96_capture_pointer,
1532         .copy =         snd_rme96_capture_copy,
1533         .mmap =         snd_pcm_lib_mmap_iomem,
1534 };
1535
1536 static void
1537 snd_rme96_free(void *private_data)
1538 {
1539         struct rme96 *rme96 = (struct rme96 *)private_data;
1540
1541         if (rme96 == NULL) {
1542                 return;
1543         }
1544         if (rme96->irq >= 0) {
1545                 snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1546                 rme96->areg &= ~RME96_AR_DAC_EN;
1547                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1548                 free_irq(rme96->irq, (void *)rme96);
1549                 rme96->irq = -1;
1550         }
1551         if (rme96->iobase) {
1552                 iounmap(rme96->iobase);
1553                 rme96->iobase = NULL;
1554         }
1555         if (rme96->port) {
1556                 pci_release_regions(rme96->pci);
1557                 rme96->port = 0;
1558         }
1559         pci_disable_device(rme96->pci);
1560 }
1561
1562 static void
1563 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1564 {
1565         struct rme96 *rme96 = pcm->private_data;
1566         rme96->spdif_pcm = NULL;
1567 }
1568
1569 static void
1570 snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1571 {
1572         struct rme96 *rme96 = pcm->private_data;
1573         rme96->adat_pcm = NULL;
1574 }
1575
1576 static int
1577 snd_rme96_create(struct rme96 *rme96)
1578 {
1579         struct pci_dev *pci = rme96->pci;
1580         int err;
1581
1582         rme96->irq = -1;
1583         spin_lock_init(&rme96->lock);
1584
1585         if ((err = pci_enable_device(pci)) < 0)
1586                 return err;
1587
1588         if ((err = pci_request_regions(pci, "RME96")) < 0)
1589                 return err;
1590         rme96->port = pci_resource_start(rme96->pci, 0);
1591
1592         rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE);
1593         if (!rme96->iobase) {
1594                 snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1595                 return -ENOMEM;
1596         }
1597
1598         if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
1599                         KBUILD_MODNAME, rme96)) {
1600                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1601                 return -EBUSY;
1602         }
1603         rme96->irq = pci->irq;
1604
1605         /* read the card's revision number */
1606         pci_read_config_byte(pci, 8, &rme96->rev);
1607
1608         /* set up ALSA pcm device for S/PDIF */
1609         if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1610                                1, 1, &rme96->spdif_pcm)) < 0)
1611         {
1612                 return err;
1613         }
1614         rme96->spdif_pcm->private_data = rme96;
1615         rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1616         strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1617         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1618         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1619
1620         rme96->spdif_pcm->info_flags = 0;
1621
1622         /* set up ALSA pcm device for ADAT */
1623         if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1624                 /* ADAT is not available on the base model */
1625                 rme96->adat_pcm = NULL;
1626         } else {
1627                 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1628                                        1, 1, &rme96->adat_pcm)) < 0)
1629                 {
1630                         return err;
1631                 }
1632                 rme96->adat_pcm->private_data = rme96;
1633                 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1634                 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1635                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1636                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1637
1638                 rme96->adat_pcm->info_flags = 0;
1639         }
1640
1641         rme96->playback_periodsize = 0;
1642         rme96->capture_periodsize = 0;
1643
1644         /* make sure playback/capture is stopped, if by some reason active */
1645         snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1646
1647         /* set default values in registers */
1648         rme96->wcreg =
1649                 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1650                 RME96_WCR_SEL |    /* normal playback */
1651                 RME96_WCR_MASTER | /* set to master clock mode */
1652                 RME96_WCR_INP_0;   /* set coaxial input */
1653
1654         rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1655
1656         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1657         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1658
1659         /* reset the ADC */
1660         writel(rme96->areg | RME96_AR_PD2,
1661                rme96->iobase + RME96_IO_ADDITIONAL_REG);
1662         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1663
1664         /* reset and enable the DAC (order is important). */
1665         snd_rme96_reset_dac(rme96);
1666         rme96->areg |= RME96_AR_DAC_EN;
1667         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1668
1669         /* reset playback and record buffer pointers */
1670         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1671         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1672
1673         /* reset volume */
1674         rme96->vol[0] = rme96->vol[1] = 0;
1675         if (RME96_HAS_ANALOG_OUT(rme96)) {
1676                 snd_rme96_apply_dac_volume(rme96);
1677         }
1678
1679         /* init switch interface */
1680         if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1681                 return err;
1682         }
1683
1684         /* init proc interface */
1685         snd_rme96_proc_init(rme96);
1686
1687         return 0;
1688 }
1689
1690 /*
1691  * proc interface
1692  */
1693
1694 static void
1695 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1696 {
1697         int n;
1698         struct rme96 *rme96 = entry->private_data;
1699
1700         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1701
1702         snd_iprintf(buffer, rme96->card->longname);
1703         snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1704
1705         snd_iprintf(buffer, "\nGeneral settings\n");
1706         if (rme96->wcreg & RME96_WCR_IDIS) {
1707                 snd_iprintf(buffer, "  period size: N/A (interrupts "
1708                             "disabled)\n");
1709         } else if (rme96->wcreg & RME96_WCR_ISEL) {
1710                 snd_iprintf(buffer, "  period size: 2048 bytes\n");
1711         } else {
1712                 snd_iprintf(buffer, "  period size: 8192 bytes\n");
1713         }
1714         snd_iprintf(buffer, "\nInput settings\n");
1715         switch (snd_rme96_getinputtype(rme96)) {
1716         case RME96_INPUT_OPTICAL:
1717                 snd_iprintf(buffer, "  input: optical");
1718                 break;
1719         case RME96_INPUT_COAXIAL:
1720                 snd_iprintf(buffer, "  input: coaxial");
1721                 break;
1722         case RME96_INPUT_INTERNAL:
1723                 snd_iprintf(buffer, "  input: internal");
1724                 break;
1725         case RME96_INPUT_XLR:
1726                 snd_iprintf(buffer, "  input: XLR");
1727                 break;
1728         case RME96_INPUT_ANALOG:
1729                 snd_iprintf(buffer, "  input: analog");
1730                 break;
1731         }
1732         if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1733                 snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1734         } else {
1735                 if (n) {
1736                         snd_iprintf(buffer, " (8 channels)\n");
1737                 } else {
1738                         snd_iprintf(buffer, " (2 channels)\n");
1739                 }
1740                 snd_iprintf(buffer, "  sample rate: %d Hz\n",
1741                             snd_rme96_capture_getrate(rme96, &n));
1742         }
1743         if (rme96->wcreg & RME96_WCR_MODE24_2) {
1744                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1745         } else {
1746                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1747         }
1748
1749         snd_iprintf(buffer, "\nOutput settings\n");
1750         if (rme96->wcreg & RME96_WCR_SEL) {
1751                 snd_iprintf(buffer, "  output signal: normal playback\n");
1752         } else {
1753                 snd_iprintf(buffer, "  output signal: same as input\n");
1754         }
1755         snd_iprintf(buffer, "  sample rate: %d Hz\n",
1756                     snd_rme96_playback_getrate(rme96));
1757         if (rme96->wcreg & RME96_WCR_MODE24) {
1758                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1759         } else {
1760                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1761         }
1762         if (rme96->areg & RME96_AR_WSEL) {
1763                 snd_iprintf(buffer, "  sample clock source: word clock\n");
1764         } else if (rme96->wcreg & RME96_WCR_MASTER) {
1765                 snd_iprintf(buffer, "  sample clock source: internal\n");
1766         } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1767                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to analog input setting)\n");
1768         } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1769                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to no valid signal)\n");
1770         } else {
1771                 snd_iprintf(buffer, "  sample clock source: autosync\n");
1772         }
1773         if (rme96->wcreg & RME96_WCR_PRO) {
1774                 snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1775         } else {
1776                 snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1777         }
1778         if (rme96->wcreg & RME96_WCR_EMP) {
1779                 snd_iprintf(buffer, "  emphasis: on\n");
1780         } else {
1781                 snd_iprintf(buffer, "  emphasis: off\n");
1782         }
1783         if (rme96->wcreg & RME96_WCR_DOLBY) {
1784                 snd_iprintf(buffer, "  non-audio (dolby): on\n");
1785         } else {
1786                 snd_iprintf(buffer, "  non-audio (dolby): off\n");
1787         }
1788         if (RME96_HAS_ANALOG_IN(rme96)) {
1789                 snd_iprintf(buffer, "\nAnalog output settings\n");
1790                 switch (snd_rme96_getmontracks(rme96)) {
1791                 case RME96_MONITOR_TRACKS_1_2:
1792                         snd_iprintf(buffer, "  monitored ADAT tracks: 1+2\n");
1793                         break;
1794                 case RME96_MONITOR_TRACKS_3_4:
1795                         snd_iprintf(buffer, "  monitored ADAT tracks: 3+4\n");
1796                         break;
1797                 case RME96_MONITOR_TRACKS_5_6:
1798                         snd_iprintf(buffer, "  monitored ADAT tracks: 5+6\n");
1799                         break;
1800                 case RME96_MONITOR_TRACKS_7_8:
1801                         snd_iprintf(buffer, "  monitored ADAT tracks: 7+8\n");
1802                         break;
1803                 }
1804                 switch (snd_rme96_getattenuation(rme96)) {
1805                 case RME96_ATTENUATION_0:
1806                         snd_iprintf(buffer, "  attenuation: 0 dB\n");
1807                         break;
1808                 case RME96_ATTENUATION_6:
1809                         snd_iprintf(buffer, "  attenuation: -6 dB\n");
1810                         break;
1811                 case RME96_ATTENUATION_12:
1812                         snd_iprintf(buffer, "  attenuation: -12 dB\n");
1813                         break;
1814                 case RME96_ATTENUATION_18:
1815                         snd_iprintf(buffer, "  attenuation: -18 dB\n");
1816                         break;
1817                 }
1818                 snd_iprintf(buffer, "  volume left: %u\n", rme96->vol[0]);
1819                 snd_iprintf(buffer, "  volume right: %u\n", rme96->vol[1]);
1820         }
1821 }
1822
1823 static void snd_rme96_proc_init(struct rme96 *rme96)
1824 {
1825         struct snd_info_entry *entry;
1826
1827         if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1828                 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
1829 }
1830
1831 /*
1832  * control interface
1833  */
1834
1835 #define snd_rme96_info_loopback_control         snd_ctl_boolean_mono_info
1836
1837 static int
1838 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1839 {
1840         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1841
1842         spin_lock_irq(&rme96->lock);
1843         ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1844         spin_unlock_irq(&rme96->lock);
1845         return 0;
1846 }
1847 static int
1848 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1849 {
1850         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1851         unsigned int val;
1852         int change;
1853
1854         val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1855         spin_lock_irq(&rme96->lock);
1856         val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1857         change = val != rme96->wcreg;
1858         rme96->wcreg = val;
1859         writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1860         spin_unlock_irq(&rme96->lock);
1861         return change;
1862 }
1863
1864 static int
1865 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1866 {
1867         static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1868         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1869         char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1870
1871         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1872         uinfo->count = 1;
1873         switch (rme96->pci->device) {
1874         case PCI_DEVICE_ID_RME_DIGI96:
1875         case PCI_DEVICE_ID_RME_DIGI96_8:
1876                 uinfo->value.enumerated.items = 3;
1877                 break;
1878         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1879                 uinfo->value.enumerated.items = 4;
1880                 break;
1881         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1882                 if (rme96->rev > 4) {
1883                         /* PST */
1884                         uinfo->value.enumerated.items = 4;
1885                         texts[3] = _texts[4]; /* Analog instead of XLR */
1886                 } else {
1887                         /* PAD */
1888                         uinfo->value.enumerated.items = 5;
1889                 }
1890                 break;
1891         default:
1892                 snd_BUG();
1893                 break;
1894         }
1895         if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1896                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1897         }
1898         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1899         return 0;
1900 }
1901 static int
1902 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1903 {
1904         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1905         unsigned int items = 3;
1906
1907         spin_lock_irq(&rme96->lock);
1908         ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1909
1910         switch (rme96->pci->device) {
1911         case PCI_DEVICE_ID_RME_DIGI96:
1912         case PCI_DEVICE_ID_RME_DIGI96_8:
1913                 items = 3;
1914                 break;
1915         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1916                 items = 4;
1917                 break;
1918         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1919                 if (rme96->rev > 4) {
1920                         /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1921                         if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1922                                 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1923                         }
1924                         items = 4;
1925                 } else {
1926                         items = 5;
1927                 }
1928                 break;
1929         default:
1930                 snd_BUG();
1931                 break;
1932         }
1933         if (ucontrol->value.enumerated.item[0] >= items) {
1934                 ucontrol->value.enumerated.item[0] = items - 1;
1935         }
1936
1937         spin_unlock_irq(&rme96->lock);
1938         return 0;
1939 }
1940 static int
1941 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1942 {
1943         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1944         unsigned int val;
1945         int change, items = 3;
1946
1947         switch (rme96->pci->device) {
1948         case PCI_DEVICE_ID_RME_DIGI96:
1949         case PCI_DEVICE_ID_RME_DIGI96_8:
1950                 items = 3;
1951                 break;
1952         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1953                 items = 4;
1954                 break;
1955         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1956                 if (rme96->rev > 4) {
1957                         items = 4;
1958                 } else {
1959                         items = 5;
1960                 }
1961                 break;
1962         default:
1963                 snd_BUG();
1964                 break;
1965         }
1966         val = ucontrol->value.enumerated.item[0] % items;
1967
1968         /* special case for PST */
1969         if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1970                 if (val == RME96_INPUT_XLR) {
1971                         val = RME96_INPUT_ANALOG;
1972                 }
1973         }
1974
1975         spin_lock_irq(&rme96->lock);
1976         change = (int)val != snd_rme96_getinputtype(rme96);
1977         snd_rme96_setinputtype(rme96, val);
1978         spin_unlock_irq(&rme96->lock);
1979         return change;
1980 }
1981
1982 static int
1983 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1984 {
1985         static char *texts[3] = { "AutoSync", "Internal", "Word" };
1986
1987         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1988         uinfo->count = 1;
1989         uinfo->value.enumerated.items = 3;
1990         if (uinfo->value.enumerated.item > 2) {
1991                 uinfo->value.enumerated.item = 2;
1992         }
1993         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1994         return 0;
1995 }
1996 static int
1997 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1998 {
1999         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2000
2001         spin_lock_irq(&rme96->lock);
2002         ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2003         spin_unlock_irq(&rme96->lock);
2004         return 0;
2005 }
2006 static int
2007 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2008 {
2009         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2010         unsigned int val;
2011         int change;
2012
2013         val = ucontrol->value.enumerated.item[0] % 3;
2014         spin_lock_irq(&rme96->lock);
2015         change = (int)val != snd_rme96_getclockmode(rme96);
2016         snd_rme96_setclockmode(rme96, val);
2017         spin_unlock_irq(&rme96->lock);
2018         return change;
2019 }
2020
2021 static int
2022 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2023 {
2024         static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2025
2026         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2027         uinfo->count = 1;
2028         uinfo->value.enumerated.items = 4;
2029         if (uinfo->value.enumerated.item > 3) {
2030                 uinfo->value.enumerated.item = 3;
2031         }
2032         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2033         return 0;
2034 }
2035 static int
2036 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2037 {
2038         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2039
2040         spin_lock_irq(&rme96->lock);
2041         ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2042         spin_unlock_irq(&rme96->lock);
2043         return 0;
2044 }
2045 static int
2046 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2047 {
2048         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2049         unsigned int val;
2050         int change;
2051
2052         val = ucontrol->value.enumerated.item[0] % 4;
2053         spin_lock_irq(&rme96->lock);
2054
2055         change = (int)val != snd_rme96_getattenuation(rme96);
2056         snd_rme96_setattenuation(rme96, val);
2057         spin_unlock_irq(&rme96->lock);
2058         return change;
2059 }
2060
2061 static int
2062 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2063 {
2064         static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2065
2066         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2067         uinfo->count = 1;
2068         uinfo->value.enumerated.items = 4;
2069         if (uinfo->value.enumerated.item > 3) {
2070                 uinfo->value.enumerated.item = 3;
2071         }
2072         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2073         return 0;
2074 }
2075 static int
2076 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2077 {
2078         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2079
2080         spin_lock_irq(&rme96->lock);
2081         ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2082         spin_unlock_irq(&rme96->lock);
2083         return 0;
2084 }
2085 static int
2086 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2087 {
2088         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2089         unsigned int val;
2090         int change;
2091
2092         val = ucontrol->value.enumerated.item[0] % 4;
2093         spin_lock_irq(&rme96->lock);
2094         change = (int)val != snd_rme96_getmontracks(rme96);
2095         snd_rme96_setmontracks(rme96, val);
2096         spin_unlock_irq(&rme96->lock);
2097         return change;
2098 }
2099
2100 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
2101 {
2102         u32 val = 0;
2103         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2104         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2105         if (val & RME96_WCR_PRO)
2106                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2107         else
2108                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2109         return val;
2110 }
2111
2112 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
2113 {
2114         aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2115                          ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2116         if (val & RME96_WCR_PRO)
2117                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2118         else
2119                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2120 }
2121
2122 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2123 {
2124         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2125         uinfo->count = 1;
2126         return 0;
2127 }
2128
2129 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2130 {
2131         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2132
2133         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2134         return 0;
2135 }
2136
2137 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2138 {
2139         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2140         int change;
2141         u32 val;
2142
2143         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2144         spin_lock_irq(&rme96->lock);
2145         change = val != rme96->wcreg_spdif;
2146         rme96->wcreg_spdif = val;
2147         spin_unlock_irq(&rme96->lock);
2148         return change;
2149 }
2150
2151 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2152 {
2153         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2154         uinfo->count = 1;
2155         return 0;
2156 }
2157
2158 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2159 {
2160         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2161
2162         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2163         return 0;
2164 }
2165
2166 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2167 {
2168         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2169         int change;
2170         u32 val;
2171
2172         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2173         spin_lock_irq(&rme96->lock);
2174         change = val != rme96->wcreg_spdif_stream;
2175         rme96->wcreg_spdif_stream = val;
2176         rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2177         rme96->wcreg |= val;
2178         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2179         spin_unlock_irq(&rme96->lock);
2180         return change;
2181 }
2182
2183 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2184 {
2185         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2186         uinfo->count = 1;
2187         return 0;
2188 }
2189
2190 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2191 {
2192         ucontrol->value.iec958.status[0] = kcontrol->private_value;
2193         return 0;
2194 }
2195
2196 static int
2197 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2198 {
2199         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2200
2201         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2202         uinfo->count = 2;
2203         uinfo->value.integer.min = 0;
2204         uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2205         return 0;
2206 }
2207
2208 static int
2209 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2210 {
2211         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2212
2213         spin_lock_irq(&rme96->lock);
2214         u->value.integer.value[0] = rme96->vol[0];
2215         u->value.integer.value[1] = rme96->vol[1];
2216         spin_unlock_irq(&rme96->lock);
2217
2218         return 0;
2219 }
2220
2221 static int
2222 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2223 {
2224         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2225         int change = 0;
2226         unsigned int vol, maxvol;
2227
2228
2229         if (!RME96_HAS_ANALOG_OUT(rme96))
2230                 return -EINVAL;
2231         maxvol = RME96_185X_MAX_OUT(rme96);
2232         spin_lock_irq(&rme96->lock);
2233         vol = u->value.integer.value[0];
2234         if (vol != rme96->vol[0] && vol <= maxvol) {
2235                 rme96->vol[0] = vol;
2236                 change = 1;
2237         }
2238         vol = u->value.integer.value[1];
2239         if (vol != rme96->vol[1] && vol <= maxvol) {
2240                 rme96->vol[1] = vol;
2241                 change = 1;
2242         }
2243         if (change)
2244                 snd_rme96_apply_dac_volume(rme96);
2245         spin_unlock_irq(&rme96->lock);
2246
2247         return change;
2248 }
2249
2250 static struct snd_kcontrol_new snd_rme96_controls[] = {
2251 {
2252         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2253         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2254         .info =         snd_rme96_control_spdif_info,
2255         .get =          snd_rme96_control_spdif_get,
2256         .put =          snd_rme96_control_spdif_put
2257 },
2258 {
2259         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2260         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2261         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2262         .info =         snd_rme96_control_spdif_stream_info,
2263         .get =          snd_rme96_control_spdif_stream_get,
2264         .put =          snd_rme96_control_spdif_stream_put
2265 },
2266 {
2267         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2268         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2269         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2270         .info =         snd_rme96_control_spdif_mask_info,
2271         .get =          snd_rme96_control_spdif_mask_get,
2272         .private_value = IEC958_AES0_NONAUDIO |
2273                         IEC958_AES0_PROFESSIONAL |
2274                         IEC958_AES0_CON_EMPHASIS
2275 },
2276 {
2277         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2278         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2279         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2280         .info =         snd_rme96_control_spdif_mask_info,
2281         .get =          snd_rme96_control_spdif_mask_get,
2282         .private_value = IEC958_AES0_NONAUDIO |
2283                         IEC958_AES0_PROFESSIONAL |
2284                         IEC958_AES0_PRO_EMPHASIS
2285 },
2286 {
2287         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2288         .name =         "Input Connector",
2289         .info =         snd_rme96_info_inputtype_control,
2290         .get =          snd_rme96_get_inputtype_control,
2291         .put =          snd_rme96_put_inputtype_control
2292 },
2293 {
2294         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2295         .name =         "Loopback Input",
2296         .info =         snd_rme96_info_loopback_control,
2297         .get =          snd_rme96_get_loopback_control,
2298         .put =          snd_rme96_put_loopback_control
2299 },
2300 {
2301         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2302         .name =         "Sample Clock Source",
2303         .info =         snd_rme96_info_clockmode_control,
2304         .get =          snd_rme96_get_clockmode_control,
2305         .put =          snd_rme96_put_clockmode_control
2306 },
2307 {
2308         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2309         .name =         "Monitor Tracks",
2310         .info =         snd_rme96_info_montracks_control,
2311         .get =          snd_rme96_get_montracks_control,
2312         .put =          snd_rme96_put_montracks_control
2313 },
2314 {
2315         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2316         .name =         "Attenuation",
2317         .info =         snd_rme96_info_attenuation_control,
2318         .get =          snd_rme96_get_attenuation_control,
2319         .put =          snd_rme96_put_attenuation_control
2320 },
2321 {
2322         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2323         .name =         "DAC Playback Volume",
2324         .info =         snd_rme96_dac_volume_info,
2325         .get =          snd_rme96_dac_volume_get,
2326         .put =          snd_rme96_dac_volume_put
2327 }
2328 };
2329
2330 static int
2331 snd_rme96_create_switches(struct snd_card *card,
2332                           struct rme96 *rme96)
2333 {
2334         int idx, err;
2335         struct snd_kcontrol *kctl;
2336
2337         for (idx = 0; idx < 7; idx++) {
2338                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2339                         return err;
2340                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
2341                         rme96->spdif_ctl = kctl;
2342         }
2343
2344         if (RME96_HAS_ANALOG_OUT(rme96)) {
2345                 for (idx = 7; idx < 10; idx++)
2346                         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2347                                 return err;
2348         }
2349
2350         return 0;
2351 }
2352
2353 /*
2354  * Card initialisation
2355  */
2356
2357 static void snd_rme96_card_free(struct snd_card *card)
2358 {
2359         snd_rme96_free(card->private_data);
2360 }
2361
2362 static int
2363 snd_rme96_probe(struct pci_dev *pci,
2364                 const struct pci_device_id *pci_id)
2365 {
2366         static int dev;
2367         struct rme96 *rme96;
2368         struct snd_card *card;
2369         int err;
2370         u8 val;
2371
2372         if (dev >= SNDRV_CARDS) {
2373                 return -ENODEV;
2374         }
2375         if (!enable[dev]) {
2376                 dev++;
2377                 return -ENOENT;
2378         }
2379         err = snd_card_create(index[dev], id[dev], THIS_MODULE,
2380                               sizeof(struct rme96), &card);
2381         if (err < 0)
2382                 return err;
2383         card->private_free = snd_rme96_card_free;
2384         rme96 = card->private_data;
2385         rme96->card = card;
2386         rme96->pci = pci;
2387         snd_card_set_dev(card, &pci->dev);
2388         if ((err = snd_rme96_create(rme96)) < 0) {
2389                 snd_card_free(card);
2390                 return err;
2391         }
2392
2393         strcpy(card->driver, "Digi96");
2394         switch (rme96->pci->device) {
2395         case PCI_DEVICE_ID_RME_DIGI96:
2396                 strcpy(card->shortname, "RME Digi96");
2397                 break;
2398         case PCI_DEVICE_ID_RME_DIGI96_8:
2399                 strcpy(card->shortname, "RME Digi96/8");
2400                 break;
2401         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
2402                 strcpy(card->shortname, "RME Digi96/8 PRO");
2403                 break;
2404         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
2405                 pci_read_config_byte(rme96->pci, 8, &val);
2406                 if (val < 5) {
2407                         strcpy(card->shortname, "RME Digi96/8 PAD");
2408                 } else {
2409                         strcpy(card->shortname, "RME Digi96/8 PST");
2410                 }
2411                 break;
2412         }
2413         sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2414                 rme96->port, rme96->irq);
2415
2416         if ((err = snd_card_register(card)) < 0) {
2417                 snd_card_free(card);
2418                 return err;
2419         }
2420         pci_set_drvdata(pci, card);
2421         dev++;
2422         return 0;
2423 }
2424
2425 static void snd_rme96_remove(struct pci_dev *pci)
2426 {
2427         snd_card_free(pci_get_drvdata(pci));
2428 }
2429
2430 static struct pci_driver rme96_driver = {
2431         .name = KBUILD_MODNAME,
2432         .id_table = snd_rme96_ids,
2433         .probe = snd_rme96_probe,
2434         .remove = snd_rme96_remove,
2435 };
2436
2437 module_pci_driver(rme96_driver);