sound/pci/rme96.c

   1 /*
   2  *   ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
   3  *   interfaces
   4  *
   5  *      Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
   6  *
   7  *      Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
   8  *      code.
   9  *
  10  *   This program is free software; you can redistribute it and/or modify
  11  *   it under the terms of the GNU General Public License as published by
  12  *   the Free Software Foundation; either version 2 of the License, or
  13  *   (at your option) any later version.
  14  *
  15  *   This program is distributed in the hope that it will be useful,
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *   GNU General Public License for more details.
  19  *
  20  *   You should have received a copy of the GNU General Public License
  21  *   along with this program; if not, write to the Free Software
  22  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/module.h>
  31
  32 #include <sound/core.h>
  33 #include <sound/info.h>
  34 #include <sound/control.h>
  35 #include <sound/pcm.h>
  36 #include <sound/pcm_params.h>
  37 #include <sound/asoundef.h>
  38 #include <sound/initval.h>
  39
  40 #include <asm/io.h>
  41
  42 /* note, two last pcis should be equal, it is not a bug */
  43
  44 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
  45 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
  46                    "Digi96/8 PAD");
  47 MODULE_LICENSE("GPL");
  48 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
  49                 "{RME,Digi96/8},"
  50                 "{RME,Digi96/8 PRO},"
  51                 "{RME,Digi96/8 PST},"
  52                 "{RME,Digi96/8 PAD}}");
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  56 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
  57
  58 module_param_array(index, int, NULL, 0444);
  59 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
  60 module_param_array(id, charp, NULL, 0444);
  61 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
  62 module_param_array(enable, bool, NULL, 0444);
  63 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
  64
  65 /*
  66  * Defines for RME Digi96 series, from internal RME reference documents
  67  * dated 12.01.00
  68  */
  69
  70 #define RME96_SPDIF_NCHANNELS 2
  71
  72 /* Playback and capture buffer size */
  73 #define RME96_BUFFER_SIZE 0x10000
  74
  75 /* IO area size */
  76 #define RME96_IO_SIZE 0x60000
  77
  78 /* IO area offsets */
  79 #define RME96_IO_PLAY_BUFFER      0x0
  80 #define RME96_IO_REC_BUFFER       0x10000
  81 #define RME96_IO_CONTROL_REGISTER 0x20000
  82 #define RME96_IO_ADDITIONAL_REG   0x20004
  83 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
  84 #define RME96_IO_CONFIRM_REC_IRQ  0x2000C
  85 #define RME96_IO_SET_PLAY_POS     0x40000
  86 #define RME96_IO_RESET_PLAY_POS   0x4FFFC
  87 #define RME96_IO_SET_REC_POS      0x50000
  88 #define RME96_IO_RESET_REC_POS    0x5FFFC
  89 #define RME96_IO_GET_PLAY_POS     0x20000
  90 #define RME96_IO_GET_REC_POS      0x30000
  91
  92 /* Write control register bits */
  93 #define RME96_WCR_START     (1 << 0)
  94 #define RME96_WCR_START_2   (1 << 1)
  95 #define RME96_WCR_GAIN_0    (1 << 2)
  96 #define RME96_WCR_GAIN_1    (1 << 3)
  97 #define RME96_WCR_MODE24    (1 << 4)
  98 #define RME96_WCR_MODE24_2  (1 << 5)
  99 #define RME96_WCR_BM        (1 << 6)
 100 #define RME96_WCR_BM_2      (1 << 7)
 101 #define RME96_WCR_ADAT      (1 << 8)
 102 #define RME96_WCR_FREQ_0    (1 << 9)
 103 #define RME96_WCR_FREQ_1    (1 << 10)
 104 #define RME96_WCR_DS        (1 << 11)
 105 #define RME96_WCR_PRO       (1 << 12)
 106 #define RME96_WCR_EMP       (1 << 13)
 107 #define RME96_WCR_SEL       (1 << 14)
 108 #define RME96_WCR_MASTER    (1 << 15)
 109 #define RME96_WCR_PD        (1 << 16)
 110 #define RME96_WCR_INP_0     (1 << 17)
 111 #define RME96_WCR_INP_1     (1 << 18)
 112 #define RME96_WCR_THRU_0    (1 << 19)
 113 #define RME96_WCR_THRU_1    (1 << 20)
 114 #define RME96_WCR_THRU_2    (1 << 21)
 115 #define RME96_WCR_THRU_3    (1 << 22)
 116 #define RME96_WCR_THRU_4    (1 << 23)
 117 #define RME96_WCR_THRU_5    (1 << 24)
 118 #define RME96_WCR_THRU_6    (1 << 25)
 119 #define RME96_WCR_THRU_7    (1 << 26)
 120 #define RME96_WCR_DOLBY     (1 << 27)
 121 #define RME96_WCR_MONITOR_0 (1 << 28)
 122 #define RME96_WCR_MONITOR_1 (1 << 29)
 123 #define RME96_WCR_ISEL      (1 << 30)
 124 #define RME96_WCR_IDIS      (1 << 31)
 125
 126 #define RME96_WCR_BITPOS_GAIN_0 2
 127 #define RME96_WCR_BITPOS_GAIN_1 3
 128 #define RME96_WCR_BITPOS_FREQ_0 9
 129 #define RME96_WCR_BITPOS_FREQ_1 10
 130 #define RME96_WCR_BITPOS_INP_0 17
 131 #define RME96_WCR_BITPOS_INP_1 18
 132 #define RME96_WCR_BITPOS_MONITOR_0 28
 133 #define RME96_WCR_BITPOS_MONITOR_1 29
 134
 135 /* Read control register bits */
 136 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
 137 #define RME96_RCR_IRQ_2     (1 << 16)
 138 #define RME96_RCR_T_OUT     (1 << 17)
 139 #define RME96_RCR_DEV_ID_0  (1 << 21)
 140 #define RME96_RCR_DEV_ID_1  (1 << 22)
 141 #define RME96_RCR_LOCK      (1 << 23)
 142 #define RME96_RCR_VERF      (1 << 26)
 143 #define RME96_RCR_F0        (1 << 27)
 144 #define RME96_RCR_F1        (1 << 28)
 145 #define RME96_RCR_F2        (1 << 29)
 146 #define RME96_RCR_AUTOSYNC  (1 << 30)
 147 #define RME96_RCR_IRQ       (1 << 31)
 148
 149 #define RME96_RCR_BITPOS_F0 27
 150 #define RME96_RCR_BITPOS_F1 28
 151 #define RME96_RCR_BITPOS_F2 29
 152
 153 /* Additional register bits */
 154 #define RME96_AR_WSEL       (1 << 0)
 155 #define RME96_AR_ANALOG     (1 << 1)
 156 #define RME96_AR_FREQPAD_0  (1 << 2)
 157 #define RME96_AR_FREQPAD_1  (1 << 3)
 158 #define RME96_AR_FREQPAD_2  (1 << 4)
 159 #define RME96_AR_PD2        (1 << 5)
 160 #define RME96_AR_DAC_EN     (1 << 6)
 161 #define RME96_AR_CLATCH     (1 << 7)
 162 #define RME96_AR_CCLK       (1 << 8)
 163 #define RME96_AR_CDATA      (1 << 9)
 164
 165 #define RME96_AR_BITPOS_F0 2
 166 #define RME96_AR_BITPOS_F1 3
 167 #define RME96_AR_BITPOS_F2 4
 168
 169 /* Monitor tracks */
 170 #define RME96_MONITOR_TRACKS_1_2 0
 171 #define RME96_MONITOR_TRACKS_3_4 1
 172 #define RME96_MONITOR_TRACKS_5_6 2
 173 #define RME96_MONITOR_TRACKS_7_8 3
 174
 175 /* Attenuation */
 176 #define RME96_ATTENUATION_0 0
 177 #define RME96_ATTENUATION_6 1
 178 #define RME96_ATTENUATION_12 2
 179 #define RME96_ATTENUATION_18 3
 180
 181 /* Input types */
 182 #define RME96_INPUT_OPTICAL 0
 183 #define RME96_INPUT_COAXIAL 1
 184 #define RME96_INPUT_INTERNAL 2
 185 #define RME96_INPUT_XLR 3
 186 #define RME96_INPUT_ANALOG 4
 187
 188 /* Clock modes */
 189 #define RME96_CLOCKMODE_SLAVE 0
 190 #define RME96_CLOCKMODE_MASTER 1
 191 #define RME96_CLOCKMODE_WORDCLOCK 2
 192
 193 /* Block sizes in bytes */
 194 #define RME96_SMALL_BLOCK_SIZE 2048
 195 #define RME96_LARGE_BLOCK_SIZE 8192
 196
 197 /* Volume control */
 198 #define RME96_AD1852_VOL_BITS 14
 199 #define RME96_AD1855_VOL_BITS 10
 200
 201 /* Defines for snd_rme96_trigger */
 202 #define RME96_TB_START_PLAYBACK 1
 203 #define RME96_TB_START_CAPTURE 2
 204 #define RME96_TB_STOP_PLAYBACK 4
 205 #define RME96_TB_STOP_CAPTURE 8
 206 #define RME96_TB_RESET_PLAYPOS 16
 207 #define RME96_TB_RESET_CAPTUREPOS 32
 208 #define RME96_TB_CLEAR_PLAYBACK_IRQ 64
 209 #define RME96_TB_CLEAR_CAPTURE_IRQ 128
 210 #define RME96_RESUME_PLAYBACK   (RME96_TB_START_PLAYBACK)
 211 #define RME96_RESUME_CAPTURE    (RME96_TB_START_CAPTURE)
 212 #define RME96_RESUME_BOTH       (RME96_RESUME_PLAYBACK \
 213                                 | RME96_RESUME_CAPTURE)
 214 #define RME96_START_PLAYBACK    (RME96_TB_START_PLAYBACK \
 215                                 | RME96_TB_RESET_PLAYPOS)
 216 #define RME96_START_CAPTURE     (RME96_TB_START_CAPTURE \
 217                                 | RME96_TB_RESET_CAPTUREPOS)
 218 #define RME96_START_BOTH        (RME96_START_PLAYBACK \
 219                                 | RME96_START_CAPTURE)
 220 #define RME96_STOP_PLAYBACK     (RME96_TB_STOP_PLAYBACK \
 221                                 | RME96_TB_CLEAR_PLAYBACK_IRQ)
 222 #define RME96_STOP_CAPTURE      (RME96_TB_STOP_CAPTURE \
 223                                 | RME96_TB_CLEAR_CAPTURE_IRQ)
 224 #define RME96_STOP_BOTH         (RME96_STOP_PLAYBACK \
 225                                 | RME96_STOP_CAPTURE)
 226
 227 struct rme96 {
 228         spinlock_t    lock;
 229         int irq;
 230         unsigned long port;
 231         void __iomem *iobase;
 232
 233         u32 wcreg;    /* cached write control register value */
 234         u32 wcreg_spdif;                /* S/PDIF setup */
 235         u32 wcreg_spdif_stream;         /* S/PDIF setup (temporary) */
 236         u32 rcreg;    /* cached read control register value */
 237         u32 areg;     /* cached additional register value */
 238         u16 vol[2]; /* cached volume of analog output */
 239
 240         u8 rev; /* card revision number */
 241
 242 #ifdef CONFIG_PM
 243         u32 playback_pointer;
 244         u32 capture_pointer;
 245         void *playback_suspend_buffer;
 246         void *capture_suspend_buffer;
 247 #endif
 248
 249         struct snd_pcm_substream *playback_substream;
 250         struct snd_pcm_substream *capture_substream;
 251
 252         int playback_frlog; /* log2 of framesize */
 253         int capture_frlog;
 254
 255         size_t playback_periodsize; /* in bytes, zero if not used */
 256         size_t capture_periodsize; /* in bytes, zero if not used */
 257
 258         struct snd_card *card;
 259         struct snd_pcm *spdif_pcm;
 260         struct snd_pcm *adat_pcm;
 261         struct pci_dev     *pci;
 262         struct snd_kcontrol   *spdif_ctl;
 263 };
 264
 265 static DEFINE_PCI_DEVICE_TABLE(snd_rme96_ids) = {
 266         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
 267         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
 268         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
 269         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
 270         { 0, }
 271 };
 272
 273 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
 274
 275 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
 276 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
 277 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
 278 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
 279                                      (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
 280 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
 281 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
 282                                   ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
 283 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
 284
 285 static int
 286 snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
 287
 288 static int
 289 snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
 290
 291 static int
 292 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
 293                            int cmd);
 294
 295 static int
 296 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
 297                           int cmd);
 298
 299 static snd_pcm_uframes_t
 300 snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
 301
 302 static snd_pcm_uframes_t
 303 snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
 304
 305 static void snd_rme96_proc_init(struct rme96 *rme96);
 306
 307 static int
 308 snd_rme96_create_switches(struct snd_card *card,
 309                           struct rme96 *rme96);
 310
 311 static int
 312 snd_rme96_getinputtype(struct rme96 *rme96);
 313
 314 static inline unsigned int
 315 snd_rme96_playback_ptr(struct rme96 *rme96)
 316 {
 317         return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
 318                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
 319 }
 320
 321 static inline unsigned int
 322 snd_rme96_capture_ptr(struct rme96 *rme96)
 323 {
 324         return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
 325                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
 326 }
 327
 328 static int
 329 snd_rme96_playback_silence(struct snd_pcm_substream *substream,
 330                            int channel, /* not used (interleaved data) */
 331                            snd_pcm_uframes_t pos,
 332                            snd_pcm_uframes_t count)
 333 {
 334         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 335         count <<= rme96->playback_frlog;
 336         pos <<= rme96->playback_frlog;
 337         memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
 338                   0, count);
 339         return 0;
 340 }
 341
 342 static int
 343 snd_rme96_playback_copy(struct snd_pcm_substream *substream,
 344                         int channel, /* not used (interleaved data) */
 345                         snd_pcm_uframes_t pos,
 346                         void __user *src,
 347                         snd_pcm_uframes_t count)
 348 {
 349         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 350         count <<= rme96->playback_frlog;
 351         pos <<= rme96->playback_frlog;
 352         copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
 353                             count);
 354         return 0;
 355 }
 356
 357 static int
 358 snd_rme96_capture_copy(struct snd_pcm_substream *substream,
 359                        int channel, /* not used (interleaved data) */
 360                        snd_pcm_uframes_t pos,
 361                        void __user *dst,
 362                        snd_pcm_uframes_t count)
 363 {
 364         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 365         count <<= rme96->capture_frlog;
 366         pos <<= rme96->capture_frlog;
 367         copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
 368                             count);
 369         return 0;
 370 }
 371
 372 /*
 373  * Digital output capabilities (S/PDIF)
 374  */
 375 static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
 376 {
 377         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 378                               SNDRV_PCM_INFO_MMAP_VALID |
 379                               SNDRV_PCM_INFO_SYNC_START |
 380                               SNDRV_PCM_INFO_RESUME |
 381                               SNDRV_PCM_INFO_INTERLEAVED |
 382                               SNDRV_PCM_INFO_PAUSE),
 383         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 384                               SNDRV_PCM_FMTBIT_S32_LE),
 385         .rates =             (SNDRV_PCM_RATE_32000 |
 386                               SNDRV_PCM_RATE_44100 |
 387                               SNDRV_PCM_RATE_48000 |
 388                               SNDRV_PCM_RATE_64000 |
 389                               SNDRV_PCM_RATE_88200 |
 390                               SNDRV_PCM_RATE_96000),
 391         .rate_min =          32000,
 392         .rate_max =          96000,
 393         .channels_min =      2,
 394         .channels_max =      2,
 395         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 396         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 397         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 398         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 399         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 400         .fifo_size =         0,
 401 };
 402
 403 /*
 404  * Digital input capabilities (S/PDIF)
 405  */
 406 static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
 407 {
 408         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 409                               SNDRV_PCM_INFO_MMAP_VALID |
 410                               SNDRV_PCM_INFO_SYNC_START |
 411                               SNDRV_PCM_INFO_RESUME |
 412                               SNDRV_PCM_INFO_INTERLEAVED |
 413                               SNDRV_PCM_INFO_PAUSE),
 414         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 415                               SNDRV_PCM_FMTBIT_S32_LE),
 416         .rates =             (SNDRV_PCM_RATE_32000 |
 417                               SNDRV_PCM_RATE_44100 |
 418                               SNDRV_PCM_RATE_48000 |
 419                               SNDRV_PCM_RATE_64000 |
 420                               SNDRV_PCM_RATE_88200 |
 421                               SNDRV_PCM_RATE_96000),
 422         .rate_min =          32000,
 423         .rate_max =          96000,
 424         .channels_min =      2,
 425         .channels_max =      2,
 426         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 427         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 428         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 429         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 430         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 431         .fifo_size =         0,
 432 };
 433
 434 /*
 435  * Digital output capabilities (ADAT)
 436  */
 437 static struct snd_pcm_hardware snd_rme96_playback_adat_info =
 438 {
 439         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 440                               SNDRV_PCM_INFO_MMAP_VALID |
 441                               SNDRV_PCM_INFO_SYNC_START |
 442                               SNDRV_PCM_INFO_RESUME |
 443                               SNDRV_PCM_INFO_INTERLEAVED |
 444                               SNDRV_PCM_INFO_PAUSE),
 445         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 446                               SNDRV_PCM_FMTBIT_S32_LE),
 447         .rates =             (SNDRV_PCM_RATE_44100 |
 448                               SNDRV_PCM_RATE_48000),
 449         .rate_min =          44100,
 450         .rate_max =          48000,
 451         .channels_min =      8,
 452         .channels_max =      8,
 453         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 454         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 455         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 456         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 457         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 458         .fifo_size =         0,
 459 };
 460
 461 /*
 462  * Digital input capabilities (ADAT)
 463  */
 464 static struct snd_pcm_hardware snd_rme96_capture_adat_info =
 465 {
 466         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 467                               SNDRV_PCM_INFO_MMAP_VALID |
 468                               SNDRV_PCM_INFO_SYNC_START |
 469                               SNDRV_PCM_INFO_RESUME |
 470                               SNDRV_PCM_INFO_INTERLEAVED |
 471                               SNDRV_PCM_INFO_PAUSE),
 472         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 473                               SNDRV_PCM_FMTBIT_S32_LE),
 474         .rates =             (SNDRV_PCM_RATE_44100 |
 475                               SNDRV_PCM_RATE_48000),
 476         .rate_min =          44100,
 477         .rate_max =          48000,
 478         .channels_min =      8,
 479         .channels_max =      8,
 480         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 481         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 482         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 483         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 484         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 485         .fifo_size =         0,
 486 };
 487
 488 /*
 489  * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
 490  * of the AD1852 or AD1852 D/A converter on the board.  CDATA must be set up
 491  * on the falling edge of CCLK and be stable on the rising edge.  The rising
 492  * edge of CLATCH after the last data bit clocks in the whole data word.
 493  * A fast processor could probably drive the SPI interface faster than the
 494  * DAC can handle (3MHz for the 1855, unknown for the 1852).  The udelay(1)
 495  * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
 496  *
 497  * NOTE: increased delay from 1 to 10, since there where problems setting
 498  * the volume.
 499  */
 500 static void
 501 snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
 502 {
 503         int i;
 504
 505         for (i = 0; i < 16; i++) {
 506                 if (val & 0x8000) {
 507                         rme96->areg |= RME96_AR_CDATA;
 508                 } else {
 509                         rme96->areg &= ~RME96_AR_CDATA;
 510                 }
 511                 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
 512                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 513                 udelay(10);
 514                 rme96->areg |= RME96_AR_CCLK;
 515                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 516                 udelay(10);
 517                 val <<= 1;
 518         }
 519         rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
 520         rme96->areg |= RME96_AR_CLATCH;
 521         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 522         udelay(10);
 523         rme96->areg &= ~RME96_AR_CLATCH;
 524         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 525 }
 526
 527 static void
 528 snd_rme96_apply_dac_volume(struct rme96 *rme96)
 529 {
 530         if (RME96_DAC_IS_1852(rme96)) {
 531                 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
 532                 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
 533         } else if (RME96_DAC_IS_1855(rme96)) {
 534                 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
 535                 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
 536         }
 537 }
 538
 539 static void
 540 snd_rme96_reset_dac(struct rme96 *rme96)
 541 {
 542         writel(rme96->wcreg | RME96_WCR_PD,
 543                rme96->iobase + RME96_IO_CONTROL_REGISTER);
 544         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 545 }
 546
 547 static int
 548 snd_rme96_getmontracks(struct rme96 *rme96)
 549 {
 550         return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
 551                 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
 552 }
 553
 554 static int
 555 snd_rme96_setmontracks(struct rme96 *rme96,
 556                        int montracks)
 557 {
 558         if (montracks & 1) {
 559                 rme96->wcreg |= RME96_WCR_MONITOR_0;
 560         } else {
 561                 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
 562         }
 563         if (montracks & 2) {
 564                 rme96->wcreg |= RME96_WCR_MONITOR_1;
 565         } else {
 566                 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
 567         }
 568         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 569         return 0;
 570 }
 571
 572 static int
 573 snd_rme96_getattenuation(struct rme96 *rme96)
 574 {
 575         return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
 576                 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
 577 }
 578
 579 static int
 580 snd_rme96_setattenuation(struct rme96 *rme96,
 581                          int attenuation)
 582 {
 583         switch (attenuation) {
 584         case 0:
 585                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
 586                         ~RME96_WCR_GAIN_1;
 587                 break;
 588         case 1:
 589                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
 590                         ~RME96_WCR_GAIN_1;
 591                 break;
 592         case 2:
 593                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
 594                         RME96_WCR_GAIN_1;
 595                 break;
 596         case 3:
 597                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
 598                         RME96_WCR_GAIN_1;
 599                 break;
 600         default:
 601                 return -EINVAL;
 602         }
 603         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 604         return 0;
 605 }
 606
 607 static int
 608 snd_rme96_capture_getrate(struct rme96 *rme96,
 609                           int *is_adat)
 610 {
 611         int n, rate;
 612
 613         *is_adat = 0;
 614         if (rme96->areg & RME96_AR_ANALOG) {
 615                 /* Analog input, overrides S/PDIF setting */
 616                 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
 617                         (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
 618                 switch (n) {
 619                 case 1:
 620                         rate = 32000;
 621                         break;
 622                 case 2:
 623                         rate = 44100;
 624                         break;
 625                 case 3:
 626                         rate = 48000;
 627                         break;
 628                 default:
 629                         return -1;
 630                 }
 631                 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
 632         }
 633
 634         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
 635         if (rme96->rcreg & RME96_RCR_LOCK) {
 636                 /* ADAT rate */
 637                 *is_adat = 1;
 638                 if (rme96->rcreg & RME96_RCR_T_OUT) {
 639                         return 48000;
 640                 }
 641                 return 44100;
 642         }
 643
 644         if (rme96->rcreg & RME96_RCR_VERF) {
 645                 return -1;
 646         }
 647
 648         /* S/PDIF rate */
 649         n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
 650                 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
 651                 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
 652
 653         switch (n) {
 654         case 0:
 655                 if (rme96->rcreg & RME96_RCR_T_OUT) {
 656                         return 64000;
 657                 }
 658                 return -1;
 659         case 3: return 96000;
 660         case 4: return 88200;
 661         case 5: return 48000;
 662         case 6: return 44100;
 663         case 7: return 32000;
 664         default:
 665                 break;
 666         }
 667         return -1;
 668 }
 669
 670 static int
 671 snd_rme96_playback_getrate(struct rme96 *rme96)
 672 {
 673         int rate, dummy;
 674
 675         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
 676             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
 677             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
 678         {
 679                 /* slave clock */
 680                 return rate;
 681         }
 682         rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
 683                 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
 684         switch (rate) {
 685         case 1:
 686                 rate = 32000;
 687                 break;
 688         case 2:
 689                 rate = 44100;
 690                 break;
 691         case 3:
 692                 rate = 48000;
 693                 break;
 694         default:
 695                 return -1;
 696         }
 697         return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
 698 }
 699
 700 static int
 701 snd_rme96_playback_setrate(struct rme96 *rme96,
 702                            int rate)
 703 {
 704         int ds;
 705
 706         ds = rme96->wcreg & RME96_WCR_DS;
 707         switch (rate) {
 708         case 32000:
 709                 rme96->wcreg &= ~RME96_WCR_DS;
 710                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
 711                         ~RME96_WCR_FREQ_1;
 712                 break;
 713         case 44100:
 714                 rme96->wcreg &= ~RME96_WCR_DS;
 715                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
 716                         ~RME96_WCR_FREQ_0;
 717                 break;
 718         case 48000:
 719                 rme96->wcreg &= ~RME96_WCR_DS;
 720                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
 721                         RME96_WCR_FREQ_1;
 722                 break;
 723         case 64000:
 724                 rme96->wcreg |= RME96_WCR_DS;
 725                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
 726                         ~RME96_WCR_FREQ_1;
 727                 break;
 728         case 88200:
 729                 rme96->wcreg |= RME96_WCR_DS;
 730                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
 731                         ~RME96_WCR_FREQ_0;
 732                 break;
 733         case 96000:
 734                 rme96->wcreg |= RME96_WCR_DS;
 735                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
 736                         RME96_WCR_FREQ_1;
 737                 break;
 738         default:
 739                 return -EINVAL;
 740         }
 741         if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
 742             (ds && !(rme96->wcreg & RME96_WCR_DS)))
 743         {
 744                 /* change to/from double-speed: reset the DAC (if available) */
 745                 snd_rme96_reset_dac(rme96);
 746         } else {
 747                 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 748         }
 749         return 0;
 750 }
 751
 752 static int
 753 snd_rme96_capture_analog_setrate(struct rme96 *rme96,
 754                                  int rate)
 755 {
 756         switch (rate) {
 757         case 32000:
 758                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
 759                                ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 760                 break;
 761         case 44100:
 762                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
 763                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 764                 break;
 765         case 48000:
 766                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
 767                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 768                 break;
 769         case 64000:
 770                 if (rme96->rev < 4) {
 771                         return -EINVAL;
 772                 }
 773                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
 774                                ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 775                 break;
 776         case 88200:
 777                 if (rme96->rev < 4) {
 778                         return -EINVAL;
 779                 }
 780                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
 781                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 782                 break;
 783         case 96000:
 784                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
 785                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 786                 break;
 787         default:
 788                 return -EINVAL;
 789         }
 790         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 791         return 0;
 792 }
 793
 794 static int
 795 snd_rme96_setclockmode(struct rme96 *rme96,
 796                        int mode)
 797 {
 798         switch (mode) {
 799         case RME96_CLOCKMODE_SLAVE:
 800                 /* AutoSync */
 801                 rme96->wcreg &= ~RME96_WCR_MASTER;
 802                 rme96->areg &= ~RME96_AR_WSEL;
 803                 break;
 804         case RME96_CLOCKMODE_MASTER:
 805                 /* Internal */
 806                 rme96->wcreg |= RME96_WCR_MASTER;
 807                 rme96->areg &= ~RME96_AR_WSEL;
 808                 break;
 809         case RME96_CLOCKMODE_WORDCLOCK:
 810                 /* Word clock is a master mode */
 811                 rme96->wcreg |= RME96_WCR_MASTER;
 812                 rme96->areg |= RME96_AR_WSEL;
 813                 break;
 814         default:
 815                 return -EINVAL;
 816         }
 817         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 818         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 819         return 0;
 820 }
 821
 822 static int
 823 snd_rme96_getclockmode(struct rme96 *rme96)
 824 {
 825         if (rme96->areg & RME96_AR_WSEL) {
 826                 return RME96_CLOCKMODE_WORDCLOCK;
 827         }
 828         return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
 829                 RME96_CLOCKMODE_SLAVE;
 830 }
 831
 832 static int
 833 snd_rme96_setinputtype(struct rme96 *rme96,
 834                        int type)
 835 {
 836         int n;
 837
 838         switch (type) {
 839         case RME96_INPUT_OPTICAL:
 840                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
 841                         ~RME96_WCR_INP_1;
 842                 break;
 843         case RME96_INPUT_COAXIAL:
 844                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
 845                         ~RME96_WCR_INP_1;
 846                 break;
 847         case RME96_INPUT_INTERNAL:
 848                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
 849                         RME96_WCR_INP_1;
 850                 break;
 851         case RME96_INPUT_XLR:
 852                 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
 853                      rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
 854                     (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
 855                      rme96->rev > 4))
 856                 {
 857                         /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
 858                         return -EINVAL;
 859                 }
 860                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
 861                         RME96_WCR_INP_1;
 862                 break;
 863         case RME96_INPUT_ANALOG:
 864                 if (!RME96_HAS_ANALOG_IN(rme96)) {
 865                         return -EINVAL;
 866                 }
 867                 rme96->areg |= RME96_AR_ANALOG;
 868                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 869                 if (rme96->rev < 4) {
 870                         /*
 871                          * Revision less than 004 does not support 64 and
 872                          * 88.2 kHz
 873                          */
 874                         if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
 875                                 snd_rme96_capture_analog_setrate(rme96, 44100);
 876                         }
 877                         if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
 878                                 snd_rme96_capture_analog_setrate(rme96, 32000);
 879                         }
 880                 }
 881                 return 0;
 882         default:
 883                 return -EINVAL;
 884         }
 885         if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
 886                 rme96->areg &= ~RME96_AR_ANALOG;
 887                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 888         }
 889         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 890         return 0;
 891 }
 892
 893 static int
 894 snd_rme96_getinputtype(struct rme96 *rme96)
 895 {
 896         if (rme96->areg & RME96_AR_ANALOG) {
 897                 return RME96_INPUT_ANALOG;
 898         }
 899         return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
 900                 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
 901 }
 902
 903 static void
 904 snd_rme96_setframelog(struct rme96 *rme96,
 905                       int n_channels,
 906                       int is_playback)
 907 {
 908         int frlog;
 909
 910         if (n_channels == 2) {
 911                 frlog = 1;
 912         } else {
 913                 /* assume 8 channels */
 914                 frlog = 3;
 915         }
 916         if (is_playback) {
 917                 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
 918                 rme96->playback_frlog = frlog;
 919         } else {
 920                 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
 921                 rme96->capture_frlog = frlog;
 922         }
 923 }
 924
 925 static int
 926 snd_rme96_playback_setformat(struct rme96 *rme96,
 927                              int format)
 928 {
 929         switch (format) {
 930         case SNDRV_PCM_FORMAT_S16_LE:
 931                 rme96->wcreg &= ~RME96_WCR_MODE24;
 932                 break;
 933         case SNDRV_PCM_FORMAT_S32_LE:
 934                 rme96->wcreg |= RME96_WCR_MODE24;
 935                 break;
 936         default:
 937                 return -EINVAL;
 938         }
 939         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 940         return 0;
 941 }
 942
 943 static int
 944 snd_rme96_capture_setformat(struct rme96 *rme96,
 945                             int format)
 946 {
 947         switch (format) {
 948         case SNDRV_PCM_FORMAT_S16_LE:
 949                 rme96->wcreg &= ~RME96_WCR_MODE24_2;
 950                 break;
 951         case SNDRV_PCM_FORMAT_S32_LE:
 952                 rme96->wcreg |= RME96_WCR_MODE24_2;
 953                 break;
 954         default:
 955                 return -EINVAL;
 956         }
 957         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 958         return 0;
 959 }
 960
 961 static void
 962 snd_rme96_set_period_properties(struct rme96 *rme96,
 963                                 size_t period_bytes)
 964 {
 965         switch (period_bytes) {
 966         case RME96_LARGE_BLOCK_SIZE:
 967                 rme96->wcreg &= ~RME96_WCR_ISEL;
 968                 break;
 969         case RME96_SMALL_BLOCK_SIZE:
 970                 rme96->wcreg |= RME96_WCR_ISEL;
 971                 break;
 972         default:
 973                 snd_BUG();
 974                 break;
 975         }
 976         rme96->wcreg &= ~RME96_WCR_IDIS;
 977         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 978 }
 979
 980 static int
 981 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
 982                              struct snd_pcm_hw_params *params)
 983 {
 984         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 985         struct snd_pcm_runtime *runtime = substream->runtime;
 986         int err, rate, dummy;
 987
 988         runtime->dma_area = (void __force *)(rme96->iobase +
 989                                              RME96_IO_PLAY_BUFFER);
 990         runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
 991         runtime->dma_bytes = RME96_BUFFER_SIZE;
 992
 993         spin_lock_irq(&rme96->lock);
 994         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
 995             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
 996             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
 997         {
 998                 /* slave clock */
 999                 if ((int)params_rate(params) != rate) {
1000                         spin_unlock_irq(&rme96->lock);
1001                         return -EIO;
1002                 }
1003         } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
1004                 spin_unlock_irq(&rme96->lock);
1005                 return err;
1006         }
1007         if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
1008                 spin_unlock_irq(&rme96->lock);
1009                 return err;
1010         }
1011         snd_rme96_setframelog(rme96, params_channels(params), 1);
1012         if (rme96->capture_periodsize != 0) {
1013                 if (params_period_size(params) << rme96->playback_frlog !=
1014                     rme96->capture_periodsize)
1015                 {
1016                         spin_unlock_irq(&rme96->lock);
1017                         return -EBUSY;
1018                 }
1019         }
1020         rme96->playback_periodsize =
1021                 params_period_size(params) << rme96->playback_frlog;
1022         snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1023         /* S/PDIF setup */
1024         if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1025                 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1026                 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1027         }
1028         spin_unlock_irq(&rme96->lock);
1029
1030         return 0;
1031 }
1032
1033 static int
1034 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1035                             struct snd_pcm_hw_params *params)
1036 {
1037         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1038         struct snd_pcm_runtime *runtime = substream->runtime;
1039         int err, isadat, rate;
1040
1041         runtime->dma_area = (void __force *)(rme96->iobase +
1042                                              RME96_IO_REC_BUFFER);
1043         runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1044         runtime->dma_bytes = RME96_BUFFER_SIZE;
1045
1046         spin_lock_irq(&rme96->lock);
1047         if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1048                 spin_unlock_irq(&rme96->lock);
1049                 return err;
1050         }
1051         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1052                 if ((err = snd_rme96_capture_analog_setrate(rme96,
1053                                                             params_rate(params))) < 0)
1054                 {
1055                         spin_unlock_irq(&rme96->lock);
1056                         return err;
1057                 }
1058         } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1059                 if ((int)params_rate(params) != rate) {
1060                         spin_unlock_irq(&rme96->lock);
1061                         return -EIO;
1062                 }
1063                 if ((isadat && runtime->hw.channels_min == 2) ||
1064                     (!isadat && runtime->hw.channels_min == 8))
1065                 {
1066                         spin_unlock_irq(&rme96->lock);
1067                         return -EIO;
1068                 }
1069         }
1070         snd_rme96_setframelog(rme96, params_channels(params), 0);
1071         if (rme96->playback_periodsize != 0) {
1072                 if (params_period_size(params) << rme96->capture_frlog !=
1073                     rme96->playback_periodsize)
1074                 {
1075                         spin_unlock_irq(&rme96->lock);
1076                         return -EBUSY;
1077                 }
1078         }
1079         rme96->capture_periodsize =
1080                 params_period_size(params) << rme96->capture_frlog;
1081         snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1082         spin_unlock_irq(&rme96->lock);
1083
1084         return 0;
1085 }
1086
1087 static void
1088 snd_rme96_trigger(struct rme96 *rme96,
1089                   int op)
1090 {
1091         if (op & RME96_TB_RESET_PLAYPOS)
1092                 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1093         if (op & RME96_TB_RESET_CAPTUREPOS)
1094                 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1095         if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) {
1096                 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1097                 if (rme96->rcreg & RME96_RCR_IRQ)
1098                         writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1099         }
1100         if (op & RME96_TB_CLEAR_CAPTURE_IRQ) {
1101                 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1102                 if (rme96->rcreg & RME96_RCR_IRQ_2)
1103                         writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1104         }
1105         if (op & RME96_TB_START_PLAYBACK)
1106                 rme96->wcreg |= RME96_WCR_START;
1107         if (op & RME96_TB_STOP_PLAYBACK)
1108                 rme96->wcreg &= ~RME96_WCR_START;
1109         if (op & RME96_TB_START_CAPTURE)
1110                 rme96->wcreg |= RME96_WCR_START_2;
1111         if (op & RME96_TB_STOP_CAPTURE)
1112                 rme96->wcreg &= ~RME96_WCR_START_2;
1113         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1114 }
1115
1116
1117
1118 static irqreturn_t
1119 snd_rme96_interrupt(int irq,
1120                     void *dev_id)
1121 {
1122         struct rme96 *rme96 = (struct rme96 *)dev_id;
1123
1124         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1125         /* fastpath out, to ease interrupt sharing */
1126         if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1127               (rme96->rcreg & RME96_RCR_IRQ_2)))
1128         {
1129                 return IRQ_NONE;
1130         }
1131
1132         if (rme96->rcreg & RME96_RCR_IRQ) {
1133                 /* playback */
1134                 snd_pcm_period_elapsed(rme96->playback_substream);
1135                 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1136         }
1137         if (rme96->rcreg & RME96_RCR_IRQ_2) {
1138                 /* capture */
1139                 snd_pcm_period_elapsed(rme96->capture_substream);
1140                 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1141         }
1142         return IRQ_HANDLED;
1143 }
1144
1145 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1146
1147 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1148         .count = ARRAY_SIZE(period_bytes),
1149         .list = period_bytes,
1150         .mask = 0
1151 };
1152
1153 static void
1154 rme96_set_buffer_size_constraint(struct rme96 *rme96,
1155                                  struct snd_pcm_runtime *runtime)
1156 {
1157         unsigned int size;
1158
1159         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1160                                      RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1161         if ((size = rme96->playback_periodsize) != 0 ||
1162             (size = rme96->capture_periodsize) != 0)
1163                 snd_pcm_hw_constraint_minmax(runtime,
1164                                              SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1165                                              size, size);
1166         else
1167                 snd_pcm_hw_constraint_list(runtime, 0,
1168                                            SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1169                                            &hw_constraints_period_bytes);
1170 }
1171
1172 static int
1173 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1174 {
1175         int rate, dummy;
1176         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1177         struct snd_pcm_runtime *runtime = substream->runtime;
1178
1179         snd_pcm_set_sync(substream);
1180         spin_lock_irq(&rme96->lock);
1181         if (rme96->playback_substream != NULL) {
1182                 spin_unlock_irq(&rme96->lock);
1183                 return -EBUSY;
1184         }
1185         rme96->wcreg &= ~RME96_WCR_ADAT;
1186         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1187         rme96->playback_substream = substream;
1188         spin_unlock_irq(&rme96->lock);
1189
1190         runtime->hw = snd_rme96_playback_spdif_info;
1191         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1192             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1193             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1194         {
1195                 /* slave clock */
1196                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1197                 runtime->hw.rate_min = rate;
1198                 runtime->hw.rate_max = rate;
1199         }
1200         rme96_set_buffer_size_constraint(rme96, runtime);
1201
1202         rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1203         rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1204         snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1205                        SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1206         return 0;
1207 }
1208
1209 static int
1210 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1211 {
1212         int isadat, rate;
1213         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1214         struct snd_pcm_runtime *runtime = substream->runtime;
1215
1216         snd_pcm_set_sync(substream);
1217         runtime->hw = snd_rme96_capture_spdif_info;
1218         if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1219             (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1220         {
1221                 if (isadat) {
1222                         return -EIO;
1223                 }
1224                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1225                 runtime->hw.rate_min = rate;
1226                 runtime->hw.rate_max = rate;
1227         }
1228
1229         spin_lock_irq(&rme96->lock);
1230         if (rme96->capture_substream != NULL) {
1231                 spin_unlock_irq(&rme96->lock);
1232                 return -EBUSY;
1233         }
1234         rme96->capture_substream = substream;
1235         spin_unlock_irq(&rme96->lock);
1236
1237         rme96_set_buffer_size_constraint(rme96, runtime);
1238         return 0;
1239 }
1240
1241 static int
1242 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1243 {
1244         int rate, dummy;
1245         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1246         struct snd_pcm_runtime *runtime = substream->runtime;
1247
1248         snd_pcm_set_sync(substream);
1249         spin_lock_irq(&rme96->lock);
1250         if (rme96->playback_substream != NULL) {
1251                 spin_unlock_irq(&rme96->lock);
1252                 return -EBUSY;
1253         }
1254         rme96->wcreg |= RME96_WCR_ADAT;
1255         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1256         rme96->playback_substream = substream;
1257         spin_unlock_irq(&rme96->lock);
1258
1259         runtime->hw = snd_rme96_playback_adat_info;
1260         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1261             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1262             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1263         {
1264                 /* slave clock */
1265                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1266                 runtime->hw.rate_min = rate;
1267                 runtime->hw.rate_max = rate;
1268         }
1269         rme96_set_buffer_size_constraint(rme96, runtime);
1270         return 0;
1271 }
1272
1273 static int
1274 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1275 {
1276         int isadat, rate;
1277         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1278         struct snd_pcm_runtime *runtime = substream->runtime;
1279
1280         snd_pcm_set_sync(substream);
1281         runtime->hw = snd_rme96_capture_adat_info;
1282         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1283                 /* makes no sense to use analog input. Note that analog
1284                    expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1285                 return -EIO;
1286         }
1287         if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1288                 if (!isadat) {
1289                         return -EIO;
1290                 }
1291                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1292                 runtime->hw.rate_min = rate;
1293                 runtime->hw.rate_max = rate;
1294         }
1295
1296         spin_lock_irq(&rme96->lock);
1297         if (rme96->capture_substream != NULL) {
1298                 spin_unlock_irq(&rme96->lock);
1299                 return -EBUSY;
1300         }
1301         rme96->capture_substream = substream;
1302         spin_unlock_irq(&rme96->lock);
1303
1304         rme96_set_buffer_size_constraint(rme96, runtime);
1305         return 0;
1306 }
1307
1308 static int
1309 snd_rme96_playback_close(struct snd_pcm_substream *substream)
1310 {
1311         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1312         int spdif = 0;
1313
1314         spin_lock_irq(&rme96->lock);
1315         if (RME96_ISPLAYING(rme96)) {
1316                 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1317         }
1318         rme96->playback_substream = NULL;
1319         rme96->playback_periodsize = 0;
1320         spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1321         spin_unlock_irq(&rme96->lock);
1322         if (spdif) {
1323                 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1324                 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1325                                SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1326         }
1327         return 0;
1328 }
1329
1330 static int
1331 snd_rme96_capture_close(struct snd_pcm_substream *substream)
1332 {
1333         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1334
1335         spin_lock_irq(&rme96->lock);
1336         if (RME96_ISRECORDING(rme96)) {
1337                 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1338         }
1339         rme96->capture_substream = NULL;
1340         rme96->capture_periodsize = 0;
1341         spin_unlock_irq(&rme96->lock);
1342         return 0;
1343 }
1344
1345 static int
1346 snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1347 {
1348         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1349
1350         spin_lock_irq(&rme96->lock);
1351         if (RME96_ISPLAYING(rme96)) {
1352                 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1353         }
1354         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1355         spin_unlock_irq(&rme96->lock);
1356         return 0;
1357 }
1358
1359 static int
1360 snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1361 {
1362         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1363
1364         spin_lock_irq(&rme96->lock);
1365         if (RME96_ISRECORDING(rme96)) {
1366                 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1367         }
1368         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1369         spin_unlock_irq(&rme96->lock);
1370         return 0;
1371 }
1372
1373 static int
1374 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1375                            int cmd)
1376 {
1377         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1378         struct snd_pcm_substream *s;
1379         bool sync;
1380
1381         snd_pcm_group_for_each_entry(s, substream) {
1382                 if (snd_pcm_substream_chip(s) == rme96)
1383                         snd_pcm_trigger_done(s, substream);
1384         }
1385
1386         sync = (rme96->playback_substream && rme96->capture_substream) &&
1387                (rme96->playback_substream->group ==
1388                 rme96->capture_substream->group);
1389
1390         switch (cmd) {
1391         case SNDRV_PCM_TRIGGER_START:
1392                 if (!RME96_ISPLAYING(rme96)) {
1393                         if (substream != rme96->playback_substream)
1394                                 return -EBUSY;
1395                         snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1396                                                  : RME96_START_PLAYBACK);
1397                 }
1398                 break;
1399
1400         case SNDRV_PCM_TRIGGER_SUSPEND:
1401         case SNDRV_PCM_TRIGGER_STOP:
1402                 if (RME96_ISPLAYING(rme96)) {
1403                         if (substream != rme96->playback_substream)
1404                                 return -EBUSY;
1405                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1406                                                  :  RME96_STOP_PLAYBACK);
1407                 }
1408                 break;
1409
1410         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1411                 if (RME96_ISPLAYING(rme96))
1412                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1413                                                  : RME96_STOP_PLAYBACK);
1414                 break;
1415
1416         case SNDRV_PCM_TRIGGER_RESUME:
1417         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1418                 if (!RME96_ISPLAYING(rme96))
1419                         snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1420                                                  : RME96_RESUME_PLAYBACK);
1421                 break;
1422
1423         default:
1424                 return -EINVAL;
1425         }
1426
1427         return 0;
1428 }
1429
1430 static int
1431 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1432                           int cmd)
1433 {
1434         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1435         struct snd_pcm_substream *s;
1436         bool sync;
1437
1438         snd_pcm_group_for_each_entry(s, substream) {
1439                 if (snd_pcm_substream_chip(s) == rme96)
1440                         snd_pcm_trigger_done(s, substream);
1441         }
1442
1443         sync = (rme96->playback_substream && rme96->capture_substream) &&
1444                (rme96->playback_substream->group ==
1445                 rme96->capture_substream->group);
1446
1447         switch (cmd) {
1448         case SNDRV_PCM_TRIGGER_START:
1449                 if (!RME96_ISRECORDING(rme96)) {
1450                         if (substream != rme96->capture_substream)
1451                                 return -EBUSY;
1452                         snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1453                                                  : RME96_START_CAPTURE);
1454                 }
1455                 break;
1456
1457         case SNDRV_PCM_TRIGGER_SUSPEND:
1458         case SNDRV_PCM_TRIGGER_STOP:
1459                 if (RME96_ISRECORDING(rme96)) {
1460                         if (substream != rme96->capture_substream)
1461                                 return -EBUSY;
1462                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1463                                                  : RME96_STOP_CAPTURE);
1464                 }
1465                 break;
1466
1467         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1468                 if (RME96_ISRECORDING(rme96))
1469                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1470                                                  : RME96_STOP_CAPTURE);
1471                 break;
1472
1473         case SNDRV_PCM_TRIGGER_RESUME:
1474         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1475                 if (!RME96_ISRECORDING(rme96))
1476                         snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1477                                                  : RME96_RESUME_CAPTURE);
1478                 break;
1479
1480         default:
1481                 return -EINVAL;
1482         }
1483
1484         return 0;
1485 }
1486
1487 static snd_pcm_uframes_t
1488 snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1489 {
1490         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1491         return snd_rme96_playback_ptr(rme96);
1492 }
1493
1494 static snd_pcm_uframes_t
1495 snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1496 {
1497         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1498         return snd_rme96_capture_ptr(rme96);
1499 }
1500
1501 static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1502         .open =         snd_rme96_playback_spdif_open,
1503         .close =        snd_rme96_playback_close,
1504         .ioctl =        snd_pcm_lib_ioctl,
1505         .hw_params =    snd_rme96_playback_hw_params,
1506         .prepare =      snd_rme96_playback_prepare,
1507         .trigger =      snd_rme96_playback_trigger,
1508         .pointer =      snd_rme96_playback_pointer,
1509         .copy =         snd_rme96_playback_copy,
1510         .silence =      snd_rme96_playback_silence,
1511         .mmap =         snd_pcm_lib_mmap_iomem,
1512 };
1513
1514 static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1515         .open =         snd_rme96_capture_spdif_open,
1516         .close =        snd_rme96_capture_close,
1517         .ioctl =        snd_pcm_lib_ioctl,
1518         .hw_params =    snd_rme96_capture_hw_params,
1519         .prepare =      snd_rme96_capture_prepare,
1520         .trigger =      snd_rme96_capture_trigger,
1521         .pointer =      snd_rme96_capture_pointer,
1522         .copy =         snd_rme96_capture_copy,
1523         .mmap =         snd_pcm_lib_mmap_iomem,
1524 };
1525
1526 static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1527         .open =         snd_rme96_playback_adat_open,
1528         .close =        snd_rme96_playback_close,
1529         .ioctl =        snd_pcm_lib_ioctl,
1530         .hw_params =    snd_rme96_playback_hw_params,
1531         .prepare =      snd_rme96_playback_prepare,
1532         .trigger =      snd_rme96_playback_trigger,
1533         .pointer =      snd_rme96_playback_pointer,
1534         .copy =         snd_rme96_playback_copy,
1535         .silence =      snd_rme96_playback_silence,
1536         .mmap =         snd_pcm_lib_mmap_iomem,
1537 };
1538
1539 static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1540         .open =         snd_rme96_capture_adat_open,
1541         .close =        snd_rme96_capture_close,
1542         .ioctl =        snd_pcm_lib_ioctl,
1543         .hw_params =    snd_rme96_capture_hw_params,
1544         .prepare =      snd_rme96_capture_prepare,
1545         .trigger =      snd_rme96_capture_trigger,
1546         .pointer =      snd_rme96_capture_pointer,
1547         .copy =         snd_rme96_capture_copy,
1548         .mmap =         snd_pcm_lib_mmap_iomem,
1549 };
1550
1551 static void
1552 snd_rme96_free(void *private_data)
1553 {
1554         struct rme96 *rme96 = (struct rme96 *)private_data;
1555
1556         if (rme96 == NULL) {
1557                 return;
1558         }
1559         if (rme96->irq >= 0) {
1560                 snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1561                 rme96->areg &= ~RME96_AR_DAC_EN;
1562                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1563                 free_irq(rme96->irq, (void *)rme96);
1564                 rme96->irq = -1;
1565         }
1566         if (rme96->iobase) {
1567                 iounmap(rme96->iobase);
1568                 rme96->iobase = NULL;
1569         }
1570         if (rme96->port) {
1571                 pci_release_regions(rme96->pci);
1572                 rme96->port = 0;
1573         }
1574 #ifdef CONFIG_PM
1575         vfree(rme96->playback_suspend_buffer);
1576         vfree(rme96->capture_suspend_buffer);
1577 #endif
1578         pci_disable_device(rme96->pci);
1579 }
1580
1581 static void
1582 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1583 {
1584         struct rme96 *rme96 = pcm->private_data;
1585         rme96->spdif_pcm = NULL;
1586 }
1587
1588 static void
1589 snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1590 {
1591         struct rme96 *rme96 = pcm->private_data;
1592         rme96->adat_pcm = NULL;
1593 }
1594
1595 static int
1596 snd_rme96_create(struct rme96 *rme96)
1597 {
1598         struct pci_dev *pci = rme96->pci;
1599         int err;
1600
1601         rme96->irq = -1;
1602         spin_lock_init(&rme96->lock);
1603
1604         if ((err = pci_enable_device(pci)) < 0)
1605                 return err;
1606
1607         if ((err = pci_request_regions(pci, "RME96")) < 0)
1608                 return err;
1609         rme96->port = pci_resource_start(rme96->pci, 0);
1610
1611         rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE);
1612         if (!rme96->iobase) {
1613                 snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1614                 return -ENOMEM;
1615         }
1616
1617         if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
1618                         KBUILD_MODNAME, rme96)) {
1619                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1620                 return -EBUSY;
1621         }
1622         rme96->irq = pci->irq;
1623
1624         /* read the card's revision number */
1625         pci_read_config_byte(pci, 8, &rme96->rev);
1626
1627         /* set up ALSA pcm device for S/PDIF */
1628         if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1629                                1, 1, &rme96->spdif_pcm)) < 0)
1630         {
1631                 return err;
1632         }
1633         rme96->spdif_pcm->private_data = rme96;
1634         rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1635         strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1636         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1637         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1638
1639         rme96->spdif_pcm->info_flags = 0;
1640
1641         /* set up ALSA pcm device for ADAT */
1642         if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1643                 /* ADAT is not available on the base model */
1644                 rme96->adat_pcm = NULL;
1645         } else {
1646                 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1647                                        1, 1, &rme96->adat_pcm)) < 0)
1648                 {
1649                         return err;
1650                 }
1651                 rme96->adat_pcm->private_data = rme96;
1652                 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1653                 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1654                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1655                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1656
1657                 rme96->adat_pcm->info_flags = 0;
1658         }
1659
1660         rme96->playback_periodsize = 0;
1661         rme96->capture_periodsize = 0;
1662
1663         /* make sure playback/capture is stopped, if by some reason active */
1664         snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1665
1666         /* set default values in registers */
1667         rme96->wcreg =
1668                 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1669                 RME96_WCR_SEL |    /* normal playback */
1670                 RME96_WCR_MASTER | /* set to master clock mode */
1671                 RME96_WCR_INP_0;   /* set coaxial input */
1672
1673         rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1674
1675         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1676         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1677
1678         /* reset the ADC */
1679         writel(rme96->areg | RME96_AR_PD2,
1680                rme96->iobase + RME96_IO_ADDITIONAL_REG);
1681         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1682
1683         /* reset and enable the DAC (order is important). */
1684         snd_rme96_reset_dac(rme96);
1685         rme96->areg |= RME96_AR_DAC_EN;
1686         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1687
1688         /* reset playback and record buffer pointers */
1689         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1690         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1691
1692         /* reset volume */
1693         rme96->vol[0] = rme96->vol[1] = 0;
1694         if (RME96_HAS_ANALOG_OUT(rme96)) {
1695                 snd_rme96_apply_dac_volume(rme96);
1696         }
1697
1698         /* init switch interface */
1699         if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1700                 return err;
1701         }
1702
1703         /* init proc interface */
1704         snd_rme96_proc_init(rme96);
1705
1706         return 0;
1707 }
1708
1709 /*
1710  * proc interface
1711  */
1712
1713 static void
1714 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1715 {
1716         int n;
1717         struct rme96 *rme96 = entry->private_data;
1718
1719         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1720
1721         snd_iprintf(buffer, rme96->card->longname);
1722         snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1723
1724         snd_iprintf(buffer, "\nGeneral settings\n");
1725         if (rme96->wcreg & RME96_WCR_IDIS) {
1726                 snd_iprintf(buffer, "  period size: N/A (interrupts "
1727                             "disabled)\n");
1728         } else if (rme96->wcreg & RME96_WCR_ISEL) {
1729                 snd_iprintf(buffer, "  period size: 2048 bytes\n");
1730         } else {
1731                 snd_iprintf(buffer, "  period size: 8192 bytes\n");
1732         }
1733         snd_iprintf(buffer, "\nInput settings\n");
1734         switch (snd_rme96_getinputtype(rme96)) {
1735         case RME96_INPUT_OPTICAL:
1736                 snd_iprintf(buffer, "  input: optical");
1737                 break;
1738         case RME96_INPUT_COAXIAL:
1739                 snd_iprintf(buffer, "  input: coaxial");
1740                 break;
1741         case RME96_INPUT_INTERNAL:
1742                 snd_iprintf(buffer, "  input: internal");
1743                 break;
1744         case RME96_INPUT_XLR:
1745                 snd_iprintf(buffer, "  input: XLR");
1746                 break;
1747         case RME96_INPUT_ANALOG:
1748                 snd_iprintf(buffer, "  input: analog");
1749                 break;
1750         }
1751         if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1752                 snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1753         } else {
1754                 if (n) {
1755                         snd_iprintf(buffer, " (8 channels)\n");
1756                 } else {
1757                         snd_iprintf(buffer, " (2 channels)\n");
1758                 }
1759                 snd_iprintf(buffer, "  sample rate: %d Hz\n",
1760                             snd_rme96_capture_getrate(rme96, &n));
1761         }
1762         if (rme96->wcreg & RME96_WCR_MODE24_2) {
1763                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1764         } else {
1765                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1766         }
1767
1768         snd_iprintf(buffer, "\nOutput settings\n");
1769         if (rme96->wcreg & RME96_WCR_SEL) {
1770                 snd_iprintf(buffer, "  output signal: normal playback\n");
1771         } else {
1772                 snd_iprintf(buffer, "  output signal: same as input\n");
1773         }
1774         snd_iprintf(buffer, "  sample rate: %d Hz\n",
1775                     snd_rme96_playback_getrate(rme96));
1776         if (rme96->wcreg & RME96_WCR_MODE24) {
1777                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1778         } else {
1779                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1780         }
1781         if (rme96->areg & RME96_AR_WSEL) {
1782                 snd_iprintf(buffer, "  sample clock source: word clock\n");
1783         } else if (rme96->wcreg & RME96_WCR_MASTER) {
1784                 snd_iprintf(buffer, "  sample clock source: internal\n");
1785         } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1786                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to analog input setting)\n");
1787         } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1788                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to no valid signal)\n");
1789         } else {
1790                 snd_iprintf(buffer, "  sample clock source: autosync\n");
1791         }
1792         if (rme96->wcreg & RME96_WCR_PRO) {
1793                 snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1794         } else {
1795                 snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1796         }
1797         if (rme96->wcreg & RME96_WCR_EMP) {
1798                 snd_iprintf(buffer, "  emphasis: on\n");
1799         } else {
1800                 snd_iprintf(buffer, "  emphasis: off\n");
1801         }
1802         if (rme96->wcreg & RME96_WCR_DOLBY) {
1803                 snd_iprintf(buffer, "  non-audio (dolby): on\n");
1804         } else {
1805                 snd_iprintf(buffer, "  non-audio (dolby): off\n");
1806         }
1807         if (RME96_HAS_ANALOG_IN(rme96)) {
1808                 snd_iprintf(buffer, "\nAnalog output settings\n");
1809                 switch (snd_rme96_getmontracks(rme96)) {
1810                 case RME96_MONITOR_TRACKS_1_2:
1811                         snd_iprintf(buffer, "  monitored ADAT tracks: 1+2\n");
1812                         break;
1813                 case RME96_MONITOR_TRACKS_3_4:
1814                         snd_iprintf(buffer, "  monitored ADAT tracks: 3+4\n");
1815                         break;
1816                 case RME96_MONITOR_TRACKS_5_6:
1817                         snd_iprintf(buffer, "  monitored ADAT tracks: 5+6\n");
1818                         break;
1819                 case RME96_MONITOR_TRACKS_7_8:
1820                         snd_iprintf(buffer, "  monitored ADAT tracks: 7+8\n");
1821                         break;
1822                 }
1823                 switch (snd_rme96_getattenuation(rme96)) {
1824                 case RME96_ATTENUATION_0:
1825                         snd_iprintf(buffer, "  attenuation: 0 dB\n");
1826                         break;
1827                 case RME96_ATTENUATION_6:
1828                         snd_iprintf(buffer, "  attenuation: -6 dB\n");
1829                         break;
1830                 case RME96_ATTENUATION_12:
1831                         snd_iprintf(buffer, "  attenuation: -12 dB\n");
1832                         break;
1833                 case RME96_ATTENUATION_18:
1834                         snd_iprintf(buffer, "  attenuation: -18 dB\n");
1835                         break;
1836                 }
1837                 snd_iprintf(buffer, "  volume left: %u\n", rme96->vol[0]);
1838                 snd_iprintf(buffer, "  volume right: %u\n", rme96->vol[1]);
1839         }
1840 }
1841
1842 static void snd_rme96_proc_init(struct rme96 *rme96)
1843 {
1844         struct snd_info_entry *entry;
1845
1846         if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1847                 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
1848 }
1849
1850 /*
1851  * control interface
1852  */
1853
1854 #define snd_rme96_info_loopback_control         snd_ctl_boolean_mono_info
1855
1856 static int
1857 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1858 {
1859         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1860
1861         spin_lock_irq(&rme96->lock);
1862         ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1863         spin_unlock_irq(&rme96->lock);
1864         return 0;
1865 }
1866 static int
1867 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1868 {
1869         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1870         unsigned int val;
1871         int change;
1872
1873         val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1874         spin_lock_irq(&rme96->lock);
1875         val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1876         change = val != rme96->wcreg;
1877         rme96->wcreg = val;
1878         writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1879         spin_unlock_irq(&rme96->lock);
1880         return change;
1881 }
1882
1883 static int
1884 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1885 {
1886         static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1887         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1888         char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1889
1890         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1891         uinfo->count = 1;
1892         switch (rme96->pci->device) {
1893         case PCI_DEVICE_ID_RME_DIGI96:
1894         case PCI_DEVICE_ID_RME_DIGI96_8:
1895                 uinfo->value.enumerated.items = 3;
1896                 break;
1897         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1898                 uinfo->value.enumerated.items = 4;
1899                 break;
1900         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1901                 if (rme96->rev > 4) {
1902                         /* PST */
1903                         uinfo->value.enumerated.items = 4;
1904                         texts[3] = _texts[4]; /* Analog instead of XLR */
1905                 } else {
1906                         /* PAD */
1907                         uinfo->value.enumerated.items = 5;
1908                 }
1909                 break;
1910         default:
1911                 snd_BUG();
1912                 break;
1913         }
1914         if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1915                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1916         }
1917         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1918         return 0;
1919 }
1920 static int
1921 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1922 {
1923         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1924         unsigned int items = 3;
1925
1926         spin_lock_irq(&rme96->lock);
1927         ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1928
1929         switch (rme96->pci->device) {
1930         case PCI_DEVICE_ID_RME_DIGI96:
1931         case PCI_DEVICE_ID_RME_DIGI96_8:
1932                 items = 3;
1933                 break;
1934         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1935                 items = 4;
1936                 break;
1937         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1938                 if (rme96->rev > 4) {
1939                         /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1940                         if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1941                                 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1942                         }
1943                         items = 4;
1944                 } else {
1945                         items = 5;
1946                 }
1947                 break;
1948         default:
1949                 snd_BUG();
1950                 break;
1951         }
1952         if (ucontrol->value.enumerated.item[0] >= items) {
1953                 ucontrol->value.enumerated.item[0] = items - 1;
1954         }
1955
1956         spin_unlock_irq(&rme96->lock);
1957         return 0;
1958 }
1959 static int
1960 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1961 {
1962         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1963         unsigned int val;
1964         int change, items = 3;
1965
1966         switch (rme96->pci->device) {
1967         case PCI_DEVICE_ID_RME_DIGI96:
1968         case PCI_DEVICE_ID_RME_DIGI96_8:
1969                 items = 3;
1970                 break;
1971         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1972                 items = 4;
1973                 break;
1974         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1975                 if (rme96->rev > 4) {
1976                         items = 4;
1977                 } else {
1978                         items = 5;
1979                 }
1980                 break;
1981         default:
1982                 snd_BUG();
1983                 break;
1984         }
1985         val = ucontrol->value.enumerated.item[0] % items;
1986
1987         /* special case for PST */
1988         if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1989                 if (val == RME96_INPUT_XLR) {
1990                         val = RME96_INPUT_ANALOG;
1991                 }
1992         }
1993
1994         spin_lock_irq(&rme96->lock);
1995         change = (int)val != snd_rme96_getinputtype(rme96);
1996         snd_rme96_setinputtype(rme96, val);
1997         spin_unlock_irq(&rme96->lock);
1998         return change;
1999 }
2000
2001 static int
2002 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2003 {
2004         static char *texts[3] = { "AutoSync", "Internal", "Word" };
2005
2006         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2007         uinfo->count = 1;
2008         uinfo->value.enumerated.items = 3;
2009         if (uinfo->value.enumerated.item > 2) {
2010                 uinfo->value.enumerated.item = 2;
2011         }
2012         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2013         return 0;
2014 }
2015 static int
2016 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2017 {
2018         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2019
2020         spin_lock_irq(&rme96->lock);
2021         ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2022         spin_unlock_irq(&rme96->lock);
2023         return 0;
2024 }
2025 static int
2026 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2027 {
2028         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2029         unsigned int val;
2030         int change;
2031
2032         val = ucontrol->value.enumerated.item[0] % 3;
2033         spin_lock_irq(&rme96->lock);
2034         change = (int)val != snd_rme96_getclockmode(rme96);
2035         snd_rme96_setclockmode(rme96, val);
2036         spin_unlock_irq(&rme96->lock);
2037         return change;
2038 }
2039
2040 static int
2041 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2042 {
2043         static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2044
2045         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2046         uinfo->count = 1;
2047         uinfo->value.enumerated.items = 4;
2048         if (uinfo->value.enumerated.item > 3) {
2049                 uinfo->value.enumerated.item = 3;
2050         }
2051         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2052         return 0;
2053 }
2054 static int
2055 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2056 {
2057         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2058
2059         spin_lock_irq(&rme96->lock);
2060         ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2061         spin_unlock_irq(&rme96->lock);
2062         return 0;
2063 }
2064 static int
2065 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2066 {
2067         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2068         unsigned int val;
2069         int change;
2070
2071         val = ucontrol->value.enumerated.item[0] % 4;
2072         spin_lock_irq(&rme96->lock);
2073
2074         change = (int)val != snd_rme96_getattenuation(rme96);
2075         snd_rme96_setattenuation(rme96, val);
2076         spin_unlock_irq(&rme96->lock);
2077         return change;
2078 }
2079
2080 static int
2081 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2082 {
2083         static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2084
2085         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2086         uinfo->count = 1;
2087         uinfo->value.enumerated.items = 4;
2088         if (uinfo->value.enumerated.item > 3) {
2089                 uinfo->value.enumerated.item = 3;
2090         }
2091         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2092         return 0;
2093 }
2094 static int
2095 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2096 {
2097         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2098
2099         spin_lock_irq(&rme96->lock);
2100         ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2101         spin_unlock_irq(&rme96->lock);
2102         return 0;
2103 }
2104 static int
2105 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2106 {
2107         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2108         unsigned int val;
2109         int change;
2110
2111         val = ucontrol->value.enumerated.item[0] % 4;
2112         spin_lock_irq(&rme96->lock);
2113         change = (int)val != snd_rme96_getmontracks(rme96);
2114         snd_rme96_setmontracks(rme96, val);
2115         spin_unlock_irq(&rme96->lock);
2116         return change;
2117 }
2118
2119 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
2120 {
2121         u32 val = 0;
2122         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2123         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2124         if (val & RME96_WCR_PRO)
2125                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2126         else
2127                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2128         return val;
2129 }
2130
2131 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
2132 {
2133         aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2134                          ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2135         if (val & RME96_WCR_PRO)
2136                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2137         else
2138                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2139 }
2140
2141 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2142 {
2143         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2144         uinfo->count = 1;
2145         return 0;
2146 }
2147
2148 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2149 {
2150         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2151
2152         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2153         return 0;
2154 }
2155
2156 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2157 {
2158         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2159         int change;
2160         u32 val;
2161
2162         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2163         spin_lock_irq(&rme96->lock);
2164         change = val != rme96->wcreg_spdif;
2165         rme96->wcreg_spdif = val;
2166         spin_unlock_irq(&rme96->lock);
2167         return change;
2168 }
2169
2170 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2171 {
2172         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2173         uinfo->count = 1;
2174         return 0;
2175 }
2176
2177 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2178 {
2179         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2180
2181         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2182         return 0;
2183 }
2184
2185 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2186 {
2187         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2188         int change;
2189         u32 val;
2190
2191         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2192         spin_lock_irq(&rme96->lock);
2193         change = val != rme96->wcreg_spdif_stream;
2194         rme96->wcreg_spdif_stream = val;
2195         rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2196         rme96->wcreg |= val;
2197         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2198         spin_unlock_irq(&rme96->lock);
2199         return change;
2200 }
2201
2202 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2203 {
2204         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2205         uinfo->count = 1;
2206         return 0;
2207 }
2208
2209 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2210 {
2211         ucontrol->value.iec958.status[0] = kcontrol->private_value;
2212         return 0;
2213 }
2214
2215 static int
2216 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2217 {
2218         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2219
2220         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2221         uinfo->count = 2;
2222         uinfo->value.integer.min = 0;
2223         uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2224         return 0;
2225 }
2226
2227 static int
2228 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2229 {
2230         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2231
2232         spin_lock_irq(&rme96->lock);
2233         u->value.integer.value[0] = rme96->vol[0];
2234         u->value.integer.value[1] = rme96->vol[1];
2235         spin_unlock_irq(&rme96->lock);
2236
2237         return 0;
2238 }
2239
2240 static int
2241 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2242 {
2243         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2244         int change = 0;
2245         unsigned int vol, maxvol;
2246
2247
2248         if (!RME96_HAS_ANALOG_OUT(rme96))
2249                 return -EINVAL;
2250         maxvol = RME96_185X_MAX_OUT(rme96);
2251         spin_lock_irq(&rme96->lock);
2252         vol = u->value.integer.value[0];
2253         if (vol != rme96->vol[0] && vol <= maxvol) {
2254                 rme96->vol[0] = vol;
2255                 change = 1;
2256         }
2257         vol = u->value.integer.value[1];
2258         if (vol != rme96->vol[1] && vol <= maxvol) {
2259                 rme96->vol[1] = vol;
2260                 change = 1;
2261         }
2262         if (change)
2263                 snd_rme96_apply_dac_volume(rme96);
2264         spin_unlock_irq(&rme96->lock);
2265
2266         return change;
2267 }
2268
2269 static struct snd_kcontrol_new snd_rme96_controls[] = {
2270 {
2271         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2272         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2273         .info =         snd_rme96_control_spdif_info,
2274         .get =          snd_rme96_control_spdif_get,
2275         .put =          snd_rme96_control_spdif_put
2276 },
2277 {
2278         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2279         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2280         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2281         .info =         snd_rme96_control_spdif_stream_info,
2282         .get =          snd_rme96_control_spdif_stream_get,
2283         .put =          snd_rme96_control_spdif_stream_put
2284 },
2285 {
2286         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2287         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2288         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2289         .info =         snd_rme96_control_spdif_mask_info,
2290         .get =          snd_rme96_control_spdif_mask_get,
2291         .private_value = IEC958_AES0_NONAUDIO |
2292                         IEC958_AES0_PROFESSIONAL |
2293                         IEC958_AES0_CON_EMPHASIS
2294 },
2295 {
2296         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2297         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2298         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2299         .info =         snd_rme96_control_spdif_mask_info,
2300         .get =          snd_rme96_control_spdif_mask_get,
2301         .private_value = IEC958_AES0_NONAUDIO |
2302                         IEC958_AES0_PROFESSIONAL |
2303                         IEC958_AES0_PRO_EMPHASIS
2304 },
2305 {
2306         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2307         .name =         "Input Connector",
2308         .info =         snd_rme96_info_inputtype_control,
2309         .get =          snd_rme96_get_inputtype_control,
2310         .put =          snd_rme96_put_inputtype_control
2311 },
2312 {
2313         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2314         .name =         "Loopback Input",
2315         .info =         snd_rme96_info_loopback_control,
2316         .get =          snd_rme96_get_loopback_control,
2317         .put =          snd_rme96_put_loopback_control
2318 },
2319 {
2320         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2321         .name =         "Sample Clock Source",
2322         .info =         snd_rme96_info_clockmode_control,
2323         .get =          snd_rme96_get_clockmode_control,
2324         .put =          snd_rme96_put_clockmode_control
2325 },
2326 {
2327         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2328         .name =         "Monitor Tracks",
2329         .info =         snd_rme96_info_montracks_control,
2330         .get =          snd_rme96_get_montracks_control,
2331         .put =          snd_rme96_put_montracks_control
2332 },
2333 {
2334         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2335         .name =         "Attenuation",
2336         .info =         snd_rme96_info_attenuation_control,
2337         .get =          snd_rme96_get_attenuation_control,
2338         .put =          snd_rme96_put_attenuation_control
2339 },
2340 {
2341         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2342         .name =         "DAC Playback Volume",
2343         .info =         snd_rme96_dac_volume_info,
2344         .get =          snd_rme96_dac_volume_get,
2345         .put =          snd_rme96_dac_volume_put
2346 }
2347 };
2348
2349 static int
2350 snd_rme96_create_switches(struct snd_card *card,
2351                           struct rme96 *rme96)
2352 {
2353         int idx, err;
2354         struct snd_kcontrol *kctl;
2355
2356         for (idx = 0; idx < 7; idx++) {
2357                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2358                         return err;
2359                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
2360                         rme96->spdif_ctl = kctl;
2361         }
2362
2363         if (RME96_HAS_ANALOG_OUT(rme96)) {
2364                 for (idx = 7; idx < 10; idx++)
2365                         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2366                                 return err;
2367         }
2368
2369         return 0;
2370 }
2371
2372 /*
2373  * Card initialisation
2374  */
2375
2376 #ifdef CONFIG_PM
2377
2378 static int
2379 snd_rme96_suspend(struct pci_dev *pci,
2380                   pm_message_t state)
2381 {
2382         struct snd_card *card = pci_get_drvdata(pci);
2383         struct rme96 *rme96 = card->private_data;
2384
2385         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2386         snd_pcm_suspend(rme96->playback_substream);
2387         snd_pcm_suspend(rme96->capture_substream);
2388
2389         /* save capture & playback pointers */
2390         rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
2391                                   & RME96_RCR_AUDIO_ADDR_MASK;
2392         rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS)
2393                                  & RME96_RCR_AUDIO_ADDR_MASK;
2394
2395         /* save playback and capture buffers */
2396         memcpy_fromio(rme96->playback_suspend_buffer,
2397                       rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE);
2398         memcpy_fromio(rme96->capture_suspend_buffer,
2399                       rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE);
2400
2401         /* disable the DAC  */
2402         rme96->areg &= ~RME96_AR_DAC_EN;
2403         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2404
2405         pci_disable_device(pci);
2406         pci_save_state(pci);
2407
2408         return 0;
2409 }
2410
2411 static int
2412 snd_rme96_resume(struct pci_dev *pci)
2413 {
2414         struct snd_card *card = pci_get_drvdata(pci);
2415         struct rme96 *rme96 = card->private_data;
2416
2417         pci_restore_state(pci);
2418         if (pci_enable_device(pci) < 0) {
2419                 printk(KERN_ERR "rme96: pci_enable_device failed, disabling device\n");
2420                 snd_card_disconnect(card);
2421                 return -EIO;
2422         }
2423
2424         /* reset playback and record buffer pointers */
2425         writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS
2426                   + rme96->playback_pointer);
2427         writel(0, rme96->iobase + RME96_IO_SET_REC_POS
2428                   + rme96->capture_pointer);
2429
2430         /* restore playback and capture buffers */
2431         memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER,
2432                     rme96->playback_suspend_buffer, RME96_BUFFER_SIZE);
2433         memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER,
2434                     rme96->capture_suspend_buffer, RME96_BUFFER_SIZE);
2435
2436         /* reset the ADC */
2437         writel(rme96->areg | RME96_AR_PD2,
2438                rme96->iobase + RME96_IO_ADDITIONAL_REG);
2439         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2440
2441         /* reset and enable DAC, restore analog volume */
2442         snd_rme96_reset_dac(rme96);
2443         rme96->areg |= RME96_AR_DAC_EN;
2444         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2445         if (RME96_HAS_ANALOG_OUT(rme96)) {
2446                 usleep_range(3000, 10000);
2447                 snd_rme96_apply_dac_volume(rme96);
2448         }
2449
2450         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2451
2452         return 0;
2453 }
2454
2455 #endif
2456
2457 static void snd_rme96_card_free(struct snd_card *card)
2458 {
2459         snd_rme96_free(card->private_data);
2460 }
2461
2462 static int
2463 snd_rme96_probe(struct pci_dev *pci,
2464                 const struct pci_device_id *pci_id)
2465 {
2466         static int dev;
2467         struct rme96 *rme96;
2468         struct snd_card *card;
2469         int err;
2470         u8 val;
2471
2472         if (dev >= SNDRV_CARDS) {
2473                 return -ENODEV;
2474         }
2475         if (!enable[dev]) {
2476                 dev++;
2477                 return -ENOENT;
2478         }
2479         err = snd_card_create(index[dev], id[dev], THIS_MODULE,
2480                               sizeof(struct rme96), &card);
2481         if (err < 0)
2482                 return err;
2483         card->private_free = snd_rme96_card_free;
2484         rme96 = card->private_data;
2485         rme96->card = card;
2486         rme96->pci = pci;
2487         snd_card_set_dev(card, &pci->dev);
2488         if ((err = snd_rme96_create(rme96)) < 0) {
2489                 snd_card_free(card);
2490                 return err;
2491         }
2492
2493 #ifdef CONFIG_PM
2494         rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2495         if (!rme96->playback_suspend_buffer) {
2496                 snd_printk(KERN_ERR
2497                            "Failed to allocate playback suspend buffer!\n");
2498                 snd_card_free(card);
2499                 return -ENOMEM;
2500         }
2501         rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2502         if (!rme96->capture_suspend_buffer) {
2503                 snd_printk(KERN_ERR
2504                            "Failed to allocate capture suspend buffer!\n");
2505                 snd_card_free(card);
2506                 return -ENOMEM;
2507         }
2508 #endif
2509
2510         strcpy(card->driver, "Digi96");
2511         switch (rme96->pci->device) {
2512         case PCI_DEVICE_ID_RME_DIGI96:
2513                 strcpy(card->shortname, "RME Digi96");
2514                 break;
2515         case PCI_DEVICE_ID_RME_DIGI96_8:
2516                 strcpy(card->shortname, "RME Digi96/8");
2517                 break;
2518         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
2519                 strcpy(card->shortname, "RME Digi96/8 PRO");
2520                 break;
2521         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
2522                 pci_read_config_byte(rme96->pci, 8, &val);
2523                 if (val < 5) {
2524                         strcpy(card->shortname, "RME Digi96/8 PAD");
2525                 } else {
2526                         strcpy(card->shortname, "RME Digi96/8 PST");
2527                 }
2528                 break;
2529         }
2530         sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2531                 rme96->port, rme96->irq);
2532
2533         if ((err = snd_card_register(card)) < 0) {
2534                 snd_card_free(card);
2535                 return err;
2536         }
2537         pci_set_drvdata(pci, card);
2538         dev++;
2539         return 0;
2540 }
2541
2542 static void snd_rme96_remove(struct pci_dev *pci)
2543 {
2544         snd_card_free(pci_get_drvdata(pci));
2545 }
2546
2547 static struct pci_driver rme96_driver = {
2548         .name = KBUILD_MODNAME,
2549         .id_table = snd_rme96_ids,
2550         .probe = snd_rme96_probe,
2551         .remove = snd_rme96_remove,
2552 #ifdef CONFIG_PM
2553         .suspend = snd_rme96_suspend,
2554         .resume = snd_rme96_resume,
2555 #endif
2556 };
2557
2558 module_pci_driver(rme96_driver);