sound/pci/rme9652/hdspm.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
   3  *
   4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
   5  *      code based on hdsp.c   Paul Davis
   6  *                             Marcus Andersson
   7  *                             Thomas Charbonnel
   8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
   9  *                                               <remy.bruno@trinnov.com>
  10  *
  11  *      Modified 2009-04-13 for proper metering by Florian Faber
  12  *                                               <faber@faberman.de>
  13  *
  14  *      Modified 2009-04-14 for native float support by Florian Faber
  15  *                                               <faber@faberman.de>
  16  *
  17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
  18  *                                               <faber@faberman.de>
  19  *
  20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
  21  *
  22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
  23  *
  24  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
  25  *
  26  *   This program is free software; you can redistribute it and/or modify
  27  *   it under the terms of the GNU General Public License as published by
  28  *   the Free Software Foundation; either version 2 of the License, or
  29  *   (at your option) any later version.
  30  *
  31  *   This program is distributed in the hope that it will be useful,
  32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  34  *   GNU General Public License for more details.
  35  *
  36  *   You should have received a copy of the GNU General Public License
  37  *   along with this program; if not, write to the Free Software
  38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  39  *
  40  */
  41 #include <linux/init.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/module.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/math64.h>
  48 #include <asm/io.h>
  49
  50 #include <sound/core.h>
  51 #include <sound/control.h>
  52 #include <sound/pcm.h>
  53 #include <sound/pcm_params.h>
  54 #include <sound/info.h>
  55 #include <sound/asoundef.h>
  56 #include <sound/rawmidi.h>
  57 #include <sound/hwdep.h>
  58 #include <sound/initval.h>
  59
  60 #include <sound/hdspm.h>
  61
  62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
  63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
  64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  65
  66 module_param_array(index, int, NULL, 0444);
  67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
  68
  69 module_param_array(id, charp, NULL, 0444);
  70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
  71
  72 module_param_array(enable, bool, NULL, 0444);
  73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
  74
  75
  76 MODULE_AUTHOR
  77 (
  78         "Winfried Ritsch <ritsch_AT_iem.at>, "
  79         "Paul Davis <paul@linuxaudiosystems.com>, "
  80         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
  81         "Remy Bruno <remy.bruno@trinnov.com>, "
  82         "Florian Faber <faberman@linuxproaudio.org>, "
  83         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
  84 );
  85 MODULE_DESCRIPTION("RME HDSPM");
  86 MODULE_LICENSE("GPL");
  87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
  88
  89 /* --- Write registers. ---
  90   These are defined as byte-offsets from the iobase value.  */
  91
  92 #define HDSPM_WR_SETTINGS             0
  93 #define HDSPM_outputBufferAddress    32
  94 #define HDSPM_inputBufferAddress     36
  95 #define HDSPM_controlRegister        64
  96 #define HDSPM_interruptConfirmation  96
  97 #define HDSPM_control2Reg            256  /* not in specs ???????? */
  98 #define HDSPM_freqReg                256  /* for AES32 */
  99 #define HDSPM_midiDataOut0           352  /* just believe in old code */
 100 #define HDSPM_midiDataOut1           356
 101 #define HDSPM_eeprom_wr              384  /* for AES32 */
 102
 103 /* DMA enable for 64 channels, only Bit 0 is relevant */
 104 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
 105 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
 106
 107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
 108    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
 109 #define HDSPM_pageAddressBufferOut       8192
 110 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
 111
 112 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
 113
 114 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
 115
 116 /* --- Read registers. ---
 117    These are defined as byte-offsets from the iobase value */
 118 #define HDSPM_statusRegister    0
 119 /*#define HDSPM_statusRegister2  96 */
 120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
 121  * offset 192, for AES32 *and* MADI
 122  * => need to check that offset 192 is working on MADI */
 123 #define HDSPM_statusRegister2  192
 124 #define HDSPM_timecodeRegister 128
 125
 126 /* AIO, RayDAT */
 127 #define HDSPM_RD_STATUS_0 0
 128 #define HDSPM_RD_STATUS_1 64
 129 #define HDSPM_RD_STATUS_2 128
 130 #define HDSPM_RD_STATUS_3 192
 131
 132 #define HDSPM_RD_TCO           256
 133 #define HDSPM_RD_PLL_FREQ      512
 134 #define HDSPM_WR_TCO           128
 135
 136 #define HDSPM_TCO1_TCO_lock                     0x00000001
 137 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
 138 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
 139 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
 140 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
 141 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
 142 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
 143
 144 #define HDSPM_TCO1_set_TC                       0x00000100
 145 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
 146 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
 147 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
 148
 149 #define HDSPM_TCO2_TC_run                       0x00010000
 150 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
 151 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
 152 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
 153 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
 154 #define HDSPM_TCO2_set_jam_sync                 0x00200000
 155 #define HDSPM_TCO2_set_flywheel                 0x00400000
 156
 157 #define HDSPM_TCO2_set_01_4                     0x01000000
 158 #define HDSPM_TCO2_set_pull_down                0x02000000
 159 #define HDSPM_TCO2_set_pull_up                  0x04000000
 160 #define HDSPM_TCO2_set_freq                     0x08000000
 161 #define HDSPM_TCO2_set_term_75R                 0x10000000
 162 #define HDSPM_TCO2_set_input_LSB                0x20000000
 163 #define HDSPM_TCO2_set_input_MSB                0x40000000
 164 #define HDSPM_TCO2_set_freq_from_app            0x80000000
 165
 166
 167 #define HDSPM_midiDataOut0    352
 168 #define HDSPM_midiDataOut1    356
 169 #define HDSPM_midiDataOut2    368
 170
 171 #define HDSPM_midiDataIn0     360
 172 #define HDSPM_midiDataIn1     364
 173 #define HDSPM_midiDataIn2     372
 174 #define HDSPM_midiDataIn3     376
 175
 176 /* status is data bytes in MIDI-FIFO (0-128) */
 177 #define HDSPM_midiStatusOut0  384
 178 #define HDSPM_midiStatusOut1  388
 179 #define HDSPM_midiStatusOut2  400
 180
 181 #define HDSPM_midiStatusIn0   392
 182 #define HDSPM_midiStatusIn1   396
 183 #define HDSPM_midiStatusIn2   404
 184 #define HDSPM_midiStatusIn3   408
 185
 186
 187 /* the meters are regular i/o-mapped registers, but offset
 188    considerably from the rest. the peak registers are reset
 189    when read; the least-significant 4 bits are full-scale counters;
 190    the actual peak value is in the most-significant 24 bits.
 191 */
 192
 193 #define HDSPM_MADI_INPUT_PEAK           4096
 194 #define HDSPM_MADI_PLAYBACK_PEAK        4352
 195 #define HDSPM_MADI_OUTPUT_PEAK          4608
 196
 197 #define HDSPM_MADI_INPUT_RMS_L          6144
 198 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
 199 #define HDSPM_MADI_OUTPUT_RMS_L         6656
 200
 201 #define HDSPM_MADI_INPUT_RMS_H          7168
 202 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
 203 #define HDSPM_MADI_OUTPUT_RMS_H         7680
 204
 205 /* --- Control Register bits --------- */
 206 #define HDSPM_Start                (1<<0) /* start engine */
 207
 208 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
 209 #define HDSPM_Latency1             (1<<2) /* where n is defined */
 210 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
 211
 212 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
 213 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
 214                                           register [RayDAT, AIO] */
 215
 216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
 217
 218 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
 219 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
 220 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
 221 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
 222
 223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
 224 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
 225                                      56channelMODE=0 */ /* MADI ONLY*/
 226 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
 227
 228 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
 229                                      0=off, 1=on  */ /* MADI ONLY */
 230 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
 231
 232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
 233                                     * -- MADI ONLY
 234                                     */
 235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
 236
 237 #define HDSPM_SyncRef2     (1<<13)
 238 #define HDSPM_SyncRef3     (1<<25)
 239
 240 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
 241 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
 242                                       AES additional bits in
 243                                       lower 5 Audiodatabits ??? */
 244 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
 245 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
 246
 247 #define HDSPM_Midi0InterruptEnable 0x0400000
 248 #define HDSPM_Midi1InterruptEnable 0x0800000
 249 #define HDSPM_Midi2InterruptEnable 0x0200000
 250 #define HDSPM_Midi3InterruptEnable 0x4000000
 251
 252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
 253 #define HDSPe_FLOAT_FORMAT         0x2000000
 254
 255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
 256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
 257 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
 258
 259 #define HDSPM_wclk_sel (1<<30)
 260
 261 /* additional control register bits for AIO*/
 262 #define HDSPM_c0_Wck48                          0x20 /* also RayDAT */
 263 #define HDSPM_c0_Input0                         0x1000
 264 #define HDSPM_c0_Input1                         0x2000
 265 #define HDSPM_c0_Spdif_Opt                      0x4000
 266 #define HDSPM_c0_Pro                            0x8000
 267 #define HDSPM_c0_clr_tms                        0x10000
 268 #define HDSPM_c0_AEB1                           0x20000
 269 #define HDSPM_c0_AEB2                           0x40000
 270 #define HDSPM_c0_LineOut                        0x80000
 271 #define HDSPM_c0_AD_GAIN0                       0x100000
 272 #define HDSPM_c0_AD_GAIN1                       0x200000
 273 #define HDSPM_c0_DA_GAIN0                       0x400000
 274 #define HDSPM_c0_DA_GAIN1                       0x800000
 275 #define HDSPM_c0_PH_GAIN0                       0x1000000
 276 #define HDSPM_c0_PH_GAIN1                       0x2000000
 277 #define HDSPM_c0_Sym6db                         0x4000000
 278
 279
 280 /* --- bit helper defines */
 281 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
 282 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
 283                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
 284 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
 285 #define HDSPM_InputOptical   0
 286 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
 287 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
 288                               HDSPM_SyncRef2|HDSPM_SyncRef3)
 289
 290 #define HDSPM_c0_SyncRef0      0x2
 291 #define HDSPM_c0_SyncRef1      0x4
 292 #define HDSPM_c0_SyncRef2      0x8
 293 #define HDSPM_c0_SyncRef3      0x10
 294 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
 295                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
 296
 297 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
 298 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
 299 #define HDSPM_SYNC_FROM_TCO     2
 300 #define HDSPM_SYNC_FROM_SYNC_IN 3
 301
 302 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
 303 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
 304 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
 305 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
 306 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
 307 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
 308                                 HDSPM_Frequency0)
 309 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
 310 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
 311 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
 312                                  HDSPM_Frequency0)
 313
 314
 315 /* Synccheck Status */
 316 #define HDSPM_SYNC_CHECK_NO_LOCK 0
 317 #define HDSPM_SYNC_CHECK_LOCK    1
 318 #define HDSPM_SYNC_CHECK_SYNC    2
 319
 320 /* AutoSync References - used by "autosync_ref" control switch */
 321 #define HDSPM_AUTOSYNC_FROM_WORD      0
 322 #define HDSPM_AUTOSYNC_FROM_MADI      1
 323 #define HDSPM_AUTOSYNC_FROM_TCO       2
 324 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
 325 #define HDSPM_AUTOSYNC_FROM_NONE      4
 326
 327 /* Possible sources of MADI input */
 328 #define HDSPM_OPTICAL 0         /* optical   */
 329 #define HDSPM_COAXIAL 1         /* BNC */
 330
 331 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
 332 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
 333
 334 #define hdspm_encode_in(x) (((x)&0x3)<<14)
 335 #define hdspm_decode_in(x) (((x)>>14)&0x3)
 336
 337 /* --- control2 register bits --- */
 338 #define HDSPM_TMS             (1<<0)
 339 #define HDSPM_TCK             (1<<1)
 340 #define HDSPM_TDI             (1<<2)
 341 #define HDSPM_JTAG            (1<<3)
 342 #define HDSPM_PWDN            (1<<4)
 343 #define HDSPM_PROGRAM         (1<<5)
 344 #define HDSPM_CONFIG_MODE_0   (1<<6)
 345 #define HDSPM_CONFIG_MODE_1   (1<<7)
 346 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
 347 #define HDSPM_BIGENDIAN_MODE  (1<<9)
 348 #define HDSPM_RD_MULTIPLE     (1<<10)
 349
 350 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
 351      that do not conflict with specific bits for AES32 seem to be valid also
 352      for the AES32
 353  */
 354 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
 355 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
 356 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
 357                                          * (like inp0)
 358                                          */
 359
 360 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
 361 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
 362
 363 #define HDSPM_tcoLock    0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
 364 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status */
 365
 366 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
 367 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
 368
 369 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 370                         /* since 64byte accurate, last 6 bits are not used */
 371
 372
 373
 374 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
 375
 376 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
 377 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
 378 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
 379 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
 380
 381 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
 382                                          * Interrupt
 383                                          */
 384 #define HDSPM_tco_detect         0x08000000
 385 #define HDSPM_tco_lock           0x20000000
 386
 387 #define HDSPM_s2_tco_detect      0x00000040
 388 #define HDSPM_s2_AEBO_D          0x00000080
 389 #define HDSPM_s2_AEBI_D          0x00000100
 390
 391
 392 #define HDSPM_midi0IRQPending    0x40000000
 393 #define HDSPM_midi1IRQPending    0x80000000
 394 #define HDSPM_midi2IRQPending    0x20000000
 395 #define HDSPM_midi2IRQPendingAES 0x00000020
 396 #define HDSPM_midi3IRQPending    0x00200000
 397
 398 /* --- status bit helpers */
 399 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
 400                              HDSPM_madiFreq2|HDSPM_madiFreq3)
 401 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
 402 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
 403 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
 404 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
 405 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
 406 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
 407 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
 408 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
 409 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
 410
 411 /* Status2 Register bits */ /* MADI ONLY */
 412
 413 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
 414 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
 415 #define HDSPM_version2 (1<<2)
 416
 417 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
 418 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
 419
 420 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
 421 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
 422 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, 111=128 */
 423 #define HDSPM_wc_freq3 0x800    /* 1000=176.4, 1001=192 */
 424
 425 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
 426 #define HDSPM_SyncRef1 0x20000
 427
 428 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
 429 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
 430 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
 431
 432 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
 433
 434 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
 435                             HDSPM_wc_freq3)
 436 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
 437 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
 438 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
 439 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
 440 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
 441 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
 442 #define HDSPM_wcFreq128   (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
 443 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
 444 #define HDSPM_wcFreq192   (HDSPM_wc_freq0|HDSPM_wc_freq3)
 445
 446 #define HDSPM_status1_F_0 0x0400000
 447 #define HDSPM_status1_F_1 0x0800000
 448 #define HDSPM_status1_F_2 0x1000000
 449 #define HDSPM_status1_F_3 0x2000000
 450 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
 451
 452
 453 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 454                                     HDSPM_SelSyncRef2)
 455 #define HDSPM_SelSyncRef_WORD      0
 456 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
 457 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
 458 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
 459 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 460                                     HDSPM_SelSyncRef2)
 461
 462 /*
 463    For AES32, bits for status, status2 and timecode are different
 464 */
 465 /* status */
 466 #define HDSPM_AES32_wcLock      0x0200000
 467 #define HDSPM_AES32_wcSync      0x0100000
 468 #define HDSPM_AES32_wcFreq_bit  22
 469 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
 470   HDSPM_bit2freq */
 471 #define HDSPM_AES32_syncref_bit  16
 472 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
 473
 474 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
 475 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
 476 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
 477 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
 478 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
 479 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
 480 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
 481 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
 482 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
 483 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
 484
 485 /*  status2 */
 486 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
 487 #define HDSPM_LockAES   0x80
 488 #define HDSPM_LockAES1  0x80
 489 #define HDSPM_LockAES2  0x40
 490 #define HDSPM_LockAES3  0x20
 491 #define HDSPM_LockAES4  0x10
 492 #define HDSPM_LockAES5  0x8
 493 #define HDSPM_LockAES6  0x4
 494 #define HDSPM_LockAES7  0x2
 495 #define HDSPM_LockAES8  0x1
 496 /*
 497    Timecode
 498    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
 499    AES i+1
 500  bits 3210
 501       0001  32kHz
 502       0010  44.1kHz
 503       0011  48kHz
 504       0100  64kHz
 505       0101  88.2kHz
 506       0110  96kHz
 507       0111  128kHz
 508       1000  176.4kHz
 509       1001  192kHz
 510   NB: Timecode register doesn't seem to work on AES32 card revision 230
 511 */
 512
 513 /* Mixer Values */
 514 #define UNITY_GAIN          32768       /* = 65536/2 */
 515 #define MINUS_INFINITY_GAIN 0
 516
 517 /* Number of channels for different Speed Modes */
 518 #define MADI_SS_CHANNELS       64
 519 #define MADI_DS_CHANNELS       32
 520 #define MADI_QS_CHANNELS       16
 521
 522 #define RAYDAT_SS_CHANNELS     36
 523 #define RAYDAT_DS_CHANNELS     20
 524 #define RAYDAT_QS_CHANNELS     12
 525
 526 #define AIO_IN_SS_CHANNELS        14
 527 #define AIO_IN_DS_CHANNELS        10
 528 #define AIO_IN_QS_CHANNELS        8
 529 #define AIO_OUT_SS_CHANNELS        16
 530 #define AIO_OUT_DS_CHANNELS        12
 531 #define AIO_OUT_QS_CHANNELS        10
 532
 533 #define AES32_CHANNELS          16
 534
 535 /* the size of a substream (1 mono data stream) */
 536 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
 537 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
 538
 539 /* the size of the area we need to allocate for DMA transfers. the
 540    size is the same regardless of the number of channels, and
 541    also the latency to use.
 542    for one direction !!!
 543 */
 544 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
 545 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
 546
 547 #define HDSPM_RAYDAT_REV        211
 548 #define HDSPM_AIO_REV           212
 549 #define HDSPM_MADIFACE_REV      213
 550
 551 /* speed factor modes */
 552 #define HDSPM_SPEED_SINGLE 0
 553 #define HDSPM_SPEED_DOUBLE 1
 554 #define HDSPM_SPEED_QUAD   2
 555
 556 /* names for speed modes */
 557 static char *hdspm_speed_names[] = { "single", "double", "quad" };
 558
 559 static char *texts_autosync_aes_tco[] = { "Word Clock",
 560                                           "AES1", "AES2", "AES3", "AES4",
 561                                           "AES5", "AES6", "AES7", "AES8",
 562                                           "TCO" };
 563 static char *texts_autosync_aes[] = { "Word Clock",
 564                                       "AES1", "AES2", "AES3", "AES4",
 565                                       "AES5", "AES6", "AES7", "AES8" };
 566 static char *texts_autosync_madi_tco[] = { "Word Clock",
 567                                            "MADI", "TCO", "Sync In" };
 568 static char *texts_autosync_madi[] = { "Word Clock",
 569                                        "MADI", "Sync In" };
 570
 571 static char *texts_autosync_raydat_tco[] = {
 572         "Word Clock",
 573         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 574         "AES", "SPDIF", "TCO", "Sync In"
 575 };
 576 static char *texts_autosync_raydat[] = {
 577         "Word Clock",
 578         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 579         "AES", "SPDIF", "Sync In"
 580 };
 581 static char *texts_autosync_aio_tco[] = {
 582         "Word Clock",
 583         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
 584 };
 585 static char *texts_autosync_aio[] = { "Word Clock",
 586                                       "ADAT", "AES", "SPDIF", "Sync In" };
 587
 588 static char *texts_freq[] = {
 589         "No Lock",
 590         "32 kHz",
 591         "44.1 kHz",
 592         "48 kHz",
 593         "64 kHz",
 594         "88.2 kHz",
 595         "96 kHz",
 596         "128 kHz",
 597         "176.4 kHz",
 598         "192 kHz"
 599 };
 600
 601 static char *texts_ports_madi[] = {
 602         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
 603         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
 604         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
 605         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
 606         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
 607         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
 608         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
 609         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
 610         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
 611         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
 612         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
 613 };
 614
 615
 616 static char *texts_ports_raydat_ss[] = {
 617         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
 618         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 619         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
 620         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
 621         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
 622         "ADAT4.7", "ADAT4.8",
 623         "AES.L", "AES.R",
 624         "SPDIF.L", "SPDIF.R"
 625 };
 626
 627 static char *texts_ports_raydat_ds[] = {
 628         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
 629         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 630         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
 631         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
 632         "AES.L", "AES.R",
 633         "SPDIF.L", "SPDIF.R"
 634 };
 635
 636 static char *texts_ports_raydat_qs[] = {
 637         "ADAT1.1", "ADAT1.2",
 638         "ADAT2.1", "ADAT2.2",
 639         "ADAT3.1", "ADAT3.2",
 640         "ADAT4.1", "ADAT4.2",
 641         "AES.L", "AES.R",
 642         "SPDIF.L", "SPDIF.R"
 643 };
 644
 645
 646 static char *texts_ports_aio_in_ss[] = {
 647         "Analogue.L", "Analogue.R",
 648         "AES.L", "AES.R",
 649         "SPDIF.L", "SPDIF.R",
 650         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 651         "ADAT.7", "ADAT.8",
 652         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 653 };
 654
 655 static char *texts_ports_aio_out_ss[] = {
 656         "Analogue.L", "Analogue.R",
 657         "AES.L", "AES.R",
 658         "SPDIF.L", "SPDIF.R",
 659         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 660         "ADAT.7", "ADAT.8",
 661         "Phone.L", "Phone.R",
 662         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 663 };
 664
 665 static char *texts_ports_aio_in_ds[] = {
 666         "Analogue.L", "Analogue.R",
 667         "AES.L", "AES.R",
 668         "SPDIF.L", "SPDIF.R",
 669         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 670         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 671 };
 672
 673 static char *texts_ports_aio_out_ds[] = {
 674         "Analogue.L", "Analogue.R",
 675         "AES.L", "AES.R",
 676         "SPDIF.L", "SPDIF.R",
 677         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 678         "Phone.L", "Phone.R",
 679         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 680 };
 681
 682 static char *texts_ports_aio_in_qs[] = {
 683         "Analogue.L", "Analogue.R",
 684         "AES.L", "AES.R",
 685         "SPDIF.L", "SPDIF.R",
 686         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 687         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 688 };
 689
 690 static char *texts_ports_aio_out_qs[] = {
 691         "Analogue.L", "Analogue.R",
 692         "AES.L", "AES.R",
 693         "SPDIF.L", "SPDIF.R",
 694         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 695         "Phone.L", "Phone.R",
 696         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 697 };
 698
 699 static char *texts_ports_aes32[] = {
 700         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
 701         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
 702         "AES.15", "AES.16"
 703 };
 704
 705 /* These tables map the ALSA channels 1..N to the channels that we
 706    need to use in order to find the relevant channel buffer. RME
 707    refers to this kind of mapping as between "the ADAT channel and
 708    the DMA channel." We index it using the logical audio channel,
 709    and the value is the DMA channel (i.e. channel buffer number)
 710    where the data for that channel can be read/written from/to.
 711 */
 712
 713 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
 714         0, 1, 2, 3, 4, 5, 6, 7,
 715         8, 9, 10, 11, 12, 13, 14, 15,
 716         16, 17, 18, 19, 20, 21, 22, 23,
 717         24, 25, 26, 27, 28, 29, 30, 31,
 718         32, 33, 34, 35, 36, 37, 38, 39,
 719         40, 41, 42, 43, 44, 45, 46, 47,
 720         48, 49, 50, 51, 52, 53, 54, 55,
 721         56, 57, 58, 59, 60, 61, 62, 63
 722 };
 723
 724 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
 725         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
 726         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
 727         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
 728         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
 729         0, 1,                   /* AES */
 730         2, 3,                   /* SPDIF */
 731         -1, -1, -1, -1,
 732         -1, -1, -1, -1, -1, -1, -1, -1,
 733         -1, -1, -1, -1, -1, -1, -1, -1,
 734         -1, -1, -1, -1, -1, -1, -1, -1,
 735 };
 736
 737 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
 738         4, 5, 6, 7,             /* ADAT 1 */
 739         8, 9, 10, 11,           /* ADAT 2 */
 740         12, 13, 14, 15,         /* ADAT 3 */
 741         16, 17, 18, 19,         /* ADAT 4 */
 742         0, 1,                   /* AES */
 743         2, 3,                   /* SPDIF */
 744         -1, -1, -1, -1,
 745         -1, -1, -1, -1, -1, -1, -1, -1,
 746         -1, -1, -1, -1, -1, -1, -1, -1,
 747         -1, -1, -1, -1, -1, -1, -1, -1,
 748         -1, -1, -1, -1, -1, -1, -1, -1,
 749         -1, -1, -1, -1, -1, -1, -1, -1,
 750 };
 751
 752 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
 753         4, 5,                   /* ADAT 1 */
 754         6, 7,                   /* ADAT 2 */
 755         8, 9,                   /* ADAT 3 */
 756         10, 11,                 /* ADAT 4 */
 757         0, 1,                   /* AES */
 758         2, 3,                   /* SPDIF */
 759         -1, -1, -1, -1,
 760         -1, -1, -1, -1, -1, -1, -1, -1,
 761         -1, -1, -1, -1, -1, -1, -1, -1,
 762         -1, -1, -1, -1, -1, -1, -1, -1,
 763         -1, -1, -1, -1, -1, -1, -1, -1,
 764         -1, -1, -1, -1, -1, -1, -1, -1,
 765         -1, -1, -1, -1, -1, -1, -1, -1,
 766 };
 767
 768 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
 769         0, 1,                   /* line in */
 770         8, 9,                   /* aes in, */
 771         10, 11,                 /* spdif in */
 772         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
 773         2, 3, 4, 5,             /* AEB */
 774         -1, -1, -1, -1, -1, -1,
 775         -1, -1, -1, -1, -1, -1, -1, -1,
 776         -1, -1, -1, -1, -1, -1, -1, -1,
 777         -1, -1, -1, -1, -1, -1, -1, -1,
 778         -1, -1, -1, -1, -1, -1, -1, -1,
 779         -1, -1, -1, -1, -1, -1, -1, -1,
 780 };
 781
 782 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
 783         0, 1,                   /* line out */
 784         8, 9,                   /* aes out */
 785         10, 11,                 /* spdif out */
 786         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
 787         6, 7,                   /* phone out */
 788         2, 3, 4, 5,             /* AEB */
 789         -1, -1, -1, -1,
 790         -1, -1, -1, -1, -1, -1, -1, -1,
 791         -1, -1, -1, -1, -1, -1, -1, -1,
 792         -1, -1, -1, -1, -1, -1, -1, -1,
 793         -1, -1, -1, -1, -1, -1, -1, -1,
 794         -1, -1, -1, -1, -1, -1, -1, -1,
 795 };
 796
 797 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
 798         0, 1,                   /* line in */
 799         8, 9,                   /* aes in */
 800         10, 11,                 /* spdif in */
 801         12, 14, 16, 18,         /* adat in */
 802         2, 3, 4, 5,             /* AEB */
 803         -1, -1,
 804         -1, -1, -1, -1, -1, -1, -1, -1,
 805         -1, -1, -1, -1, -1, -1, -1, -1,
 806         -1, -1, -1, -1, -1, -1, -1, -1,
 807         -1, -1, -1, -1, -1, -1, -1, -1,
 808         -1, -1, -1, -1, -1, -1, -1, -1,
 809         -1, -1, -1, -1, -1, -1, -1, -1
 810 };
 811
 812 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
 813         0, 1,                   /* line out */
 814         8, 9,                   /* aes out */
 815         10, 11,                 /* spdif out */
 816         12, 14, 16, 18,         /* adat out */
 817         6, 7,                   /* phone out */
 818         2, 3, 4, 5,             /* AEB */
 819         -1, -1, -1, -1, -1, -1, -1, -1,
 820         -1, -1, -1, -1, -1, -1, -1, -1,
 821         -1, -1, -1, -1, -1, -1, -1, -1,
 822         -1, -1, -1, -1, -1, -1, -1, -1,
 823         -1, -1, -1, -1, -1, -1, -1, -1,
 824         -1, -1, -1, -1, -1, -1, -1, -1
 825 };
 826
 827 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
 828         0, 1,                   /* line in */
 829         8, 9,                   /* aes in */
 830         10, 11,                 /* spdif in */
 831         12, 16,                 /* adat in */
 832         2, 3, 4, 5,             /* AEB */
 833         -1, -1, -1, -1,
 834         -1, -1, -1, -1, -1, -1, -1, -1,
 835         -1, -1, -1, -1, -1, -1, -1, -1,
 836         -1, -1, -1, -1, -1, -1, -1, -1,
 837         -1, -1, -1, -1, -1, -1, -1, -1,
 838         -1, -1, -1, -1, -1, -1, -1, -1,
 839         -1, -1, -1, -1, -1, -1, -1, -1
 840 };
 841
 842 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
 843         0, 1,                   /* line out */
 844         8, 9,                   /* aes out */
 845         10, 11,                 /* spdif out */
 846         12, 16,                 /* adat out */
 847         6, 7,                   /* phone out */
 848         2, 3, 4, 5,             /* AEB */
 849         -1, -1,
 850         -1, -1, -1, -1, -1, -1, -1, -1,
 851         -1, -1, -1, -1, -1, -1, -1, -1,
 852         -1, -1, -1, -1, -1, -1, -1, -1,
 853         -1, -1, -1, -1, -1, -1, -1, -1,
 854         -1, -1, -1, -1, -1, -1, -1, -1,
 855         -1, -1, -1, -1, -1, -1, -1, -1
 856 };
 857
 858 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
 859         0, 1, 2, 3, 4, 5, 6, 7,
 860         8, 9, 10, 11, 12, 13, 14, 15,
 861         -1, -1, -1, -1, -1, -1, -1, -1,
 862         -1, -1, -1, -1, -1, -1, -1, -1,
 863         -1, -1, -1, -1, -1, -1, -1, -1,
 864         -1, -1, -1, -1, -1, -1, -1, -1,
 865         -1, -1, -1, -1, -1, -1, -1, -1,
 866         -1, -1, -1, -1, -1, -1, -1, -1
 867 };
 868
 869 struct hdspm_midi {
 870         struct hdspm *hdspm;
 871         int id;
 872         struct snd_rawmidi *rmidi;
 873         struct snd_rawmidi_substream *input;
 874         struct snd_rawmidi_substream *output;
 875         char istimer;           /* timer in use */
 876         struct timer_list timer;
 877         spinlock_t lock;
 878         int pending;
 879         int dataIn;
 880         int statusIn;
 881         int dataOut;
 882         int statusOut;
 883         int ie;
 884         int irq;
 885 };
 886
 887 struct hdspm_tco {
 888         int input;
 889         int framerate;
 890         int wordclock;
 891         int samplerate;
 892         int pull;
 893         int term; /* 0 = off, 1 = on */
 894 };
 895
 896 struct hdspm {
 897         spinlock_t lock;
 898         /* only one playback and/or capture stream */
 899         struct snd_pcm_substream *capture_substream;
 900         struct snd_pcm_substream *playback_substream;
 901
 902         char *card_name;             /* for procinfo */
 903         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
 904
 905         uint8_t io_type;
 906
 907         int monitor_outs;       /* set up monitoring outs init flag */
 908
 909         u32 control_register;   /* cached value */
 910         u32 control2_register;  /* cached value */
 911         u32 settings_register;
 912
 913         struct hdspm_midi midi[4];
 914         struct tasklet_struct midi_tasklet;
 915
 916         size_t period_bytes;
 917         unsigned char ss_in_channels;
 918         unsigned char ds_in_channels;
 919         unsigned char qs_in_channels;
 920         unsigned char ss_out_channels;
 921         unsigned char ds_out_channels;
 922         unsigned char qs_out_channels;
 923
 924         unsigned char max_channels_in;
 925         unsigned char max_channels_out;
 926
 927         signed char *channel_map_in;
 928         signed char *channel_map_out;
 929
 930         signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
 931         signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
 932
 933         char **port_names_in;
 934         char **port_names_out;
 935
 936         char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
 937         char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
 938
 939         unsigned char *playback_buffer; /* suitably aligned address */
 940         unsigned char *capture_buffer;  /* suitably aligned address */
 941
 942         pid_t capture_pid;      /* process id which uses capture */
 943         pid_t playback_pid;     /* process id which uses capture */
 944         int running;            /* running status */
 945
 946         int last_external_sample_rate;  /* samplerate mystic ... */
 947         int last_internal_sample_rate;
 948         int system_sample_rate;
 949
 950         int dev;                /* Hardware vars... */
 951         int irq;
 952         unsigned long port;
 953         void __iomem *iobase;
 954
 955         int irq_count;          /* for debug */
 956         int midiPorts;
 957
 958         struct snd_card *card;  /* one card */
 959         struct snd_pcm *pcm;            /* has one pcm */
 960         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
 961         struct pci_dev *pci;    /* and an pci info */
 962
 963         /* Mixer vars */
 964         /* fast alsa mixer */
 965         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
 966         /* but input to much, so not used */
 967         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
 968         /* full mixer accessible over mixer ioctl or hwdep-device */
 969         struct hdspm_mixer *mixer;
 970
 971         struct hdspm_tco *tco;  /* NULL if no TCO detected */
 972
 973         char **texts_autosync;
 974         int texts_autosync_items;
 975
 976         cycles_t last_interrupt;
 977
 978         unsigned int serial;
 979
 980         struct hdspm_peak_rms peak_rms;
 981 };
 982
 983
 984 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
 985         {
 986          .vendor = PCI_VENDOR_ID_XILINX,
 987          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
 988          .subvendor = PCI_ANY_ID,
 989          .subdevice = PCI_ANY_ID,
 990          .class = 0,
 991          .class_mask = 0,
 992          .driver_data = 0},
 993         {0,}
 994 };
 995
 996 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
 997
 998 /* prototypes */
 999 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
1000                                          struct hdspm *hdspm);
1001 static int snd_hdspm_create_pcm(struct snd_card *card,
1002                                 struct hdspm *hdspm);
1003
1004 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
1005 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
1006 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
1007 static int hdspm_autosync_ref(struct hdspm *hdspm);
1008 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
1009 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
1010 static int hdspm_system_clock_mode(struct hdspm *hdspm);
1011 static void hdspm_set_sgbuf(struct hdspm *hdspm,
1012                             struct snd_pcm_substream *substream,
1013                              unsigned int reg, int channels);
1014
1015 static inline int HDSPM_bit2freq(int n)
1016 {
1017         static const int bit2freq_tab[] = {
1018                 0, 32000, 44100, 48000, 64000, 88200,
1019                 96000, 128000, 176400, 192000 };
1020         if (n < 1 || n > 9)
1021                 return 0;
1022         return bit2freq_tab[n];
1023 }
1024
1025 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1026 {
1027         return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1028 }
1029
1030
1031 /* Write/read to/from HDSPM with Adresses in Bytes
1032    not words but only 32Bit writes are allowed */
1033
1034 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
1035                                unsigned int val)
1036 {
1037         writel(val, hdspm->iobase + reg);
1038 }
1039
1040 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1041 {
1042         return readl(hdspm->iobase + reg);
1043 }
1044
1045 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1046    mixer is write only on hardware so we have to cache him for read
1047    each fader is a u32, but uses only the first 16 bit */
1048
1049 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1050                                      unsigned int in)
1051 {
1052         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1053                 return 0;
1054
1055         return hdspm->mixer->ch[chan].in[in];
1056 }
1057
1058 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1059                                      unsigned int pb)
1060 {
1061         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1062                 return 0;
1063         return hdspm->mixer->ch[chan].pb[pb];
1064 }
1065
1066 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1067                                       unsigned int in, unsigned short data)
1068 {
1069         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1070                 return -1;
1071
1072         hdspm_write(hdspm,
1073                     HDSPM_MADI_mixerBase +
1074                     ((in + 128 * chan) * sizeof(u32)),
1075                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1076         return 0;
1077 }
1078
1079 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1080                                       unsigned int pb, unsigned short data)
1081 {
1082         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1083                 return -1;
1084
1085         hdspm_write(hdspm,
1086                     HDSPM_MADI_mixerBase +
1087                     ((64 + pb + 128 * chan) * sizeof(u32)),
1088                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1089         return 0;
1090 }
1091
1092
1093 /* enable DMA for specific channels, now available for DSP-MADI */
1094 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1095 {
1096         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1097 }
1098
1099 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1100 {
1101         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1102 }
1103
1104 /* check if same process is writing and reading */
1105 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1106 {
1107         unsigned long flags;
1108         int ret = 1;
1109
1110         spin_lock_irqsave(&hdspm->lock, flags);
1111         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1112             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1113                 ret = 0;
1114         }
1115         spin_unlock_irqrestore(&hdspm->lock, flags);
1116         return ret;
1117 }
1118
1119 /* round arbitary sample rates to commonly known rates */
1120 static int hdspm_round_frequency(int rate)
1121 {
1122         if (rate < 38050)
1123                 return 32000;
1124         if (rate < 46008)
1125                 return 44100;
1126         else
1127                 return 48000;
1128 }
1129
1130 /* QS and DS rates normally can not be detected
1131  * automatically by the card. Only exception is MADI
1132  * in 96k frame mode.
1133  *
1134  * So if we read SS values (32 .. 48k), check for
1135  * user-provided DS/QS bits in the control register
1136  * and multiply the base frequency accordingly.
1137  */
1138 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1139 {
1140         if (rate <= 48000) {
1141                 if (hdspm->control_register & HDSPM_QuadSpeed)
1142                         return rate * 4;
1143                 else if (hdspm->control_register &
1144                                 HDSPM_DoubleSpeed)
1145                         return rate * 2;
1146         };
1147         return rate;
1148 }
1149
1150 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1151 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1152
1153 /* check for external sample rate */
1154 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1155 {
1156         unsigned int status, status2, timecode;
1157         int syncref, rate = 0, rate_bits;
1158
1159         switch (hdspm->io_type) {
1160         case AES32:
1161                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1162                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1163                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1164
1165                 syncref = hdspm_autosync_ref(hdspm);
1166
1167                 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1168                                 status & HDSPM_AES32_wcLock)
1169                         return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1170
1171                 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1172                                 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1173                                 status2 & (HDSPM_LockAES >>
1174                                 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1175                         return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1176                 return 0;
1177                 break;
1178
1179         case MADIface:
1180                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1181
1182                 if (!(status & HDSPM_madiLock)) {
1183                         rate = 0;  /* no lock */
1184                 } else {
1185                         switch (status & (HDSPM_status1_freqMask)) {
1186                         case HDSPM_status1_F_0*1:
1187                                 rate = 32000; break;
1188                         case HDSPM_status1_F_0*2:
1189                                 rate = 44100; break;
1190                         case HDSPM_status1_F_0*3:
1191                                 rate = 48000; break;
1192                         case HDSPM_status1_F_0*4:
1193                                 rate = 64000; break;
1194                         case HDSPM_status1_F_0*5:
1195                                 rate = 88200; break;
1196                         case HDSPM_status1_F_0*6:
1197                                 rate = 96000; break;
1198                         case HDSPM_status1_F_0*7:
1199                                 rate = 128000; break;
1200                         case HDSPM_status1_F_0*8:
1201                                 rate = 176400; break;
1202                         case HDSPM_status1_F_0*9:
1203                                 rate = 192000; break;
1204                         default:
1205                                 rate = 0; break;
1206                         }
1207                 }
1208
1209                 break;
1210
1211         case MADI:
1212         case AIO:
1213         case RayDAT:
1214                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1215                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1216                 rate = 0;
1217
1218                 /* if wordclock has synced freq and wordclock is valid */
1219                 if ((status2 & HDSPM_wcLock) != 0 &&
1220                                 (status2 & HDSPM_SelSyncRef0) == 0) {
1221
1222                         rate_bits = status2 & HDSPM_wcFreqMask;
1223
1224
1225                         switch (rate_bits) {
1226                         case HDSPM_wcFreq32:
1227                                 rate = 32000;
1228                                 break;
1229                         case HDSPM_wcFreq44_1:
1230                                 rate = 44100;
1231                                 break;
1232                         case HDSPM_wcFreq48:
1233                                 rate = 48000;
1234                                 break;
1235                         case HDSPM_wcFreq64:
1236                                 rate = 64000;
1237                                 break;
1238                         case HDSPM_wcFreq88_2:
1239                                 rate = 88200;
1240                                 break;
1241                         case HDSPM_wcFreq96:
1242                                 rate = 96000;
1243                                 break;
1244                         case HDSPM_wcFreq128:
1245                                 rate = 128000;
1246                                 break;
1247                         case HDSPM_wcFreq176_4:
1248                                 rate = 176400;
1249                                 break;
1250                         case HDSPM_wcFreq192:
1251                                 rate = 192000;
1252                                 break;
1253                         default:
1254                                 rate = 0;
1255                                 break;
1256                         }
1257                 }
1258
1259                 /* if rate detected and Syncref is Word than have it,
1260                  * word has priority to MADI
1261                  */
1262                 if (rate != 0 &&
1263                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1264                         return hdspm_rate_multiplier(hdspm, rate);
1265
1266                 /* maybe a madi input (which is taken if sel sync is madi) */
1267                 if (status & HDSPM_madiLock) {
1268                         rate_bits = status & HDSPM_madiFreqMask;
1269
1270                         switch (rate_bits) {
1271                         case HDSPM_madiFreq32:
1272                                 rate = 32000;
1273                                 break;
1274                         case HDSPM_madiFreq44_1:
1275                                 rate = 44100;
1276                                 break;
1277                         case HDSPM_madiFreq48:
1278                                 rate = 48000;
1279                                 break;
1280                         case HDSPM_madiFreq64:
1281                                 rate = 64000;
1282                                 break;
1283                         case HDSPM_madiFreq88_2:
1284                                 rate = 88200;
1285                                 break;
1286                         case HDSPM_madiFreq96:
1287                                 rate = 96000;
1288                                 break;
1289                         case HDSPM_madiFreq128:
1290                                 rate = 128000;
1291                                 break;
1292                         case HDSPM_madiFreq176_4:
1293                                 rate = 176400;
1294                                 break;
1295                         case HDSPM_madiFreq192:
1296                                 rate = 192000;
1297                                 break;
1298                         default:
1299                                 rate = 0;
1300                                 break;
1301                         }
1302
1303                 } /* endif HDSPM_madiLock */
1304
1305                 /* check sample rate from TCO or SYNC_IN */
1306                 {
1307                         bool is_valid_input = 0;
1308                         bool has_sync = 0;
1309
1310                         syncref = hdspm_autosync_ref(hdspm);
1311                         if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1312                                 is_valid_input = 1;
1313                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1314                                         hdspm_tco_sync_check(hdspm));
1315                         } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1316                                 is_valid_input = 1;
1317                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1318                                         hdspm_sync_in_sync_check(hdspm));
1319                         }
1320
1321                         if (is_valid_input && has_sync) {
1322                                 rate = hdspm_round_frequency(
1323                                         hdspm_get_pll_freq(hdspm));
1324                         }
1325                 }
1326
1327                 rate = hdspm_rate_multiplier(hdspm, rate);
1328
1329                 break;
1330         }
1331
1332         return rate;
1333 }
1334
1335 /* return latency in samples per period */
1336 static int hdspm_get_latency(struct hdspm *hdspm)
1337 {
1338         int n;
1339
1340         n = hdspm_decode_latency(hdspm->control_register);
1341
1342         /* Special case for new RME cards with 32 samples period size.
1343          * The three latency bits in the control register
1344          * (HDSP_LatencyMask) encode latency values of 64 samples as
1345          * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1346          * denotes 8192 samples, but on new cards like RayDAT or AIO,
1347          * it corresponds to 32 samples.
1348          */
1349         if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1350                 n = -1;
1351
1352         return 1 << (n + 6);
1353 }
1354
1355 /* Latency function */
1356 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1357 {
1358         hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1359 }
1360
1361
1362 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1363 {
1364         int position;
1365
1366         position = hdspm_read(hdspm, HDSPM_statusRegister);
1367
1368         switch (hdspm->io_type) {
1369         case RayDAT:
1370         case AIO:
1371                 position &= HDSPM_BufferPositionMask;
1372                 position /= 4; /* Bytes per sample */
1373                 break;
1374         default:
1375                 position = (position & HDSPM_BufferID) ?
1376                         (hdspm->period_bytes / 4) : 0;
1377         }
1378
1379         return position;
1380 }
1381
1382
1383 static inline void hdspm_start_audio(struct hdspm * s)
1384 {
1385         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1386         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1387 }
1388
1389 static inline void hdspm_stop_audio(struct hdspm * s)
1390 {
1391         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1392         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1393 }
1394
1395 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1396 static void hdspm_silence_playback(struct hdspm *hdspm)
1397 {
1398         int i;
1399         int n = hdspm->period_bytes;
1400         void *buf = hdspm->playback_buffer;
1401
1402         if (buf == NULL)
1403                 return;
1404
1405         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1406                 memset(buf, 0, n);
1407                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1408         }
1409 }
1410
1411 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1412 {
1413         int n;
1414
1415         spin_lock_irq(&s->lock);
1416
1417         if (32 == frames) {
1418                 /* Special case for new RME cards like RayDAT/AIO which
1419                  * support period sizes of 32 samples. Since latency is
1420                  * encoded in the three bits of HDSP_LatencyMask, we can only
1421                  * have values from 0 .. 7. While 0 still means 64 samples and
1422                  * 6 represents 4096 samples on all cards, 7 represents 8192
1423                  * on older cards and 32 samples on new cards.
1424                  *
1425                  * In other words, period size in samples is calculated by
1426                  * 2^(n+6) with n ranging from 0 .. 7.
1427                  */
1428                 n = 7;
1429         } else {
1430                 frames >>= 7;
1431                 n = 0;
1432                 while (frames) {
1433                         n++;
1434                         frames >>= 1;
1435                 }
1436         }
1437
1438         s->control_register &= ~HDSPM_LatencyMask;
1439         s->control_register |= hdspm_encode_latency(n);
1440
1441         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1442
1443         hdspm_compute_period_size(s);
1444
1445         spin_unlock_irq(&s->lock);
1446
1447         return 0;
1448 }
1449
1450 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1451 {
1452         u64 freq_const;
1453
1454         if (period == 0)
1455                 return 0;
1456
1457         switch (hdspm->io_type) {
1458         case MADI:
1459         case AES32:
1460                 freq_const = 110069313433624ULL;
1461                 break;
1462         case RayDAT:
1463         case AIO:
1464                 freq_const = 104857600000000ULL;
1465                 break;
1466         case MADIface:
1467                 freq_const = 131072000000000ULL;
1468                 break;
1469         default:
1470                 snd_BUG();
1471                 return 0;
1472         }
1473
1474         return div_u64(freq_const, period);
1475 }
1476
1477
1478 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1479 {
1480         u64 n;
1481
1482         if (rate >= 112000)
1483                 rate /= 4;
1484         else if (rate >= 56000)
1485                 rate /= 2;
1486
1487         switch (hdspm->io_type) {
1488         case MADIface:
1489                 n = 131072000000000ULL;  /* 125 MHz */
1490                 break;
1491         case MADI:
1492         case AES32:
1493                 n = 110069313433624ULL;  /* 105 MHz */
1494                 break;
1495         case RayDAT:
1496         case AIO:
1497                 n = 104857600000000ULL;  /* 100 MHz */
1498                 break;
1499         default:
1500                 snd_BUG();
1501                 return;
1502         }
1503
1504         n = div_u64(n, rate);
1505         /* n should be less than 2^32 for being written to FREQ register */
1506         snd_BUG_ON(n >> 32);
1507         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1508 }
1509
1510 /* dummy set rate lets see what happens */
1511 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1512 {
1513         int current_rate;
1514         int rate_bits;
1515         int not_set = 0;
1516         int current_speed, target_speed;
1517
1518         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1519            it (e.g. during module initialization).
1520          */
1521
1522         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1523
1524                 /* SLAVE --- */
1525                 if (called_internally) {
1526
1527                         /* request from ctl or card initialization
1528                            just make a warning an remember setting
1529                            for future master mode switching */
1530
1531                         snd_printk(KERN_WARNING "HDSPM: "
1532                                    "Warning: device is not running "
1533                                    "as a clock master.\n");
1534                         not_set = 1;
1535                 } else {
1536
1537                         /* hw_param request while in AutoSync mode */
1538                         int external_freq =
1539                             hdspm_external_sample_rate(hdspm);
1540
1541                         if (hdspm_autosync_ref(hdspm) ==
1542                             HDSPM_AUTOSYNC_FROM_NONE) {
1543
1544                                 snd_printk(KERN_WARNING "HDSPM: "
1545                                            "Detected no Externel Sync \n");
1546                                 not_set = 1;
1547
1548                         } else if (rate != external_freq) {
1549
1550                                 snd_printk(KERN_WARNING "HDSPM: "
1551                                            "Warning: No AutoSync source for "
1552                                            "requested rate\n");
1553                                 not_set = 1;
1554                         }
1555                 }
1556         }
1557
1558         current_rate = hdspm->system_sample_rate;
1559
1560         /* Changing between Singe, Double and Quad speed is not
1561            allowed if any substreams are open. This is because such a change
1562            causes a shift in the location of the DMA buffers and a reduction
1563            in the number of available buffers.
1564
1565            Note that a similar but essentially insoluble problem exists for
1566            externally-driven rate changes. All we can do is to flag rate
1567            changes in the read/write routines.
1568          */
1569
1570         if (current_rate <= 48000)
1571                 current_speed = HDSPM_SPEED_SINGLE;
1572         else if (current_rate <= 96000)
1573                 current_speed = HDSPM_SPEED_DOUBLE;
1574         else
1575                 current_speed = HDSPM_SPEED_QUAD;
1576
1577         if (rate <= 48000)
1578                 target_speed = HDSPM_SPEED_SINGLE;
1579         else if (rate <= 96000)
1580                 target_speed = HDSPM_SPEED_DOUBLE;
1581         else
1582                 target_speed = HDSPM_SPEED_QUAD;
1583
1584         switch (rate) {
1585         case 32000:
1586                 rate_bits = HDSPM_Frequency32KHz;
1587                 break;
1588         case 44100:
1589                 rate_bits = HDSPM_Frequency44_1KHz;
1590                 break;
1591         case 48000:
1592                 rate_bits = HDSPM_Frequency48KHz;
1593                 break;
1594         case 64000:
1595                 rate_bits = HDSPM_Frequency64KHz;
1596                 break;
1597         case 88200:
1598                 rate_bits = HDSPM_Frequency88_2KHz;
1599                 break;
1600         case 96000:
1601                 rate_bits = HDSPM_Frequency96KHz;
1602                 break;
1603         case 128000:
1604                 rate_bits = HDSPM_Frequency128KHz;
1605                 break;
1606         case 176400:
1607                 rate_bits = HDSPM_Frequency176_4KHz;
1608                 break;
1609         case 192000:
1610                 rate_bits = HDSPM_Frequency192KHz;
1611                 break;
1612         default:
1613                 return -EINVAL;
1614         }
1615
1616         if (current_speed != target_speed
1617             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1618                 snd_printk
1619                     (KERN_ERR "HDSPM: "
1620                      "cannot change from %s speed to %s speed mode "
1621                      "(capture PID = %d, playback PID = %d)\n",
1622                      hdspm_speed_names[current_speed],
1623                      hdspm_speed_names[target_speed],
1624                      hdspm->capture_pid, hdspm->playback_pid);
1625                 return -EBUSY;
1626         }
1627
1628         hdspm->control_register &= ~HDSPM_FrequencyMask;
1629         hdspm->control_register |= rate_bits;
1630         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1631
1632         /* For AES32, need to set DDS value in FREQ register
1633            For MADI, also apparently */
1634         hdspm_set_dds_value(hdspm, rate);
1635
1636         if (AES32 == hdspm->io_type && rate != current_rate)
1637                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1638
1639         hdspm->system_sample_rate = rate;
1640
1641         if (rate <= 48000) {
1642                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1643                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1644                 hdspm->max_channels_in = hdspm->ss_in_channels;
1645                 hdspm->max_channels_out = hdspm->ss_out_channels;
1646                 hdspm->port_names_in = hdspm->port_names_in_ss;
1647                 hdspm->port_names_out = hdspm->port_names_out_ss;
1648         } else if (rate <= 96000) {
1649                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1650                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1651                 hdspm->max_channels_in = hdspm->ds_in_channels;
1652                 hdspm->max_channels_out = hdspm->ds_out_channels;
1653                 hdspm->port_names_in = hdspm->port_names_in_ds;
1654                 hdspm->port_names_out = hdspm->port_names_out_ds;
1655         } else {
1656                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1657                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1658                 hdspm->max_channels_in = hdspm->qs_in_channels;
1659                 hdspm->max_channels_out = hdspm->qs_out_channels;
1660                 hdspm->port_names_in = hdspm->port_names_in_qs;
1661                 hdspm->port_names_out = hdspm->port_names_out_qs;
1662         }
1663
1664         if (not_set != 0)
1665                 return -1;
1666
1667         return 0;
1668 }
1669
1670 /* mainly for init to 0 on load */
1671 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1672 {
1673         int i, j;
1674         unsigned int gain;
1675
1676         if (sgain > UNITY_GAIN)
1677                 gain = UNITY_GAIN;
1678         else if (sgain < 0)
1679                 gain = 0;
1680         else
1681                 gain = sgain;
1682
1683         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1684                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1685                         hdspm_write_in_gain(hdspm, i, j, gain);
1686                         hdspm_write_pb_gain(hdspm, i, j, gain);
1687                 }
1688 }
1689
1690 /*----------------------------------------------------------------------------
1691    MIDI
1692   ----------------------------------------------------------------------------*/
1693
1694 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1695                                                       int id)
1696 {
1697         /* the hardware already does the relevant bit-mask with 0xff */
1698         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1699 }
1700
1701 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1702                                               int val)
1703 {
1704         /* the hardware already does the relevant bit-mask with 0xff */
1705         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1706 }
1707
1708 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1709 {
1710         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1711 }
1712
1713 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1714 {
1715         int fifo_bytes_used;
1716
1717         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1718
1719         if (fifo_bytes_used < 128)
1720                 return  128 - fifo_bytes_used;
1721         else
1722                 return 0;
1723 }
1724
1725 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1726 {
1727         while (snd_hdspm_midi_input_available (hdspm, id))
1728                 snd_hdspm_midi_read_byte (hdspm, id);
1729 }
1730
1731 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1732 {
1733         unsigned long flags;
1734         int n_pending;
1735         int to_write;
1736         int i;
1737         unsigned char buf[128];
1738
1739         /* Output is not interrupt driven */
1740
1741         spin_lock_irqsave (&hmidi->lock, flags);
1742         if (hmidi->output &&
1743             !snd_rawmidi_transmit_empty (hmidi->output)) {
1744                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1745                                                             hmidi->id);
1746                 if (n_pending > 0) {
1747                         if (n_pending > (int)sizeof (buf))
1748                                 n_pending = sizeof (buf);
1749
1750                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1751                                                          n_pending);
1752                         if (to_write > 0) {
1753                                 for (i = 0; i < to_write; ++i)
1754                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1755                                                                    hmidi->id,
1756                                                                    buf[i]);
1757                         }
1758                 }
1759         }
1760         spin_unlock_irqrestore (&hmidi->lock, flags);
1761         return 0;
1762 }
1763
1764 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1765 {
1766         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1767                                  * input FIFO size
1768                                  */
1769         unsigned long flags;
1770         int n_pending;
1771         int i;
1772
1773         spin_lock_irqsave (&hmidi->lock, flags);
1774         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1775         if (n_pending > 0) {
1776                 if (hmidi->input) {
1777                         if (n_pending > (int)sizeof (buf))
1778                                 n_pending = sizeof (buf);
1779                         for (i = 0; i < n_pending; ++i)
1780                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1781                                                                    hmidi->id);
1782                         if (n_pending)
1783                                 snd_rawmidi_receive (hmidi->input, buf,
1784                                                      n_pending);
1785                 } else {
1786                         /* flush the MIDI input FIFO */
1787                         while (n_pending--)
1788                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1789                                                           hmidi->id);
1790                 }
1791         }
1792         hmidi->pending = 0;
1793         spin_unlock_irqrestore(&hmidi->lock, flags);
1794
1795         spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1796         hmidi->hdspm->control_register |= hmidi->ie;
1797         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1798                     hmidi->hdspm->control_register);
1799         spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1800
1801         return snd_hdspm_midi_output_write (hmidi);
1802 }
1803
1804 static void
1805 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1806 {
1807         struct hdspm *hdspm;
1808         struct hdspm_midi *hmidi;
1809         unsigned long flags;
1810
1811         hmidi = substream->rmidi->private_data;
1812         hdspm = hmidi->hdspm;
1813
1814         spin_lock_irqsave (&hdspm->lock, flags);
1815         if (up) {
1816                 if (!(hdspm->control_register & hmidi->ie)) {
1817                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1818                         hdspm->control_register |= hmidi->ie;
1819                 }
1820         } else {
1821                 hdspm->control_register &= ~hmidi->ie;
1822         }
1823
1824         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1825         spin_unlock_irqrestore (&hdspm->lock, flags);
1826 }
1827
1828 static void snd_hdspm_midi_output_timer(unsigned long data)
1829 {
1830         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1831         unsigned long flags;
1832
1833         snd_hdspm_midi_output_write(hmidi);
1834         spin_lock_irqsave (&hmidi->lock, flags);
1835
1836         /* this does not bump hmidi->istimer, because the
1837            kernel automatically removed the timer when it
1838            expired, and we are now adding it back, thus
1839            leaving istimer wherever it was set before.
1840         */
1841
1842         if (hmidi->istimer) {
1843                 hmidi->timer.expires = 1 + jiffies;
1844                 add_timer(&hmidi->timer);
1845         }
1846
1847         spin_unlock_irqrestore (&hmidi->lock, flags);
1848 }
1849
1850 static void
1851 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1852 {
1853         struct hdspm_midi *hmidi;
1854         unsigned long flags;
1855
1856         hmidi = substream->rmidi->private_data;
1857         spin_lock_irqsave (&hmidi->lock, flags);
1858         if (up) {
1859                 if (!hmidi->istimer) {
1860                         init_timer(&hmidi->timer);
1861                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1862                         hmidi->timer.data = (unsigned long) hmidi;
1863                         hmidi->timer.expires = 1 + jiffies;
1864                         add_timer(&hmidi->timer);
1865                         hmidi->istimer++;
1866                 }
1867         } else {
1868                 if (hmidi->istimer && --hmidi->istimer <= 0)
1869                         del_timer (&hmidi->timer);
1870         }
1871         spin_unlock_irqrestore (&hmidi->lock, flags);
1872         if (up)
1873                 snd_hdspm_midi_output_write(hmidi);
1874 }
1875
1876 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1877 {
1878         struct hdspm_midi *hmidi;
1879
1880         hmidi = substream->rmidi->private_data;
1881         spin_lock_irq (&hmidi->lock);
1882         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1883         hmidi->input = substream;
1884         spin_unlock_irq (&hmidi->lock);
1885
1886         return 0;
1887 }
1888
1889 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1890 {
1891         struct hdspm_midi *hmidi;
1892
1893         hmidi = substream->rmidi->private_data;
1894         spin_lock_irq (&hmidi->lock);
1895         hmidi->output = substream;
1896         spin_unlock_irq (&hmidi->lock);
1897
1898         return 0;
1899 }
1900
1901 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1902 {
1903         struct hdspm_midi *hmidi;
1904
1905         snd_hdspm_midi_input_trigger (substream, 0);
1906
1907         hmidi = substream->rmidi->private_data;
1908         spin_lock_irq (&hmidi->lock);
1909         hmidi->input = NULL;
1910         spin_unlock_irq (&hmidi->lock);
1911
1912         return 0;
1913 }
1914
1915 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1916 {
1917         struct hdspm_midi *hmidi;
1918
1919         snd_hdspm_midi_output_trigger (substream, 0);
1920
1921         hmidi = substream->rmidi->private_data;
1922         spin_lock_irq (&hmidi->lock);
1923         hmidi->output = NULL;
1924         spin_unlock_irq (&hmidi->lock);
1925
1926         return 0;
1927 }
1928
1929 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1930 {
1931         .open =         snd_hdspm_midi_output_open,
1932         .close =        snd_hdspm_midi_output_close,
1933         .trigger =      snd_hdspm_midi_output_trigger,
1934 };
1935
1936 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1937 {
1938         .open =         snd_hdspm_midi_input_open,
1939         .close =        snd_hdspm_midi_input_close,
1940         .trigger =      snd_hdspm_midi_input_trigger,
1941 };
1942
1943 static int snd_hdspm_create_midi(struct snd_card *card,
1944                                  struct hdspm *hdspm, int id)
1945 {
1946         int err;
1947         char buf[32];
1948
1949         hdspm->midi[id].id = id;
1950         hdspm->midi[id].hdspm = hdspm;
1951         spin_lock_init (&hdspm->midi[id].lock);
1952
1953         if (0 == id) {
1954                 if (MADIface == hdspm->io_type) {
1955                         /* MIDI-over-MADI on HDSPe MADIface */
1956                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1957                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1958                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1959                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1960                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1961                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1962                 } else {
1963                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1964                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1965                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1966                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1967                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1968                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1969                 }
1970         } else if (1 == id) {
1971                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1972                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1973                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1974                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1975                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1976                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1977         } else if ((2 == id) && (MADI == hdspm->io_type)) {
1978                 /* MIDI-over-MADI on HDSPe MADI */
1979                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1980                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1981                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1982                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1983                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1984                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1985         } else if (2 == id) {
1986                 /* TCO MTC, read only */
1987                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1988                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1989                 hdspm->midi[2].dataOut = -1;
1990                 hdspm->midi[2].statusOut = -1;
1991                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1992                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1993         } else if (3 == id) {
1994                 /* TCO MTC on HDSPe MADI */
1995                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1996                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1997                 hdspm->midi[3].dataOut = -1;
1998                 hdspm->midi[3].statusOut = -1;
1999                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2000                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2001         }
2002
2003         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2004                                         (MADIface == hdspm->io_type)))) {
2005                 if ((id == 0) && (MADIface == hdspm->io_type)) {
2006                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
2007                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
2008                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
2009                 } else {
2010                         sprintf(buf, "%s MIDI %d", card->shortname, id+1);
2011                 }
2012                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2013                                 &hdspm->midi[id].rmidi);
2014                 if (err < 0)
2015                         return err;
2016
2017                 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
2018                                 card->id, id+1);
2019                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2020
2021                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2022                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
2023                                 &snd_hdspm_midi_output);
2024                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2025                                 SNDRV_RAWMIDI_STREAM_INPUT,
2026                                 &snd_hdspm_midi_input);
2027
2028                 hdspm->midi[id].rmidi->info_flags |=
2029                         SNDRV_RAWMIDI_INFO_OUTPUT |
2030                         SNDRV_RAWMIDI_INFO_INPUT |
2031                         SNDRV_RAWMIDI_INFO_DUPLEX;
2032         } else {
2033                 /* TCO MTC, read only */
2034                 sprintf(buf, "%s MTC %d", card->shortname, id+1);
2035                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2036                                 &hdspm->midi[id].rmidi);
2037                 if (err < 0)
2038                         return err;
2039
2040                 sprintf(hdspm->midi[id].rmidi->name,
2041                                 "%s MTC %d", card->id, id+1);
2042                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2043
2044                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2045                                 SNDRV_RAWMIDI_STREAM_INPUT,
2046                                 &snd_hdspm_midi_input);
2047
2048                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2049         }
2050
2051         return 0;
2052 }
2053
2054
2055 static void hdspm_midi_tasklet(unsigned long arg)
2056 {
2057         struct hdspm *hdspm = (struct hdspm *)arg;
2058         int i = 0;
2059
2060         while (i < hdspm->midiPorts) {
2061                 if (hdspm->midi[i].pending)
2062                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
2063
2064                 i++;
2065         }
2066 }
2067
2068
2069 /*-----------------------------------------------------------------------------
2070   Status Interface
2071   ----------------------------------------------------------------------------*/
2072
2073 /* get the system sample rate which is set */
2074
2075
2076 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2077 {
2078         unsigned int period, rate;
2079
2080         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2081         rate = hdspm_calc_dds_value(hdspm, period);
2082
2083         return rate;
2084 }
2085
2086 /**
2087  * Calculate the real sample rate from the
2088  * current DDS value.
2089  **/
2090 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2091 {
2092         unsigned int rate;
2093
2094         rate = hdspm_get_pll_freq(hdspm);
2095
2096         if (rate > 207000) {
2097                 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2098                 if (0 == hdspm_system_clock_mode(hdspm)) {
2099                         /* master mode, return internal sample rate */
2100                         rate = hdspm->system_sample_rate;
2101                 } else {
2102                         /* slave mode, return external sample rate */
2103                         rate = hdspm_external_sample_rate(hdspm);
2104                 }
2105         }
2106
2107         return rate;
2108 }
2109
2110
2111 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2112 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2113         .name = xname, \
2114         .index = xindex, \
2115         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2116                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2117         .info = snd_hdspm_info_system_sample_rate, \
2118         .put = snd_hdspm_put_system_sample_rate, \
2119         .get = snd_hdspm_get_system_sample_rate \
2120 }
2121
2122 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2123                                              struct snd_ctl_elem_info *uinfo)
2124 {
2125         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2126         uinfo->count = 1;
2127         uinfo->value.integer.min = 27000;
2128         uinfo->value.integer.max = 207000;
2129         uinfo->value.integer.step = 1;
2130         return 0;
2131 }
2132
2133
2134 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2135                                             struct snd_ctl_elem_value *
2136                                             ucontrol)
2137 {
2138         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2139
2140         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2141         return 0;
2142 }
2143
2144 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2145                                             struct snd_ctl_elem_value *
2146                                             ucontrol)
2147 {
2148         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2149
2150         hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]);
2151         return 0;
2152 }
2153
2154
2155 /**
2156  * Returns the WordClock sample rate class for the given card.
2157  **/
2158 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2159 {
2160         int status;
2161
2162         switch (hdspm->io_type) {
2163         case RayDAT:
2164         case AIO:
2165                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2166                 return (status >> 16) & 0xF;
2167                 break;
2168         default:
2169                 break;
2170         }
2171
2172
2173         return 0;
2174 }
2175
2176
2177 /**
2178  * Returns the TCO sample rate class for the given card.
2179  **/
2180 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2181 {
2182         int status;
2183
2184         if (hdspm->tco) {
2185                 switch (hdspm->io_type) {
2186                 case RayDAT:
2187                 case AIO:
2188                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2189                         return (status >> 20) & 0xF;
2190                         break;
2191                 default:
2192                         break;
2193                 }
2194         }
2195
2196         return 0;
2197 }
2198
2199
2200 /**
2201  * Returns the SYNC_IN sample rate class for the given card.
2202  **/
2203 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2204 {
2205         int status;
2206
2207         if (hdspm->tco) {
2208                 switch (hdspm->io_type) {
2209                 case RayDAT:
2210                 case AIO:
2211                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2212                         return (status >> 12) & 0xF;
2213                         break;
2214                 default:
2215                         break;
2216                 }
2217         }
2218
2219         return 0;
2220 }
2221
2222
2223 /**
2224  * Returns the sample rate class for input source <idx> for
2225  * 'new style' cards like the AIO and RayDAT.
2226  **/
2227 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2228 {
2229         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2230
2231         return (status >> (idx*4)) & 0xF;
2232 }
2233
2234 static void snd_hdspm_set_infotext(struct snd_ctl_elem_info *uinfo,
2235                 char **texts, const int count)
2236 {
2237         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2238         uinfo->count = 1;
2239         uinfo->value.enumerated.items = count;
2240         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2241                 uinfo->value.enumerated.item =
2242                         uinfo->value.enumerated.items - 1;
2243         strcpy(uinfo->value.enumerated.name,
2244                         texts[uinfo->value.enumerated.item]);
2245 }
2246
2247 #define ENUMERATED_CTL_INFO(info, texts) \
2248         snd_hdspm_set_infotext(info, texts, ARRAY_SIZE(texts))
2249
2250
2251
2252 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2253 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2254         .name = xname, \
2255         .private_value = xindex, \
2256         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2257         .info = snd_hdspm_info_autosync_sample_rate, \
2258         .get = snd_hdspm_get_autosync_sample_rate \
2259 }
2260
2261
2262 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2263                                                struct snd_ctl_elem_info *uinfo)
2264 {
2265         ENUMERATED_CTL_INFO(uinfo, texts_freq);
2266         return 0;
2267 }
2268
2269
2270 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2271                                               struct snd_ctl_elem_value *
2272                                               ucontrol)
2273 {
2274         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2275
2276         switch (hdspm->io_type) {
2277         case RayDAT:
2278                 switch (kcontrol->private_value) {
2279                 case 0:
2280                         ucontrol->value.enumerated.item[0] =
2281                                 hdspm_get_wc_sample_rate(hdspm);
2282                         break;
2283                 case 7:
2284                         ucontrol->value.enumerated.item[0] =
2285                                 hdspm_get_tco_sample_rate(hdspm);
2286                         break;
2287                 case 8:
2288                         ucontrol->value.enumerated.item[0] =
2289                                 hdspm_get_sync_in_sample_rate(hdspm);
2290                         break;
2291                 default:
2292                         ucontrol->value.enumerated.item[0] =
2293                                 hdspm_get_s1_sample_rate(hdspm,
2294                                                 kcontrol->private_value-1);
2295                 }
2296                 break;
2297
2298         case AIO:
2299                 switch (kcontrol->private_value) {
2300                 case 0: /* WC */
2301                         ucontrol->value.enumerated.item[0] =
2302                                 hdspm_get_wc_sample_rate(hdspm);
2303                         break;
2304                 case 4: /* TCO */
2305                         ucontrol->value.enumerated.item[0] =
2306                                 hdspm_get_tco_sample_rate(hdspm);
2307                         break;
2308                 case 5: /* SYNC_IN */
2309                         ucontrol->value.enumerated.item[0] =
2310                                 hdspm_get_sync_in_sample_rate(hdspm);
2311                         break;
2312                 default:
2313                         ucontrol->value.enumerated.item[0] =
2314                                 hdspm_get_s1_sample_rate(hdspm,
2315                                                 kcontrol->private_value-1);
2316                 }
2317                 break;
2318
2319         case AES32:
2320
2321                 switch (kcontrol->private_value) {
2322                 case 0: /* WC */
2323                         ucontrol->value.enumerated.item[0] =
2324                                 hdspm_get_wc_sample_rate(hdspm);
2325                         break;
2326                 case 9: /* TCO */
2327                         ucontrol->value.enumerated.item[0] =
2328                                 hdspm_get_tco_sample_rate(hdspm);
2329                         break;
2330                 case 10: /* SYNC_IN */
2331                         ucontrol->value.enumerated.item[0] =
2332                                 hdspm_get_sync_in_sample_rate(hdspm);
2333                         break;
2334                 default: /* AES1 to AES8 */
2335                         ucontrol->value.enumerated.item[0] =
2336                                 hdspm_get_s1_sample_rate(hdspm,
2337                                                 kcontrol->private_value-1);
2338                         break;
2339                 }
2340                 break;
2341
2342         case MADI:
2343         case MADIface:
2344                 {
2345                         int rate = hdspm_external_sample_rate(hdspm);
2346                         int i, selected_rate = 0;
2347                         for (i = 1; i < 10; i++)
2348                                 if (HDSPM_bit2freq(i) == rate) {
2349                                         selected_rate = i;
2350                                         break;
2351                                 }
2352                         ucontrol->value.enumerated.item[0] = selected_rate;
2353                 }
2354                 break;
2355
2356         default:
2357                 break;
2358         }
2359
2360         return 0;
2361 }
2362
2363
2364 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2365 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2366         .name = xname, \
2367         .index = xindex, \
2368         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2369                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2370         .info = snd_hdspm_info_system_clock_mode, \
2371         .get = snd_hdspm_get_system_clock_mode, \
2372         .put = snd_hdspm_put_system_clock_mode, \
2373 }
2374
2375
2376 /**
2377  * Returns the system clock mode for the given card.
2378  * @returns 0 - master, 1 - slave
2379  **/
2380 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2381 {
2382         switch (hdspm->io_type) {
2383         case AIO:
2384         case RayDAT:
2385                 if (hdspm->settings_register & HDSPM_c0Master)
2386                         return 0;
2387                 break;
2388
2389         default:
2390                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2391                         return 0;
2392         }
2393
2394         return 1;
2395 }
2396
2397
2398 /**
2399  * Sets the system clock mode.
2400  * @param mode 0 - master, 1 - slave
2401  **/
2402 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2403 {
2404         hdspm_set_toggle_setting(hdspm,
2405                         (hdspm_is_raydat_or_aio(hdspm)) ?
2406                         HDSPM_c0Master : HDSPM_ClockModeMaster,
2407                         (0 == mode));
2408 }
2409
2410
2411 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2412                                             struct snd_ctl_elem_info *uinfo)
2413 {
2414         static char *texts[] = { "Master", "AutoSync" };
2415         ENUMERATED_CTL_INFO(uinfo, texts);
2416         return 0;
2417 }
2418
2419 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2420                                            struct snd_ctl_elem_value *ucontrol)
2421 {
2422         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2423
2424         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2425         return 0;
2426 }
2427
2428 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2429                                            struct snd_ctl_elem_value *ucontrol)
2430 {
2431         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2432         int val;
2433
2434         if (!snd_hdspm_use_is_exclusive(hdspm))
2435                 return -EBUSY;
2436
2437         val = ucontrol->value.enumerated.item[0];
2438         if (val < 0)
2439                 val = 0;
2440         else if (val > 1)
2441                 val = 1;
2442
2443         hdspm_set_system_clock_mode(hdspm, val);
2444
2445         return 0;
2446 }
2447
2448
2449 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2450 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2451         .name = xname, \
2452         .index = xindex, \
2453         .info = snd_hdspm_info_clock_source, \
2454         .get = snd_hdspm_get_clock_source, \
2455         .put = snd_hdspm_put_clock_source \
2456 }
2457
2458
2459 static int hdspm_clock_source(struct hdspm * hdspm)
2460 {
2461         switch (hdspm->system_sample_rate) {
2462         case 32000: return 0;
2463         case 44100: return 1;
2464         case 48000: return 2;
2465         case 64000: return 3;
2466         case 88200: return 4;
2467         case 96000: return 5;
2468         case 128000: return 6;
2469         case 176400: return 7;
2470         case 192000: return 8;
2471         }
2472
2473         return -1;
2474 }
2475
2476 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2477 {
2478         int rate;
2479         switch (mode) {
2480         case 0:
2481                 rate = 32000; break;
2482         case 1:
2483                 rate = 44100; break;
2484         case 2:
2485                 rate = 48000; break;
2486         case 3:
2487                 rate = 64000; break;
2488         case 4:
2489                 rate = 88200; break;
2490         case 5:
2491                 rate = 96000; break;
2492         case 6:
2493                 rate = 128000; break;
2494         case 7:
2495                 rate = 176400; break;
2496         case 8:
2497                 rate = 192000; break;
2498         default:
2499                 rate = 48000;
2500         }
2501         hdspm_set_rate(hdspm, rate, 1);
2502         return 0;
2503 }
2504
2505 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2506                                        struct snd_ctl_elem_info *uinfo)
2507 {
2508         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2509         uinfo->count = 1;
2510         uinfo->value.enumerated.items = 9;
2511
2512         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2513                 uinfo->value.enumerated.item =
2514                     uinfo->value.enumerated.items - 1;
2515
2516         strcpy(uinfo->value.enumerated.name,
2517                texts_freq[uinfo->value.enumerated.item+1]);
2518
2519         return 0;
2520 }
2521
2522 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2523                                       struct snd_ctl_elem_value *ucontrol)
2524 {
2525         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2526
2527         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2528         return 0;
2529 }
2530
2531 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2532                                       struct snd_ctl_elem_value *ucontrol)
2533 {
2534         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2535         int change;
2536         int val;
2537
2538         if (!snd_hdspm_use_is_exclusive(hdspm))
2539                 return -EBUSY;
2540         val = ucontrol->value.enumerated.item[0];
2541         if (val < 0)
2542                 val = 0;
2543         if (val > 9)
2544                 val = 9;
2545         spin_lock_irq(&hdspm->lock);
2546         if (val != hdspm_clock_source(hdspm))
2547                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2548         else
2549                 change = 0;
2550         spin_unlock_irq(&hdspm->lock);
2551         return change;
2552 }
2553
2554
2555 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2556 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2557         .name = xname, \
2558         .index = xindex, \
2559         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2560                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2561         .info = snd_hdspm_info_pref_sync_ref, \
2562         .get = snd_hdspm_get_pref_sync_ref, \
2563         .put = snd_hdspm_put_pref_sync_ref \
2564 }
2565
2566
2567 /**
2568  * Returns the current preferred sync reference setting.
2569  * The semantics of the return value are depending on the
2570  * card, please see the comments for clarification.
2571  **/
2572 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2573 {
2574         switch (hdspm->io_type) {
2575         case AES32:
2576                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2577                 case 0: return 0;  /* WC */
2578                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2579                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2580                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2581                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2582                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2583                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2584                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2585                                                     return 7; /* AES 7 */
2586                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2587                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2588                 }
2589                 break;
2590
2591         case MADI:
2592         case MADIface:
2593                 if (hdspm->tco) {
2594                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2595                         case 0: return 0;  /* WC */
2596                         case HDSPM_SyncRef0: return 1;  /* MADI */
2597                         case HDSPM_SyncRef1: return 2;  /* TCO */
2598                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2599                                              return 3;  /* SYNC_IN */
2600                         }
2601                 } else {
2602                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2603                         case 0: return 0;  /* WC */
2604                         case HDSPM_SyncRef0: return 1;  /* MADI */
2605                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2606                                              return 2;  /* SYNC_IN */
2607                         }
2608                 }
2609                 break;
2610
2611         case RayDAT:
2612                 if (hdspm->tco) {
2613                         switch ((hdspm->settings_register &
2614                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2615                         case 0: return 0;  /* WC */
2616                         case 3: return 1;  /* ADAT 1 */
2617                         case 4: return 2;  /* ADAT 2 */
2618                         case 5: return 3;  /* ADAT 3 */
2619                         case 6: return 4;  /* ADAT 4 */
2620                         case 1: return 5;  /* AES */
2621                         case 2: return 6;  /* SPDIF */
2622                         case 9: return 7;  /* TCO */
2623                         case 10: return 8; /* SYNC_IN */
2624                         }
2625                 } else {
2626                         switch ((hdspm->settings_register &
2627                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2628                         case 0: return 0;  /* WC */
2629                         case 3: return 1;  /* ADAT 1 */
2630                         case 4: return 2;  /* ADAT 2 */
2631                         case 5: return 3;  /* ADAT 3 */
2632                         case 6: return 4;  /* ADAT 4 */
2633                         case 1: return 5;  /* AES */
2634                         case 2: return 6;  /* SPDIF */
2635                         case 10: return 7; /* SYNC_IN */
2636                         }
2637                 }
2638
2639                 break;
2640
2641         case AIO:
2642                 if (hdspm->tco) {
2643                         switch ((hdspm->settings_register &
2644                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2645                         case 0: return 0;  /* WC */
2646                         case 3: return 1;  /* ADAT */
2647                         case 1: return 2;  /* AES */
2648                         case 2: return 3;  /* SPDIF */
2649                         case 9: return 4;  /* TCO */
2650                         case 10: return 5; /* SYNC_IN */
2651                         }
2652                 } else {
2653                         switch ((hdspm->settings_register &
2654                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2655                         case 0: return 0;  /* WC */
2656                         case 3: return 1;  /* ADAT */
2657                         case 1: return 2;  /* AES */
2658                         case 2: return 3;  /* SPDIF */
2659                         case 10: return 4; /* SYNC_IN */
2660                         }
2661                 }
2662
2663                 break;
2664         }
2665
2666         return -1;
2667 }
2668
2669
2670 /**
2671  * Set the preferred sync reference to <pref>. The semantics
2672  * of <pref> are depending on the card type, see the comments
2673  * for clarification.
2674  **/
2675 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2676 {
2677         int p = 0;
2678
2679         switch (hdspm->io_type) {
2680         case AES32:
2681                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2682                 switch (pref) {
2683                 case 0: /* WC  */
2684                         break;
2685                 case 1: /* AES 1 */
2686                         hdspm->control_register |= HDSPM_SyncRef0;
2687                         break;
2688                 case 2: /* AES 2 */
2689                         hdspm->control_register |= HDSPM_SyncRef1;
2690                         break;
2691                 case 3: /* AES 3 */
2692                         hdspm->control_register |=
2693                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2694                         break;
2695                 case 4: /* AES 4 */
2696                         hdspm->control_register |= HDSPM_SyncRef2;
2697                         break;
2698                 case 5: /* AES 5 */
2699                         hdspm->control_register |=
2700                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2701                         break;
2702                 case 6: /* AES 6 */
2703                         hdspm->control_register |=
2704                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2705                         break;
2706                 case 7: /* AES 7 */
2707                         hdspm->control_register |=
2708                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2709                         break;
2710                 case 8: /* AES 8 */
2711                         hdspm->control_register |= HDSPM_SyncRef3;
2712                         break;
2713                 case 9: /* TCO */
2714                         hdspm->control_register |=
2715                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2716                         break;
2717                 default:
2718                         return -1;
2719                 }
2720
2721                 break;
2722
2723         case MADI:
2724         case MADIface:
2725                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2726                 if (hdspm->tco) {
2727                         switch (pref) {
2728                         case 0: /* WC */
2729                                 break;
2730                         case 1: /* MADI */
2731                                 hdspm->control_register |= HDSPM_SyncRef0;
2732                                 break;
2733                         case 2: /* TCO */
2734                                 hdspm->control_register |= HDSPM_SyncRef1;
2735                                 break;
2736                         case 3: /* SYNC_IN */
2737                                 hdspm->control_register |=
2738                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2739                                 break;
2740                         default:
2741                                 return -1;
2742                         }
2743                 } else {
2744                         switch (pref) {
2745                         case 0: /* WC */
2746                                 break;
2747                         case 1: /* MADI */
2748                                 hdspm->control_register |= HDSPM_SyncRef0;
2749                                 break;
2750                         case 2: /* SYNC_IN */
2751                                 hdspm->control_register |=
2752                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2753                                 break;
2754                         default:
2755                                 return -1;
2756                         }
2757                 }
2758
2759                 break;
2760
2761         case RayDAT:
2762                 if (hdspm->tco) {
2763                         switch (pref) {
2764                         case 0: p = 0; break;  /* WC */
2765                         case 1: p = 3; break;  /* ADAT 1 */
2766                         case 2: p = 4; break;  /* ADAT 2 */
2767                         case 3: p = 5; break;  /* ADAT 3 */
2768                         case 4: p = 6; break;  /* ADAT 4 */
2769                         case 5: p = 1; break;  /* AES */
2770                         case 6: p = 2; break;  /* SPDIF */
2771                         case 7: p = 9; break;  /* TCO */
2772                         case 8: p = 10; break; /* SYNC_IN */
2773                         default: return -1;
2774                         }
2775                 } else {
2776                         switch (pref) {
2777                         case 0: p = 0; break;  /* WC */
2778                         case 1: p = 3; break;  /* ADAT 1 */
2779                         case 2: p = 4; break;  /* ADAT 2 */
2780                         case 3: p = 5; break;  /* ADAT 3 */
2781                         case 4: p = 6; break;  /* ADAT 4 */
2782                         case 5: p = 1; break;  /* AES */
2783                         case 6: p = 2; break;  /* SPDIF */
2784                         case 7: p = 10; break; /* SYNC_IN */
2785                         default: return -1;
2786                         }
2787                 }
2788                 break;
2789
2790         case AIO:
2791                 if (hdspm->tco) {
2792                         switch (pref) {
2793                         case 0: p = 0; break;  /* WC */
2794                         case 1: p = 3; break;  /* ADAT */
2795                         case 2: p = 1; break;  /* AES */
2796                         case 3: p = 2; break;  /* SPDIF */
2797                         case 4: p = 9; break;  /* TCO */
2798                         case 5: p = 10; break; /* SYNC_IN */
2799                         default: return -1;
2800                         }
2801                 } else {
2802                         switch (pref) {
2803                         case 0: p = 0; break;  /* WC */
2804                         case 1: p = 3; break;  /* ADAT */
2805                         case 2: p = 1; break;  /* AES */
2806                         case 3: p = 2; break;  /* SPDIF */
2807                         case 4: p = 10; break; /* SYNC_IN */
2808                         default: return -1;
2809                         }
2810                 }
2811                 break;
2812         }
2813
2814         switch (hdspm->io_type) {
2815         case RayDAT:
2816         case AIO:
2817                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2818                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2819                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2820                 break;
2821
2822         case MADI:
2823         case MADIface:
2824         case AES32:
2825                 hdspm_write(hdspm, HDSPM_controlRegister,
2826                                 hdspm->control_register);
2827         }
2828
2829         return 0;
2830 }
2831
2832
2833 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2834                                         struct snd_ctl_elem_info *uinfo)
2835 {
2836         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2837
2838         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2839         uinfo->count = 1;
2840         uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2841
2842         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2843                 uinfo->value.enumerated.item =
2844                         uinfo->value.enumerated.items - 1;
2845
2846         strcpy(uinfo->value.enumerated.name,
2847                         hdspm->texts_autosync[uinfo->value.enumerated.item]);
2848
2849         return 0;
2850 }
2851
2852 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2853                                        struct snd_ctl_elem_value *ucontrol)
2854 {
2855         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2856         int psf = hdspm_pref_sync_ref(hdspm);
2857
2858         if (psf >= 0) {
2859                 ucontrol->value.enumerated.item[0] = psf;
2860                 return 0;
2861         }
2862
2863         return -1;
2864 }
2865
2866 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2867                                        struct snd_ctl_elem_value *ucontrol)
2868 {
2869         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2870         int val, change = 0;
2871
2872         if (!snd_hdspm_use_is_exclusive(hdspm))
2873                 return -EBUSY;
2874
2875         val = ucontrol->value.enumerated.item[0];
2876
2877         if (val < 0)
2878                 val = 0;
2879         else if (val >= hdspm->texts_autosync_items)
2880                 val = hdspm->texts_autosync_items-1;
2881
2882         spin_lock_irq(&hdspm->lock);
2883         if (val != hdspm_pref_sync_ref(hdspm))
2884                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2885
2886         spin_unlock_irq(&hdspm->lock);
2887         return change;
2888 }
2889
2890
2891 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2892 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2893         .name = xname, \
2894         .index = xindex, \
2895         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2896         .info = snd_hdspm_info_autosync_ref, \
2897         .get = snd_hdspm_get_autosync_ref, \
2898 }
2899
2900 static int hdspm_autosync_ref(struct hdspm *hdspm)
2901 {
2902         if (AES32 == hdspm->io_type) {
2903                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2904                 unsigned int syncref =
2905                         (status >> HDSPM_AES32_syncref_bit) & 0xF;
2906                 if (syncref == 0)
2907                         return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2908                 if (syncref <= 8)
2909                         return syncref;
2910                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2911         } else if (MADI == hdspm->io_type) {
2912                 /* This looks at the autosync selected sync reference */
2913                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2914
2915                 switch (status2 & HDSPM_SelSyncRefMask) {
2916                 case HDSPM_SelSyncRef_WORD:
2917                         return HDSPM_AUTOSYNC_FROM_WORD;
2918                 case HDSPM_SelSyncRef_MADI:
2919                         return HDSPM_AUTOSYNC_FROM_MADI;
2920                 case HDSPM_SelSyncRef_TCO:
2921                         return HDSPM_AUTOSYNC_FROM_TCO;
2922                 case HDSPM_SelSyncRef_SyncIn:
2923                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2924                 case HDSPM_SelSyncRef_NVALID:
2925                         return HDSPM_AUTOSYNC_FROM_NONE;
2926                 default:
2927                         return 0;
2928                 }
2929
2930         }
2931         return 0;
2932 }
2933
2934
2935 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2936                                        struct snd_ctl_elem_info *uinfo)
2937 {
2938         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2939
2940         if (AES32 == hdspm->io_type) {
2941                 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2942                         "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2943
2944                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2945                 uinfo->count = 1;
2946                 uinfo->value.enumerated.items = 10;
2947                 if (uinfo->value.enumerated.item >=
2948                     uinfo->value.enumerated.items)
2949                         uinfo->value.enumerated.item =
2950                                 uinfo->value.enumerated.items - 1;
2951                 strcpy(uinfo->value.enumerated.name,
2952                                 texts[uinfo->value.enumerated.item]);
2953         } else if (MADI == hdspm->io_type) {
2954                 static char *texts[] = {"Word Clock", "MADI", "TCO",
2955                         "Sync In", "None" };
2956
2957                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2958                 uinfo->count = 1;
2959                 uinfo->value.enumerated.items = 5;
2960                 if (uinfo->value.enumerated.item >=
2961                                 uinfo->value.enumerated.items)
2962                         uinfo->value.enumerated.item =
2963                                 uinfo->value.enumerated.items - 1;
2964                 strcpy(uinfo->value.enumerated.name,
2965                                 texts[uinfo->value.enumerated.item]);
2966         }
2967         return 0;
2968 }
2969
2970 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2971                                       struct snd_ctl_elem_value *ucontrol)
2972 {
2973         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2974
2975         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2976         return 0;
2977 }
2978
2979
2980
2981 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
2982 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2983         .name = xname, \
2984         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
2985                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2986         .info = snd_hdspm_info_tco_video_input_format, \
2987         .get = snd_hdspm_get_tco_video_input_format, \
2988 }
2989
2990 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
2991                                        struct snd_ctl_elem_info *uinfo)
2992 {
2993         static char *texts[] = {"No video", "NTSC", "PAL"};
2994         ENUMERATED_CTL_INFO(uinfo, texts);
2995         return 0;
2996 }
2997
2998 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
2999                                       struct snd_ctl_elem_value *ucontrol)
3000 {
3001         u32 status;
3002         int ret = 0;
3003
3004         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3005         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3006         switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
3007                         HDSPM_TCO1_Video_Input_Format_PAL)) {
3008         case HDSPM_TCO1_Video_Input_Format_NTSC:
3009                 /* ntsc */
3010                 ret = 1;
3011                 break;
3012         case HDSPM_TCO1_Video_Input_Format_PAL:
3013                 /* pal */
3014                 ret = 2;
3015                 break;
3016         default:
3017                 /* no video */
3018                 ret = 0;
3019                 break;
3020         }
3021         ucontrol->value.enumerated.item[0] = ret;
3022         return 0;
3023 }
3024
3025
3026
3027 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
3028 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3029         .name = xname, \
3030         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3031                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3032         .info = snd_hdspm_info_tco_ltc_frames, \
3033         .get = snd_hdspm_get_tco_ltc_frames, \
3034 }
3035
3036 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3037                                        struct snd_ctl_elem_info *uinfo)
3038 {
3039         static char *texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3040                                 "30 fps"};
3041         ENUMERATED_CTL_INFO(uinfo, texts);
3042         return 0;
3043 }
3044
3045 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3046 {
3047         u32 status;
3048         int ret = 0;
3049
3050         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3051         if (status & HDSPM_TCO1_LTC_Input_valid) {
3052                 switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3053                                         HDSPM_TCO1_LTC_Format_MSB)) {
3054                 case 0:
3055                         /* 24 fps */
3056                         ret = 1;
3057                         break;
3058                 case HDSPM_TCO1_LTC_Format_LSB:
3059                         /* 25 fps */
3060                         ret = 2;
3061                         break;
3062                 case HDSPM_TCO1_LTC_Format_MSB:
3063                         /* 25 fps */
3064                         ret = 3;
3065                         break;
3066                 default:
3067                         /* 30 fps */
3068                         ret = 4;
3069                         break;
3070                 }
3071         }
3072
3073         return ret;
3074 }
3075
3076 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3077                                       struct snd_ctl_elem_value *ucontrol)
3078 {
3079         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3080
3081         ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3082         return 0;
3083 }
3084
3085 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3086 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3087         .name = xname, \
3088         .private_value = xindex, \
3089         .info = snd_hdspm_info_toggle_setting, \
3090         .get = snd_hdspm_get_toggle_setting, \
3091         .put = snd_hdspm_put_toggle_setting \
3092 }
3093
3094 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3095 {
3096         u32 reg;
3097
3098         if (hdspm_is_raydat_or_aio(hdspm))
3099                 reg = hdspm->settings_register;
3100         else
3101                 reg = hdspm->control_register;
3102
3103         return (reg & regmask) ? 1 : 0;
3104 }
3105
3106 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3107 {
3108         u32 *reg;
3109         u32 target_reg;
3110
3111         if (hdspm_is_raydat_or_aio(hdspm)) {
3112                 reg = &(hdspm->settings_register);
3113                 target_reg = HDSPM_WR_SETTINGS;
3114         } else {
3115                 reg = &(hdspm->control_register);
3116                 target_reg = HDSPM_controlRegister;
3117         }
3118
3119         if (out)
3120                 *reg |= regmask;
3121         else
3122                 *reg &= ~regmask;
3123
3124         hdspm_write(hdspm, target_reg, *reg);
3125
3126         return 0;
3127 }
3128
3129 #define snd_hdspm_info_toggle_setting           snd_ctl_boolean_mono_info
3130
3131 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3132                                struct snd_ctl_elem_value *ucontrol)
3133 {
3134         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3135         u32 regmask = kcontrol->private_value;
3136
3137         spin_lock_irq(&hdspm->lock);
3138         ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3139         spin_unlock_irq(&hdspm->lock);
3140         return 0;
3141 }
3142
3143 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3144                                struct snd_ctl_elem_value *ucontrol)
3145 {
3146         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3147         u32 regmask = kcontrol->private_value;
3148         int change;
3149         unsigned int val;
3150
3151         if (!snd_hdspm_use_is_exclusive(hdspm))
3152                 return -EBUSY;
3153         val = ucontrol->value.integer.value[0] & 1;
3154         spin_lock_irq(&hdspm->lock);
3155         change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3156         hdspm_set_toggle_setting(hdspm, regmask, val);
3157         spin_unlock_irq(&hdspm->lock);
3158         return change;
3159 }
3160
3161 #define HDSPM_INPUT_SELECT(xname, xindex) \
3162 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3163         .name = xname, \
3164         .index = xindex, \
3165         .info = snd_hdspm_info_input_select, \
3166         .get = snd_hdspm_get_input_select, \
3167         .put = snd_hdspm_put_input_select \
3168 }
3169
3170 static int hdspm_input_select(struct hdspm * hdspm)
3171 {
3172         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3173 }
3174
3175 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3176 {
3177         if (out)
3178                 hdspm->control_register |= HDSPM_InputSelect0;
3179         else
3180                 hdspm->control_register &= ~HDSPM_InputSelect0;
3181         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3182
3183         return 0;
3184 }
3185
3186 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3187                                        struct snd_ctl_elem_info *uinfo)
3188 {
3189         static char *texts[] = { "optical", "coaxial" };
3190         ENUMERATED_CTL_INFO(uinfo, texts);
3191         return 0;
3192 }
3193
3194 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3195                                       struct snd_ctl_elem_value *ucontrol)
3196 {
3197         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3198
3199         spin_lock_irq(&hdspm->lock);
3200         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3201         spin_unlock_irq(&hdspm->lock);
3202         return 0;
3203 }
3204
3205 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3206                                       struct snd_ctl_elem_value *ucontrol)
3207 {
3208         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3209         int change;
3210         unsigned int val;
3211
3212         if (!snd_hdspm_use_is_exclusive(hdspm))
3213                 return -EBUSY;
3214         val = ucontrol->value.integer.value[0] & 1;
3215         spin_lock_irq(&hdspm->lock);
3216         change = (int) val != hdspm_input_select(hdspm);
3217         hdspm_set_input_select(hdspm, val);
3218         spin_unlock_irq(&hdspm->lock);
3219         return change;
3220 }
3221
3222
3223 #define HDSPM_DS_WIRE(xname, xindex) \
3224 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3225         .name = xname, \
3226         .index = xindex, \
3227         .info = snd_hdspm_info_ds_wire, \
3228         .get = snd_hdspm_get_ds_wire, \
3229         .put = snd_hdspm_put_ds_wire \
3230 }
3231
3232 static int hdspm_ds_wire(struct hdspm * hdspm)
3233 {
3234         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3235 }
3236
3237 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3238 {
3239         if (ds)
3240                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3241         else
3242                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3243         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3244
3245         return 0;
3246 }
3247
3248 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3249                                   struct snd_ctl_elem_info *uinfo)
3250 {
3251         static char *texts[] = { "Single", "Double" };
3252         ENUMERATED_CTL_INFO(uinfo, texts);
3253         return 0;
3254 }
3255
3256 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3257                                  struct snd_ctl_elem_value *ucontrol)
3258 {
3259         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3260
3261         spin_lock_irq(&hdspm->lock);
3262         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3263         spin_unlock_irq(&hdspm->lock);
3264         return 0;
3265 }
3266
3267 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3268                                  struct snd_ctl_elem_value *ucontrol)
3269 {
3270         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3271         int change;
3272         unsigned int val;
3273
3274         if (!snd_hdspm_use_is_exclusive(hdspm))
3275                 return -EBUSY;
3276         val = ucontrol->value.integer.value[0] & 1;
3277         spin_lock_irq(&hdspm->lock);
3278         change = (int) val != hdspm_ds_wire(hdspm);
3279         hdspm_set_ds_wire(hdspm, val);
3280         spin_unlock_irq(&hdspm->lock);
3281         return change;
3282 }
3283
3284
3285 #define HDSPM_QS_WIRE(xname, xindex) \
3286 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3287         .name = xname, \
3288         .index = xindex, \
3289         .info = snd_hdspm_info_qs_wire, \
3290         .get = snd_hdspm_get_qs_wire, \
3291         .put = snd_hdspm_put_qs_wire \
3292 }
3293
3294 static int hdspm_qs_wire(struct hdspm * hdspm)
3295 {
3296         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3297                 return 1;
3298         if (hdspm->control_register & HDSPM_QS_QuadWire)
3299                 return 2;
3300         return 0;
3301 }
3302
3303 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3304 {
3305         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3306         switch (mode) {
3307         case 0:
3308                 break;
3309         case 1:
3310                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3311                 break;
3312         case 2:
3313                 hdspm->control_register |= HDSPM_QS_QuadWire;
3314                 break;
3315         }
3316         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3317
3318         return 0;
3319 }
3320
3321 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3322                                        struct snd_ctl_elem_info *uinfo)
3323 {
3324         static char *texts[] = { "Single", "Double", "Quad" };
3325         ENUMERATED_CTL_INFO(uinfo, texts);
3326         return 0;
3327 }
3328
3329 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3330                                       struct snd_ctl_elem_value *ucontrol)
3331 {
3332         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3333
3334         spin_lock_irq(&hdspm->lock);
3335         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3336         spin_unlock_irq(&hdspm->lock);
3337         return 0;
3338 }
3339
3340 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3341                                       struct snd_ctl_elem_value *ucontrol)
3342 {
3343         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3344         int change;
3345         int val;
3346
3347         if (!snd_hdspm_use_is_exclusive(hdspm))
3348                 return -EBUSY;
3349         val = ucontrol->value.integer.value[0];
3350         if (val < 0)
3351                 val = 0;
3352         if (val > 2)
3353                 val = 2;
3354         spin_lock_irq(&hdspm->lock);
3355         change = val != hdspm_qs_wire(hdspm);
3356         hdspm_set_qs_wire(hdspm, val);
3357         spin_unlock_irq(&hdspm->lock);
3358         return change;
3359 }
3360
3361 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \
3362 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3363         .name = xname, \
3364         .private_value = xindex, \
3365         .info = snd_hdspm_info_tristate, \
3366         .get = snd_hdspm_get_tristate, \
3367         .put = snd_hdspm_put_tristate \
3368 }
3369
3370 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3371 {
3372         u32 reg = hdspm->settings_register & (regmask * 3);
3373         return reg / regmask;
3374 }
3375
3376 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3377 {
3378         hdspm->settings_register &= ~(regmask * 3);
3379         hdspm->settings_register |= (regmask * mode);
3380         hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3381
3382         return 0;
3383 }
3384
3385 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol,
3386                                        struct snd_ctl_elem_info *uinfo)
3387 {
3388         u32 regmask = kcontrol->private_value;
3389
3390         static char *texts_spdif[] = { "Optical", "Coaxial", "Internal" };
3391         static char *texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
3392
3393         switch (regmask) {
3394         case HDSPM_c0_Input0:
3395                 ENUMERATED_CTL_INFO(uinfo, texts_spdif);
3396                 break;
3397         default:
3398                 ENUMERATED_CTL_INFO(uinfo, texts_levels);
3399                 break;
3400         }
3401         return 0;
3402 }
3403
3404 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol,
3405                                       struct snd_ctl_elem_value *ucontrol)
3406 {
3407         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3408         u32 regmask = kcontrol->private_value;
3409
3410         spin_lock_irq(&hdspm->lock);
3411         ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3412         spin_unlock_irq(&hdspm->lock);
3413         return 0;
3414 }
3415
3416 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol,
3417                                       struct snd_ctl_elem_value *ucontrol)
3418 {
3419         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3420         u32 regmask = kcontrol->private_value;
3421         int change;
3422         int val;
3423
3424         if (!snd_hdspm_use_is_exclusive(hdspm))
3425                 return -EBUSY;
3426         val = ucontrol->value.integer.value[0];
3427         if (val < 0)
3428                 val = 0;
3429         if (val > 2)
3430                 val = 2;
3431
3432         spin_lock_irq(&hdspm->lock);
3433         change = val != hdspm_tristate(hdspm, regmask);
3434         hdspm_set_tristate(hdspm, val, regmask);
3435         spin_unlock_irq(&hdspm->lock);
3436         return change;
3437 }
3438
3439 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3440 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3441         .name = xname, \
3442         .index = xindex, \
3443         .info = snd_hdspm_info_madi_speedmode, \
3444         .get = snd_hdspm_get_madi_speedmode, \
3445         .put = snd_hdspm_put_madi_speedmode \
3446 }
3447
3448 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3449 {
3450         if (hdspm->control_register & HDSPM_QuadSpeed)
3451                 return 2;
3452         if (hdspm->control_register & HDSPM_DoubleSpeed)
3453                 return 1;
3454         return 0;
3455 }
3456
3457 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3458 {
3459         hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3460         switch (mode) {
3461         case 0:
3462                 break;
3463         case 1:
3464                 hdspm->control_register |= HDSPM_DoubleSpeed;
3465                 break;
3466         case 2:
3467                 hdspm->control_register |= HDSPM_QuadSpeed;
3468                 break;
3469         }
3470         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3471
3472         return 0;
3473 }
3474
3475 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3476                                        struct snd_ctl_elem_info *uinfo)
3477 {
3478         static char *texts[] = { "Single", "Double", "Quad" };
3479         ENUMERATED_CTL_INFO(uinfo, texts);
3480         return 0;
3481 }
3482
3483 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3484                                       struct snd_ctl_elem_value *ucontrol)
3485 {
3486         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3487
3488         spin_lock_irq(&hdspm->lock);
3489         ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3490         spin_unlock_irq(&hdspm->lock);
3491         return 0;
3492 }
3493
3494 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3495                                       struct snd_ctl_elem_value *ucontrol)
3496 {
3497         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3498         int change;
3499         int val;
3500
3501         if (!snd_hdspm_use_is_exclusive(hdspm))
3502                 return -EBUSY;
3503         val = ucontrol->value.integer.value[0];
3504         if (val < 0)
3505                 val = 0;
3506         if (val > 2)
3507                 val = 2;
3508         spin_lock_irq(&hdspm->lock);
3509         change = val != hdspm_madi_speedmode(hdspm);
3510         hdspm_set_madi_speedmode(hdspm, val);
3511         spin_unlock_irq(&hdspm->lock);
3512         return change;
3513 }
3514
3515 #define HDSPM_MIXER(xname, xindex) \
3516 {       .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3517         .name = xname, \
3518         .index = xindex, \
3519         .device = 0, \
3520         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3521                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3522         .info = snd_hdspm_info_mixer, \
3523         .get = snd_hdspm_get_mixer, \
3524         .put = snd_hdspm_put_mixer \
3525 }
3526
3527 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3528                                 struct snd_ctl_elem_info *uinfo)
3529 {
3530         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3531         uinfo->count = 3;
3532         uinfo->value.integer.min = 0;
3533         uinfo->value.integer.max = 65535;
3534         uinfo->value.integer.step = 1;
3535         return 0;
3536 }
3537
3538 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3539                                struct snd_ctl_elem_value *ucontrol)
3540 {
3541         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3542         int source;
3543         int destination;
3544
3545         source = ucontrol->value.integer.value[0];
3546         if (source < 0)
3547                 source = 0;
3548         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3549                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3550
3551         destination = ucontrol->value.integer.value[1];
3552         if (destination < 0)
3553                 destination = 0;
3554         else if (destination >= HDSPM_MAX_CHANNELS)
3555                 destination = HDSPM_MAX_CHANNELS - 1;
3556
3557         spin_lock_irq(&hdspm->lock);
3558         if (source >= HDSPM_MAX_CHANNELS)
3559                 ucontrol->value.integer.value[2] =
3560                     hdspm_read_pb_gain(hdspm, destination,
3561                                        source - HDSPM_MAX_CHANNELS);
3562         else
3563                 ucontrol->value.integer.value[2] =
3564                     hdspm_read_in_gain(hdspm, destination, source);
3565
3566         spin_unlock_irq(&hdspm->lock);
3567
3568         return 0;
3569 }
3570
3571 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3572                                struct snd_ctl_elem_value *ucontrol)
3573 {
3574         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3575         int change;
3576         int source;
3577         int destination;
3578         int gain;
3579
3580         if (!snd_hdspm_use_is_exclusive(hdspm))
3581                 return -EBUSY;
3582
3583         source = ucontrol->value.integer.value[0];
3584         destination = ucontrol->value.integer.value[1];
3585
3586         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3587                 return -1;
3588         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3589                 return -1;
3590
3591         gain = ucontrol->value.integer.value[2];
3592
3593         spin_lock_irq(&hdspm->lock);
3594
3595         if (source >= HDSPM_MAX_CHANNELS)
3596                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3597                                                     source -
3598                                                     HDSPM_MAX_CHANNELS);
3599         else
3600                 change = gain != hdspm_read_in_gain(hdspm, destination,
3601                                                     source);
3602
3603         if (change) {
3604                 if (source >= HDSPM_MAX_CHANNELS)
3605                         hdspm_write_pb_gain(hdspm, destination,
3606                                             source - HDSPM_MAX_CHANNELS,
3607                                             gain);
3608                 else
3609                         hdspm_write_in_gain(hdspm, destination, source,
3610                                             gain);
3611         }
3612         spin_unlock_irq(&hdspm->lock);
3613
3614         return change;
3615 }
3616
3617 /* The simple mixer control(s) provide gain control for the
3618    basic 1:1 mappings of playback streams to output
3619    streams.
3620 */
3621
3622 #define HDSPM_PLAYBACK_MIXER \
3623 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3624         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3625                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3626         .info = snd_hdspm_info_playback_mixer, \
3627         .get = snd_hdspm_get_playback_mixer, \
3628         .put = snd_hdspm_put_playback_mixer \
3629 }
3630
3631 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3632                                          struct snd_ctl_elem_info *uinfo)
3633 {
3634         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3635         uinfo->count = 1;
3636         uinfo->value.integer.min = 0;
3637         uinfo->value.integer.max = 64;
3638         uinfo->value.integer.step = 1;
3639         return 0;
3640 }
3641
3642 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3643                                         struct snd_ctl_elem_value *ucontrol)
3644 {
3645         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3646         int channel;
3647
3648         channel = ucontrol->id.index - 1;
3649
3650         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3651                 return -EINVAL;
3652
3653         spin_lock_irq(&hdspm->lock);
3654         ucontrol->value.integer.value[0] =
3655           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3656         spin_unlock_irq(&hdspm->lock);
3657
3658         return 0;
3659 }
3660
3661 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3662                                         struct snd_ctl_elem_value *ucontrol)
3663 {
3664         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3665         int change;
3666         int channel;
3667         int gain;
3668
3669         if (!snd_hdspm_use_is_exclusive(hdspm))
3670                 return -EBUSY;
3671
3672         channel = ucontrol->id.index - 1;
3673
3674         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3675                 return -EINVAL;
3676
3677         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3678
3679         spin_lock_irq(&hdspm->lock);
3680         change =
3681             gain != hdspm_read_pb_gain(hdspm, channel,
3682                                        channel);
3683         if (change)
3684                 hdspm_write_pb_gain(hdspm, channel, channel,
3685                                     gain);
3686         spin_unlock_irq(&hdspm->lock);
3687         return change;
3688 }
3689
3690 #define HDSPM_SYNC_CHECK(xname, xindex) \
3691 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3692         .name = xname, \
3693         .private_value = xindex, \
3694         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3695         .info = snd_hdspm_info_sync_check, \
3696         .get = snd_hdspm_get_sync_check \
3697 }
3698
3699 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3700 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3701         .name = xname, \
3702         .private_value = xindex, \
3703         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3704         .info = snd_hdspm_tco_info_lock_check, \
3705         .get = snd_hdspm_get_sync_check \
3706 }
3707
3708
3709
3710 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3711                                      struct snd_ctl_elem_info *uinfo)
3712 {
3713         static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3714         ENUMERATED_CTL_INFO(uinfo, texts);
3715         return 0;
3716 }
3717
3718 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3719                                      struct snd_ctl_elem_info *uinfo)
3720 {
3721         static char *texts[] = { "No Lock", "Lock" };
3722         ENUMERATED_CTL_INFO(uinfo, texts);
3723         return 0;
3724 }
3725
3726 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3727 {
3728         int status, status2;
3729
3730         switch (hdspm->io_type) {
3731         case AES32:
3732                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3733                 if (status & HDSPM_AES32_wcLock) {
3734                         if (status & HDSPM_AES32_wcSync)
3735                                 return 2;
3736                         else
3737                                 return 1;
3738                 }
3739                 return 0;
3740                 break;
3741
3742         case MADI:
3743                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3744                 if (status2 & HDSPM_wcLock) {
3745                         if (status2 & HDSPM_wcSync)
3746                                 return 2;
3747                         else
3748                                 return 1;
3749                 }
3750                 return 0;
3751                 break;
3752
3753         case RayDAT:
3754         case AIO:
3755                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3756
3757                 if (status & 0x2000000)
3758                         return 2;
3759                 else if (status & 0x1000000)
3760                         return 1;
3761                 return 0;
3762
3763                 break;
3764
3765         case MADIface:
3766                 break;
3767         }
3768
3769
3770         return 3;
3771 }
3772
3773
3774 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3775 {
3776         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3777         if (status & HDSPM_madiLock) {
3778                 if (status & HDSPM_madiSync)
3779                         return 2;
3780                 else
3781                         return 1;
3782         }
3783         return 0;
3784 }
3785
3786
3787 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3788 {
3789         int status, lock, sync;
3790
3791         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3792
3793         lock = (status & (0x1<<idx)) ? 1 : 0;
3794         sync = (status & (0x100<<idx)) ? 1 : 0;
3795
3796         if (lock && sync)
3797                 return 2;
3798         else if (lock)
3799                 return 1;
3800         return 0;
3801 }
3802
3803
3804 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3805 {
3806         int status, lock = 0, sync = 0;
3807
3808         switch (hdspm->io_type) {
3809         case RayDAT:
3810         case AIO:
3811                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3812                 lock = (status & 0x400) ? 1 : 0;
3813                 sync = (status & 0x800) ? 1 : 0;
3814                 break;
3815
3816         case MADI:
3817                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3818                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3819                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3820                 break;
3821
3822         case AES32:
3823                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3824                 lock = (status & 0x100000) ? 1 : 0;
3825                 sync = (status & 0x200000) ? 1 : 0;
3826                 break;
3827
3828         case MADIface:
3829                 break;
3830         }
3831
3832         if (lock && sync)
3833                 return 2;
3834         else if (lock)
3835                 return 1;
3836
3837         return 0;
3838 }
3839
3840 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3841 {
3842         int status2, lock, sync;
3843         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3844
3845         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3846         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3847
3848         if (sync)
3849                 return 2;
3850         else if (lock)
3851                 return 1;
3852         return 0;
3853 }
3854
3855 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3856 {
3857         u32 status;
3858         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3859
3860         return (status & mask) ? 1 : 0;
3861 }
3862
3863
3864 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3865 {
3866         int status;
3867
3868         if (hdspm->tco) {
3869                 switch (hdspm->io_type) {
3870                 case MADI:
3871                 case AES32:
3872                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3873                         if (status & HDSPM_tcoLock) {
3874                                 if (status & HDSPM_tcoSync)
3875                                         return 2;
3876                                 else
3877                                         return 1;
3878                         }
3879                         return 0;
3880
3881                         break;
3882
3883                 case RayDAT:
3884                 case AIO:
3885                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3886
3887                         if (status & 0x8000000)
3888                                 return 2; /* Sync */
3889                         if (status & 0x4000000)
3890                                 return 1; /* Lock */
3891                         return 0; /* No signal */
3892                         break;
3893
3894                 default:
3895                         break;
3896                 }
3897         }
3898
3899         return 3; /* N/A */
3900 }
3901
3902
3903 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3904                                     struct snd_ctl_elem_value *ucontrol)
3905 {
3906         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3907         int val = -1;
3908
3909         switch (hdspm->io_type) {
3910         case RayDAT:
3911                 switch (kcontrol->private_value) {
3912                 case 0: /* WC */
3913                         val = hdspm_wc_sync_check(hdspm); break;
3914                 case 7: /* TCO */
3915                         val = hdspm_tco_sync_check(hdspm); break;
3916                 case 8: /* SYNC IN */
3917                         val = hdspm_sync_in_sync_check(hdspm); break;
3918                 default:
3919                         val = hdspm_s1_sync_check(hdspm,
3920                                         kcontrol->private_value-1);
3921                 }
3922                 break;
3923
3924         case AIO:
3925                 switch (kcontrol->private_value) {
3926                 case 0: /* WC */
3927                         val = hdspm_wc_sync_check(hdspm); break;
3928                 case 4: /* TCO */
3929                         val = hdspm_tco_sync_check(hdspm); break;
3930                 case 5: /* SYNC IN */
3931                         val = hdspm_sync_in_sync_check(hdspm); break;
3932                 default:
3933                         val = hdspm_s1_sync_check(hdspm,
3934                                         kcontrol->private_value-1);
3935                 }
3936                 break;
3937
3938         case MADI:
3939                 switch (kcontrol->private_value) {
3940                 case 0: /* WC */
3941                         val = hdspm_wc_sync_check(hdspm); break;
3942                 case 1: /* MADI */
3943                         val = hdspm_madi_sync_check(hdspm); break;
3944                 case 2: /* TCO */
3945                         val = hdspm_tco_sync_check(hdspm); break;
3946                 case 3: /* SYNC_IN */
3947                         val = hdspm_sync_in_sync_check(hdspm); break;
3948                 }
3949                 break;
3950
3951         case MADIface:
3952                 val = hdspm_madi_sync_check(hdspm); /* MADI */
3953                 break;
3954
3955         case AES32:
3956                 switch (kcontrol->private_value) {
3957                 case 0: /* WC */
3958                         val = hdspm_wc_sync_check(hdspm); break;
3959                 case 9: /* TCO */
3960                         val = hdspm_tco_sync_check(hdspm); break;
3961                 case 10 /* SYNC IN */:
3962                         val = hdspm_sync_in_sync_check(hdspm); break;
3963                 default: /* AES1 to AES8 */
3964                          val = hdspm_aes_sync_check(hdspm,
3965                                          kcontrol->private_value-1);
3966                 }
3967                 break;
3968
3969         }
3970
3971         if (hdspm->tco) {
3972                 switch (kcontrol->private_value) {
3973                 case 11:
3974                         /* Check TCO for lock state of its current input */
3975                         val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
3976                         break;
3977                 case 12:
3978                         /* Check TCO for valid time code on LTC input. */
3979                         val = hdspm_tco_input_check(hdspm,
3980                                 HDSPM_TCO1_LTC_Input_valid);
3981                         break;
3982                 default:
3983                         break;
3984                 }
3985         }
3986
3987         if (-1 == val)
3988                 val = 3;
3989
3990         ucontrol->value.enumerated.item[0] = val;
3991         return 0;
3992 }
3993
3994
3995
3996 /**
3997  * TCO controls
3998  **/
3999 static void hdspm_tco_write(struct hdspm *hdspm)
4000 {
4001         unsigned int tc[4] = { 0, 0, 0, 0};
4002
4003         switch (hdspm->tco->input) {
4004         case 0:
4005                 tc[2] |= HDSPM_TCO2_set_input_MSB;
4006                 break;
4007         case 1:
4008                 tc[2] |= HDSPM_TCO2_set_input_LSB;
4009                 break;
4010         default:
4011                 break;
4012         }
4013
4014         switch (hdspm->tco->framerate) {
4015         case 1:
4016                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4017                 break;
4018         case 2:
4019                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4020                 break;
4021         case 3:
4022                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4023                         HDSPM_TCO1_set_drop_frame_flag;
4024                 break;
4025         case 4:
4026                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4027                         HDSPM_TCO1_LTC_Format_MSB;
4028                 break;
4029         case 5:
4030                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4031                         HDSPM_TCO1_LTC_Format_MSB +
4032                         HDSPM_TCO1_set_drop_frame_flag;
4033                 break;
4034         default:
4035                 break;
4036         }
4037
4038         switch (hdspm->tco->wordclock) {
4039         case 1:
4040                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4041                 break;
4042         case 2:
4043                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4044                 break;
4045         default:
4046                 break;
4047         }
4048
4049         switch (hdspm->tco->samplerate) {
4050         case 1:
4051                 tc[2] |= HDSPM_TCO2_set_freq;
4052                 break;
4053         case 2:
4054                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4055                 break;
4056         default:
4057                 break;
4058         }
4059
4060         switch (hdspm->tco->pull) {
4061         case 1:
4062                 tc[2] |= HDSPM_TCO2_set_pull_up;
4063                 break;
4064         case 2:
4065                 tc[2] |= HDSPM_TCO2_set_pull_down;
4066                 break;
4067         case 3:
4068                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4069                 break;
4070         case 4:
4071                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4072                 break;
4073         default:
4074                 break;
4075         }
4076
4077         if (1 == hdspm->tco->term) {
4078                 tc[2] |= HDSPM_TCO2_set_term_75R;
4079         }
4080
4081         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4082         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4083         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4084         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4085 }
4086
4087
4088 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4089 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4090         .name = xname, \
4091         .index = xindex, \
4092         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4093                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4094         .info = snd_hdspm_info_tco_sample_rate, \
4095         .get = snd_hdspm_get_tco_sample_rate, \
4096         .put = snd_hdspm_put_tco_sample_rate \
4097 }
4098
4099 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4100                                           struct snd_ctl_elem_info *uinfo)
4101 {
4102         static char *texts[] = { "44.1 kHz", "48 kHz" };
4103         ENUMERATED_CTL_INFO(uinfo, texts);
4104         return 0;
4105 }
4106
4107 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4108                                       struct snd_ctl_elem_value *ucontrol)
4109 {
4110         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4111
4112         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4113
4114         return 0;
4115 }
4116
4117 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4118                                          struct snd_ctl_elem_value *ucontrol)
4119 {
4120         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4121
4122         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4123                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4124
4125                 hdspm_tco_write(hdspm);
4126
4127                 return 1;
4128         }
4129
4130         return 0;
4131 }
4132
4133
4134 #define HDSPM_TCO_PULL(xname, xindex) \
4135 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4136         .name = xname, \
4137         .index = xindex, \
4138         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4139                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4140         .info = snd_hdspm_info_tco_pull, \
4141         .get = snd_hdspm_get_tco_pull, \
4142         .put = snd_hdspm_put_tco_pull \
4143 }
4144
4145 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4146                                    struct snd_ctl_elem_info *uinfo)
4147 {
4148         static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4149         ENUMERATED_CTL_INFO(uinfo, texts);
4150         return 0;
4151 }
4152
4153 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4154                                   struct snd_ctl_elem_value *ucontrol)
4155 {
4156         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4157
4158         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4159
4160         return 0;
4161 }
4162
4163 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4164                                   struct snd_ctl_elem_value *ucontrol)
4165 {
4166         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4167
4168         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4169                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4170
4171                 hdspm_tco_write(hdspm);
4172
4173                 return 1;
4174         }
4175
4176         return 0;
4177 }
4178
4179 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4180 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4181         .name = xname, \
4182         .index = xindex, \
4183         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4184                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4185         .info = snd_hdspm_info_tco_wck_conversion, \
4186         .get = snd_hdspm_get_tco_wck_conversion, \
4187         .put = snd_hdspm_put_tco_wck_conversion \
4188 }
4189
4190 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4191                                              struct snd_ctl_elem_info *uinfo)
4192 {
4193         static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4194         ENUMERATED_CTL_INFO(uinfo, texts);
4195         return 0;
4196 }
4197
4198 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4199                                             struct snd_ctl_elem_value *ucontrol)
4200 {
4201         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4202
4203         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4204
4205         return 0;
4206 }
4207
4208 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4209                                             struct snd_ctl_elem_value *ucontrol)
4210 {
4211         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4212
4213         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4214                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4215
4216                 hdspm_tco_write(hdspm);
4217
4218                 return 1;
4219         }
4220
4221         return 0;
4222 }
4223
4224
4225 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4226 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4227         .name = xname, \
4228         .index = xindex, \
4229         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4230                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4231         .info = snd_hdspm_info_tco_frame_rate, \
4232         .get = snd_hdspm_get_tco_frame_rate, \
4233         .put = snd_hdspm_put_tco_frame_rate \
4234 }
4235
4236 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4237                                           struct snd_ctl_elem_info *uinfo)
4238 {
4239         static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4240                 "29.97 dfps", "30 fps", "30 dfps" };
4241         ENUMERATED_CTL_INFO(uinfo, texts);
4242         return 0;
4243 }
4244
4245 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4246                                         struct snd_ctl_elem_value *ucontrol)
4247 {
4248         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4249
4250         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4251
4252         return 0;
4253 }
4254
4255 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4256                                         struct snd_ctl_elem_value *ucontrol)
4257 {
4258         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4259
4260         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4261                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4262
4263                 hdspm_tco_write(hdspm);
4264
4265                 return 1;
4266         }
4267
4268         return 0;
4269 }
4270
4271
4272 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4273 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4274         .name = xname, \
4275         .index = xindex, \
4276         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4277                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4278         .info = snd_hdspm_info_tco_sync_source, \
4279         .get = snd_hdspm_get_tco_sync_source, \
4280         .put = snd_hdspm_put_tco_sync_source \
4281 }
4282
4283 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4284                                           struct snd_ctl_elem_info *uinfo)
4285 {
4286         static char *texts[] = { "LTC", "Video", "WCK" };
4287         ENUMERATED_CTL_INFO(uinfo, texts);
4288         return 0;
4289 }
4290
4291 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4292                                          struct snd_ctl_elem_value *ucontrol)
4293 {
4294         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4295
4296         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4297
4298         return 0;
4299 }
4300
4301 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4302                                          struct snd_ctl_elem_value *ucontrol)
4303 {
4304         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4305
4306         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4307                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4308
4309                 hdspm_tco_write(hdspm);
4310
4311                 return 1;
4312         }
4313
4314         return 0;
4315 }
4316
4317
4318 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4319 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4320         .name = xname, \
4321         .index = xindex, \
4322         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4323                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4324         .info = snd_hdspm_info_tco_word_term, \
4325         .get = snd_hdspm_get_tco_word_term, \
4326         .put = snd_hdspm_put_tco_word_term \
4327 }
4328
4329 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4330                                         struct snd_ctl_elem_info *uinfo)
4331 {
4332         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4333         uinfo->count = 1;
4334         uinfo->value.integer.min = 0;
4335         uinfo->value.integer.max = 1;
4336
4337         return 0;
4338 }
4339
4340
4341 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4342                                        struct snd_ctl_elem_value *ucontrol)
4343 {
4344         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4345
4346         ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4347
4348         return 0;
4349 }
4350
4351
4352 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4353                                        struct snd_ctl_elem_value *ucontrol)
4354 {
4355         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4356
4357         if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4358                 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4359
4360                 hdspm_tco_write(hdspm);
4361
4362                 return 1;
4363         }
4364
4365         return 0;
4366 }
4367
4368
4369
4370
4371 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4372         HDSPM_MIXER("Mixer", 0),
4373         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4374         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4375         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4376         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4377         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4378         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4379         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4380         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4381         HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4382         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4383         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4384         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4385         HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4386         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4387         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4388         HDSPM_INPUT_SELECT("Input Select", 0),
4389         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4390 };
4391
4392
4393 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4394         HDSPM_MIXER("Mixer", 0),
4395         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4396         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4397         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4398         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4399         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4400         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4401         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4402         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4403         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4404 };
4405
4406 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4407         HDSPM_MIXER("Mixer", 0),
4408         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4409         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4410         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4411         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4412         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4413         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4414         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4415         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4416         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4417         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4418         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4419         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4420         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4421         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4422         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4423         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4424         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4425         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
4426         HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0),
4427         HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt),
4428         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4429         HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1),
4430         HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db),
4431         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48),
4432         HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0),
4433         HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0),
4434         HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0)
4435
4436                 /*
4437                    HDSPM_INPUT_SELECT("Input Select", 0),
4438                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4439                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4440                    HDSPM_SPDIF_IN("SPDIF In", 0);
4441                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4442                    HDSPM_INPUT_LEVEL("Input Level", 0);
4443                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4444                    HDSPM_PHONES("Phones", 0);
4445                    */
4446 };
4447
4448 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4449         HDSPM_MIXER("Mixer", 0),
4450         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4451         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4452         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4453         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4454         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4455         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4456         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4457         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4458         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4459         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4460         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4461         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4462         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4463         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4464         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4465         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4466         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4467         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4468         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4469         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4470         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4471         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4472         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4473         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
4474 };
4475
4476 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4477         HDSPM_MIXER("Mixer", 0),
4478         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4479         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4480         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4481         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4482         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4483         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4484         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4485         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4486         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4487         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4488         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4489         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4490         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4491         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4492         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4493         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4494         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4495         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4496         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4497         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4498         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4499         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4500         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4501         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4502         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4503         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4504         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4505         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4506         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4507         HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4508         HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4509         HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4510         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4511         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4512         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4513 };
4514
4515
4516
4517 /* Control elements for the optional TCO module */
4518 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4519         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4520         HDSPM_TCO_PULL("TCO Pull", 0),
4521         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4522         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4523         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4524         HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4525         HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4526         HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4527         HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4528         HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4529 };
4530
4531
4532 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4533
4534
4535 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4536 {
4537         int i;
4538
4539         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4540                 if (hdspm->system_sample_rate > 48000) {
4541                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4542                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4543                                 SNDRV_CTL_ELEM_ACCESS_READ |
4544                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4545                 } else {
4546                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4547                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4548                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4549                 }
4550                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4551                                 SNDRV_CTL_EVENT_MASK_INFO,
4552                                 &hdspm->playback_mixer_ctls[i]->id);
4553         }
4554
4555         return 0;
4556 }
4557
4558
4559 static int snd_hdspm_create_controls(struct snd_card *card,
4560                                         struct hdspm *hdspm)
4561 {
4562         unsigned int idx, limit;
4563         int err;
4564         struct snd_kcontrol *kctl;
4565         struct snd_kcontrol_new *list = NULL;
4566
4567         switch (hdspm->io_type) {
4568         case MADI:
4569                 list = snd_hdspm_controls_madi;
4570                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4571                 break;
4572         case MADIface:
4573                 list = snd_hdspm_controls_madiface;
4574                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4575                 break;
4576         case AIO:
4577                 list = snd_hdspm_controls_aio;
4578                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4579                 break;
4580         case RayDAT:
4581                 list = snd_hdspm_controls_raydat;
4582                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4583                 break;
4584         case AES32:
4585                 list = snd_hdspm_controls_aes32;
4586                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4587                 break;
4588         }
4589
4590         if (NULL != list) {
4591                 for (idx = 0; idx < limit; idx++) {
4592                         err = snd_ctl_add(card,
4593                                         snd_ctl_new1(&list[idx], hdspm));
4594                         if (err < 0)
4595                                 return err;
4596                 }
4597         }
4598
4599
4600         /* create simple 1:1 playback mixer controls */
4601         snd_hdspm_playback_mixer.name = "Chn";
4602         if (hdspm->system_sample_rate >= 128000) {
4603                 limit = hdspm->qs_out_channels;
4604         } else if (hdspm->system_sample_rate >= 64000) {
4605                 limit = hdspm->ds_out_channels;
4606         } else {
4607                 limit = hdspm->ss_out_channels;
4608         }
4609         for (idx = 0; idx < limit; ++idx) {
4610                 snd_hdspm_playback_mixer.index = idx + 1;
4611                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4612                 err = snd_ctl_add(card, kctl);
4613                 if (err < 0)
4614                         return err;
4615                 hdspm->playback_mixer_ctls[idx] = kctl;
4616         }
4617
4618
4619         if (hdspm->tco) {
4620                 /* add tco control elements */
4621                 list = snd_hdspm_controls_tco;
4622                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4623                 for (idx = 0; idx < limit; idx++) {
4624                         err = snd_ctl_add(card,
4625                                         snd_ctl_new1(&list[idx], hdspm));
4626                         if (err < 0)
4627                                 return err;
4628                 }
4629         }
4630
4631         return 0;
4632 }
4633
4634 /*------------------------------------------------------------
4635    /proc interface
4636  ------------------------------------------------------------*/
4637
4638 static void
4639 snd_hdspm_proc_read_tco(struct snd_info_entry *entry,
4640                                         struct snd_info_buffer *buffer)
4641 {
4642         struct hdspm *hdspm = entry->private_data;
4643         unsigned int status, control;
4644         int a, ltc, frames, seconds, minutes, hours;
4645         unsigned int period;
4646         u64 freq_const = 0;
4647         u32 rate;
4648
4649         snd_iprintf(buffer, "--- TCO ---\n");
4650
4651         status = hdspm_read(hdspm, HDSPM_statusRegister);
4652         control = hdspm->control_register;
4653
4654
4655         if (status & HDSPM_tco_detect) {
4656                 snd_iprintf(buffer, "TCO module detected.\n");
4657                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4658                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4659                         snd_iprintf(buffer, "  LTC valid, ");
4660                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4661                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4662                         case 0:
4663                                 snd_iprintf(buffer, "24 fps, ");
4664                                 break;
4665                         case HDSPM_TCO1_LTC_Format_LSB:
4666                                 snd_iprintf(buffer, "25 fps, ");
4667                                 break;
4668                         case HDSPM_TCO1_LTC_Format_MSB:
4669                                 snd_iprintf(buffer, "29.97 fps, ");
4670                                 break;
4671                         default:
4672                                 snd_iprintf(buffer, "30 fps, ");
4673                                 break;
4674                         }
4675                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4676                                 snd_iprintf(buffer, "drop frame\n");
4677                         } else {
4678                                 snd_iprintf(buffer, "full frame\n");
4679                         }
4680                 } else {
4681                         snd_iprintf(buffer, "  no LTC\n");
4682                 }
4683                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4684                         snd_iprintf(buffer, "  Video: NTSC\n");
4685                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4686                         snd_iprintf(buffer, "  Video: PAL\n");
4687                 } else {
4688                         snd_iprintf(buffer, "  No video\n");
4689                 }
4690                 if (a & HDSPM_TCO1_TCO_lock) {
4691                         snd_iprintf(buffer, "  Sync: lock\n");
4692                 } else {
4693                         snd_iprintf(buffer, "  Sync: no lock\n");
4694                 }
4695
4696                 switch (hdspm->io_type) {
4697                 case MADI:
4698                 case AES32:
4699                         freq_const = 110069313433624ULL;
4700                         break;
4701                 case RayDAT:
4702                 case AIO:
4703                         freq_const = 104857600000000ULL;
4704                         break;
4705                 case MADIface:
4706                         break; /* no TCO possible */
4707                 }
4708
4709                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4710                 snd_iprintf(buffer, "    period: %u\n", period);
4711
4712
4713                 /* rate = freq_const/period; */
4714                 rate = div_u64(freq_const, period);
4715
4716                 if (control & HDSPM_QuadSpeed) {
4717                         rate *= 4;
4718                 } else if (control & HDSPM_DoubleSpeed) {
4719                         rate *= 2;
4720                 }
4721
4722                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4723                                 (unsigned int) rate);
4724
4725                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4726                 frames = ltc & 0xF;
4727                 ltc >>= 4;
4728                 frames += (ltc & 0x3) * 10;
4729                 ltc >>= 4;
4730                 seconds = ltc & 0xF;
4731                 ltc >>= 4;
4732                 seconds += (ltc & 0x7) * 10;
4733                 ltc >>= 4;
4734                 minutes = ltc & 0xF;
4735                 ltc >>= 4;
4736                 minutes += (ltc & 0x7) * 10;
4737                 ltc >>= 4;
4738                 hours = ltc & 0xF;
4739                 ltc >>= 4;
4740                 hours += (ltc & 0x3) * 10;
4741                 snd_iprintf(buffer,
4742                         "  LTC In: %02d:%02d:%02d:%02d\n",
4743                         hours, minutes, seconds, frames);
4744
4745         } else {
4746                 snd_iprintf(buffer, "No TCO module detected.\n");
4747         }
4748 }
4749
4750 static void
4751 snd_hdspm_proc_read_madi(struct snd_info_entry *entry,
4752                          struct snd_info_buffer *buffer)
4753 {
4754         struct hdspm *hdspm = entry->private_data;
4755         unsigned int status, status2, control, freq;
4756
4757         char *pref_sync_ref;
4758         char *autosync_ref;
4759         char *system_clock_mode;
4760         char *insel;
4761         int x, x2;
4762
4763         status = hdspm_read(hdspm, HDSPM_statusRegister);
4764         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4765         control = hdspm->control_register;
4766         freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4767
4768         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4769                         hdspm->card_name, hdspm->card->number + 1,
4770                         hdspm->firmware_rev,
4771                         (status2 & HDSPM_version0) |
4772                         (status2 & HDSPM_version1) | (status2 &
4773                                 HDSPM_version2));
4774
4775         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4776                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4777                         hdspm->serial);
4778
4779         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4780                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4781
4782         snd_iprintf(buffer, "--- System ---\n");
4783
4784         snd_iprintf(buffer,
4785                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4786                 status & HDSPM_audioIRQPending,
4787                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4788                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4789                 hdspm->irq_count);
4790         snd_iprintf(buffer,
4791                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4792                 "estimated= %ld (bytes)\n",
4793                 ((status & HDSPM_BufferID) ? 1 : 0),
4794                 (status & HDSPM_BufferPositionMask),
4795                 (status & HDSPM_BufferPositionMask) %
4796                 (2 * (int)hdspm->period_bytes),
4797                 ((status & HDSPM_BufferPositionMask) - 64) %
4798                 (2 * (int)hdspm->period_bytes),
4799                 (long) hdspm_hw_pointer(hdspm) * 4);
4800
4801         snd_iprintf(buffer,
4802                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4803                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4804                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4805                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4806                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4807         snd_iprintf(buffer,
4808                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4809                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4810                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4811         snd_iprintf(buffer,
4812                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4813                 "status2=0x%x\n",
4814                 hdspm->control_register, hdspm->control2_register,
4815                 status, status2);
4816
4817
4818         snd_iprintf(buffer, "--- Settings ---\n");
4819
4820         x = hdspm_get_latency(hdspm);
4821
4822         snd_iprintf(buffer,
4823                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4824                 x, (unsigned long) hdspm->period_bytes);
4825
4826         snd_iprintf(buffer, "Line out: %s\n",
4827                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4828
4829         switch (hdspm->control_register & HDSPM_InputMask) {
4830         case HDSPM_InputOptical:
4831                 insel = "Optical";
4832                 break;
4833         case HDSPM_InputCoaxial:
4834                 insel = "Coaxial";
4835                 break;
4836         default:
4837                 insel = "Unknown";
4838         }
4839
4840         snd_iprintf(buffer,
4841                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4842                 "Auto Input %s\n",
4843                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4844                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4845                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4846
4847
4848         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4849                 system_clock_mode = "AutoSync";
4850         else
4851                 system_clock_mode = "Master";
4852         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4853
4854         switch (hdspm_pref_sync_ref(hdspm)) {
4855         case HDSPM_SYNC_FROM_WORD:
4856                 pref_sync_ref = "Word Clock";
4857                 break;
4858         case HDSPM_SYNC_FROM_MADI:
4859                 pref_sync_ref = "MADI Sync";
4860                 break;
4861         case HDSPM_SYNC_FROM_TCO:
4862                 pref_sync_ref = "TCO";
4863                 break;
4864         case HDSPM_SYNC_FROM_SYNC_IN:
4865                 pref_sync_ref = "Sync In";
4866                 break;
4867         default:
4868                 pref_sync_ref = "XXXX Clock";
4869                 break;
4870         }
4871         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4872                         pref_sync_ref);
4873
4874         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4875                         hdspm->system_sample_rate);
4876
4877
4878         snd_iprintf(buffer, "--- Status:\n");
4879
4880         x = status & HDSPM_madiSync;
4881         x2 = status2 & HDSPM_wcSync;
4882
4883         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4884                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4885                         "NoLock",
4886                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4887                         "NoLock");
4888
4889         switch (hdspm_autosync_ref(hdspm)) {
4890         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4891                 autosync_ref = "Sync In";
4892                 break;
4893         case HDSPM_AUTOSYNC_FROM_TCO:
4894                 autosync_ref = "TCO";
4895                 break;
4896         case HDSPM_AUTOSYNC_FROM_WORD:
4897                 autosync_ref = "Word Clock";
4898                 break;
4899         case HDSPM_AUTOSYNC_FROM_MADI:
4900                 autosync_ref = "MADI Sync";
4901                 break;
4902         case HDSPM_AUTOSYNC_FROM_NONE:
4903                 autosync_ref = "Input not valid";
4904                 break;
4905         default:
4906                 autosync_ref = "---";
4907                 break;
4908         }
4909         snd_iprintf(buffer,
4910                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4911                 autosync_ref, hdspm_external_sample_rate(hdspm),
4912                 (status & HDSPM_madiFreqMask) >> 22,
4913                 (status2 & HDSPM_wcFreqMask) >> 5);
4914
4915         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4916                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4917                 (status & HDSPM_RX_64ch) ? "64 channels" :
4918                 "56 channels");
4919
4920         /* call readout function for TCO specific status */
4921         snd_hdspm_proc_read_tco(entry, buffer);
4922
4923         snd_iprintf(buffer, "\n");
4924 }
4925
4926 static void
4927 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4928                           struct snd_info_buffer *buffer)
4929 {
4930         struct hdspm *hdspm = entry->private_data;
4931         unsigned int status;
4932         unsigned int status2;
4933         unsigned int timecode;
4934         unsigned int wcLock, wcSync;
4935         int pref_syncref;
4936         char *autosync_ref;
4937         int x;
4938
4939         status = hdspm_read(hdspm, HDSPM_statusRegister);
4940         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4941         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4942
4943         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4944                     hdspm->card_name, hdspm->card->number + 1,
4945                     hdspm->firmware_rev);
4946
4947         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4948                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4949
4950         snd_iprintf(buffer, "--- System ---\n");
4951
4952         snd_iprintf(buffer,
4953                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4954                     status & HDSPM_audioIRQPending,
4955                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
4956                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
4957                     hdspm->irq_count);
4958         snd_iprintf(buffer,
4959                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
4960                     "estimated= %ld (bytes)\n",
4961                     ((status & HDSPM_BufferID) ? 1 : 0),
4962                     (status & HDSPM_BufferPositionMask),
4963                     (status & HDSPM_BufferPositionMask) %
4964                     (2 * (int)hdspm->period_bytes),
4965                     ((status & HDSPM_BufferPositionMask) - 64) %
4966                     (2 * (int)hdspm->period_bytes),
4967                     (long) hdspm_hw_pointer(hdspm) * 4);
4968
4969         snd_iprintf(buffer,
4970                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4971                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4972                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4973                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4974                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4975         snd_iprintf(buffer,
4976                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4977                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4978                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4979         snd_iprintf(buffer,
4980                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4981                     "status2=0x%x\n",
4982                     hdspm->control_register, hdspm->control2_register,
4983                     status, status2);
4984
4985         snd_iprintf(buffer, "--- Settings ---\n");
4986
4987         x = hdspm_get_latency(hdspm);
4988
4989         snd_iprintf(buffer,
4990                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4991                     x, (unsigned long) hdspm->period_bytes);
4992
4993         snd_iprintf(buffer, "Line out: %s\n",
4994                     (hdspm->
4995                      control_register & HDSPM_LineOut) ? "on " : "off");
4996
4997         snd_iprintf(buffer,
4998                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
4999                     (hdspm->
5000                      control_register & HDSPM_clr_tms) ? "on" : "off",
5001                     (hdspm->
5002                      control_register & HDSPM_Emphasis) ? "on" : "off",
5003                     (hdspm->
5004                      control_register & HDSPM_Dolby) ? "on" : "off");
5005
5006
5007         pref_syncref = hdspm_pref_sync_ref(hdspm);
5008         if (pref_syncref == 0)
5009                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5010         else
5011                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5012                                 pref_syncref);
5013
5014         snd_iprintf(buffer, "System Clock Frequency: %d\n",
5015                     hdspm->system_sample_rate);
5016
5017         snd_iprintf(buffer, "Double speed: %s\n",
5018                         hdspm->control_register & HDSPM_DS_DoubleWire?
5019                         "Double wire" : "Single wire");
5020         snd_iprintf(buffer, "Quad speed: %s\n",
5021                         hdspm->control_register & HDSPM_QS_DoubleWire?
5022                         "Double wire" :
5023                         hdspm->control_register & HDSPM_QS_QuadWire?
5024                         "Quad wire" : "Single wire");
5025
5026         snd_iprintf(buffer, "--- Status:\n");
5027
5028         wcLock = status & HDSPM_AES32_wcLock;
5029         wcSync = wcLock && (status & HDSPM_AES32_wcSync);
5030
5031         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
5032                     (wcLock) ? (wcSync ? "Sync   " : "Lock   ") : "No Lock",
5033                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5034
5035         for (x = 0; x < 8; x++) {
5036                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
5037                             x+1,
5038                             (status2 & (HDSPM_LockAES >> x)) ?
5039                             "Sync   " : "No Lock",
5040                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5041         }
5042
5043         switch (hdspm_autosync_ref(hdspm)) {
5044         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5045                 autosync_ref = "None"; break;
5046         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5047                 autosync_ref = "Word Clock"; break;
5048         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5049                 autosync_ref = "AES1"; break;
5050         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5051                 autosync_ref = "AES2"; break;
5052         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5053                 autosync_ref = "AES3"; break;
5054         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5055                 autosync_ref = "AES4"; break;
5056         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5057                 autosync_ref = "AES5"; break;
5058         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5059                 autosync_ref = "AES6"; break;
5060         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5061                 autosync_ref = "AES7"; break;
5062         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5063                 autosync_ref = "AES8"; break;
5064         default:
5065                 autosync_ref = "---"; break;
5066         }
5067         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5068
5069         snd_iprintf(buffer, "\n");
5070 }
5071
5072 static void
5073 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5074                          struct snd_info_buffer *buffer)
5075 {
5076         struct hdspm *hdspm = entry->private_data;
5077         unsigned int status1, status2, status3, control, i;
5078         unsigned int lock, sync;
5079
5080         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5081         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5082         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5083
5084         control = hdspm->control_register;
5085
5086         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5087         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5088         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5089
5090
5091         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5092
5093         snd_iprintf(buffer, "Clock mode      : %s\n",
5094                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5095         snd_iprintf(buffer, "System frequency: %d Hz\n",
5096                 hdspm_get_system_sample_rate(hdspm));
5097
5098         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5099
5100         lock = 0x1;
5101         sync = 0x100;
5102
5103         for (i = 0; i < 8; i++) {
5104                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5105                                 i,
5106                                 (status1 & lock) ? 1 : 0,
5107                                 (status1 & sync) ? 1 : 0,
5108                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
5109
5110                 lock = lock<<1;
5111                 sync = sync<<1;
5112         }
5113
5114         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5115                         (status1 & 0x1000000) ? 1 : 0,
5116                         (status1 & 0x2000000) ? 1 : 0,
5117                         texts_freq[(status1 >> 16) & 0xF]);
5118
5119         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5120                         (status1 & 0x4000000) ? 1 : 0,
5121                         (status1 & 0x8000000) ? 1 : 0,
5122                         texts_freq[(status1 >> 20) & 0xF]);
5123
5124         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5125                         (status3 & 0x400) ? 1 : 0,
5126                         (status3 & 0x800) ? 1 : 0,
5127                         texts_freq[(status2 >> 12) & 0xF]);
5128
5129 }
5130
5131 #ifdef CONFIG_SND_DEBUG
5132 static void
5133 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5134                           struct snd_info_buffer *buffer)
5135 {
5136         struct hdspm *hdspm = entry->private_data;
5137
5138         int j,i;
5139
5140         for (i = 0; i < 256 /* 1024*64 */; i += j) {
5141                 snd_iprintf(buffer, "0x%08X: ", i);
5142                 for (j = 0; j < 16; j += 4)
5143                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5144                 snd_iprintf(buffer, "\n");
5145         }
5146 }
5147 #endif
5148
5149
5150 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5151                           struct snd_info_buffer *buffer)
5152 {
5153         struct hdspm *hdspm = entry->private_data;
5154         int i;
5155
5156         snd_iprintf(buffer, "# generated by hdspm\n");
5157
5158         for (i = 0; i < hdspm->max_channels_in; i++) {
5159                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5160         }
5161 }
5162
5163 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5164                           struct snd_info_buffer *buffer)
5165 {
5166         struct hdspm *hdspm = entry->private_data;
5167         int i;
5168
5169         snd_iprintf(buffer, "# generated by hdspm\n");
5170
5171         for (i = 0; i < hdspm->max_channels_out; i++) {
5172                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5173         }
5174 }
5175
5176
5177 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5178 {
5179         struct snd_info_entry *entry;
5180
5181         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5182                 switch (hdspm->io_type) {
5183                 case AES32:
5184                         snd_info_set_text_ops(entry, hdspm,
5185                                         snd_hdspm_proc_read_aes32);
5186                         break;
5187                 case MADI:
5188                         snd_info_set_text_ops(entry, hdspm,
5189                                         snd_hdspm_proc_read_madi);
5190                         break;
5191                 case MADIface:
5192                         /* snd_info_set_text_ops(entry, hdspm,
5193                          snd_hdspm_proc_read_madiface); */
5194                         break;
5195                 case RayDAT:
5196                         snd_info_set_text_ops(entry, hdspm,
5197                                         snd_hdspm_proc_read_raydat);
5198                         break;
5199                 case AIO:
5200                         break;
5201                 }
5202         }
5203
5204         if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5205                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5206         }
5207
5208         if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5209                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5210         }
5211
5212 #ifdef CONFIG_SND_DEBUG
5213         /* debug file to read all hdspm registers */
5214         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5215                 snd_info_set_text_ops(entry, hdspm,
5216                                 snd_hdspm_proc_read_debug);
5217 #endif
5218 }
5219
5220 /*------------------------------------------------------------
5221    hdspm intitialize
5222  ------------------------------------------------------------*/
5223
5224 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5225 {
5226         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5227            hold it (e.g. during module initialization).
5228            */
5229
5230         /* set defaults:       */
5231
5232         hdspm->settings_register = 0;
5233
5234         switch (hdspm->io_type) {
5235         case MADI:
5236         case MADIface:
5237                 hdspm->control_register =
5238                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5239                 break;
5240
5241         case RayDAT:
5242         case AIO:
5243                 hdspm->settings_register = 0x1 + 0x1000;
5244                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5245                  * line_out */
5246                 hdspm->control_register =
5247                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5248                 break;
5249
5250         case AES32:
5251                 hdspm->control_register =
5252                         HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5253                         hdspm_encode_latency(7) | /* latency max=8192samples */
5254                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5255                         HDSPM_LineOut | /* Analog output in */
5256                         HDSPM_Professional;  /* Professional mode */
5257                 break;
5258         }
5259
5260         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5261
5262         if (AES32 == hdspm->io_type) {
5263                 /* No control2 register for AES32 */
5264 #ifdef SNDRV_BIG_ENDIAN
5265                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5266 #else
5267                 hdspm->control2_register = 0;
5268 #endif
5269
5270                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5271         }
5272         hdspm_compute_period_size(hdspm);
5273
5274         /* silence everything */
5275
5276         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5277
5278         if (hdspm_is_raydat_or_aio(hdspm))
5279                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5280
5281         /* set a default rate so that the channel map is set up. */
5282         hdspm_set_rate(hdspm, 48000, 1);
5283
5284         return 0;
5285 }
5286
5287
5288 /*------------------------------------------------------------
5289    interrupt
5290  ------------------------------------------------------------*/
5291
5292 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5293 {
5294         struct hdspm *hdspm = (struct hdspm *) dev_id;
5295         unsigned int status;
5296         int i, audio, midi, schedule = 0;
5297         /* cycles_t now; */
5298
5299         status = hdspm_read(hdspm, HDSPM_statusRegister);
5300
5301         audio = status & HDSPM_audioIRQPending;
5302         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5303                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5304
5305         /* now = get_cycles(); */
5306         /**
5307          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5308          *          6       4096   ~256053425     ~514672358
5309          *          5       2048   ~128024983     ~257373821
5310          *          4       1024    ~64023706     ~128718089
5311          *          3        512    ~32005945      ~64385999
5312          *          2        256    ~16003039      ~32260176
5313          *          1        128     ~7998738      ~16194507
5314          *          0         64     ~3998231       ~8191558
5315          **/
5316         /*
5317            snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5318            now-hdspm->last_interrupt, status & 0xFFC0);
5319            hdspm->last_interrupt = now;
5320         */
5321
5322         if (!audio && !midi)
5323                 return IRQ_NONE;
5324
5325         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5326         hdspm->irq_count++;
5327
5328
5329         if (audio) {
5330                 if (hdspm->capture_substream)
5331                         snd_pcm_period_elapsed(hdspm->capture_substream);
5332
5333                 if (hdspm->playback_substream)
5334                         snd_pcm_period_elapsed(hdspm->playback_substream);
5335         }
5336
5337         if (midi) {
5338                 i = 0;
5339                 while (i < hdspm->midiPorts) {
5340                         if ((hdspm_read(hdspm,
5341                                 hdspm->midi[i].statusIn) & 0xff) &&
5342                                         (status & hdspm->midi[i].irq)) {
5343                                 /* we disable interrupts for this input until
5344                                  * processing is done
5345                                  */
5346                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5347                                 hdspm_write(hdspm, HDSPM_controlRegister,
5348                                                 hdspm->control_register);
5349                                 hdspm->midi[i].pending = 1;
5350                                 schedule = 1;
5351                         }
5352
5353                         i++;
5354                 }
5355
5356                 if (schedule)
5357                         tasklet_hi_schedule(&hdspm->midi_tasklet);
5358         }
5359
5360         return IRQ_HANDLED;
5361 }
5362
5363 /*------------------------------------------------------------
5364    pcm interface
5365   ------------------------------------------------------------*/
5366
5367
5368 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5369                                               *substream)
5370 {
5371         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5372         return hdspm_hw_pointer(hdspm);
5373 }
5374
5375
5376 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5377 {
5378         struct snd_pcm_runtime *runtime = substream->runtime;
5379         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5380         struct snd_pcm_substream *other;
5381
5382         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5383                 other = hdspm->capture_substream;
5384         else
5385                 other = hdspm->playback_substream;
5386
5387         if (hdspm->running)
5388                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5389         else
5390                 runtime->status->hw_ptr = 0;
5391         if (other) {
5392                 struct snd_pcm_substream *s;
5393                 struct snd_pcm_runtime *oruntime = other->runtime;
5394                 snd_pcm_group_for_each_entry(s, substream) {
5395                         if (s == other) {
5396                                 oruntime->status->hw_ptr =
5397                                         runtime->status->hw_ptr;
5398                                 break;
5399                         }
5400                 }
5401         }
5402         return 0;
5403 }
5404
5405 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5406                                struct snd_pcm_hw_params *params)
5407 {
5408         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5409         int err;
5410         int i;
5411         pid_t this_pid;
5412         pid_t other_pid;
5413
5414         spin_lock_irq(&hdspm->lock);
5415
5416         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5417                 this_pid = hdspm->playback_pid;
5418                 other_pid = hdspm->capture_pid;
5419         } else {
5420                 this_pid = hdspm->capture_pid;
5421                 other_pid = hdspm->playback_pid;
5422         }
5423
5424         if (other_pid > 0 && this_pid != other_pid) {
5425
5426                 /* The other stream is open, and not by the same
5427                    task as this one. Make sure that the parameters
5428                    that matter are the same.
5429                    */
5430
5431                 if (params_rate(params) != hdspm->system_sample_rate) {
5432                         spin_unlock_irq(&hdspm->lock);
5433                         _snd_pcm_hw_param_setempty(params,
5434                                         SNDRV_PCM_HW_PARAM_RATE);
5435                         return -EBUSY;
5436                 }
5437
5438                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5439                         spin_unlock_irq(&hdspm->lock);
5440                         _snd_pcm_hw_param_setempty(params,
5441                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5442                         return -EBUSY;
5443                 }
5444
5445         }
5446         /* We're fine. */
5447         spin_unlock_irq(&hdspm->lock);
5448
5449         /* how to make sure that the rate matches an externally-set one ?   */
5450
5451         spin_lock_irq(&hdspm->lock);
5452         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5453         if (err < 0) {
5454                 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5455                 spin_unlock_irq(&hdspm->lock);
5456                 _snd_pcm_hw_param_setempty(params,
5457                                 SNDRV_PCM_HW_PARAM_RATE);
5458                 return err;
5459         }
5460         spin_unlock_irq(&hdspm->lock);
5461
5462         err = hdspm_set_interrupt_interval(hdspm,
5463                         params_period_size(params));
5464         if (err < 0) {
5465                 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5466                 _snd_pcm_hw_param_setempty(params,
5467                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5468                 return err;
5469         }
5470
5471         /* Memory allocation, takashi's method, dont know if we should
5472          * spinlock
5473          */
5474         /* malloc all buffer even if not enabled to get sure */
5475         /* Update for MADI rev 204: we need to allocate for all channels,
5476          * otherwise it doesn't work at 96kHz */
5477
5478         err =
5479                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5480         if (err < 0) {
5481                 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5482                 return err;
5483         }
5484
5485         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5486
5487                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5488                                 params_channels(params));
5489
5490                 for (i = 0; i < params_channels(params); ++i)
5491                         snd_hdspm_enable_out(hdspm, i, 1);
5492
5493                 hdspm->playback_buffer =
5494                         (unsigned char *) substream->runtime->dma_area;
5495                 snd_printdd("Allocated sample buffer for playback at %p\n",
5496                                 hdspm->playback_buffer);
5497         } else {
5498                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5499                                 params_channels(params));
5500
5501                 for (i = 0; i < params_channels(params); ++i)
5502                         snd_hdspm_enable_in(hdspm, i, 1);
5503
5504                 hdspm->capture_buffer =
5505                         (unsigned char *) substream->runtime->dma_area;
5506                 snd_printdd("Allocated sample buffer for capture at %p\n",
5507                                 hdspm->capture_buffer);
5508         }
5509
5510         /*
5511            snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5512            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5513            "playback" : "capture",
5514            snd_pcm_sgbuf_get_addr(substream, 0));
5515            */
5516         /*
5517            snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5518            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5519            "playback" : "capture",
5520            params_rate(params), params_channels(params),
5521            params_buffer_size(params));
5522            */
5523
5524
5525         /* Switch to native float format if requested */
5526         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5527                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5528                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5529
5530                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5531         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5532                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5533                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5534
5535                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5536         }
5537         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5538
5539         return 0;
5540 }
5541
5542 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5543 {
5544         int i;
5545         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5546
5547         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5548
5549                 /* params_channels(params) should be enough,
5550                    but to get sure in case of error */
5551                 for (i = 0; i < hdspm->max_channels_out; ++i)
5552                         snd_hdspm_enable_out(hdspm, i, 0);
5553
5554                 hdspm->playback_buffer = NULL;
5555         } else {
5556                 for (i = 0; i < hdspm->max_channels_in; ++i)
5557                         snd_hdspm_enable_in(hdspm, i, 0);
5558
5559                 hdspm->capture_buffer = NULL;
5560
5561         }
5562
5563         snd_pcm_lib_free_pages(substream);
5564
5565         return 0;
5566 }
5567
5568
5569 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5570                 struct snd_pcm_channel_info *info)
5571 {
5572         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5573
5574         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5575                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5576                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5577                         return -EINVAL;
5578                 }
5579
5580                 if (hdspm->channel_map_out[info->channel] < 0) {
5581                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5582                         return -EINVAL;
5583                 }
5584
5585                 info->offset = hdspm->channel_map_out[info->channel] *
5586                         HDSPM_CHANNEL_BUFFER_BYTES;
5587         } else {
5588                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5589                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5590                         return -EINVAL;
5591                 }
5592
5593                 if (hdspm->channel_map_in[info->channel] < 0) {
5594                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5595                         return -EINVAL;
5596                 }
5597
5598                 info->offset = hdspm->channel_map_in[info->channel] *
5599                         HDSPM_CHANNEL_BUFFER_BYTES;
5600         }
5601
5602         info->first = 0;
5603         info->step = 32;
5604         return 0;
5605 }
5606
5607
5608 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5609                 unsigned int cmd, void *arg)
5610 {
5611         switch (cmd) {
5612         case SNDRV_PCM_IOCTL1_RESET:
5613                 return snd_hdspm_reset(substream);
5614
5615         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5616                 {
5617                         struct snd_pcm_channel_info *info = arg;
5618                         return snd_hdspm_channel_info(substream, info);
5619                 }
5620         default:
5621                 break;
5622         }
5623
5624         return snd_pcm_lib_ioctl(substream, cmd, arg);
5625 }
5626
5627 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5628 {
5629         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5630         struct snd_pcm_substream *other;
5631         int running;
5632
5633         spin_lock(&hdspm->lock);
5634         running = hdspm->running;
5635         switch (cmd) {
5636         case SNDRV_PCM_TRIGGER_START:
5637                 running |= 1 << substream->stream;
5638                 break;
5639         case SNDRV_PCM_TRIGGER_STOP:
5640                 running &= ~(1 << substream->stream);
5641                 break;
5642         default:
5643                 snd_BUG();
5644                 spin_unlock(&hdspm->lock);
5645                 return -EINVAL;
5646         }
5647         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5648                 other = hdspm->capture_substream;
5649         else
5650                 other = hdspm->playback_substream;
5651
5652         if (other) {
5653                 struct snd_pcm_substream *s;
5654                 snd_pcm_group_for_each_entry(s, substream) {
5655                         if (s == other) {
5656                                 snd_pcm_trigger_done(s, substream);
5657                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5658                                         running |= 1 << s->stream;
5659                                 else
5660                                         running &= ~(1 << s->stream);
5661                                 goto _ok;
5662                         }
5663                 }
5664                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5665                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5666                                         && substream->stream ==
5667                                         SNDRV_PCM_STREAM_CAPTURE)
5668                                 hdspm_silence_playback(hdspm);
5669                 } else {
5670                         if (running &&
5671                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5672                                 hdspm_silence_playback(hdspm);
5673                 }
5674         } else {
5675                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5676                         hdspm_silence_playback(hdspm);
5677         }
5678 _ok:
5679         snd_pcm_trigger_done(substream, substream);
5680         if (!hdspm->running && running)
5681                 hdspm_start_audio(hdspm);
5682         else if (hdspm->running && !running)
5683                 hdspm_stop_audio(hdspm);
5684         hdspm->running = running;
5685         spin_unlock(&hdspm->lock);
5686
5687         return 0;
5688 }
5689
5690 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5691 {
5692         return 0;
5693 }
5694
5695 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5696         .info = (SNDRV_PCM_INFO_MMAP |
5697                  SNDRV_PCM_INFO_MMAP_VALID |
5698                  SNDRV_PCM_INFO_NONINTERLEAVED |
5699                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5700         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5701         .rates = (SNDRV_PCM_RATE_32000 |
5702                   SNDRV_PCM_RATE_44100 |
5703                   SNDRV_PCM_RATE_48000 |
5704                   SNDRV_PCM_RATE_64000 |
5705                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5706                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5707         .rate_min = 32000,
5708         .rate_max = 192000,
5709         .channels_min = 1,
5710         .channels_max = HDSPM_MAX_CHANNELS,
5711         .buffer_bytes_max =
5712             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5713         .period_bytes_min = (32 * 4),
5714         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5715         .periods_min = 2,
5716         .periods_max = 512,
5717         .fifo_size = 0
5718 };
5719
5720 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5721         .info = (SNDRV_PCM_INFO_MMAP |
5722                  SNDRV_PCM_INFO_MMAP_VALID |
5723                  SNDRV_PCM_INFO_NONINTERLEAVED |
5724                  SNDRV_PCM_INFO_SYNC_START),
5725         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5726         .rates = (SNDRV_PCM_RATE_32000 |
5727                   SNDRV_PCM_RATE_44100 |
5728                   SNDRV_PCM_RATE_48000 |
5729                   SNDRV_PCM_RATE_64000 |
5730                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5731                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5732         .rate_min = 32000,
5733         .rate_max = 192000,
5734         .channels_min = 1,
5735         .channels_max = HDSPM_MAX_CHANNELS,
5736         .buffer_bytes_max =
5737             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5738         .period_bytes_min = (32 * 4),
5739         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5740         .periods_min = 2,
5741         .periods_max = 512,
5742         .fifo_size = 0
5743 };
5744
5745 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5746                                            struct snd_pcm_hw_rule *rule)
5747 {
5748         struct hdspm *hdspm = rule->private;
5749         struct snd_interval *c =
5750             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5751         struct snd_interval *r =
5752             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5753
5754         if (r->min > 96000 && r->max <= 192000) {
5755                 struct snd_interval t = {
5756                         .min = hdspm->qs_in_channels,
5757                         .max = hdspm->qs_in_channels,
5758                         .integer = 1,
5759                 };
5760                 return snd_interval_refine(c, &t);
5761         } else if (r->min > 48000 && r->max <= 96000) {
5762                 struct snd_interval t = {
5763                         .min = hdspm->ds_in_channels,
5764                         .max = hdspm->ds_in_channels,
5765                         .integer = 1,
5766                 };
5767                 return snd_interval_refine(c, &t);
5768         } else if (r->max < 64000) {
5769                 struct snd_interval t = {
5770                         .min = hdspm->ss_in_channels,
5771                         .max = hdspm->ss_in_channels,
5772                         .integer = 1,
5773                 };
5774                 return snd_interval_refine(c, &t);
5775         }
5776
5777         return 0;
5778 }
5779
5780 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5781                                            struct snd_pcm_hw_rule * rule)
5782 {
5783         struct hdspm *hdspm = rule->private;
5784         struct snd_interval *c =
5785             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5786         struct snd_interval *r =
5787             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5788
5789         if (r->min > 96000 && r->max <= 192000) {
5790                 struct snd_interval t = {
5791                         .min = hdspm->qs_out_channels,
5792                         .max = hdspm->qs_out_channels,
5793                         .integer = 1,
5794                 };
5795                 return snd_interval_refine(c, &t);
5796         } else if (r->min > 48000 && r->max <= 96000) {
5797                 struct snd_interval t = {
5798                         .min = hdspm->ds_out_channels,
5799                         .max = hdspm->ds_out_channels,
5800                         .integer = 1,
5801                 };
5802                 return snd_interval_refine(c, &t);
5803         } else if (r->max < 64000) {
5804                 struct snd_interval t = {
5805                         .min = hdspm->ss_out_channels,
5806                         .max = hdspm->ss_out_channels,
5807                         .integer = 1,
5808                 };
5809                 return snd_interval_refine(c, &t);
5810         } else {
5811         }
5812         return 0;
5813 }
5814
5815 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5816                                            struct snd_pcm_hw_rule * rule)
5817 {
5818         struct hdspm *hdspm = rule->private;
5819         struct snd_interval *c =
5820             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5821         struct snd_interval *r =
5822             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5823
5824         if (c->min >= hdspm->ss_in_channels) {
5825                 struct snd_interval t = {
5826                         .min = 32000,
5827                         .max = 48000,
5828                         .integer = 1,
5829                 };
5830                 return snd_interval_refine(r, &t);
5831         } else if (c->max <= hdspm->qs_in_channels) {
5832                 struct snd_interval t = {
5833                         .min = 128000,
5834                         .max = 192000,
5835                         .integer = 1,
5836                 };
5837                 return snd_interval_refine(r, &t);
5838         } else if (c->max <= hdspm->ds_in_channels) {
5839                 struct snd_interval t = {
5840                         .min = 64000,
5841                         .max = 96000,
5842                         .integer = 1,
5843                 };
5844                 return snd_interval_refine(r, &t);
5845         }
5846
5847         return 0;
5848 }
5849 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5850                                            struct snd_pcm_hw_rule *rule)
5851 {
5852         struct hdspm *hdspm = rule->private;
5853         struct snd_interval *c =
5854             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5855         struct snd_interval *r =
5856             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5857
5858         if (c->min >= hdspm->ss_out_channels) {
5859                 struct snd_interval t = {
5860                         .min = 32000,
5861                         .max = 48000,
5862                         .integer = 1,
5863                 };
5864                 return snd_interval_refine(r, &t);
5865         } else if (c->max <= hdspm->qs_out_channels) {
5866                 struct snd_interval t = {
5867                         .min = 128000,
5868                         .max = 192000,
5869                         .integer = 1,
5870                 };
5871                 return snd_interval_refine(r, &t);
5872         } else if (c->max <= hdspm->ds_out_channels) {
5873                 struct snd_interval t = {
5874                         .min = 64000,
5875                         .max = 96000,
5876                         .integer = 1,
5877                 };
5878                 return snd_interval_refine(r, &t);
5879         }
5880
5881         return 0;
5882 }
5883
5884 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5885                                       struct snd_pcm_hw_rule *rule)
5886 {
5887         unsigned int list[3];
5888         struct hdspm *hdspm = rule->private;
5889         struct snd_interval *c = hw_param_interval(params,
5890                         SNDRV_PCM_HW_PARAM_CHANNELS);
5891
5892         list[0] = hdspm->qs_in_channels;
5893         list[1] = hdspm->ds_in_channels;
5894         list[2] = hdspm->ss_in_channels;
5895         return snd_interval_list(c, 3, list, 0);
5896 }
5897
5898 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5899                                       struct snd_pcm_hw_rule *rule)
5900 {
5901         unsigned int list[3];
5902         struct hdspm *hdspm = rule->private;
5903         struct snd_interval *c = hw_param_interval(params,
5904                         SNDRV_PCM_HW_PARAM_CHANNELS);
5905
5906         list[0] = hdspm->qs_out_channels;
5907         list[1] = hdspm->ds_out_channels;
5908         list[2] = hdspm->ss_out_channels;
5909         return snd_interval_list(c, 3, list, 0);
5910 }
5911
5912
5913 static unsigned int hdspm_aes32_sample_rates[] = {
5914         32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5915 };
5916
5917 static struct snd_pcm_hw_constraint_list
5918 hdspm_hw_constraints_aes32_sample_rates = {
5919         .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5920         .list = hdspm_aes32_sample_rates,
5921         .mask = 0
5922 };
5923
5924 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5925 {
5926         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5927         struct snd_pcm_runtime *runtime = substream->runtime;
5928
5929         spin_lock_irq(&hdspm->lock);
5930
5931         snd_pcm_set_sync(substream);
5932
5933
5934         runtime->hw = snd_hdspm_playback_subinfo;
5935
5936         if (hdspm->capture_substream == NULL)
5937                 hdspm_stop_audio(hdspm);
5938
5939         hdspm->playback_pid = current->pid;
5940         hdspm->playback_substream = substream;
5941
5942         spin_unlock_irq(&hdspm->lock);
5943
5944         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5945         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5946
5947         switch (hdspm->io_type) {
5948         case AIO:
5949         case RayDAT:
5950                 snd_pcm_hw_constraint_minmax(runtime,
5951                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5952                                              32, 4096);
5953                 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
5954                 snd_pcm_hw_constraint_minmax(runtime,
5955                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5956                                              16384, 16384);
5957                 break;
5958
5959         default:
5960                 snd_pcm_hw_constraint_minmax(runtime,
5961                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5962                                              64, 8192);
5963                 break;
5964         }
5965
5966         if (AES32 == hdspm->io_type) {
5967                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
5968                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5969                                 &hdspm_hw_constraints_aes32_sample_rates);
5970         } else {
5971                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5972                                 snd_hdspm_hw_rule_rate_out_channels, hdspm,
5973                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5974         }
5975
5976         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5977                         snd_hdspm_hw_rule_out_channels, hdspm,
5978                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5979
5980         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5981                         snd_hdspm_hw_rule_out_channels_rate, hdspm,
5982                         SNDRV_PCM_HW_PARAM_RATE, -1);
5983
5984         return 0;
5985 }
5986
5987 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
5988 {
5989         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5990
5991         spin_lock_irq(&hdspm->lock);
5992
5993         hdspm->playback_pid = -1;
5994         hdspm->playback_substream = NULL;
5995
5996         spin_unlock_irq(&hdspm->lock);
5997
5998         return 0;
5999 }
6000
6001
6002 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6003 {
6004         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6005         struct snd_pcm_runtime *runtime = substream->runtime;
6006
6007         spin_lock_irq(&hdspm->lock);
6008         snd_pcm_set_sync(substream);
6009         runtime->hw = snd_hdspm_capture_subinfo;
6010
6011         if (hdspm->playback_substream == NULL)
6012                 hdspm_stop_audio(hdspm);
6013
6014         hdspm->capture_pid = current->pid;
6015         hdspm->capture_substream = substream;
6016
6017         spin_unlock_irq(&hdspm->lock);
6018
6019         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6020         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6021
6022         switch (hdspm->io_type) {
6023         case AIO:
6024         case RayDAT:
6025                 snd_pcm_hw_constraint_minmax(runtime,
6026                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6027                                              32, 4096);
6028                 snd_pcm_hw_constraint_minmax(runtime,
6029                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6030                                              16384, 16384);
6031                 break;
6032
6033         default:
6034                 snd_pcm_hw_constraint_minmax(runtime,
6035                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6036                                              64, 8192);
6037                 break;
6038         }
6039
6040         if (AES32 == hdspm->io_type) {
6041                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6042                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6043                                 &hdspm_hw_constraints_aes32_sample_rates);
6044         } else {
6045                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6046                                 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6047                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6048         }
6049
6050         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6051                         snd_hdspm_hw_rule_in_channels, hdspm,
6052                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6053
6054         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6055                         snd_hdspm_hw_rule_in_channels_rate, hdspm,
6056                         SNDRV_PCM_HW_PARAM_RATE, -1);
6057
6058         return 0;
6059 }
6060
6061 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6062 {
6063         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6064
6065         spin_lock_irq(&hdspm->lock);
6066
6067         hdspm->capture_pid = -1;
6068         hdspm->capture_substream = NULL;
6069
6070         spin_unlock_irq(&hdspm->lock);
6071         return 0;
6072 }
6073
6074 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6075 {
6076         /* we have nothing to initialize but the call is required */
6077         return 0;
6078 }
6079
6080 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6081 {
6082         u32 val = readl(src);
6083         return copy_to_user(dest, &val, 4);
6084 }
6085
6086 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6087                 unsigned int cmd, unsigned long arg)
6088 {
6089         void __user *argp = (void __user *)arg;
6090         struct hdspm *hdspm = hw->private_data;
6091         struct hdspm_mixer_ioctl mixer;
6092         struct hdspm_config info;
6093         struct hdspm_status status;
6094         struct hdspm_version hdspm_version;
6095         struct hdspm_peak_rms *levels;
6096         struct hdspm_ltc ltc;
6097         unsigned int statusregister;
6098         long unsigned int s;
6099         int i = 0;
6100
6101         switch (cmd) {
6102
6103         case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6104                 levels = &hdspm->peak_rms;
6105                 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6106                         levels->input_peaks[i] =
6107                                 readl(hdspm->iobase +
6108                                                 HDSPM_MADI_INPUT_PEAK + i*4);
6109                         levels->playback_peaks[i] =
6110                                 readl(hdspm->iobase +
6111                                                 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6112                         levels->output_peaks[i] =
6113                                 readl(hdspm->iobase +
6114                                                 HDSPM_MADI_OUTPUT_PEAK + i*4);
6115
6116                         levels->input_rms[i] =
6117                                 ((uint64_t) readl(hdspm->iobase +
6118                                         HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6119                                 (uint64_t) readl(hdspm->iobase +
6120                                                 HDSPM_MADI_INPUT_RMS_L + i*4);
6121                         levels->playback_rms[i] =
6122                                 ((uint64_t)readl(hdspm->iobase +
6123                                         HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6124                                 (uint64_t)readl(hdspm->iobase +
6125                                         HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6126                         levels->output_rms[i] =
6127                                 ((uint64_t)readl(hdspm->iobase +
6128                                         HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6129                                 (uint64_t)readl(hdspm->iobase +
6130                                                 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6131                 }
6132
6133                 if (hdspm->system_sample_rate > 96000) {
6134                         levels->speed = qs;
6135                 } else if (hdspm->system_sample_rate > 48000) {
6136                         levels->speed = ds;
6137                 } else {
6138                         levels->speed = ss;
6139                 }
6140                 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6141
6142                 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6143                 if (0 != s) {
6144                         /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6145                          [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6146                          */
6147                         return -EFAULT;
6148                 }
6149                 break;
6150
6151         case SNDRV_HDSPM_IOCTL_GET_LTC:
6152                 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6153                 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6154                 if (i & HDSPM_TCO1_LTC_Input_valid) {
6155                         switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6156                                 HDSPM_TCO1_LTC_Format_MSB)) {
6157                         case 0:
6158                                 ltc.format = fps_24;
6159                                 break;
6160                         case HDSPM_TCO1_LTC_Format_LSB:
6161                                 ltc.format = fps_25;
6162                                 break;
6163                         case HDSPM_TCO1_LTC_Format_MSB:
6164                                 ltc.format = fps_2997;
6165                                 break;
6166                         default:
6167                                 ltc.format = 30;
6168                                 break;
6169                         }
6170                         if (i & HDSPM_TCO1_set_drop_frame_flag) {
6171                                 ltc.frame = drop_frame;
6172                         } else {
6173                                 ltc.frame = full_frame;
6174                         }
6175                 } else {
6176                         ltc.format = format_invalid;
6177                         ltc.frame = frame_invalid;
6178                 }
6179                 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6180                         ltc.input_format = ntsc;
6181                 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6182                         ltc.input_format = pal;
6183                 } else {
6184                         ltc.input_format = no_video;
6185                 }
6186
6187                 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6188                 if (0 != s) {
6189                         /*
6190                          snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6191                         return -EFAULT;
6192                 }
6193
6194                 break;
6195
6196         case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6197
6198                 memset(&info, 0, sizeof(info));
6199                 spin_lock_irq(&hdspm->lock);
6200                 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6201                 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6202
6203                 info.system_sample_rate = hdspm->system_sample_rate;
6204                 info.autosync_sample_rate =
6205                         hdspm_external_sample_rate(hdspm);
6206                 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6207                 info.clock_source = hdspm_clock_source(hdspm);
6208                 info.autosync_ref = hdspm_autosync_ref(hdspm);
6209                 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut);
6210                 info.passthru = 0;
6211                 spin_unlock_irq(&hdspm->lock);
6212                 if (copy_to_user(argp, &info, sizeof(info)))
6213                         return -EFAULT;
6214                 break;
6215
6216         case SNDRV_HDSPM_IOCTL_GET_STATUS:
6217                 memset(&status, 0, sizeof(status));
6218
6219                 status.card_type = hdspm->io_type;
6220
6221                 status.autosync_source = hdspm_autosync_ref(hdspm);
6222
6223                 status.card_clock = 110069313433624ULL;
6224                 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6225
6226                 switch (hdspm->io_type) {
6227                 case MADI:
6228                 case MADIface:
6229                         status.card_specific.madi.sync_wc =
6230                                 hdspm_wc_sync_check(hdspm);
6231                         status.card_specific.madi.sync_madi =
6232                                 hdspm_madi_sync_check(hdspm);
6233                         status.card_specific.madi.sync_tco =
6234                                 hdspm_tco_sync_check(hdspm);
6235                         status.card_specific.madi.sync_in =
6236                                 hdspm_sync_in_sync_check(hdspm);
6237
6238                         statusregister =
6239                                 hdspm_read(hdspm, HDSPM_statusRegister);
6240                         status.card_specific.madi.madi_input =
6241                                 (statusregister & HDSPM_AB_int) ? 1 : 0;
6242                         status.card_specific.madi.channel_format =
6243                                 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6244                         /* TODO: Mac driver sets it when f_s>48kHz */
6245                         status.card_specific.madi.frame_format = 0;
6246
6247                 default:
6248                         break;
6249                 }
6250
6251                 if (copy_to_user(argp, &status, sizeof(status)))
6252                         return -EFAULT;
6253
6254
6255                 break;
6256
6257         case SNDRV_HDSPM_IOCTL_GET_VERSION:
6258                 memset(&hdspm_version, 0, sizeof(hdspm_version));
6259
6260                 hdspm_version.card_type = hdspm->io_type;
6261                 strncpy(hdspm_version.cardname, hdspm->card_name,
6262                                 sizeof(hdspm_version.cardname));
6263                 hdspm_version.serial = hdspm->serial;
6264                 hdspm_version.firmware_rev = hdspm->firmware_rev;
6265                 hdspm_version.addons = 0;
6266                 if (hdspm->tco)
6267                         hdspm_version.addons |= HDSPM_ADDON_TCO;
6268
6269                 if (copy_to_user(argp, &hdspm_version,
6270                                         sizeof(hdspm_version)))
6271                         return -EFAULT;
6272                 break;
6273
6274         case SNDRV_HDSPM_IOCTL_GET_MIXER:
6275                 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6276                         return -EFAULT;
6277                 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6278                                         sizeof(struct hdspm_mixer)))
6279                         return -EFAULT;
6280                 break;
6281
6282         default:
6283                 return -EINVAL;
6284         }
6285         return 0;
6286 }
6287
6288 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6289         .open = snd_hdspm_playback_open,
6290         .close = snd_hdspm_playback_release,
6291         .ioctl = snd_hdspm_ioctl,
6292         .hw_params = snd_hdspm_hw_params,
6293         .hw_free = snd_hdspm_hw_free,
6294         .prepare = snd_hdspm_prepare,
6295         .trigger = snd_hdspm_trigger,
6296         .pointer = snd_hdspm_hw_pointer,
6297         .page = snd_pcm_sgbuf_ops_page,
6298 };
6299
6300 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6301         .open = snd_hdspm_capture_open,
6302         .close = snd_hdspm_capture_release,
6303         .ioctl = snd_hdspm_ioctl,
6304         .hw_params = snd_hdspm_hw_params,
6305         .hw_free = snd_hdspm_hw_free,
6306         .prepare = snd_hdspm_prepare,
6307         .trigger = snd_hdspm_trigger,
6308         .pointer = snd_hdspm_hw_pointer,
6309         .page = snd_pcm_sgbuf_ops_page,
6310 };
6311
6312 static int snd_hdspm_create_hwdep(struct snd_card *card,
6313                                   struct hdspm *hdspm)
6314 {
6315         struct snd_hwdep *hw;
6316         int err;
6317
6318         err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6319         if (err < 0)
6320                 return err;
6321
6322         hdspm->hwdep = hw;
6323         hw->private_data = hdspm;
6324         strcpy(hw->name, "HDSPM hwdep interface");
6325
6326         hw->ops.open = snd_hdspm_hwdep_dummy_op;
6327         hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6328         hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6329         hw->ops.release = snd_hdspm_hwdep_dummy_op;
6330
6331         return 0;
6332 }
6333
6334
6335 /*------------------------------------------------------------
6336    memory interface
6337  ------------------------------------------------------------*/
6338 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6339 {
6340         int err;
6341         struct snd_pcm *pcm;
6342         size_t wanted;
6343
6344         pcm = hdspm->pcm;
6345
6346         wanted = HDSPM_DMA_AREA_BYTES;
6347
6348         err =
6349              snd_pcm_lib_preallocate_pages_for_all(pcm,
6350                                                    SNDRV_DMA_TYPE_DEV_SG,
6351                                                    snd_dma_pci_data(hdspm->pci),
6352                                                    wanted,
6353                                                    wanted);
6354         if (err < 0) {
6355                 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6356
6357                 return err;
6358         } else
6359                 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6360
6361         return 0;
6362 }
6363
6364
6365 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6366                             struct snd_pcm_substream *substream,
6367                              unsigned int reg, int channels)
6368 {
6369         int i;
6370
6371         /* continuous memory segment */
6372         for (i = 0; i < (channels * 16); i++)
6373                 hdspm_write(hdspm, reg + 4 * i,
6374                                 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6375 }
6376
6377
6378 /* ------------- ALSA Devices ---------------------------- */
6379 static int snd_hdspm_create_pcm(struct snd_card *card,
6380                                 struct hdspm *hdspm)
6381 {
6382         struct snd_pcm *pcm;
6383         int err;
6384
6385         err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6386         if (err < 0)
6387                 return err;
6388
6389         hdspm->pcm = pcm;
6390         pcm->private_data = hdspm;
6391         strcpy(pcm->name, hdspm->card_name);
6392
6393         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6394                         &snd_hdspm_playback_ops);
6395         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6396                         &snd_hdspm_capture_ops);
6397
6398         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6399
6400         err = snd_hdspm_preallocate_memory(hdspm);
6401         if (err < 0)
6402                 return err;
6403
6404         return 0;
6405 }
6406
6407 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6408 {
6409         int i;
6410
6411         for (i = 0; i < hdspm->midiPorts; i++)
6412                 snd_hdspm_flush_midi_input(hdspm, i);
6413 }
6414
6415 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
6416                                          struct hdspm *hdspm)
6417 {
6418         int err, i;
6419
6420         snd_printdd("Create card...\n");
6421         err = snd_hdspm_create_pcm(card, hdspm);
6422         if (err < 0)
6423                 return err;
6424
6425         i = 0;
6426         while (i < hdspm->midiPorts) {
6427                 err = snd_hdspm_create_midi(card, hdspm, i);
6428                 if (err < 0) {
6429                         return err;
6430                 }
6431                 i++;
6432         }
6433
6434         err = snd_hdspm_create_controls(card, hdspm);
6435         if (err < 0)
6436                 return err;
6437
6438         err = snd_hdspm_create_hwdep(card, hdspm);
6439         if (err < 0)
6440                 return err;
6441
6442         snd_printdd("proc init...\n");
6443         snd_hdspm_proc_init(hdspm);
6444
6445         hdspm->system_sample_rate = -1;
6446         hdspm->last_external_sample_rate = -1;
6447         hdspm->last_internal_sample_rate = -1;
6448         hdspm->playback_pid = -1;
6449         hdspm->capture_pid = -1;
6450         hdspm->capture_substream = NULL;
6451         hdspm->playback_substream = NULL;
6452
6453         snd_printdd("Set defaults...\n");
6454         err = snd_hdspm_set_defaults(hdspm);
6455         if (err < 0)
6456                 return err;
6457
6458         snd_printdd("Update mixer controls...\n");
6459         hdspm_update_simple_mixer_controls(hdspm);
6460
6461         snd_printdd("Initializeing complete ???\n");
6462
6463         err = snd_card_register(card);
6464         if (err < 0) {
6465                 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6466                 return err;
6467         }
6468
6469         snd_printdd("... yes now\n");
6470
6471         return 0;
6472 }
6473
6474 static int snd_hdspm_create(struct snd_card *card,
6475                             struct hdspm *hdspm)
6476 {
6477
6478         struct pci_dev *pci = hdspm->pci;
6479         int err;
6480         unsigned long io_extent;
6481
6482         hdspm->irq = -1;
6483         hdspm->card = card;
6484
6485         spin_lock_init(&hdspm->lock);
6486
6487         pci_read_config_word(hdspm->pci,
6488                         PCI_CLASS_REVISION, &hdspm->firmware_rev);
6489
6490         strcpy(card->mixername, "Xilinx FPGA");
6491         strcpy(card->driver, "HDSPM");
6492
6493         switch (hdspm->firmware_rev) {
6494         case HDSPM_RAYDAT_REV:
6495                 hdspm->io_type = RayDAT;
6496                 hdspm->card_name = "RME RayDAT";
6497                 hdspm->midiPorts = 2;
6498                 break;
6499         case HDSPM_AIO_REV:
6500                 hdspm->io_type = AIO;
6501                 hdspm->card_name = "RME AIO";
6502                 hdspm->midiPorts = 1;
6503                 break;
6504         case HDSPM_MADIFACE_REV:
6505                 hdspm->io_type = MADIface;
6506                 hdspm->card_name = "RME MADIface";
6507                 hdspm->midiPorts = 1;
6508                 break;
6509         default:
6510                 if ((hdspm->firmware_rev == 0xf0) ||
6511                         ((hdspm->firmware_rev >= 0xe6) &&
6512                                         (hdspm->firmware_rev <= 0xea))) {
6513                         hdspm->io_type = AES32;
6514                         hdspm->card_name = "RME AES32";
6515                         hdspm->midiPorts = 2;
6516                 } else if ((hdspm->firmware_rev == 0xd2) ||
6517                         ((hdspm->firmware_rev >= 0xc8)  &&
6518                                 (hdspm->firmware_rev <= 0xcf))) {
6519                         hdspm->io_type = MADI;
6520                         hdspm->card_name = "RME MADI";
6521                         hdspm->midiPorts = 3;
6522                 } else {
6523                         snd_printk(KERN_ERR
6524                                 "HDSPM: unknown firmware revision %x\n",
6525                                 hdspm->firmware_rev);
6526                         return -ENODEV;
6527                 }
6528         }
6529
6530         err = pci_enable_device(pci);
6531         if (err < 0)
6532                 return err;
6533
6534         pci_set_master(hdspm->pci);
6535
6536         err = pci_request_regions(pci, "hdspm");
6537         if (err < 0)
6538                 return err;
6539
6540         hdspm->port = pci_resource_start(pci, 0);
6541         io_extent = pci_resource_len(pci, 0);
6542
6543         snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6544                         hdspm->port, hdspm->port + io_extent - 1);
6545
6546         hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6547         if (!hdspm->iobase) {
6548                 snd_printk(KERN_ERR "HDSPM: "
6549                                 "unable to remap region 0x%lx-0x%lx\n",
6550                                 hdspm->port, hdspm->port + io_extent - 1);
6551                 return -EBUSY;
6552         }
6553         snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6554                         (unsigned long)hdspm->iobase, hdspm->port,
6555                         hdspm->port + io_extent - 1);
6556
6557         if (request_irq(pci->irq, snd_hdspm_interrupt,
6558                         IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6559                 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6560                 return -EBUSY;
6561         }
6562
6563         snd_printdd("use IRQ %d\n", pci->irq);
6564
6565         hdspm->irq = pci->irq;
6566
6567         snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6568                         sizeof(struct hdspm_mixer));
6569         hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6570         if (!hdspm->mixer) {
6571                 snd_printk(KERN_ERR "HDSPM: "
6572                                 "unable to kmalloc Mixer memory of %d Bytes\n",
6573                                 (int)sizeof(struct hdspm_mixer));
6574                 return -ENOMEM;
6575         }
6576
6577         hdspm->port_names_in = NULL;
6578         hdspm->port_names_out = NULL;
6579
6580         switch (hdspm->io_type) {
6581         case AES32:
6582                 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6583                 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6584                 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6585
6586                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6587                         channel_map_aes32;
6588                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6589                         channel_map_aes32;
6590                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6591                         channel_map_aes32;
6592                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6593                         texts_ports_aes32;
6594                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6595                         texts_ports_aes32;
6596                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6597                         texts_ports_aes32;
6598
6599                 hdspm->max_channels_out = hdspm->max_channels_in =
6600                         AES32_CHANNELS;
6601                 hdspm->port_names_in = hdspm->port_names_out =
6602                         texts_ports_aes32;
6603                 hdspm->channel_map_in = hdspm->channel_map_out =
6604                         channel_map_aes32;
6605
6606                 break;
6607
6608         case MADI:
6609         case MADIface:
6610                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6611                         MADI_SS_CHANNELS;
6612                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6613                         MADI_DS_CHANNELS;
6614                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6615                         MADI_QS_CHANNELS;
6616
6617                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6618                         channel_map_unity_ss;
6619                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6620                         channel_map_unity_ss;
6621                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6622                         channel_map_unity_ss;
6623
6624                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6625                         texts_ports_madi;
6626                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6627                         texts_ports_madi;
6628                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6629                         texts_ports_madi;
6630                 break;
6631
6632         case AIO:
6633                 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6634                 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6635                 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6636                 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6637                 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6638                 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6639
6640                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6641                         snd_printk(KERN_INFO "HDSPM: AEB input board found\n");
6642                         hdspm->ss_in_channels += 4;
6643                         hdspm->ds_in_channels += 4;
6644                         hdspm->qs_in_channels += 4;
6645                 }
6646
6647                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) {
6648                         snd_printk(KERN_INFO "HDSPM: AEB output board found\n");
6649                         hdspm->ss_out_channels += 4;
6650                         hdspm->ds_out_channels += 4;
6651                         hdspm->qs_out_channels += 4;
6652                 }
6653
6654                 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6655                 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6656                 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6657
6658                 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6659                 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6660                 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6661
6662                 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6663                 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6664                 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6665                 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6666                 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6667                 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6668
6669                 break;
6670
6671         case RayDAT:
6672                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6673                         RAYDAT_SS_CHANNELS;
6674                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6675                         RAYDAT_DS_CHANNELS;
6676                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6677                         RAYDAT_QS_CHANNELS;
6678
6679                 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6680                 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6681
6682                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6683                         channel_map_raydat_ss;
6684                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6685                         channel_map_raydat_ds;
6686                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6687                         channel_map_raydat_qs;
6688                 hdspm->channel_map_in = hdspm->channel_map_out =
6689                         channel_map_raydat_ss;
6690
6691                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6692                         texts_ports_raydat_ss;
6693                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6694                         texts_ports_raydat_ds;
6695                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6696                         texts_ports_raydat_qs;
6697
6698
6699                 break;
6700
6701         }
6702
6703         /* TCO detection */
6704         switch (hdspm->io_type) {
6705         case AIO:
6706         case RayDAT:
6707                 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6708                                 HDSPM_s2_tco_detect) {
6709                         hdspm->midiPorts++;
6710                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6711                                         GFP_KERNEL);
6712                         if (NULL != hdspm->tco) {
6713                                 hdspm_tco_write(hdspm);
6714                         }
6715                         snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6716                 } else {
6717                         hdspm->tco = NULL;
6718                 }
6719                 break;
6720
6721         case MADI:
6722                 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6723                         hdspm->midiPorts++;
6724                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6725                                         GFP_KERNEL);
6726                         if (NULL != hdspm->tco) {
6727                                 hdspm_tco_write(hdspm);
6728                         }
6729                         snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6730                 } else {
6731                         hdspm->tco = NULL;
6732                 }
6733                 break;
6734
6735         default:
6736                 hdspm->tco = NULL;
6737         }
6738
6739         /* texts */
6740         switch (hdspm->io_type) {
6741         case AES32:
6742                 if (hdspm->tco) {
6743                         hdspm->texts_autosync = texts_autosync_aes_tco;
6744                         hdspm->texts_autosync_items = 10;
6745                 } else {
6746                         hdspm->texts_autosync = texts_autosync_aes;
6747                         hdspm->texts_autosync_items = 9;
6748                 }
6749                 break;
6750
6751         case MADI:
6752                 if (hdspm->tco) {
6753                         hdspm->texts_autosync = texts_autosync_madi_tco;
6754                         hdspm->texts_autosync_items = 4;
6755                 } else {
6756                         hdspm->texts_autosync = texts_autosync_madi;
6757                         hdspm->texts_autosync_items = 3;
6758                 }
6759                 break;
6760
6761         case MADIface:
6762
6763                 break;
6764
6765         case RayDAT:
6766                 if (hdspm->tco) {
6767                         hdspm->texts_autosync = texts_autosync_raydat_tco;
6768                         hdspm->texts_autosync_items = 9;
6769                 } else {
6770                         hdspm->texts_autosync = texts_autosync_raydat;
6771                         hdspm->texts_autosync_items = 8;
6772                 }
6773                 break;
6774
6775         case AIO:
6776                 if (hdspm->tco) {
6777                         hdspm->texts_autosync = texts_autosync_aio_tco;
6778                         hdspm->texts_autosync_items = 6;
6779                 } else {
6780                         hdspm->texts_autosync = texts_autosync_aio;
6781                         hdspm->texts_autosync_items = 5;
6782                 }
6783                 break;
6784
6785         }
6786
6787         tasklet_init(&hdspm->midi_tasklet,
6788                         hdspm_midi_tasklet, (unsigned long) hdspm);
6789
6790
6791         if (hdspm->io_type != MADIface) {
6792                 hdspm->serial = (hdspm_read(hdspm,
6793                                 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6794                 /* id contains either a user-provided value or the default
6795                  * NULL. If it's the default, we're safe to
6796                  * fill card->id with the serial number.
6797                  *
6798                  * If the serial number is 0xFFFFFF, then we're dealing with
6799                  * an old PCI revision that comes without a sane number. In
6800                  * this case, we don't set card->id to avoid collisions
6801                  * when running with multiple cards.
6802                  */
6803                 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6804                         sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6805                         snd_card_set_id(card, card->id);
6806                 }
6807         }
6808
6809         snd_printdd("create alsa devices.\n");
6810         err = snd_hdspm_create_alsa_devices(card, hdspm);
6811         if (err < 0)
6812                 return err;
6813
6814         snd_hdspm_initialize_midi_flush(hdspm);
6815
6816         return 0;
6817 }
6818
6819
6820 static int snd_hdspm_free(struct hdspm * hdspm)
6821 {
6822
6823         if (hdspm->port) {
6824
6825                 /* stop th audio, and cancel all interrupts */
6826                 hdspm->control_register &=
6827                     ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6828                       HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6829                       HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6830                 hdspm_write(hdspm, HDSPM_controlRegister,
6831                             hdspm->control_register);
6832         }
6833
6834         if (hdspm->irq >= 0)
6835                 free_irq(hdspm->irq, (void *) hdspm);
6836
6837         kfree(hdspm->mixer);
6838
6839         if (hdspm->iobase)
6840                 iounmap(hdspm->iobase);
6841
6842         if (hdspm->port)
6843                 pci_release_regions(hdspm->pci);
6844
6845         pci_disable_device(hdspm->pci);
6846         return 0;
6847 }
6848
6849
6850 static void snd_hdspm_card_free(struct snd_card *card)
6851 {
6852         struct hdspm *hdspm = card->private_data;
6853
6854         if (hdspm)
6855                 snd_hdspm_free(hdspm);
6856 }
6857
6858
6859 static int snd_hdspm_probe(struct pci_dev *pci,
6860                            const struct pci_device_id *pci_id)
6861 {
6862         static int dev;
6863         struct hdspm *hdspm;
6864         struct snd_card *card;
6865         int err;
6866
6867         if (dev >= SNDRV_CARDS)
6868                 return -ENODEV;
6869         if (!enable[dev]) {
6870                 dev++;
6871                 return -ENOENT;
6872         }
6873
6874         err = snd_card_create(index[dev], id[dev],
6875                         THIS_MODULE, sizeof(struct hdspm), &card);
6876         if (err < 0)
6877                 return err;
6878
6879         hdspm = card->private_data;
6880         card->private_free = snd_hdspm_card_free;
6881         hdspm->dev = dev;
6882         hdspm->pci = pci;
6883
6884         snd_card_set_dev(card, &pci->dev);
6885
6886         err = snd_hdspm_create(card, hdspm);
6887         if (err < 0) {
6888                 snd_card_free(card);
6889                 return err;
6890         }
6891
6892         if (hdspm->io_type != MADIface) {
6893                 sprintf(card->shortname, "%s_%x",
6894                         hdspm->card_name,
6895                         hdspm->serial);
6896                 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6897                         hdspm->card_name,
6898                         hdspm->serial,
6899                         hdspm->port, hdspm->irq);
6900         } else {
6901                 sprintf(card->shortname, "%s", hdspm->card_name);
6902                 sprintf(card->longname, "%s at 0x%lx, irq %d",
6903                                 hdspm->card_name, hdspm->port, hdspm->irq);
6904         }
6905
6906         err = snd_card_register(card);
6907         if (err < 0) {
6908                 snd_card_free(card);
6909                 return err;
6910         }
6911
6912         pci_set_drvdata(pci, card);
6913
6914         dev++;
6915         return 0;
6916 }
6917
6918 static void snd_hdspm_remove(struct pci_dev *pci)
6919 {
6920         snd_card_free(pci_get_drvdata(pci));
6921 }
6922
6923 static struct pci_driver hdspm_driver = {
6924         .name = KBUILD_MODNAME,
6925         .id_table = snd_hdspm_ids,
6926         .probe = snd_hdspm_probe,
6927         .remove = snd_hdspm_remove,
6928 };
6929
6930 module_pci_driver(hdspm_driver);