sound/pci/rme9652/hdspm.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
   3  *
   4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
   5  *      code based on hdsp.c   Paul Davis
   6  *                             Marcus Andersson
   7  *                             Thomas Charbonnel
   8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
   9  *                                               <remy.bruno@trinnov.com>
  10  *
  11  *      Modified 2009-04-13 for proper metering by Florian Faber
  12  *                                               <faber@faberman.de>
  13  *
  14  *      Modified 2009-04-14 for native float support by Florian Faber
  15  *                                               <faber@faberman.de>
  16  *
  17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
  18  *                                               <faber@faberman.de>
  19  *
  20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
  21  *
  22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
  23  *
  24  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
  25  *
  26  *   This program is free software; you can redistribute it and/or modify
  27  *   it under the terms of the GNU General Public License as published by
  28  *   the Free Software Foundation; either version 2 of the License, or
  29  *   (at your option) any later version.
  30  *
  31  *   This program is distributed in the hope that it will be useful,
  32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  34  *   GNU General Public License for more details.
  35  *
  36  *   You should have received a copy of the GNU General Public License
  37  *   along with this program; if not, write to the Free Software
  38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  39  *
  40  */
  41 #include <linux/init.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/module.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/math64.h>
  48 #include <asm/io.h>
  49
  50 #include <sound/core.h>
  51 #include <sound/control.h>
  52 #include <sound/pcm.h>
  53 #include <sound/pcm_params.h>
  54 #include <sound/info.h>
  55 #include <sound/asoundef.h>
  56 #include <sound/rawmidi.h>
  57 #include <sound/hwdep.h>
  58 #include <sound/initval.h>
  59
  60 #include <sound/hdspm.h>
  61
  62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
  63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
  64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  65
  66 module_param_array(index, int, NULL, 0444);
  67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
  68
  69 module_param_array(id, charp, NULL, 0444);
  70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
  71
  72 module_param_array(enable, bool, NULL, 0444);
  73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
  74
  75
  76 MODULE_AUTHOR
  77 (
  78         "Winfried Ritsch <ritsch_AT_iem.at>, "
  79         "Paul Davis <paul@linuxaudiosystems.com>, "
  80         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
  81         "Remy Bruno <remy.bruno@trinnov.com>, "
  82         "Florian Faber <faberman@linuxproaudio.org>, "
  83         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
  84 );
  85 MODULE_DESCRIPTION("RME HDSPM");
  86 MODULE_LICENSE("GPL");
  87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
  88
  89 /* --- Write registers. ---
  90   These are defined as byte-offsets from the iobase value.  */
  91
  92 #define HDSPM_WR_SETTINGS             0
  93 #define HDSPM_outputBufferAddress    32
  94 #define HDSPM_inputBufferAddress     36
  95 #define HDSPM_controlRegister        64
  96 #define HDSPM_interruptConfirmation  96
  97 #define HDSPM_control2Reg            256  /* not in specs ???????? */
  98 #define HDSPM_freqReg                256  /* for AES32 */
  99 #define HDSPM_midiDataOut0           352  /* just believe in old code */
 100 #define HDSPM_midiDataOut1           356
 101 #define HDSPM_eeprom_wr              384  /* for AES32 */
 102
 103 /* DMA enable for 64 channels, only Bit 0 is relevant */
 104 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
 105 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
 106
 107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
 108    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
 109 #define HDSPM_pageAddressBufferOut       8192
 110 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
 111
 112 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
 113
 114 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
 115
 116 /* --- Read registers. ---
 117    These are defined as byte-offsets from the iobase value */
 118 #define HDSPM_statusRegister    0
 119 /*#define HDSPM_statusRegister2  96 */
 120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
 121  * offset 192, for AES32 *and* MADI
 122  * => need to check that offset 192 is working on MADI */
 123 #define HDSPM_statusRegister2  192
 124 #define HDSPM_timecodeRegister 128
 125
 126 /* AIO, RayDAT */
 127 #define HDSPM_RD_STATUS_0 0
 128 #define HDSPM_RD_STATUS_1 64
 129 #define HDSPM_RD_STATUS_2 128
 130 #define HDSPM_RD_STATUS_3 192
 131
 132 #define HDSPM_RD_TCO           256
 133 #define HDSPM_RD_PLL_FREQ      512
 134 #define HDSPM_WR_TCO           128
 135
 136 #define HDSPM_TCO1_TCO_lock                     0x00000001
 137 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
 138 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
 139 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
 140 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
 141 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
 142 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
 143
 144 #define HDSPM_TCO1_set_TC                       0x00000100
 145 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
 146 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
 147 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
 148
 149 #define HDSPM_TCO2_TC_run                       0x00010000
 150 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
 151 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
 152 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
 153 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
 154 #define HDSPM_TCO2_set_jam_sync                 0x00200000
 155 #define HDSPM_TCO2_set_flywheel                 0x00400000
 156
 157 #define HDSPM_TCO2_set_01_4                     0x01000000
 158 #define HDSPM_TCO2_set_pull_down                0x02000000
 159 #define HDSPM_TCO2_set_pull_up                  0x04000000
 160 #define HDSPM_TCO2_set_freq                     0x08000000
 161 #define HDSPM_TCO2_set_term_75R                 0x10000000
 162 #define HDSPM_TCO2_set_input_LSB                0x20000000
 163 #define HDSPM_TCO2_set_input_MSB                0x40000000
 164 #define HDSPM_TCO2_set_freq_from_app            0x80000000
 165
 166
 167 #define HDSPM_midiDataOut0    352
 168 #define HDSPM_midiDataOut1    356
 169 #define HDSPM_midiDataOut2    368
 170
 171 #define HDSPM_midiDataIn0     360
 172 #define HDSPM_midiDataIn1     364
 173 #define HDSPM_midiDataIn2     372
 174 #define HDSPM_midiDataIn3     376
 175
 176 /* status is data bytes in MIDI-FIFO (0-128) */
 177 #define HDSPM_midiStatusOut0  384
 178 #define HDSPM_midiStatusOut1  388
 179 #define HDSPM_midiStatusOut2  400
 180
 181 #define HDSPM_midiStatusIn0   392
 182 #define HDSPM_midiStatusIn1   396
 183 #define HDSPM_midiStatusIn2   404
 184 #define HDSPM_midiStatusIn3   408
 185
 186
 187 /* the meters are regular i/o-mapped registers, but offset
 188    considerably from the rest. the peak registers are reset
 189    when read; the least-significant 4 bits are full-scale counters;
 190    the actual peak value is in the most-significant 24 bits.
 191 */
 192
 193 #define HDSPM_MADI_INPUT_PEAK           4096
 194 #define HDSPM_MADI_PLAYBACK_PEAK        4352
 195 #define HDSPM_MADI_OUTPUT_PEAK          4608
 196
 197 #define HDSPM_MADI_INPUT_RMS_L          6144
 198 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
 199 #define HDSPM_MADI_OUTPUT_RMS_L         6656
 200
 201 #define HDSPM_MADI_INPUT_RMS_H          7168
 202 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
 203 #define HDSPM_MADI_OUTPUT_RMS_H         7680
 204
 205 /* --- Control Register bits --------- */
 206 #define HDSPM_Start                (1<<0) /* start engine */
 207
 208 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
 209 #define HDSPM_Latency1             (1<<2) /* where n is defined */
 210 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
 211
 212 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
 213 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
 214                                           register [RayDAT, AIO] */
 215
 216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
 217
 218 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
 219 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
 220 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
 221 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
 222
 223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
 224 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
 225                                      56channelMODE=0 */ /* MADI ONLY*/
 226 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
 227
 228 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
 229                                      0=off, 1=on  */ /* MADI ONLY */
 230 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
 231
 232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
 233                                     * -- MADI ONLY
 234                                     */
 235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
 236
 237 #define HDSPM_SyncRef2     (1<<13)
 238 #define HDSPM_SyncRef3     (1<<25)
 239
 240 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
 241 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
 242                                       AES additional bits in
 243                                       lower 5 Audiodatabits ??? */
 244 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
 245 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
 246
 247 #define HDSPM_Midi0InterruptEnable 0x0400000
 248 #define HDSPM_Midi1InterruptEnable 0x0800000
 249 #define HDSPM_Midi2InterruptEnable 0x0200000
 250 #define HDSPM_Midi3InterruptEnable 0x4000000
 251
 252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
 253 #define HDSPe_FLOAT_FORMAT         0x2000000
 254
 255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
 256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
 257 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
 258
 259 #define HDSPM_wclk_sel (1<<30)
 260
 261 /* additional control register bits for AIO*/
 262 #define HDSPM_c0_Wck48                          0x20 /* also RayDAT */
 263 #define HDSPM_c0_Input0                         0x1000
 264 #define HDSPM_c0_Input1                         0x2000
 265 #define HDSPM_c0_Spdif_Opt                      0x4000
 266 #define HDSPM_c0_Pro                            0x8000
 267 #define HDSPM_c0_clr_tms                        0x10000
 268 #define HDSPM_c0_AEB1                           0x20000
 269 #define HDSPM_c0_AEB2                           0x40000
 270 #define HDSPM_c0_LineOut                        0x80000
 271 #define HDSPM_c0_AD_GAIN0                       0x100000
 272 #define HDSPM_c0_AD_GAIN1                       0x200000
 273 #define HDSPM_c0_DA_GAIN0                       0x400000
 274 #define HDSPM_c0_DA_GAIN1                       0x800000
 275 #define HDSPM_c0_PH_GAIN0                       0x1000000
 276 #define HDSPM_c0_PH_GAIN1                       0x2000000
 277 #define HDSPM_c0_Sym6db                         0x4000000
 278
 279
 280 /* --- bit helper defines */
 281 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
 282 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
 283                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
 284 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
 285 #define HDSPM_InputOptical   0
 286 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
 287 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
 288                               HDSPM_SyncRef2|HDSPM_SyncRef3)
 289
 290 #define HDSPM_c0_SyncRef0      0x2
 291 #define HDSPM_c0_SyncRef1      0x4
 292 #define HDSPM_c0_SyncRef2      0x8
 293 #define HDSPM_c0_SyncRef3      0x10
 294 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
 295                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
 296
 297 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
 298 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
 299 #define HDSPM_SYNC_FROM_TCO     2
 300 #define HDSPM_SYNC_FROM_SYNC_IN 3
 301
 302 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
 303 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
 304 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
 305 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
 306 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
 307 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
 308                                 HDSPM_Frequency0)
 309 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
 310 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
 311 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
 312                                  HDSPM_Frequency0)
 313
 314
 315 /* Synccheck Status */
 316 #define HDSPM_SYNC_CHECK_NO_LOCK 0
 317 #define HDSPM_SYNC_CHECK_LOCK    1
 318 #define HDSPM_SYNC_CHECK_SYNC    2
 319
 320 /* AutoSync References - used by "autosync_ref" control switch */
 321 #define HDSPM_AUTOSYNC_FROM_WORD      0
 322 #define HDSPM_AUTOSYNC_FROM_MADI      1
 323 #define HDSPM_AUTOSYNC_FROM_TCO       2
 324 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
 325 #define HDSPM_AUTOSYNC_FROM_NONE      4
 326
 327 /* Possible sources of MADI input */
 328 #define HDSPM_OPTICAL 0         /* optical   */
 329 #define HDSPM_COAXIAL 1         /* BNC */
 330
 331 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
 332 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
 333
 334 #define hdspm_encode_in(x) (((x)&0x3)<<14)
 335 #define hdspm_decode_in(x) (((x)>>14)&0x3)
 336
 337 /* --- control2 register bits --- */
 338 #define HDSPM_TMS             (1<<0)
 339 #define HDSPM_TCK             (1<<1)
 340 #define HDSPM_TDI             (1<<2)
 341 #define HDSPM_JTAG            (1<<3)
 342 #define HDSPM_PWDN            (1<<4)
 343 #define HDSPM_PROGRAM         (1<<5)
 344 #define HDSPM_CONFIG_MODE_0   (1<<6)
 345 #define HDSPM_CONFIG_MODE_1   (1<<7)
 346 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
 347 #define HDSPM_BIGENDIAN_MODE  (1<<9)
 348 #define HDSPM_RD_MULTIPLE     (1<<10)
 349
 350 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
 351      that do not conflict with specific bits for AES32 seem to be valid also
 352      for the AES32
 353  */
 354 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
 355 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
 356 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
 357                                          * (like inp0)
 358                                          */
 359
 360 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
 361 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
 362
 363 #define HDSPM_tcoLockMadi    0x00000020 /* Optional TCO locked status for HDSPe MADI*/
 364 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/
 365
 366 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */
 367 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */
 368
 369 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 370                         /* since 64byte accurate, last 6 bits are not used */
 371
 372
 373
 374 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
 375
 376 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
 377 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
 378 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
 379 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
 380
 381 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
 382                                          * Interrupt
 383                                          */
 384 #define HDSPM_tco_detect         0x08000000
 385 #define HDSPM_tcoLockAes         0x20000000 /* Optional TCO locked status for HDSPe AES */
 386
 387 #define HDSPM_s2_tco_detect      0x00000040
 388 #define HDSPM_s2_AEBO_D          0x00000080
 389 #define HDSPM_s2_AEBI_D          0x00000100
 390
 391
 392 #define HDSPM_midi0IRQPending    0x40000000
 393 #define HDSPM_midi1IRQPending    0x80000000
 394 #define HDSPM_midi2IRQPending    0x20000000
 395 #define HDSPM_midi2IRQPendingAES 0x00000020
 396 #define HDSPM_midi3IRQPending    0x00200000
 397
 398 /* --- status bit helpers */
 399 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
 400                              HDSPM_madiFreq2|HDSPM_madiFreq3)
 401 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
 402 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
 403 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
 404 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
 405 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
 406 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
 407 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
 408 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
 409 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
 410
 411 /* Status2 Register bits */ /* MADI ONLY */
 412
 413 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
 414 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
 415 #define HDSPM_version2 (1<<2)
 416
 417 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
 418 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
 419
 420 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
 421 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
 422 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, 111=128 */
 423 #define HDSPM_wc_freq3 0x800    /* 1000=176.4, 1001=192 */
 424
 425 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
 426 #define HDSPM_SyncRef1 0x20000
 427
 428 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
 429 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
 430 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
 431
 432 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
 433
 434 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
 435                             HDSPM_wc_freq3)
 436 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
 437 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
 438 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
 439 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
 440 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
 441 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
 442 #define HDSPM_wcFreq128   (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
 443 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
 444 #define HDSPM_wcFreq192   (HDSPM_wc_freq0|HDSPM_wc_freq3)
 445
 446 #define HDSPM_status1_F_0 0x0400000
 447 #define HDSPM_status1_F_1 0x0800000
 448 #define HDSPM_status1_F_2 0x1000000
 449 #define HDSPM_status1_F_3 0x2000000
 450 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
 451
 452
 453 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 454                                     HDSPM_SelSyncRef2)
 455 #define HDSPM_SelSyncRef_WORD      0
 456 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
 457 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
 458 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
 459 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 460                                     HDSPM_SelSyncRef2)
 461
 462 /*
 463    For AES32, bits for status, status2 and timecode are different
 464 */
 465 /* status */
 466 #define HDSPM_AES32_wcLock      0x0200000
 467 #define HDSPM_AES32_wcSync      0x0100000
 468 #define HDSPM_AES32_wcFreq_bit  22
 469 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
 470   HDSPM_bit2freq */
 471 #define HDSPM_AES32_syncref_bit  16
 472 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
 473
 474 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
 475 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
 476 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
 477 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
 478 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
 479 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
 480 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
 481 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
 482 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
 483 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9
 484 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10
 485 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11
 486
 487 /*  status2 */
 488 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
 489 #define HDSPM_LockAES   0x80
 490 #define HDSPM_LockAES1  0x80
 491 #define HDSPM_LockAES2  0x40
 492 #define HDSPM_LockAES3  0x20
 493 #define HDSPM_LockAES4  0x10
 494 #define HDSPM_LockAES5  0x8
 495 #define HDSPM_LockAES6  0x4
 496 #define HDSPM_LockAES7  0x2
 497 #define HDSPM_LockAES8  0x1
 498 /*
 499    Timecode
 500    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
 501    AES i+1
 502  bits 3210
 503       0001  32kHz
 504       0010  44.1kHz
 505       0011  48kHz
 506       0100  64kHz
 507       0101  88.2kHz
 508       0110  96kHz
 509       0111  128kHz
 510       1000  176.4kHz
 511       1001  192kHz
 512   NB: Timecode register doesn't seem to work on AES32 card revision 230
 513 */
 514
 515 /* Mixer Values */
 516 #define UNITY_GAIN          32768       /* = 65536/2 */
 517 #define MINUS_INFINITY_GAIN 0
 518
 519 /* Number of channels for different Speed Modes */
 520 #define MADI_SS_CHANNELS       64
 521 #define MADI_DS_CHANNELS       32
 522 #define MADI_QS_CHANNELS       16
 523
 524 #define RAYDAT_SS_CHANNELS     36
 525 #define RAYDAT_DS_CHANNELS     20
 526 #define RAYDAT_QS_CHANNELS     12
 527
 528 #define AIO_IN_SS_CHANNELS        14
 529 #define AIO_IN_DS_CHANNELS        10
 530 #define AIO_IN_QS_CHANNELS        8
 531 #define AIO_OUT_SS_CHANNELS        16
 532 #define AIO_OUT_DS_CHANNELS        12
 533 #define AIO_OUT_QS_CHANNELS        10
 534
 535 #define AES32_CHANNELS          16
 536
 537 /* the size of a substream (1 mono data stream) */
 538 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
 539 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
 540
 541 /* the size of the area we need to allocate for DMA transfers. the
 542    size is the same regardless of the number of channels, and
 543    also the latency to use.
 544    for one direction !!!
 545 */
 546 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
 547 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
 548
 549 #define HDSPM_RAYDAT_REV        211
 550 #define HDSPM_AIO_REV           212
 551 #define HDSPM_MADIFACE_REV      213
 552
 553 /* speed factor modes */
 554 #define HDSPM_SPEED_SINGLE 0
 555 #define HDSPM_SPEED_DOUBLE 1
 556 #define HDSPM_SPEED_QUAD   2
 557
 558 /* names for speed modes */
 559 static char *hdspm_speed_names[] = { "single", "double", "quad" };
 560
 561 static const char *const texts_autosync_aes_tco[] = { "Word Clock",
 562                                           "AES1", "AES2", "AES3", "AES4",
 563                                           "AES5", "AES6", "AES7", "AES8",
 564                                           "TCO", "Sync In"
 565 };
 566 static const char *const texts_autosync_aes[] = { "Word Clock",
 567                                       "AES1", "AES2", "AES3", "AES4",
 568                                       "AES5", "AES6", "AES7", "AES8",
 569                                       "Sync In"
 570 };
 571 static const char *const texts_autosync_madi_tco[] = { "Word Clock",
 572                                            "MADI", "TCO", "Sync In" };
 573 static const char *const texts_autosync_madi[] = { "Word Clock",
 574                                        "MADI", "Sync In" };
 575
 576 static const char *const texts_autosync_raydat_tco[] = {
 577         "Word Clock",
 578         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 579         "AES", "SPDIF", "TCO", "Sync In"
 580 };
 581 static const char *const texts_autosync_raydat[] = {
 582         "Word Clock",
 583         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 584         "AES", "SPDIF", "Sync In"
 585 };
 586 static const char *const texts_autosync_aio_tco[] = {
 587         "Word Clock",
 588         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
 589 };
 590 static const char *const texts_autosync_aio[] = { "Word Clock",
 591                                       "ADAT", "AES", "SPDIF", "Sync In" };
 592
 593 static const char *const texts_freq[] = {
 594         "No Lock",
 595         "32 kHz",
 596         "44.1 kHz",
 597         "48 kHz",
 598         "64 kHz",
 599         "88.2 kHz",
 600         "96 kHz",
 601         "128 kHz",
 602         "176.4 kHz",
 603         "192 kHz"
 604 };
 605
 606 static char *texts_ports_madi[] = {
 607         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
 608         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
 609         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
 610         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
 611         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
 612         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
 613         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
 614         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
 615         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
 616         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
 617         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
 618 };
 619
 620
 621 static char *texts_ports_raydat_ss[] = {
 622         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
 623         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 624         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
 625         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
 626         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
 627         "ADAT4.7", "ADAT4.8",
 628         "AES.L", "AES.R",
 629         "SPDIF.L", "SPDIF.R"
 630 };
 631
 632 static char *texts_ports_raydat_ds[] = {
 633         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
 634         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 635         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
 636         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
 637         "AES.L", "AES.R",
 638         "SPDIF.L", "SPDIF.R"
 639 };
 640
 641 static char *texts_ports_raydat_qs[] = {
 642         "ADAT1.1", "ADAT1.2",
 643         "ADAT2.1", "ADAT2.2",
 644         "ADAT3.1", "ADAT3.2",
 645         "ADAT4.1", "ADAT4.2",
 646         "AES.L", "AES.R",
 647         "SPDIF.L", "SPDIF.R"
 648 };
 649
 650
 651 static char *texts_ports_aio_in_ss[] = {
 652         "Analogue.L", "Analogue.R",
 653         "AES.L", "AES.R",
 654         "SPDIF.L", "SPDIF.R",
 655         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 656         "ADAT.7", "ADAT.8",
 657         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 658 };
 659
 660 static char *texts_ports_aio_out_ss[] = {
 661         "Analogue.L", "Analogue.R",
 662         "AES.L", "AES.R",
 663         "SPDIF.L", "SPDIF.R",
 664         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 665         "ADAT.7", "ADAT.8",
 666         "Phone.L", "Phone.R",
 667         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 668 };
 669
 670 static char *texts_ports_aio_in_ds[] = {
 671         "Analogue.L", "Analogue.R",
 672         "AES.L", "AES.R",
 673         "SPDIF.L", "SPDIF.R",
 674         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 675         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 676 };
 677
 678 static char *texts_ports_aio_out_ds[] = {
 679         "Analogue.L", "Analogue.R",
 680         "AES.L", "AES.R",
 681         "SPDIF.L", "SPDIF.R",
 682         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 683         "Phone.L", "Phone.R",
 684         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 685 };
 686
 687 static char *texts_ports_aio_in_qs[] = {
 688         "Analogue.L", "Analogue.R",
 689         "AES.L", "AES.R",
 690         "SPDIF.L", "SPDIF.R",
 691         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 692         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 693 };
 694
 695 static char *texts_ports_aio_out_qs[] = {
 696         "Analogue.L", "Analogue.R",
 697         "AES.L", "AES.R",
 698         "SPDIF.L", "SPDIF.R",
 699         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 700         "Phone.L", "Phone.R",
 701         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 702 };
 703
 704 static char *texts_ports_aes32[] = {
 705         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
 706         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
 707         "AES.15", "AES.16"
 708 };
 709
 710 /* These tables map the ALSA channels 1..N to the channels that we
 711    need to use in order to find the relevant channel buffer. RME
 712    refers to this kind of mapping as between "the ADAT channel and
 713    the DMA channel." We index it using the logical audio channel,
 714    and the value is the DMA channel (i.e. channel buffer number)
 715    where the data for that channel can be read/written from/to.
 716 */
 717
 718 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
 719         0, 1, 2, 3, 4, 5, 6, 7,
 720         8, 9, 10, 11, 12, 13, 14, 15,
 721         16, 17, 18, 19, 20, 21, 22, 23,
 722         24, 25, 26, 27, 28, 29, 30, 31,
 723         32, 33, 34, 35, 36, 37, 38, 39,
 724         40, 41, 42, 43, 44, 45, 46, 47,
 725         48, 49, 50, 51, 52, 53, 54, 55,
 726         56, 57, 58, 59, 60, 61, 62, 63
 727 };
 728
 729 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
 730         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
 731         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
 732         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
 733         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
 734         0, 1,                   /* AES */
 735         2, 3,                   /* SPDIF */
 736         -1, -1, -1, -1,
 737         -1, -1, -1, -1, -1, -1, -1, -1,
 738         -1, -1, -1, -1, -1, -1, -1, -1,
 739         -1, -1, -1, -1, -1, -1, -1, -1,
 740 };
 741
 742 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
 743         4, 5, 6, 7,             /* ADAT 1 */
 744         8, 9, 10, 11,           /* ADAT 2 */
 745         12, 13, 14, 15,         /* ADAT 3 */
 746         16, 17, 18, 19,         /* ADAT 4 */
 747         0, 1,                   /* AES */
 748         2, 3,                   /* SPDIF */
 749         -1, -1, -1, -1,
 750         -1, -1, -1, -1, -1, -1, -1, -1,
 751         -1, -1, -1, -1, -1, -1, -1, -1,
 752         -1, -1, -1, -1, -1, -1, -1, -1,
 753         -1, -1, -1, -1, -1, -1, -1, -1,
 754         -1, -1, -1, -1, -1, -1, -1, -1,
 755 };
 756
 757 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
 758         4, 5,                   /* ADAT 1 */
 759         6, 7,                   /* ADAT 2 */
 760         8, 9,                   /* ADAT 3 */
 761         10, 11,                 /* ADAT 4 */
 762         0, 1,                   /* AES */
 763         2, 3,                   /* SPDIF */
 764         -1, -1, -1, -1,
 765         -1, -1, -1, -1, -1, -1, -1, -1,
 766         -1, -1, -1, -1, -1, -1, -1, -1,
 767         -1, -1, -1, -1, -1, -1, -1, -1,
 768         -1, -1, -1, -1, -1, -1, -1, -1,
 769         -1, -1, -1, -1, -1, -1, -1, -1,
 770         -1, -1, -1, -1, -1, -1, -1, -1,
 771 };
 772
 773 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
 774         0, 1,                   /* line in */
 775         8, 9,                   /* aes in, */
 776         10, 11,                 /* spdif in */
 777         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
 778         2, 3, 4, 5,             /* AEB */
 779         -1, -1, -1, -1, -1, -1,
 780         -1, -1, -1, -1, -1, -1, -1, -1,
 781         -1, -1, -1, -1, -1, -1, -1, -1,
 782         -1, -1, -1, -1, -1, -1, -1, -1,
 783         -1, -1, -1, -1, -1, -1, -1, -1,
 784         -1, -1, -1, -1, -1, -1, -1, -1,
 785 };
 786
 787 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
 788         0, 1,                   /* line out */
 789         8, 9,                   /* aes out */
 790         10, 11,                 /* spdif out */
 791         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
 792         6, 7,                   /* phone out */
 793         2, 3, 4, 5,             /* AEB */
 794         -1, -1, -1, -1,
 795         -1, -1, -1, -1, -1, -1, -1, -1,
 796         -1, -1, -1, -1, -1, -1, -1, -1,
 797         -1, -1, -1, -1, -1, -1, -1, -1,
 798         -1, -1, -1, -1, -1, -1, -1, -1,
 799         -1, -1, -1, -1, -1, -1, -1, -1,
 800 };
 801
 802 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
 803         0, 1,                   /* line in */
 804         8, 9,                   /* aes in */
 805         10, 11,                 /* spdif in */
 806         12, 14, 16, 18,         /* adat in */
 807         2, 3, 4, 5,             /* AEB */
 808         -1, -1,
 809         -1, -1, -1, -1, -1, -1, -1, -1,
 810         -1, -1, -1, -1, -1, -1, -1, -1,
 811         -1, -1, -1, -1, -1, -1, -1, -1,
 812         -1, -1, -1, -1, -1, -1, -1, -1,
 813         -1, -1, -1, -1, -1, -1, -1, -1,
 814         -1, -1, -1, -1, -1, -1, -1, -1
 815 };
 816
 817 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
 818         0, 1,                   /* line out */
 819         8, 9,                   /* aes out */
 820         10, 11,                 /* spdif out */
 821         12, 14, 16, 18,         /* adat out */
 822         6, 7,                   /* phone out */
 823         2, 3, 4, 5,             /* AEB */
 824         -1, -1, -1, -1, -1, -1, -1, -1,
 825         -1, -1, -1, -1, -1, -1, -1, -1,
 826         -1, -1, -1, -1, -1, -1, -1, -1,
 827         -1, -1, -1, -1, -1, -1, -1, -1,
 828         -1, -1, -1, -1, -1, -1, -1, -1,
 829         -1, -1, -1, -1, -1, -1, -1, -1
 830 };
 831
 832 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
 833         0, 1,                   /* line in */
 834         8, 9,                   /* aes in */
 835         10, 11,                 /* spdif in */
 836         12, 16,                 /* adat in */
 837         2, 3, 4, 5,             /* AEB */
 838         -1, -1, -1, -1,
 839         -1, -1, -1, -1, -1, -1, -1, -1,
 840         -1, -1, -1, -1, -1, -1, -1, -1,
 841         -1, -1, -1, -1, -1, -1, -1, -1,
 842         -1, -1, -1, -1, -1, -1, -1, -1,
 843         -1, -1, -1, -1, -1, -1, -1, -1,
 844         -1, -1, -1, -1, -1, -1, -1, -1
 845 };
 846
 847 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
 848         0, 1,                   /* line out */
 849         8, 9,                   /* aes out */
 850         10, 11,                 /* spdif out */
 851         12, 16,                 /* adat out */
 852         6, 7,                   /* phone out */
 853         2, 3, 4, 5,             /* AEB */
 854         -1, -1,
 855         -1, -1, -1, -1, -1, -1, -1, -1,
 856         -1, -1, -1, -1, -1, -1, -1, -1,
 857         -1, -1, -1, -1, -1, -1, -1, -1,
 858         -1, -1, -1, -1, -1, -1, -1, -1,
 859         -1, -1, -1, -1, -1, -1, -1, -1,
 860         -1, -1, -1, -1, -1, -1, -1, -1
 861 };
 862
 863 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
 864         0, 1, 2, 3, 4, 5, 6, 7,
 865         8, 9, 10, 11, 12, 13, 14, 15,
 866         -1, -1, -1, -1, -1, -1, -1, -1,
 867         -1, -1, -1, -1, -1, -1, -1, -1,
 868         -1, -1, -1, -1, -1, -1, -1, -1,
 869         -1, -1, -1, -1, -1, -1, -1, -1,
 870         -1, -1, -1, -1, -1, -1, -1, -1,
 871         -1, -1, -1, -1, -1, -1, -1, -1
 872 };
 873
 874 struct hdspm_midi {
 875         struct hdspm *hdspm;
 876         int id;
 877         struct snd_rawmidi *rmidi;
 878         struct snd_rawmidi_substream *input;
 879         struct snd_rawmidi_substream *output;
 880         char istimer;           /* timer in use */
 881         struct timer_list timer;
 882         spinlock_t lock;
 883         int pending;
 884         int dataIn;
 885         int statusIn;
 886         int dataOut;
 887         int statusOut;
 888         int ie;
 889         int irq;
 890 };
 891
 892 struct hdspm_tco {
 893         int input;
 894         int framerate;
 895         int wordclock;
 896         int samplerate;
 897         int pull;
 898         int term; /* 0 = off, 1 = on */
 899 };
 900
 901 struct hdspm {
 902         spinlock_t lock;
 903         /* only one playback and/or capture stream */
 904         struct snd_pcm_substream *capture_substream;
 905         struct snd_pcm_substream *playback_substream;
 906
 907         char *card_name;             /* for procinfo */
 908         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
 909
 910         uint8_t io_type;
 911
 912         int monitor_outs;       /* set up monitoring outs init flag */
 913
 914         u32 control_register;   /* cached value */
 915         u32 control2_register;  /* cached value */
 916         u32 settings_register;
 917
 918         struct hdspm_midi midi[4];
 919         struct tasklet_struct midi_tasklet;
 920
 921         size_t period_bytes;
 922         unsigned char ss_in_channels;
 923         unsigned char ds_in_channels;
 924         unsigned char qs_in_channels;
 925         unsigned char ss_out_channels;
 926         unsigned char ds_out_channels;
 927         unsigned char qs_out_channels;
 928
 929         unsigned char max_channels_in;
 930         unsigned char max_channels_out;
 931
 932         signed char *channel_map_in;
 933         signed char *channel_map_out;
 934
 935         signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
 936         signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
 937
 938         char **port_names_in;
 939         char **port_names_out;
 940
 941         char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
 942         char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
 943
 944         unsigned char *playback_buffer; /* suitably aligned address */
 945         unsigned char *capture_buffer;  /* suitably aligned address */
 946
 947         pid_t capture_pid;      /* process id which uses capture */
 948         pid_t playback_pid;     /* process id which uses capture */
 949         int running;            /* running status */
 950
 951         int last_external_sample_rate;  /* samplerate mystic ... */
 952         int last_internal_sample_rate;
 953         int system_sample_rate;
 954
 955         int dev;                /* Hardware vars... */
 956         int irq;
 957         unsigned long port;
 958         void __iomem *iobase;
 959
 960         int irq_count;          /* for debug */
 961         int midiPorts;
 962
 963         struct snd_card *card;  /* one card */
 964         struct snd_pcm *pcm;            /* has one pcm */
 965         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
 966         struct pci_dev *pci;    /* and an pci info */
 967
 968         /* Mixer vars */
 969         /* fast alsa mixer */
 970         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
 971         /* but input to much, so not used */
 972         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
 973         /* full mixer accessible over mixer ioctl or hwdep-device */
 974         struct hdspm_mixer *mixer;
 975
 976         struct hdspm_tco *tco;  /* NULL if no TCO detected */
 977
 978         const char *const *texts_autosync;
 979         int texts_autosync_items;
 980
 981         cycles_t last_interrupt;
 982
 983         unsigned int serial;
 984
 985         struct hdspm_peak_rms peak_rms;
 986 };
 987
 988
 989 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
 990         {
 991          .vendor = PCI_VENDOR_ID_XILINX,
 992          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
 993          .subvendor = PCI_ANY_ID,
 994          .subdevice = PCI_ANY_ID,
 995          .class = 0,
 996          .class_mask = 0,
 997          .driver_data = 0},
 998         {0,}
 999 };
1000
1001 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
1002
1003 /* prototypes */
1004 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
1005                                          struct hdspm *hdspm);
1006 static int snd_hdspm_create_pcm(struct snd_card *card,
1007                                 struct hdspm *hdspm);
1008
1009 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
1010 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
1011 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
1012 static int hdspm_autosync_ref(struct hdspm *hdspm);
1013 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
1014 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
1015 static int hdspm_system_clock_mode(struct hdspm *hdspm);
1016 static void hdspm_set_sgbuf(struct hdspm *hdspm,
1017                             struct snd_pcm_substream *substream,
1018                              unsigned int reg, int channels);
1019
1020 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx);
1021 static int hdspm_wc_sync_check(struct hdspm *hdspm);
1022 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1023 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1024
1025 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index);
1026 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm);
1027 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm);
1028
1029
1030
1031 static inline int HDSPM_bit2freq(int n)
1032 {
1033         static const int bit2freq_tab[] = {
1034                 0, 32000, 44100, 48000, 64000, 88200,
1035                 96000, 128000, 176400, 192000 };
1036         if (n < 1 || n > 9)
1037                 return 0;
1038         return bit2freq_tab[n];
1039 }
1040
1041 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1042 {
1043         return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1044 }
1045
1046
1047 /* Write/read to/from HDSPM with Adresses in Bytes
1048    not words but only 32Bit writes are allowed */
1049
1050 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
1051                                unsigned int val)
1052 {
1053         writel(val, hdspm->iobase + reg);
1054 }
1055
1056 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1057 {
1058         return readl(hdspm->iobase + reg);
1059 }
1060
1061 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1062    mixer is write only on hardware so we have to cache him for read
1063    each fader is a u32, but uses only the first 16 bit */
1064
1065 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1066                                      unsigned int in)
1067 {
1068         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1069                 return 0;
1070
1071         return hdspm->mixer->ch[chan].in[in];
1072 }
1073
1074 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1075                                      unsigned int pb)
1076 {
1077         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1078                 return 0;
1079         return hdspm->mixer->ch[chan].pb[pb];
1080 }
1081
1082 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1083                                       unsigned int in, unsigned short data)
1084 {
1085         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1086                 return -1;
1087
1088         hdspm_write(hdspm,
1089                     HDSPM_MADI_mixerBase +
1090                     ((in + 128 * chan) * sizeof(u32)),
1091                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1092         return 0;
1093 }
1094
1095 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1096                                       unsigned int pb, unsigned short data)
1097 {
1098         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1099                 return -1;
1100
1101         hdspm_write(hdspm,
1102                     HDSPM_MADI_mixerBase +
1103                     ((64 + pb + 128 * chan) * sizeof(u32)),
1104                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1105         return 0;
1106 }
1107
1108
1109 /* enable DMA for specific channels, now available for DSP-MADI */
1110 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1111 {
1112         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1113 }
1114
1115 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1116 {
1117         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1118 }
1119
1120 /* check if same process is writing and reading */
1121 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1122 {
1123         unsigned long flags;
1124         int ret = 1;
1125
1126         spin_lock_irqsave(&hdspm->lock, flags);
1127         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1128             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1129                 ret = 0;
1130         }
1131         spin_unlock_irqrestore(&hdspm->lock, flags);
1132         return ret;
1133 }
1134
1135 /* round arbitary sample rates to commonly known rates */
1136 static int hdspm_round_frequency(int rate)
1137 {
1138         if (rate < 38050)
1139                 return 32000;
1140         if (rate < 46008)
1141                 return 44100;
1142         else
1143                 return 48000;
1144 }
1145
1146 /* QS and DS rates normally can not be detected
1147  * automatically by the card. Only exception is MADI
1148  * in 96k frame mode.
1149  *
1150  * So if we read SS values (32 .. 48k), check for
1151  * user-provided DS/QS bits in the control register
1152  * and multiply the base frequency accordingly.
1153  */
1154 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1155 {
1156         if (rate <= 48000) {
1157                 if (hdspm->control_register & HDSPM_QuadSpeed)
1158                         return rate * 4;
1159                 else if (hdspm->control_register &
1160                                 HDSPM_DoubleSpeed)
1161                         return rate * 2;
1162         };
1163         return rate;
1164 }
1165
1166 /* check for external sample rate, returns the sample rate in Hz*/
1167 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1168 {
1169         unsigned int status, status2, timecode;
1170         int syncref, rate = 0, rate_bits;
1171
1172         switch (hdspm->io_type) {
1173         case AES32:
1174                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1175                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1176                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1177
1178                 syncref = hdspm_autosync_ref(hdspm);
1179                 switch (syncref) {
1180                 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
1181                 /* Check WC sync and get sample rate */
1182                         if (hdspm_wc_sync_check(hdspm))
1183                                 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm));
1184                         break;
1185
1186                 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
1187                 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
1188                 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
1189                 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
1190                 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
1191                 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
1192                 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
1193                 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
1194                 /* Check AES sync and get sample rate */
1195                         if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))
1196                                 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm,
1197                                                         syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1));
1198                         break;
1199
1200
1201                 case HDSPM_AES32_AUTOSYNC_FROM_TCO:
1202                 /* Check TCO sync and get sample rate */
1203                         if (hdspm_tco_sync_check(hdspm))
1204                                 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm));
1205                         break;
1206                 default:
1207                         return 0;
1208                 } /* end switch(syncref) */
1209                 break;
1210
1211         case MADIface:
1212                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1213
1214                 if (!(status & HDSPM_madiLock)) {
1215                         rate = 0;  /* no lock */
1216                 } else {
1217                         switch (status & (HDSPM_status1_freqMask)) {
1218                         case HDSPM_status1_F_0*1:
1219                                 rate = 32000; break;
1220                         case HDSPM_status1_F_0*2:
1221                                 rate = 44100; break;
1222                         case HDSPM_status1_F_0*3:
1223                                 rate = 48000; break;
1224                         case HDSPM_status1_F_0*4:
1225                                 rate = 64000; break;
1226                         case HDSPM_status1_F_0*5:
1227                                 rate = 88200; break;
1228                         case HDSPM_status1_F_0*6:
1229                                 rate = 96000; break;
1230                         case HDSPM_status1_F_0*7:
1231                                 rate = 128000; break;
1232                         case HDSPM_status1_F_0*8:
1233                                 rate = 176400; break;
1234                         case HDSPM_status1_F_0*9:
1235                                 rate = 192000; break;
1236                         default:
1237                                 rate = 0; break;
1238                         }
1239                 }
1240
1241                 break;
1242
1243         case MADI:
1244         case AIO:
1245         case RayDAT:
1246                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1247                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1248                 rate = 0;
1249
1250                 /* if wordclock has synced freq and wordclock is valid */
1251                 if ((status2 & HDSPM_wcLock) != 0 &&
1252                                 (status2 & HDSPM_SelSyncRef0) == 0) {
1253
1254                         rate_bits = status2 & HDSPM_wcFreqMask;
1255
1256
1257                         switch (rate_bits) {
1258                         case HDSPM_wcFreq32:
1259                                 rate = 32000;
1260                                 break;
1261                         case HDSPM_wcFreq44_1:
1262                                 rate = 44100;
1263                                 break;
1264                         case HDSPM_wcFreq48:
1265                                 rate = 48000;
1266                                 break;
1267                         case HDSPM_wcFreq64:
1268                                 rate = 64000;
1269                                 break;
1270                         case HDSPM_wcFreq88_2:
1271                                 rate = 88200;
1272                                 break;
1273                         case HDSPM_wcFreq96:
1274                                 rate = 96000;
1275                                 break;
1276                         case HDSPM_wcFreq128:
1277                                 rate = 128000;
1278                                 break;
1279                         case HDSPM_wcFreq176_4:
1280                                 rate = 176400;
1281                                 break;
1282                         case HDSPM_wcFreq192:
1283                                 rate = 192000;
1284                                 break;
1285                         default:
1286                                 rate = 0;
1287                                 break;
1288                         }
1289                 }
1290
1291                 /* if rate detected and Syncref is Word than have it,
1292                  * word has priority to MADI
1293                  */
1294                 if (rate != 0 &&
1295                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1296                         return hdspm_rate_multiplier(hdspm, rate);
1297
1298                 /* maybe a madi input (which is taken if sel sync is madi) */
1299                 if (status & HDSPM_madiLock) {
1300                         rate_bits = status & HDSPM_madiFreqMask;
1301
1302                         switch (rate_bits) {
1303                         case HDSPM_madiFreq32:
1304                                 rate = 32000;
1305                                 break;
1306                         case HDSPM_madiFreq44_1:
1307                                 rate = 44100;
1308                                 break;
1309                         case HDSPM_madiFreq48:
1310                                 rate = 48000;
1311                                 break;
1312                         case HDSPM_madiFreq64:
1313                                 rate = 64000;
1314                                 break;
1315                         case HDSPM_madiFreq88_2:
1316                                 rate = 88200;
1317                                 break;
1318                         case HDSPM_madiFreq96:
1319                                 rate = 96000;
1320                                 break;
1321                         case HDSPM_madiFreq128:
1322                                 rate = 128000;
1323                                 break;
1324                         case HDSPM_madiFreq176_4:
1325                                 rate = 176400;
1326                                 break;
1327                         case HDSPM_madiFreq192:
1328                                 rate = 192000;
1329                                 break;
1330                         default:
1331                                 rate = 0;
1332                                 break;
1333                         }
1334
1335                 } /* endif HDSPM_madiLock */
1336
1337                 /* check sample rate from TCO or SYNC_IN */
1338                 {
1339                         bool is_valid_input = 0;
1340                         bool has_sync = 0;
1341
1342                         syncref = hdspm_autosync_ref(hdspm);
1343                         if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1344                                 is_valid_input = 1;
1345                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1346                                         hdspm_tco_sync_check(hdspm));
1347                         } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1348                                 is_valid_input = 1;
1349                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1350                                         hdspm_sync_in_sync_check(hdspm));
1351                         }
1352
1353                         if (is_valid_input && has_sync) {
1354                                 rate = hdspm_round_frequency(
1355                                         hdspm_get_pll_freq(hdspm));
1356                         }
1357                 }
1358
1359                 rate = hdspm_rate_multiplier(hdspm, rate);
1360
1361                 break;
1362         }
1363
1364         return rate;
1365 }
1366
1367 /* return latency in samples per period */
1368 static int hdspm_get_latency(struct hdspm *hdspm)
1369 {
1370         int n;
1371
1372         n = hdspm_decode_latency(hdspm->control_register);
1373
1374         /* Special case for new RME cards with 32 samples period size.
1375          * The three latency bits in the control register
1376          * (HDSP_LatencyMask) encode latency values of 64 samples as
1377          * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1378          * denotes 8192 samples, but on new cards like RayDAT or AIO,
1379          * it corresponds to 32 samples.
1380          */
1381         if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1382                 n = -1;
1383
1384         return 1 << (n + 6);
1385 }
1386
1387 /* Latency function */
1388 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1389 {
1390         hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1391 }
1392
1393
1394 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1395 {
1396         int position;
1397
1398         position = hdspm_read(hdspm, HDSPM_statusRegister);
1399
1400         switch (hdspm->io_type) {
1401         case RayDAT:
1402         case AIO:
1403                 position &= HDSPM_BufferPositionMask;
1404                 position /= 4; /* Bytes per sample */
1405                 break;
1406         default:
1407                 position = (position & HDSPM_BufferID) ?
1408                         (hdspm->period_bytes / 4) : 0;
1409         }
1410
1411         return position;
1412 }
1413
1414
1415 static inline void hdspm_start_audio(struct hdspm * s)
1416 {
1417         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1418         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1419 }
1420
1421 static inline void hdspm_stop_audio(struct hdspm * s)
1422 {
1423         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1424         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1425 }
1426
1427 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1428 static void hdspm_silence_playback(struct hdspm *hdspm)
1429 {
1430         int i;
1431         int n = hdspm->period_bytes;
1432         void *buf = hdspm->playback_buffer;
1433
1434         if (buf == NULL)
1435                 return;
1436
1437         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1438                 memset(buf, 0, n);
1439                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1440         }
1441 }
1442
1443 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1444 {
1445         int n;
1446
1447         spin_lock_irq(&s->lock);
1448
1449         if (32 == frames) {
1450                 /* Special case for new RME cards like RayDAT/AIO which
1451                  * support period sizes of 32 samples. Since latency is
1452                  * encoded in the three bits of HDSP_LatencyMask, we can only
1453                  * have values from 0 .. 7. While 0 still means 64 samples and
1454                  * 6 represents 4096 samples on all cards, 7 represents 8192
1455                  * on older cards and 32 samples on new cards.
1456                  *
1457                  * In other words, period size in samples is calculated by
1458                  * 2^(n+6) with n ranging from 0 .. 7.
1459                  */
1460                 n = 7;
1461         } else {
1462                 frames >>= 7;
1463                 n = 0;
1464                 while (frames) {
1465                         n++;
1466                         frames >>= 1;
1467                 }
1468         }
1469
1470         s->control_register &= ~HDSPM_LatencyMask;
1471         s->control_register |= hdspm_encode_latency(n);
1472
1473         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1474
1475         hdspm_compute_period_size(s);
1476
1477         spin_unlock_irq(&s->lock);
1478
1479         return 0;
1480 }
1481
1482 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1483 {
1484         u64 freq_const;
1485
1486         if (period == 0)
1487                 return 0;
1488
1489         switch (hdspm->io_type) {
1490         case MADI:
1491         case AES32:
1492                 freq_const = 110069313433624ULL;
1493                 break;
1494         case RayDAT:
1495         case AIO:
1496                 freq_const = 104857600000000ULL;
1497                 break;
1498         case MADIface:
1499                 freq_const = 131072000000000ULL;
1500                 break;
1501         default:
1502                 snd_BUG();
1503                 return 0;
1504         }
1505
1506         return div_u64(freq_const, period);
1507 }
1508
1509
1510 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1511 {
1512         u64 n;
1513
1514         if (rate >= 112000)
1515                 rate /= 4;
1516         else if (rate >= 56000)
1517                 rate /= 2;
1518
1519         switch (hdspm->io_type) {
1520         case MADIface:
1521                 n = 131072000000000ULL;  /* 125 MHz */
1522                 break;
1523         case MADI:
1524         case AES32:
1525                 n = 110069313433624ULL;  /* 105 MHz */
1526                 break;
1527         case RayDAT:
1528         case AIO:
1529                 n = 104857600000000ULL;  /* 100 MHz */
1530                 break;
1531         default:
1532                 snd_BUG();
1533                 return;
1534         }
1535
1536         n = div_u64(n, rate);
1537         /* n should be less than 2^32 for being written to FREQ register */
1538         snd_BUG_ON(n >> 32);
1539         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1540 }
1541
1542 /* dummy set rate lets see what happens */
1543 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1544 {
1545         int current_rate;
1546         int rate_bits;
1547         int not_set = 0;
1548         int current_speed, target_speed;
1549
1550         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1551            it (e.g. during module initialization).
1552          */
1553
1554         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1555
1556                 /* SLAVE --- */
1557                 if (called_internally) {
1558
1559                         /* request from ctl or card initialization
1560                            just make a warning an remember setting
1561                            for future master mode switching */
1562
1563                         snd_printk(KERN_WARNING "HDSPM: "
1564                                    "Warning: device is not running "
1565                                    "as a clock master.\n");
1566                         not_set = 1;
1567                 } else {
1568
1569                         /* hw_param request while in AutoSync mode */
1570                         int external_freq =
1571                             hdspm_external_sample_rate(hdspm);
1572
1573                         if (hdspm_autosync_ref(hdspm) ==
1574                             HDSPM_AUTOSYNC_FROM_NONE) {
1575
1576                                 snd_printk(KERN_WARNING "HDSPM: "
1577                                            "Detected no Externel Sync \n");
1578                                 not_set = 1;
1579
1580                         } else if (rate != external_freq) {
1581
1582                                 snd_printk(KERN_WARNING "HDSPM: "
1583                                            "Warning: No AutoSync source for "
1584                                            "requested rate\n");
1585                                 not_set = 1;
1586                         }
1587                 }
1588         }
1589
1590         current_rate = hdspm->system_sample_rate;
1591
1592         /* Changing between Singe, Double and Quad speed is not
1593            allowed if any substreams are open. This is because such a change
1594            causes a shift in the location of the DMA buffers and a reduction
1595            in the number of available buffers.
1596
1597            Note that a similar but essentially insoluble problem exists for
1598            externally-driven rate changes. All we can do is to flag rate
1599            changes in the read/write routines.
1600          */
1601
1602         if (current_rate <= 48000)
1603                 current_speed = HDSPM_SPEED_SINGLE;
1604         else if (current_rate <= 96000)
1605                 current_speed = HDSPM_SPEED_DOUBLE;
1606         else
1607                 current_speed = HDSPM_SPEED_QUAD;
1608
1609         if (rate <= 48000)
1610                 target_speed = HDSPM_SPEED_SINGLE;
1611         else if (rate <= 96000)
1612                 target_speed = HDSPM_SPEED_DOUBLE;
1613         else
1614                 target_speed = HDSPM_SPEED_QUAD;
1615
1616         switch (rate) {
1617         case 32000:
1618                 rate_bits = HDSPM_Frequency32KHz;
1619                 break;
1620         case 44100:
1621                 rate_bits = HDSPM_Frequency44_1KHz;
1622                 break;
1623         case 48000:
1624                 rate_bits = HDSPM_Frequency48KHz;
1625                 break;
1626         case 64000:
1627                 rate_bits = HDSPM_Frequency64KHz;
1628                 break;
1629         case 88200:
1630                 rate_bits = HDSPM_Frequency88_2KHz;
1631                 break;
1632         case 96000:
1633                 rate_bits = HDSPM_Frequency96KHz;
1634                 break;
1635         case 128000:
1636                 rate_bits = HDSPM_Frequency128KHz;
1637                 break;
1638         case 176400:
1639                 rate_bits = HDSPM_Frequency176_4KHz;
1640                 break;
1641         case 192000:
1642                 rate_bits = HDSPM_Frequency192KHz;
1643                 break;
1644         default:
1645                 return -EINVAL;
1646         }
1647
1648         if (current_speed != target_speed
1649             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1650                 snd_printk
1651                     (KERN_ERR "HDSPM: "
1652                      "cannot change from %s speed to %s speed mode "
1653                      "(capture PID = %d, playback PID = %d)\n",
1654                      hdspm_speed_names[current_speed],
1655                      hdspm_speed_names[target_speed],
1656                      hdspm->capture_pid, hdspm->playback_pid);
1657                 return -EBUSY;
1658         }
1659
1660         hdspm->control_register &= ~HDSPM_FrequencyMask;
1661         hdspm->control_register |= rate_bits;
1662         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1663
1664         /* For AES32, need to set DDS value in FREQ register
1665            For MADI, also apparently */
1666         hdspm_set_dds_value(hdspm, rate);
1667
1668         if (AES32 == hdspm->io_type && rate != current_rate)
1669                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1670
1671         hdspm->system_sample_rate = rate;
1672
1673         if (rate <= 48000) {
1674                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1675                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1676                 hdspm->max_channels_in = hdspm->ss_in_channels;
1677                 hdspm->max_channels_out = hdspm->ss_out_channels;
1678                 hdspm->port_names_in = hdspm->port_names_in_ss;
1679                 hdspm->port_names_out = hdspm->port_names_out_ss;
1680         } else if (rate <= 96000) {
1681                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1682                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1683                 hdspm->max_channels_in = hdspm->ds_in_channels;
1684                 hdspm->max_channels_out = hdspm->ds_out_channels;
1685                 hdspm->port_names_in = hdspm->port_names_in_ds;
1686                 hdspm->port_names_out = hdspm->port_names_out_ds;
1687         } else {
1688                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1689                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1690                 hdspm->max_channels_in = hdspm->qs_in_channels;
1691                 hdspm->max_channels_out = hdspm->qs_out_channels;
1692                 hdspm->port_names_in = hdspm->port_names_in_qs;
1693                 hdspm->port_names_out = hdspm->port_names_out_qs;
1694         }
1695
1696         if (not_set != 0)
1697                 return -1;
1698
1699         return 0;
1700 }
1701
1702 /* mainly for init to 0 on load */
1703 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1704 {
1705         int i, j;
1706         unsigned int gain;
1707
1708         if (sgain > UNITY_GAIN)
1709                 gain = UNITY_GAIN;
1710         else if (sgain < 0)
1711                 gain = 0;
1712         else
1713                 gain = sgain;
1714
1715         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1716                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1717                         hdspm_write_in_gain(hdspm, i, j, gain);
1718                         hdspm_write_pb_gain(hdspm, i, j, gain);
1719                 }
1720 }
1721
1722 /*----------------------------------------------------------------------------
1723    MIDI
1724   ----------------------------------------------------------------------------*/
1725
1726 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1727                                                       int id)
1728 {
1729         /* the hardware already does the relevant bit-mask with 0xff */
1730         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1731 }
1732
1733 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1734                                               int val)
1735 {
1736         /* the hardware already does the relevant bit-mask with 0xff */
1737         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1738 }
1739
1740 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1741 {
1742         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1743 }
1744
1745 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1746 {
1747         int fifo_bytes_used;
1748
1749         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1750
1751         if (fifo_bytes_used < 128)
1752                 return  128 - fifo_bytes_used;
1753         else
1754                 return 0;
1755 }
1756
1757 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1758 {
1759         while (snd_hdspm_midi_input_available (hdspm, id))
1760                 snd_hdspm_midi_read_byte (hdspm, id);
1761 }
1762
1763 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1764 {
1765         unsigned long flags;
1766         int n_pending;
1767         int to_write;
1768         int i;
1769         unsigned char buf[128];
1770
1771         /* Output is not interrupt driven */
1772
1773         spin_lock_irqsave (&hmidi->lock, flags);
1774         if (hmidi->output &&
1775             !snd_rawmidi_transmit_empty (hmidi->output)) {
1776                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1777                                                             hmidi->id);
1778                 if (n_pending > 0) {
1779                         if (n_pending > (int)sizeof (buf))
1780                                 n_pending = sizeof (buf);
1781
1782                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1783                                                          n_pending);
1784                         if (to_write > 0) {
1785                                 for (i = 0; i < to_write; ++i)
1786                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1787                                                                    hmidi->id,
1788                                                                    buf[i]);
1789                         }
1790                 }
1791         }
1792         spin_unlock_irqrestore (&hmidi->lock, flags);
1793         return 0;
1794 }
1795
1796 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1797 {
1798         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1799                                  * input FIFO size
1800                                  */
1801         unsigned long flags;
1802         int n_pending;
1803         int i;
1804
1805         spin_lock_irqsave (&hmidi->lock, flags);
1806         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1807         if (n_pending > 0) {
1808                 if (hmidi->input) {
1809                         if (n_pending > (int)sizeof (buf))
1810                                 n_pending = sizeof (buf);
1811                         for (i = 0; i < n_pending; ++i)
1812                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1813                                                                    hmidi->id);
1814                         if (n_pending)
1815                                 snd_rawmidi_receive (hmidi->input, buf,
1816                                                      n_pending);
1817                 } else {
1818                         /* flush the MIDI input FIFO */
1819                         while (n_pending--)
1820                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1821                                                           hmidi->id);
1822                 }
1823         }
1824         hmidi->pending = 0;
1825         spin_unlock_irqrestore(&hmidi->lock, flags);
1826
1827         spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1828         hmidi->hdspm->control_register |= hmidi->ie;
1829         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1830                     hmidi->hdspm->control_register);
1831         spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1832
1833         return snd_hdspm_midi_output_write (hmidi);
1834 }
1835
1836 static void
1837 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1838 {
1839         struct hdspm *hdspm;
1840         struct hdspm_midi *hmidi;
1841         unsigned long flags;
1842
1843         hmidi = substream->rmidi->private_data;
1844         hdspm = hmidi->hdspm;
1845
1846         spin_lock_irqsave (&hdspm->lock, flags);
1847         if (up) {
1848                 if (!(hdspm->control_register & hmidi->ie)) {
1849                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1850                         hdspm->control_register |= hmidi->ie;
1851                 }
1852         } else {
1853                 hdspm->control_register &= ~hmidi->ie;
1854         }
1855
1856         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1857         spin_unlock_irqrestore (&hdspm->lock, flags);
1858 }
1859
1860 static void snd_hdspm_midi_output_timer(unsigned long data)
1861 {
1862         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1863         unsigned long flags;
1864
1865         snd_hdspm_midi_output_write(hmidi);
1866         spin_lock_irqsave (&hmidi->lock, flags);
1867
1868         /* this does not bump hmidi->istimer, because the
1869            kernel automatically removed the timer when it
1870            expired, and we are now adding it back, thus
1871            leaving istimer wherever it was set before.
1872         */
1873
1874         if (hmidi->istimer) {
1875                 hmidi->timer.expires = 1 + jiffies;
1876                 add_timer(&hmidi->timer);
1877         }
1878
1879         spin_unlock_irqrestore (&hmidi->lock, flags);
1880 }
1881
1882 static void
1883 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1884 {
1885         struct hdspm_midi *hmidi;
1886         unsigned long flags;
1887
1888         hmidi = substream->rmidi->private_data;
1889         spin_lock_irqsave (&hmidi->lock, flags);
1890         if (up) {
1891                 if (!hmidi->istimer) {
1892                         init_timer(&hmidi->timer);
1893                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1894                         hmidi->timer.data = (unsigned long) hmidi;
1895                         hmidi->timer.expires = 1 + jiffies;
1896                         add_timer(&hmidi->timer);
1897                         hmidi->istimer++;
1898                 }
1899         } else {
1900                 if (hmidi->istimer && --hmidi->istimer <= 0)
1901                         del_timer (&hmidi->timer);
1902         }
1903         spin_unlock_irqrestore (&hmidi->lock, flags);
1904         if (up)
1905                 snd_hdspm_midi_output_write(hmidi);
1906 }
1907
1908 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1909 {
1910         struct hdspm_midi *hmidi;
1911
1912         hmidi = substream->rmidi->private_data;
1913         spin_lock_irq (&hmidi->lock);
1914         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1915         hmidi->input = substream;
1916         spin_unlock_irq (&hmidi->lock);
1917
1918         return 0;
1919 }
1920
1921 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1922 {
1923         struct hdspm_midi *hmidi;
1924
1925         hmidi = substream->rmidi->private_data;
1926         spin_lock_irq (&hmidi->lock);
1927         hmidi->output = substream;
1928         spin_unlock_irq (&hmidi->lock);
1929
1930         return 0;
1931 }
1932
1933 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1934 {
1935         struct hdspm_midi *hmidi;
1936
1937         snd_hdspm_midi_input_trigger (substream, 0);
1938
1939         hmidi = substream->rmidi->private_data;
1940         spin_lock_irq (&hmidi->lock);
1941         hmidi->input = NULL;
1942         spin_unlock_irq (&hmidi->lock);
1943
1944         return 0;
1945 }
1946
1947 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1948 {
1949         struct hdspm_midi *hmidi;
1950
1951         snd_hdspm_midi_output_trigger (substream, 0);
1952
1953         hmidi = substream->rmidi->private_data;
1954         spin_lock_irq (&hmidi->lock);
1955         hmidi->output = NULL;
1956         spin_unlock_irq (&hmidi->lock);
1957
1958         return 0;
1959 }
1960
1961 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1962 {
1963         .open =         snd_hdspm_midi_output_open,
1964         .close =        snd_hdspm_midi_output_close,
1965         .trigger =      snd_hdspm_midi_output_trigger,
1966 };
1967
1968 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1969 {
1970         .open =         snd_hdspm_midi_input_open,
1971         .close =        snd_hdspm_midi_input_close,
1972         .trigger =      snd_hdspm_midi_input_trigger,
1973 };
1974
1975 static int snd_hdspm_create_midi(struct snd_card *card,
1976                                  struct hdspm *hdspm, int id)
1977 {
1978         int err;
1979         char buf[32];
1980
1981         hdspm->midi[id].id = id;
1982         hdspm->midi[id].hdspm = hdspm;
1983         spin_lock_init (&hdspm->midi[id].lock);
1984
1985         if (0 == id) {
1986                 if (MADIface == hdspm->io_type) {
1987                         /* MIDI-over-MADI on HDSPe MADIface */
1988                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1989                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1990                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1991                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1992                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1993                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1994                 } else {
1995                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1996                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1997                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1998                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1999                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
2000                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
2001                 }
2002         } else if (1 == id) {
2003                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
2004                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
2005                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
2006                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
2007                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
2008                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
2009         } else if ((2 == id) && (MADI == hdspm->io_type)) {
2010                 /* MIDI-over-MADI on HDSPe MADI */
2011                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2012                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2013                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
2014                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
2015                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2016                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
2017         } else if (2 == id) {
2018                 /* TCO MTC, read only */
2019                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2020                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2021                 hdspm->midi[2].dataOut = -1;
2022                 hdspm->midi[2].statusOut = -1;
2023                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2024                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
2025         } else if (3 == id) {
2026                 /* TCO MTC on HDSPe MADI */
2027                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
2028                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
2029                 hdspm->midi[3].dataOut = -1;
2030                 hdspm->midi[3].statusOut = -1;
2031                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2032                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2033         }
2034
2035         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2036                                         (MADIface == hdspm->io_type)))) {
2037                 if ((id == 0) && (MADIface == hdspm->io_type)) {
2038                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
2039                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
2040                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
2041                 } else {
2042                         sprintf(buf, "%s MIDI %d", card->shortname, id+1);
2043                 }
2044                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2045                                 &hdspm->midi[id].rmidi);
2046                 if (err < 0)
2047                         return err;
2048
2049                 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
2050                                 card->id, id+1);
2051                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2052
2053                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2054                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
2055                                 &snd_hdspm_midi_output);
2056                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2057                                 SNDRV_RAWMIDI_STREAM_INPUT,
2058                                 &snd_hdspm_midi_input);
2059
2060                 hdspm->midi[id].rmidi->info_flags |=
2061                         SNDRV_RAWMIDI_INFO_OUTPUT |
2062                         SNDRV_RAWMIDI_INFO_INPUT |
2063                         SNDRV_RAWMIDI_INFO_DUPLEX;
2064         } else {
2065                 /* TCO MTC, read only */
2066                 sprintf(buf, "%s MTC %d", card->shortname, id+1);
2067                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2068                                 &hdspm->midi[id].rmidi);
2069                 if (err < 0)
2070                         return err;
2071
2072                 sprintf(hdspm->midi[id].rmidi->name,
2073                                 "%s MTC %d", card->id, id+1);
2074                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2075
2076                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2077                                 SNDRV_RAWMIDI_STREAM_INPUT,
2078                                 &snd_hdspm_midi_input);
2079
2080                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2081         }
2082
2083         return 0;
2084 }
2085
2086
2087 static void hdspm_midi_tasklet(unsigned long arg)
2088 {
2089         struct hdspm *hdspm = (struct hdspm *)arg;
2090         int i = 0;
2091
2092         while (i < hdspm->midiPorts) {
2093                 if (hdspm->midi[i].pending)
2094                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
2095
2096                 i++;
2097         }
2098 }
2099
2100
2101 /*-----------------------------------------------------------------------------
2102   Status Interface
2103   ----------------------------------------------------------------------------*/
2104
2105 /* get the system sample rate which is set */
2106
2107
2108 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2109 {
2110         unsigned int period, rate;
2111
2112         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2113         rate = hdspm_calc_dds_value(hdspm, period);
2114
2115         return rate;
2116 }
2117
2118 /**
2119  * Calculate the real sample rate from the
2120  * current DDS value.
2121  **/
2122 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2123 {
2124         unsigned int rate;
2125
2126         rate = hdspm_get_pll_freq(hdspm);
2127
2128         if (rate > 207000) {
2129                 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2130                 if (0 == hdspm_system_clock_mode(hdspm)) {
2131                         /* master mode, return internal sample rate */
2132                         rate = hdspm->system_sample_rate;
2133                 } else {
2134                         /* slave mode, return external sample rate */
2135                         rate = hdspm_external_sample_rate(hdspm);
2136                 }
2137         }
2138
2139         return rate;
2140 }
2141
2142
2143 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2144 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2145         .name = xname, \
2146         .index = xindex, \
2147         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2148                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2149         .info = snd_hdspm_info_system_sample_rate, \
2150         .put = snd_hdspm_put_system_sample_rate, \
2151         .get = snd_hdspm_get_system_sample_rate \
2152 }
2153
2154 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2155                                              struct snd_ctl_elem_info *uinfo)
2156 {
2157         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2158         uinfo->count = 1;
2159         uinfo->value.integer.min = 27000;
2160         uinfo->value.integer.max = 207000;
2161         uinfo->value.integer.step = 1;
2162         return 0;
2163 }
2164
2165
2166 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2167                                             struct snd_ctl_elem_value *
2168                                             ucontrol)
2169 {
2170         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2171
2172         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2173         return 0;
2174 }
2175
2176 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2177                                             struct snd_ctl_elem_value *
2178                                             ucontrol)
2179 {
2180         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2181
2182         hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]);
2183         return 0;
2184 }
2185
2186
2187 /**
2188  * Returns the WordClock sample rate class for the given card.
2189  **/
2190 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2191 {
2192         int status;
2193
2194         switch (hdspm->io_type) {
2195         case RayDAT:
2196         case AIO:
2197                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2198                 return (status >> 16) & 0xF;
2199                 break;
2200         case AES32:
2201                 status = hdspm_read(hdspm, HDSPM_statusRegister);
2202                 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF;
2203         default:
2204                 break;
2205         }
2206
2207
2208         return 0;
2209 }
2210
2211
2212 /**
2213  * Returns the TCO sample rate class for the given card.
2214  **/
2215 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2216 {
2217         int status;
2218
2219         if (hdspm->tco) {
2220                 switch (hdspm->io_type) {
2221                 case RayDAT:
2222                 case AIO:
2223                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2224                         return (status >> 20) & 0xF;
2225                         break;
2226                 case AES32:
2227                         status = hdspm_read(hdspm, HDSPM_statusRegister);
2228                         return (status >> 1) & 0xF;
2229                 default:
2230                         break;
2231                 }
2232         }
2233
2234         return 0;
2235 }
2236
2237
2238 /**
2239  * Returns the SYNC_IN sample rate class for the given card.
2240  **/
2241 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2242 {
2243         int status;
2244
2245         if (hdspm->tco) {
2246                 switch (hdspm->io_type) {
2247                 case RayDAT:
2248                 case AIO:
2249                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2250                         return (status >> 12) & 0xF;
2251                         break;
2252                 default:
2253                         break;
2254                 }
2255         }
2256
2257         return 0;
2258 }
2259
2260 /**
2261  * Returns the AES sample rate class for the given card.
2262  **/
2263 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index)
2264 {
2265         int timecode;
2266
2267         switch (hdspm->io_type) {
2268         case AES32:
2269                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
2270                 return (timecode >> (4*index)) & 0xF;
2271                 break;
2272         default:
2273                 break;
2274         }
2275         return 0;
2276 }
2277
2278 /**
2279  * Returns the sample rate class for input source <idx> for
2280  * 'new style' cards like the AIO and RayDAT.
2281  **/
2282 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2283 {
2284         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2285
2286         return (status >> (idx*4)) & 0xF;
2287 }
2288
2289 #define ENUMERATED_CTL_INFO(info, texts) \
2290         snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts)
2291
2292
2293 /* Helper function to query the external sample rate and return the
2294  * corresponding enum to be returned to userspace.
2295  */
2296 static int hdspm_external_rate_to_enum(struct hdspm *hdspm)
2297 {
2298         int rate = hdspm_external_sample_rate(hdspm);
2299         int i, selected_rate = 0;
2300         for (i = 1; i < 10; i++)
2301                 if (HDSPM_bit2freq(i) == rate) {
2302                         selected_rate = i;
2303                         break;
2304                 }
2305         return selected_rate;
2306 }
2307
2308
2309 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2310 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2311         .name = xname, \
2312         .private_value = xindex, \
2313         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2314         .info = snd_hdspm_info_autosync_sample_rate, \
2315         .get = snd_hdspm_get_autosync_sample_rate \
2316 }
2317
2318
2319 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2320                                                struct snd_ctl_elem_info *uinfo)
2321 {
2322         ENUMERATED_CTL_INFO(uinfo, texts_freq);
2323         return 0;
2324 }
2325
2326
2327 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2328                                               struct snd_ctl_elem_value *
2329                                               ucontrol)
2330 {
2331         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2332
2333         switch (hdspm->io_type) {
2334         case RayDAT:
2335                 switch (kcontrol->private_value) {
2336                 case 0:
2337                         ucontrol->value.enumerated.item[0] =
2338                                 hdspm_get_wc_sample_rate(hdspm);
2339                         break;
2340                 case 7:
2341                         ucontrol->value.enumerated.item[0] =
2342                                 hdspm_get_tco_sample_rate(hdspm);
2343                         break;
2344                 case 8:
2345                         ucontrol->value.enumerated.item[0] =
2346                                 hdspm_get_sync_in_sample_rate(hdspm);
2347                         break;
2348                 default:
2349                         ucontrol->value.enumerated.item[0] =
2350                                 hdspm_get_s1_sample_rate(hdspm,
2351                                                 kcontrol->private_value-1);
2352                 }
2353                 break;
2354
2355         case AIO:
2356                 switch (kcontrol->private_value) {
2357                 case 0: /* WC */
2358                         ucontrol->value.enumerated.item[0] =
2359                                 hdspm_get_wc_sample_rate(hdspm);
2360                         break;
2361                 case 4: /* TCO */
2362                         ucontrol->value.enumerated.item[0] =
2363                                 hdspm_get_tco_sample_rate(hdspm);
2364                         break;
2365                 case 5: /* SYNC_IN */
2366                         ucontrol->value.enumerated.item[0] =
2367                                 hdspm_get_sync_in_sample_rate(hdspm);
2368                         break;
2369                 default:
2370                         ucontrol->value.enumerated.item[0] =
2371                                 hdspm_get_s1_sample_rate(hdspm,
2372                                                 kcontrol->private_value-1);
2373                 }
2374                 break;
2375
2376         case AES32:
2377
2378                 switch (kcontrol->private_value) {
2379                 case 0: /* WC */
2380                         ucontrol->value.enumerated.item[0] =
2381                                 hdspm_get_wc_sample_rate(hdspm);
2382                         break;
2383                 case 9: /* TCO */
2384                         ucontrol->value.enumerated.item[0] =
2385                                 hdspm_get_tco_sample_rate(hdspm);
2386                         break;
2387                 case 10: /* SYNC_IN */
2388                         ucontrol->value.enumerated.item[0] =
2389                                 hdspm_get_sync_in_sample_rate(hdspm);
2390                         break;
2391                 case 11: /* External Rate */
2392                         ucontrol->value.enumerated.item[0] =
2393                                 hdspm_external_rate_to_enum(hdspm);
2394                         break;
2395                 default: /* AES1 to AES8 */
2396                         ucontrol->value.enumerated.item[0] =
2397                                 hdspm_get_aes_sample_rate(hdspm,
2398                                                 kcontrol->private_value -
2399                                                 HDSPM_AES32_AUTOSYNC_FROM_AES1);
2400                         break;
2401                 }
2402                 break;
2403
2404         case MADI:
2405         case MADIface:
2406                 ucontrol->value.enumerated.item[0] =
2407                         hdspm_external_rate_to_enum(hdspm);
2408                 break;
2409         default:
2410                 break;
2411         }
2412
2413         return 0;
2414 }
2415
2416
2417 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2418 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2419         .name = xname, \
2420         .index = xindex, \
2421         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2422                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2423         .info = snd_hdspm_info_system_clock_mode, \
2424         .get = snd_hdspm_get_system_clock_mode, \
2425         .put = snd_hdspm_put_system_clock_mode, \
2426 }
2427
2428
2429 /**
2430  * Returns the system clock mode for the given card.
2431  * @returns 0 - master, 1 - slave
2432  **/
2433 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2434 {
2435         switch (hdspm->io_type) {
2436         case AIO:
2437         case RayDAT:
2438                 if (hdspm->settings_register & HDSPM_c0Master)
2439                         return 0;
2440                 break;
2441
2442         default:
2443                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2444                         return 0;
2445         }
2446
2447         return 1;
2448 }
2449
2450
2451 /**
2452  * Sets the system clock mode.
2453  * @param mode 0 - master, 1 - slave
2454  **/
2455 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2456 {
2457         hdspm_set_toggle_setting(hdspm,
2458                         (hdspm_is_raydat_or_aio(hdspm)) ?
2459                         HDSPM_c0Master : HDSPM_ClockModeMaster,
2460                         (0 == mode));
2461 }
2462
2463
2464 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2465                                             struct snd_ctl_elem_info *uinfo)
2466 {
2467         static const char *const texts[] = { "Master", "AutoSync" };
2468         ENUMERATED_CTL_INFO(uinfo, texts);
2469         return 0;
2470 }
2471
2472 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2473                                            struct snd_ctl_elem_value *ucontrol)
2474 {
2475         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2476
2477         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2478         return 0;
2479 }
2480
2481 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2482                                            struct snd_ctl_elem_value *ucontrol)
2483 {
2484         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2485         int val;
2486
2487         if (!snd_hdspm_use_is_exclusive(hdspm))
2488                 return -EBUSY;
2489
2490         val = ucontrol->value.enumerated.item[0];
2491         if (val < 0)
2492                 val = 0;
2493         else if (val > 1)
2494                 val = 1;
2495
2496         hdspm_set_system_clock_mode(hdspm, val);
2497
2498         return 0;
2499 }
2500
2501
2502 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2503 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2504         .name = xname, \
2505         .index = xindex, \
2506         .info = snd_hdspm_info_clock_source, \
2507         .get = snd_hdspm_get_clock_source, \
2508         .put = snd_hdspm_put_clock_source \
2509 }
2510
2511
2512 static int hdspm_clock_source(struct hdspm * hdspm)
2513 {
2514         switch (hdspm->system_sample_rate) {
2515         case 32000: return 0;
2516         case 44100: return 1;
2517         case 48000: return 2;
2518         case 64000: return 3;
2519         case 88200: return 4;
2520         case 96000: return 5;
2521         case 128000: return 6;
2522         case 176400: return 7;
2523         case 192000: return 8;
2524         }
2525
2526         return -1;
2527 }
2528
2529 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2530 {
2531         int rate;
2532         switch (mode) {
2533         case 0:
2534                 rate = 32000; break;
2535         case 1:
2536                 rate = 44100; break;
2537         case 2:
2538                 rate = 48000; break;
2539         case 3:
2540                 rate = 64000; break;
2541         case 4:
2542                 rate = 88200; break;
2543         case 5:
2544                 rate = 96000; break;
2545         case 6:
2546                 rate = 128000; break;
2547         case 7:
2548                 rate = 176400; break;
2549         case 8:
2550                 rate = 192000; break;
2551         default:
2552                 rate = 48000;
2553         }
2554         hdspm_set_rate(hdspm, rate, 1);
2555         return 0;
2556 }
2557
2558 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2559                                        struct snd_ctl_elem_info *uinfo)
2560 {
2561         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2562         uinfo->count = 1;
2563         uinfo->value.enumerated.items = 9;
2564
2565         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2566                 uinfo->value.enumerated.item =
2567                     uinfo->value.enumerated.items - 1;
2568
2569         strcpy(uinfo->value.enumerated.name,
2570                texts_freq[uinfo->value.enumerated.item+1]);
2571
2572         return 0;
2573 }
2574
2575 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2576                                       struct snd_ctl_elem_value *ucontrol)
2577 {
2578         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2579
2580         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2581         return 0;
2582 }
2583
2584 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2585                                       struct snd_ctl_elem_value *ucontrol)
2586 {
2587         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2588         int change;
2589         int val;
2590
2591         if (!snd_hdspm_use_is_exclusive(hdspm))
2592                 return -EBUSY;
2593         val = ucontrol->value.enumerated.item[0];
2594         if (val < 0)
2595                 val = 0;
2596         if (val > 9)
2597                 val = 9;
2598         spin_lock_irq(&hdspm->lock);
2599         if (val != hdspm_clock_source(hdspm))
2600                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2601         else
2602                 change = 0;
2603         spin_unlock_irq(&hdspm->lock);
2604         return change;
2605 }
2606
2607
2608 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2609 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2610         .name = xname, \
2611         .index = xindex, \
2612         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2613                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2614         .info = snd_hdspm_info_pref_sync_ref, \
2615         .get = snd_hdspm_get_pref_sync_ref, \
2616         .put = snd_hdspm_put_pref_sync_ref \
2617 }
2618
2619
2620 /**
2621  * Returns the current preferred sync reference setting.
2622  * The semantics of the return value are depending on the
2623  * card, please see the comments for clarification.
2624  **/
2625 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2626 {
2627         switch (hdspm->io_type) {
2628         case AES32:
2629                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2630                 case 0: return 0;  /* WC */
2631                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2632                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2633                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2634                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2635                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2636                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2637                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2638                                                     return 7; /* AES 7 */
2639                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2640                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2641                 }
2642                 break;
2643
2644         case MADI:
2645         case MADIface:
2646                 if (hdspm->tco) {
2647                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2648                         case 0: return 0;  /* WC */
2649                         case HDSPM_SyncRef0: return 1;  /* MADI */
2650                         case HDSPM_SyncRef1: return 2;  /* TCO */
2651                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2652                                              return 3;  /* SYNC_IN */
2653                         }
2654                 } else {
2655                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2656                         case 0: return 0;  /* WC */
2657                         case HDSPM_SyncRef0: return 1;  /* MADI */
2658                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2659                                              return 2;  /* SYNC_IN */
2660                         }
2661                 }
2662                 break;
2663
2664         case RayDAT:
2665                 if (hdspm->tco) {
2666                         switch ((hdspm->settings_register &
2667                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2668                         case 0: return 0;  /* WC */
2669                         case 3: return 1;  /* ADAT 1 */
2670                         case 4: return 2;  /* ADAT 2 */
2671                         case 5: return 3;  /* ADAT 3 */
2672                         case 6: return 4;  /* ADAT 4 */
2673                         case 1: return 5;  /* AES */
2674                         case 2: return 6;  /* SPDIF */
2675                         case 9: return 7;  /* TCO */
2676                         case 10: return 8; /* SYNC_IN */
2677                         }
2678                 } else {
2679                         switch ((hdspm->settings_register &
2680                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2681                         case 0: return 0;  /* WC */
2682                         case 3: return 1;  /* ADAT 1 */
2683                         case 4: return 2;  /* ADAT 2 */
2684                         case 5: return 3;  /* ADAT 3 */
2685                         case 6: return 4;  /* ADAT 4 */
2686                         case 1: return 5;  /* AES */
2687                         case 2: return 6;  /* SPDIF */
2688                         case 10: return 7; /* SYNC_IN */
2689                         }
2690                 }
2691
2692                 break;
2693
2694         case AIO:
2695                 if (hdspm->tco) {
2696                         switch ((hdspm->settings_register &
2697                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2698                         case 0: return 0;  /* WC */
2699                         case 3: return 1;  /* ADAT */
2700                         case 1: return 2;  /* AES */
2701                         case 2: return 3;  /* SPDIF */
2702                         case 9: return 4;  /* TCO */
2703                         case 10: return 5; /* SYNC_IN */
2704                         }
2705                 } else {
2706                         switch ((hdspm->settings_register &
2707                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2708                         case 0: return 0;  /* WC */
2709                         case 3: return 1;  /* ADAT */
2710                         case 1: return 2;  /* AES */
2711                         case 2: return 3;  /* SPDIF */
2712                         case 10: return 4; /* SYNC_IN */
2713                         }
2714                 }
2715
2716                 break;
2717         }
2718
2719         return -1;
2720 }
2721
2722
2723 /**
2724  * Set the preferred sync reference to <pref>. The semantics
2725  * of <pref> are depending on the card type, see the comments
2726  * for clarification.
2727  **/
2728 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2729 {
2730         int p = 0;
2731
2732         switch (hdspm->io_type) {
2733         case AES32:
2734                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2735                 switch (pref) {
2736                 case 0: /* WC  */
2737                         break;
2738                 case 1: /* AES 1 */
2739                         hdspm->control_register |= HDSPM_SyncRef0;
2740                         break;
2741                 case 2: /* AES 2 */
2742                         hdspm->control_register |= HDSPM_SyncRef1;
2743                         break;
2744                 case 3: /* AES 3 */
2745                         hdspm->control_register |=
2746                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2747                         break;
2748                 case 4: /* AES 4 */
2749                         hdspm->control_register |= HDSPM_SyncRef2;
2750                         break;
2751                 case 5: /* AES 5 */
2752                         hdspm->control_register |=
2753                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2754                         break;
2755                 case 6: /* AES 6 */
2756                         hdspm->control_register |=
2757                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2758                         break;
2759                 case 7: /* AES 7 */
2760                         hdspm->control_register |=
2761                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2762                         break;
2763                 case 8: /* AES 8 */
2764                         hdspm->control_register |= HDSPM_SyncRef3;
2765                         break;
2766                 case 9: /* TCO */
2767                         hdspm->control_register |=
2768                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2769                         break;
2770                 default:
2771                         return -1;
2772                 }
2773
2774                 break;
2775
2776         case MADI:
2777         case MADIface:
2778                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2779                 if (hdspm->tco) {
2780                         switch (pref) {
2781                         case 0: /* WC */
2782                                 break;
2783                         case 1: /* MADI */
2784                                 hdspm->control_register |= HDSPM_SyncRef0;
2785                                 break;
2786                         case 2: /* TCO */
2787                                 hdspm->control_register |= HDSPM_SyncRef1;
2788                                 break;
2789                         case 3: /* SYNC_IN */
2790                                 hdspm->control_register |=
2791                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2792                                 break;
2793                         default:
2794                                 return -1;
2795                         }
2796                 } else {
2797                         switch (pref) {
2798                         case 0: /* WC */
2799                                 break;
2800                         case 1: /* MADI */
2801                                 hdspm->control_register |= HDSPM_SyncRef0;
2802                                 break;
2803                         case 2: /* SYNC_IN */
2804                                 hdspm->control_register |=
2805                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2806                                 break;
2807                         default:
2808                                 return -1;
2809                         }
2810                 }
2811
2812                 break;
2813
2814         case RayDAT:
2815                 if (hdspm->tco) {
2816                         switch (pref) {
2817                         case 0: p = 0; break;  /* WC */
2818                         case 1: p = 3; break;  /* ADAT 1 */
2819                         case 2: p = 4; break;  /* ADAT 2 */
2820                         case 3: p = 5; break;  /* ADAT 3 */
2821                         case 4: p = 6; break;  /* ADAT 4 */
2822                         case 5: p = 1; break;  /* AES */
2823                         case 6: p = 2; break;  /* SPDIF */
2824                         case 7: p = 9; break;  /* TCO */
2825                         case 8: p = 10; break; /* SYNC_IN */
2826                         default: return -1;
2827                         }
2828                 } else {
2829                         switch (pref) {
2830                         case 0: p = 0; break;  /* WC */
2831                         case 1: p = 3; break;  /* ADAT 1 */
2832                         case 2: p = 4; break;  /* ADAT 2 */
2833                         case 3: p = 5; break;  /* ADAT 3 */
2834                         case 4: p = 6; break;  /* ADAT 4 */
2835                         case 5: p = 1; break;  /* AES */
2836                         case 6: p = 2; break;  /* SPDIF */
2837                         case 7: p = 10; break; /* SYNC_IN */
2838                         default: return -1;
2839                         }
2840                 }
2841                 break;
2842
2843         case AIO:
2844                 if (hdspm->tco) {
2845                         switch (pref) {
2846                         case 0: p = 0; break;  /* WC */
2847                         case 1: p = 3; break;  /* ADAT */
2848                         case 2: p = 1; break;  /* AES */
2849                         case 3: p = 2; break;  /* SPDIF */
2850                         case 4: p = 9; break;  /* TCO */
2851                         case 5: p = 10; break; /* SYNC_IN */
2852                         default: return -1;
2853                         }
2854                 } else {
2855                         switch (pref) {
2856                         case 0: p = 0; break;  /* WC */
2857                         case 1: p = 3; break;  /* ADAT */
2858                         case 2: p = 1; break;  /* AES */
2859                         case 3: p = 2; break;  /* SPDIF */
2860                         case 4: p = 10; break; /* SYNC_IN */
2861                         default: return -1;
2862                         }
2863                 }
2864                 break;
2865         }
2866
2867         switch (hdspm->io_type) {
2868         case RayDAT:
2869         case AIO:
2870                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2871                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2872                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2873                 break;
2874
2875         case MADI:
2876         case MADIface:
2877         case AES32:
2878                 hdspm_write(hdspm, HDSPM_controlRegister,
2879                                 hdspm->control_register);
2880         }
2881
2882         return 0;
2883 }
2884
2885
2886 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2887                                         struct snd_ctl_elem_info *uinfo)
2888 {
2889         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2890
2891         snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync);
2892
2893         return 0;
2894 }
2895
2896 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2897                                        struct snd_ctl_elem_value *ucontrol)
2898 {
2899         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2900         int psf = hdspm_pref_sync_ref(hdspm);
2901
2902         if (psf >= 0) {
2903                 ucontrol->value.enumerated.item[0] = psf;
2904                 return 0;
2905         }
2906
2907         return -1;
2908 }
2909
2910 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2911                                        struct snd_ctl_elem_value *ucontrol)
2912 {
2913         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2914         int val, change = 0;
2915
2916         if (!snd_hdspm_use_is_exclusive(hdspm))
2917                 return -EBUSY;
2918
2919         val = ucontrol->value.enumerated.item[0];
2920
2921         if (val < 0)
2922                 val = 0;
2923         else if (val >= hdspm->texts_autosync_items)
2924                 val = hdspm->texts_autosync_items-1;
2925
2926         spin_lock_irq(&hdspm->lock);
2927         if (val != hdspm_pref_sync_ref(hdspm))
2928                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2929
2930         spin_unlock_irq(&hdspm->lock);
2931         return change;
2932 }
2933
2934
2935 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2936 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2937         .name = xname, \
2938         .index = xindex, \
2939         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2940         .info = snd_hdspm_info_autosync_ref, \
2941         .get = snd_hdspm_get_autosync_ref, \
2942 }
2943
2944 static int hdspm_autosync_ref(struct hdspm *hdspm)
2945 {
2946         /* This looks at the autosync selected sync reference */
2947         if (AES32 == hdspm->io_type) {
2948
2949                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2950                 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF;
2951                 if ((syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD) &&
2952                                 (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN)) {
2953                         return syncref;
2954                 }
2955                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2956
2957         } else if (MADI == hdspm->io_type) {
2958
2959                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2960                 switch (status2 & HDSPM_SelSyncRefMask) {
2961                 case HDSPM_SelSyncRef_WORD:
2962                         return HDSPM_AUTOSYNC_FROM_WORD;
2963                 case HDSPM_SelSyncRef_MADI:
2964                         return HDSPM_AUTOSYNC_FROM_MADI;
2965                 case HDSPM_SelSyncRef_TCO:
2966                         return HDSPM_AUTOSYNC_FROM_TCO;
2967                 case HDSPM_SelSyncRef_SyncIn:
2968                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2969                 case HDSPM_SelSyncRef_NVALID:
2970                         return HDSPM_AUTOSYNC_FROM_NONE;
2971                 default:
2972                         return HDSPM_AUTOSYNC_FROM_NONE;
2973                 }
2974
2975         }
2976         return 0;
2977 }
2978
2979
2980 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2981                                        struct snd_ctl_elem_info *uinfo)
2982 {
2983         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2984
2985         if (AES32 == hdspm->io_type) {
2986                 static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3",
2987                         "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"};
2988
2989                 ENUMERATED_CTL_INFO(uinfo, texts);
2990         } else if (MADI == hdspm->io_type) {
2991                 static const char *const texts[] = {"Word Clock", "MADI", "TCO",
2992                         "Sync In", "None" };
2993
2994                 ENUMERATED_CTL_INFO(uinfo, texts);
2995         }
2996         return 0;
2997 }
2998
2999 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
3000                                       struct snd_ctl_elem_value *ucontrol)
3001 {
3002         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3003
3004         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
3005         return 0;
3006 }
3007
3008
3009
3010 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
3011 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3012         .name = xname, \
3013         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3014                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3015         .info = snd_hdspm_info_tco_video_input_format, \
3016         .get = snd_hdspm_get_tco_video_input_format, \
3017 }
3018
3019 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
3020                                        struct snd_ctl_elem_info *uinfo)
3021 {
3022         static const char *const texts[] = {"No video", "NTSC", "PAL"};
3023         ENUMERATED_CTL_INFO(uinfo, texts);
3024         return 0;
3025 }
3026
3027 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
3028                                       struct snd_ctl_elem_value *ucontrol)
3029 {
3030         u32 status;
3031         int ret = 0;
3032
3033         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3034         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3035         switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
3036                         HDSPM_TCO1_Video_Input_Format_PAL)) {
3037         case HDSPM_TCO1_Video_Input_Format_NTSC:
3038                 /* ntsc */
3039                 ret = 1;
3040                 break;
3041         case HDSPM_TCO1_Video_Input_Format_PAL:
3042                 /* pal */
3043                 ret = 2;
3044                 break;
3045         default:
3046                 /* no video */
3047                 ret = 0;
3048                 break;
3049         }
3050         ucontrol->value.enumerated.item[0] = ret;
3051         return 0;
3052 }
3053
3054
3055
3056 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
3057 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3058         .name = xname, \
3059         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3060                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3061         .info = snd_hdspm_info_tco_ltc_frames, \
3062         .get = snd_hdspm_get_tco_ltc_frames, \
3063 }
3064
3065 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3066                                        struct snd_ctl_elem_info *uinfo)
3067 {
3068         static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3069                                 "30 fps"};
3070         ENUMERATED_CTL_INFO(uinfo, texts);
3071         return 0;
3072 }
3073
3074 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3075 {
3076         u32 status;
3077         int ret = 0;
3078
3079         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3080         if (status & HDSPM_TCO1_LTC_Input_valid) {
3081                 switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3082                                         HDSPM_TCO1_LTC_Format_MSB)) {
3083                 case 0:
3084                         /* 24 fps */
3085                         ret = 1;
3086                         break;
3087                 case HDSPM_TCO1_LTC_Format_LSB:
3088                         /* 25 fps */
3089                         ret = 2;
3090                         break;
3091                 case HDSPM_TCO1_LTC_Format_MSB:
3092                         /* 25 fps */
3093                         ret = 3;
3094                         break;
3095                 default:
3096                         /* 30 fps */
3097                         ret = 4;
3098                         break;
3099                 }
3100         }
3101
3102         return ret;
3103 }
3104
3105 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3106                                       struct snd_ctl_elem_value *ucontrol)
3107 {
3108         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3109
3110         ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3111         return 0;
3112 }
3113
3114 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3115 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3116         .name = xname, \
3117         .private_value = xindex, \
3118         .info = snd_hdspm_info_toggle_setting, \
3119         .get = snd_hdspm_get_toggle_setting, \
3120         .put = snd_hdspm_put_toggle_setting \
3121 }
3122
3123 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3124 {
3125         u32 reg;
3126
3127         if (hdspm_is_raydat_or_aio(hdspm))
3128                 reg = hdspm->settings_register;
3129         else
3130                 reg = hdspm->control_register;
3131
3132         return (reg & regmask) ? 1 : 0;
3133 }
3134
3135 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3136 {
3137         u32 *reg;
3138         u32 target_reg;
3139
3140         if (hdspm_is_raydat_or_aio(hdspm)) {
3141                 reg = &(hdspm->settings_register);
3142                 target_reg = HDSPM_WR_SETTINGS;
3143         } else {
3144                 reg = &(hdspm->control_register);
3145                 target_reg = HDSPM_controlRegister;
3146         }
3147
3148         if (out)
3149                 *reg |= regmask;
3150         else
3151                 *reg &= ~regmask;
3152
3153         hdspm_write(hdspm, target_reg, *reg);
3154
3155         return 0;
3156 }
3157
3158 #define snd_hdspm_info_toggle_setting           snd_ctl_boolean_mono_info
3159
3160 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3161                                struct snd_ctl_elem_value *ucontrol)
3162 {
3163         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3164         u32 regmask = kcontrol->private_value;
3165
3166         spin_lock_irq(&hdspm->lock);
3167         ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3168         spin_unlock_irq(&hdspm->lock);
3169         return 0;
3170 }
3171
3172 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3173                                struct snd_ctl_elem_value *ucontrol)
3174 {
3175         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3176         u32 regmask = kcontrol->private_value;
3177         int change;
3178         unsigned int val;
3179
3180         if (!snd_hdspm_use_is_exclusive(hdspm))
3181                 return -EBUSY;
3182         val = ucontrol->value.integer.value[0] & 1;
3183         spin_lock_irq(&hdspm->lock);
3184         change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3185         hdspm_set_toggle_setting(hdspm, regmask, val);
3186         spin_unlock_irq(&hdspm->lock);
3187         return change;
3188 }
3189
3190 #define HDSPM_INPUT_SELECT(xname, xindex) \
3191 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3192         .name = xname, \
3193         .index = xindex, \
3194         .info = snd_hdspm_info_input_select, \
3195         .get = snd_hdspm_get_input_select, \
3196         .put = snd_hdspm_put_input_select \
3197 }
3198
3199 static int hdspm_input_select(struct hdspm * hdspm)
3200 {
3201         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3202 }
3203
3204 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3205 {
3206         if (out)
3207                 hdspm->control_register |= HDSPM_InputSelect0;
3208         else
3209                 hdspm->control_register &= ~HDSPM_InputSelect0;
3210         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3211
3212         return 0;
3213 }
3214
3215 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3216                                        struct snd_ctl_elem_info *uinfo)
3217 {
3218         static const char *const texts[] = { "optical", "coaxial" };
3219         ENUMERATED_CTL_INFO(uinfo, texts);
3220         return 0;
3221 }
3222
3223 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3224                                       struct snd_ctl_elem_value *ucontrol)
3225 {
3226         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3227
3228         spin_lock_irq(&hdspm->lock);
3229         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3230         spin_unlock_irq(&hdspm->lock);
3231         return 0;
3232 }
3233
3234 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3235                                       struct snd_ctl_elem_value *ucontrol)
3236 {
3237         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3238         int change;
3239         unsigned int val;
3240
3241         if (!snd_hdspm_use_is_exclusive(hdspm))
3242                 return -EBUSY;
3243         val = ucontrol->value.integer.value[0] & 1;
3244         spin_lock_irq(&hdspm->lock);
3245         change = (int) val != hdspm_input_select(hdspm);
3246         hdspm_set_input_select(hdspm, val);
3247         spin_unlock_irq(&hdspm->lock);
3248         return change;
3249 }
3250
3251
3252 #define HDSPM_DS_WIRE(xname, xindex) \
3253 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3254         .name = xname, \
3255         .index = xindex, \
3256         .info = snd_hdspm_info_ds_wire, \
3257         .get = snd_hdspm_get_ds_wire, \
3258         .put = snd_hdspm_put_ds_wire \
3259 }
3260
3261 static int hdspm_ds_wire(struct hdspm * hdspm)
3262 {
3263         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3264 }
3265
3266 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3267 {
3268         if (ds)
3269                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3270         else
3271                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3272         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3273
3274         return 0;
3275 }
3276
3277 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3278                                   struct snd_ctl_elem_info *uinfo)
3279 {
3280         static const char *const texts[] = { "Single", "Double" };
3281         ENUMERATED_CTL_INFO(uinfo, texts);
3282         return 0;
3283 }
3284
3285 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3286                                  struct snd_ctl_elem_value *ucontrol)
3287 {
3288         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3289
3290         spin_lock_irq(&hdspm->lock);
3291         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3292         spin_unlock_irq(&hdspm->lock);
3293         return 0;
3294 }
3295
3296 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3297                                  struct snd_ctl_elem_value *ucontrol)
3298 {
3299         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3300         int change;
3301         unsigned int val;
3302
3303         if (!snd_hdspm_use_is_exclusive(hdspm))
3304                 return -EBUSY;
3305         val = ucontrol->value.integer.value[0] & 1;
3306         spin_lock_irq(&hdspm->lock);
3307         change = (int) val != hdspm_ds_wire(hdspm);
3308         hdspm_set_ds_wire(hdspm, val);
3309         spin_unlock_irq(&hdspm->lock);
3310         return change;
3311 }
3312
3313
3314 #define HDSPM_QS_WIRE(xname, xindex) \
3315 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3316         .name = xname, \
3317         .index = xindex, \
3318         .info = snd_hdspm_info_qs_wire, \
3319         .get = snd_hdspm_get_qs_wire, \
3320         .put = snd_hdspm_put_qs_wire \
3321 }
3322
3323 static int hdspm_qs_wire(struct hdspm * hdspm)
3324 {
3325         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3326                 return 1;
3327         if (hdspm->control_register & HDSPM_QS_QuadWire)
3328                 return 2;
3329         return 0;
3330 }
3331
3332 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3333 {
3334         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3335         switch (mode) {
3336         case 0:
3337                 break;
3338         case 1:
3339                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3340                 break;
3341         case 2:
3342                 hdspm->control_register |= HDSPM_QS_QuadWire;
3343                 break;
3344         }
3345         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3346
3347         return 0;
3348 }
3349
3350 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3351                                        struct snd_ctl_elem_info *uinfo)
3352 {
3353         static const char *const texts[] = { "Single", "Double", "Quad" };
3354         ENUMERATED_CTL_INFO(uinfo, texts);
3355         return 0;
3356 }
3357
3358 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3359                                       struct snd_ctl_elem_value *ucontrol)
3360 {
3361         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3362
3363         spin_lock_irq(&hdspm->lock);
3364         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3365         spin_unlock_irq(&hdspm->lock);
3366         return 0;
3367 }
3368
3369 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3370                                       struct snd_ctl_elem_value *ucontrol)
3371 {
3372         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3373         int change;
3374         int val;
3375
3376         if (!snd_hdspm_use_is_exclusive(hdspm))
3377                 return -EBUSY;
3378         val = ucontrol->value.integer.value[0];
3379         if (val < 0)
3380                 val = 0;
3381         if (val > 2)
3382                 val = 2;
3383         spin_lock_irq(&hdspm->lock);
3384         change = val != hdspm_qs_wire(hdspm);
3385         hdspm_set_qs_wire(hdspm, val);
3386         spin_unlock_irq(&hdspm->lock);
3387         return change;
3388 }
3389
3390 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \
3391 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3392         .name = xname, \
3393         .private_value = xindex, \
3394         .info = snd_hdspm_info_tristate, \
3395         .get = snd_hdspm_get_tristate, \
3396         .put = snd_hdspm_put_tristate \
3397 }
3398
3399 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3400 {
3401         u32 reg = hdspm->settings_register & (regmask * 3);
3402         return reg / regmask;
3403 }
3404
3405 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3406 {
3407         hdspm->settings_register &= ~(regmask * 3);
3408         hdspm->settings_register |= (regmask * mode);
3409         hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3410
3411         return 0;
3412 }
3413
3414 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol,
3415                                        struct snd_ctl_elem_info *uinfo)
3416 {
3417         u32 regmask = kcontrol->private_value;
3418
3419         static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" };
3420         static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
3421
3422         switch (regmask) {
3423         case HDSPM_c0_Input0:
3424                 ENUMERATED_CTL_INFO(uinfo, texts_spdif);
3425                 break;
3426         default:
3427                 ENUMERATED_CTL_INFO(uinfo, texts_levels);
3428                 break;
3429         }
3430         return 0;
3431 }
3432
3433 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol,
3434                                       struct snd_ctl_elem_value *ucontrol)
3435 {
3436         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3437         u32 regmask = kcontrol->private_value;
3438
3439         spin_lock_irq(&hdspm->lock);
3440         ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3441         spin_unlock_irq(&hdspm->lock);
3442         return 0;
3443 }
3444
3445 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol,
3446                                       struct snd_ctl_elem_value *ucontrol)
3447 {
3448         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3449         u32 regmask = kcontrol->private_value;
3450         int change;
3451         int val;
3452
3453         if (!snd_hdspm_use_is_exclusive(hdspm))
3454                 return -EBUSY;
3455         val = ucontrol->value.integer.value[0];
3456         if (val < 0)
3457                 val = 0;
3458         if (val > 2)
3459                 val = 2;
3460
3461         spin_lock_irq(&hdspm->lock);
3462         change = val != hdspm_tristate(hdspm, regmask);
3463         hdspm_set_tristate(hdspm, val, regmask);
3464         spin_unlock_irq(&hdspm->lock);
3465         return change;
3466 }
3467
3468 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3469 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3470         .name = xname, \
3471         .index = xindex, \
3472         .info = snd_hdspm_info_madi_speedmode, \
3473         .get = snd_hdspm_get_madi_speedmode, \
3474         .put = snd_hdspm_put_madi_speedmode \
3475 }
3476
3477 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3478 {
3479         if (hdspm->control_register & HDSPM_QuadSpeed)
3480                 return 2;
3481         if (hdspm->control_register & HDSPM_DoubleSpeed)
3482                 return 1;
3483         return 0;
3484 }
3485
3486 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3487 {
3488         hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3489         switch (mode) {
3490         case 0:
3491                 break;
3492         case 1:
3493                 hdspm->control_register |= HDSPM_DoubleSpeed;
3494                 break;
3495         case 2:
3496                 hdspm->control_register |= HDSPM_QuadSpeed;
3497                 break;
3498         }
3499         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3500
3501         return 0;
3502 }
3503
3504 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3505                                        struct snd_ctl_elem_info *uinfo)
3506 {
3507         static const char *const texts[] = { "Single", "Double", "Quad" };
3508         ENUMERATED_CTL_INFO(uinfo, texts);
3509         return 0;
3510 }
3511
3512 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3513                                       struct snd_ctl_elem_value *ucontrol)
3514 {
3515         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3516
3517         spin_lock_irq(&hdspm->lock);
3518         ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3519         spin_unlock_irq(&hdspm->lock);
3520         return 0;
3521 }
3522
3523 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3524                                       struct snd_ctl_elem_value *ucontrol)
3525 {
3526         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3527         int change;
3528         int val;
3529
3530         if (!snd_hdspm_use_is_exclusive(hdspm))
3531                 return -EBUSY;
3532         val = ucontrol->value.integer.value[0];
3533         if (val < 0)
3534                 val = 0;
3535         if (val > 2)
3536                 val = 2;
3537         spin_lock_irq(&hdspm->lock);
3538         change = val != hdspm_madi_speedmode(hdspm);
3539         hdspm_set_madi_speedmode(hdspm, val);
3540         spin_unlock_irq(&hdspm->lock);
3541         return change;
3542 }
3543
3544 #define HDSPM_MIXER(xname, xindex) \
3545 {       .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3546         .name = xname, \
3547         .index = xindex, \
3548         .device = 0, \
3549         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3550                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3551         .info = snd_hdspm_info_mixer, \
3552         .get = snd_hdspm_get_mixer, \
3553         .put = snd_hdspm_put_mixer \
3554 }
3555
3556 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3557                                 struct snd_ctl_elem_info *uinfo)
3558 {
3559         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3560         uinfo->count = 3;
3561         uinfo->value.integer.min = 0;
3562         uinfo->value.integer.max = 65535;
3563         uinfo->value.integer.step = 1;
3564         return 0;
3565 }
3566
3567 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3568                                struct snd_ctl_elem_value *ucontrol)
3569 {
3570         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3571         int source;
3572         int destination;
3573
3574         source = ucontrol->value.integer.value[0];
3575         if (source < 0)
3576                 source = 0;
3577         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3578                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3579
3580         destination = ucontrol->value.integer.value[1];
3581         if (destination < 0)
3582                 destination = 0;
3583         else if (destination >= HDSPM_MAX_CHANNELS)
3584                 destination = HDSPM_MAX_CHANNELS - 1;
3585
3586         spin_lock_irq(&hdspm->lock);
3587         if (source >= HDSPM_MAX_CHANNELS)
3588                 ucontrol->value.integer.value[2] =
3589                     hdspm_read_pb_gain(hdspm, destination,
3590                                        source - HDSPM_MAX_CHANNELS);
3591         else
3592                 ucontrol->value.integer.value[2] =
3593                     hdspm_read_in_gain(hdspm, destination, source);
3594
3595         spin_unlock_irq(&hdspm->lock);
3596
3597         return 0;
3598 }
3599
3600 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3601                                struct snd_ctl_elem_value *ucontrol)
3602 {
3603         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3604         int change;
3605         int source;
3606         int destination;
3607         int gain;
3608
3609         if (!snd_hdspm_use_is_exclusive(hdspm))
3610                 return -EBUSY;
3611
3612         source = ucontrol->value.integer.value[0];
3613         destination = ucontrol->value.integer.value[1];
3614
3615         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3616                 return -1;
3617         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3618                 return -1;
3619
3620         gain = ucontrol->value.integer.value[2];
3621
3622         spin_lock_irq(&hdspm->lock);
3623
3624         if (source >= HDSPM_MAX_CHANNELS)
3625                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3626                                                     source -
3627                                                     HDSPM_MAX_CHANNELS);
3628         else
3629                 change = gain != hdspm_read_in_gain(hdspm, destination,
3630                                                     source);
3631
3632         if (change) {
3633                 if (source >= HDSPM_MAX_CHANNELS)
3634                         hdspm_write_pb_gain(hdspm, destination,
3635                                             source - HDSPM_MAX_CHANNELS,
3636                                             gain);
3637                 else
3638                         hdspm_write_in_gain(hdspm, destination, source,
3639                                             gain);
3640         }
3641         spin_unlock_irq(&hdspm->lock);
3642
3643         return change;
3644 }
3645
3646 /* The simple mixer control(s) provide gain control for the
3647    basic 1:1 mappings of playback streams to output
3648    streams.
3649 */
3650
3651 #define HDSPM_PLAYBACK_MIXER \
3652 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3653         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3654                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3655         .info = snd_hdspm_info_playback_mixer, \
3656         .get = snd_hdspm_get_playback_mixer, \
3657         .put = snd_hdspm_put_playback_mixer \
3658 }
3659
3660 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3661                                          struct snd_ctl_elem_info *uinfo)
3662 {
3663         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3664         uinfo->count = 1;
3665         uinfo->value.integer.min = 0;
3666         uinfo->value.integer.max = 64;
3667         uinfo->value.integer.step = 1;
3668         return 0;
3669 }
3670
3671 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3672                                         struct snd_ctl_elem_value *ucontrol)
3673 {
3674         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3675         int channel;
3676
3677         channel = ucontrol->id.index - 1;
3678
3679         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3680                 return -EINVAL;
3681
3682         spin_lock_irq(&hdspm->lock);
3683         ucontrol->value.integer.value[0] =
3684           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3685         spin_unlock_irq(&hdspm->lock);
3686
3687         return 0;
3688 }
3689
3690 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3691                                         struct snd_ctl_elem_value *ucontrol)
3692 {
3693         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3694         int change;
3695         int channel;
3696         int gain;
3697
3698         if (!snd_hdspm_use_is_exclusive(hdspm))
3699                 return -EBUSY;
3700
3701         channel = ucontrol->id.index - 1;
3702
3703         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3704                 return -EINVAL;
3705
3706         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3707
3708         spin_lock_irq(&hdspm->lock);
3709         change =
3710             gain != hdspm_read_pb_gain(hdspm, channel,
3711                                        channel);
3712         if (change)
3713                 hdspm_write_pb_gain(hdspm, channel, channel,
3714                                     gain);
3715         spin_unlock_irq(&hdspm->lock);
3716         return change;
3717 }
3718
3719 #define HDSPM_SYNC_CHECK(xname, xindex) \
3720 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3721         .name = xname, \
3722         .private_value = xindex, \
3723         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3724         .info = snd_hdspm_info_sync_check, \
3725         .get = snd_hdspm_get_sync_check \
3726 }
3727
3728 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3729 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3730         .name = xname, \
3731         .private_value = xindex, \
3732         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3733         .info = snd_hdspm_tco_info_lock_check, \
3734         .get = snd_hdspm_get_sync_check \
3735 }
3736
3737
3738
3739 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3740                                      struct snd_ctl_elem_info *uinfo)
3741 {
3742         static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3743         ENUMERATED_CTL_INFO(uinfo, texts);
3744         return 0;
3745 }
3746
3747 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3748                                      struct snd_ctl_elem_info *uinfo)
3749 {
3750         static const char *const texts[] = { "No Lock", "Lock" };
3751         ENUMERATED_CTL_INFO(uinfo, texts);
3752         return 0;
3753 }
3754
3755 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3756 {
3757         int status, status2;
3758
3759         switch (hdspm->io_type) {
3760         case AES32:
3761                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3762                 if (status & HDSPM_AES32_wcLock) {
3763                         if (status & HDSPM_AES32_wcSync)
3764                                 return 2;
3765                         else
3766                                 return 1;
3767                 }
3768                 return 0;
3769                 break;
3770
3771         case MADI:
3772                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3773                 if (status2 & HDSPM_wcLock) {
3774                         if (status2 & HDSPM_wcSync)
3775                                 return 2;
3776                         else
3777                                 return 1;
3778                 }
3779                 return 0;
3780                 break;
3781
3782         case RayDAT:
3783         case AIO:
3784                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3785
3786                 if (status & 0x2000000)
3787                         return 2;
3788                 else if (status & 0x1000000)
3789                         return 1;
3790                 return 0;
3791
3792                 break;
3793
3794         case MADIface:
3795                 break;
3796         }
3797
3798
3799         return 3;
3800 }
3801
3802
3803 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3804 {
3805         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3806         if (status & HDSPM_madiLock) {
3807                 if (status & HDSPM_madiSync)
3808                         return 2;
3809                 else
3810                         return 1;
3811         }
3812         return 0;
3813 }
3814
3815
3816 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3817 {
3818         int status, lock, sync;
3819
3820         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3821
3822         lock = (status & (0x1<<idx)) ? 1 : 0;
3823         sync = (status & (0x100<<idx)) ? 1 : 0;
3824
3825         if (lock && sync)
3826                 return 2;
3827         else if (lock)
3828                 return 1;
3829         return 0;
3830 }
3831
3832
3833 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3834 {
3835         int status, lock = 0, sync = 0;
3836
3837         switch (hdspm->io_type) {
3838         case RayDAT:
3839         case AIO:
3840                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3841                 lock = (status & 0x400) ? 1 : 0;
3842                 sync = (status & 0x800) ? 1 : 0;
3843                 break;
3844
3845         case MADI:
3846                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3847                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3848                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3849                 break;
3850
3851         case AES32:
3852                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3853                 lock = (status & 0x100000) ? 1 : 0;
3854                 sync = (status & 0x200000) ? 1 : 0;
3855                 break;
3856
3857         case MADIface:
3858                 break;
3859         }
3860
3861         if (lock && sync)
3862                 return 2;
3863         else if (lock)
3864                 return 1;
3865
3866         return 0;
3867 }
3868
3869 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3870 {
3871         int status2, lock, sync;
3872         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3873
3874         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3875         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3876
3877         if (sync)
3878                 return 2;
3879         else if (lock)
3880                 return 1;
3881         return 0;
3882 }
3883
3884 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3885 {
3886         u32 status;
3887         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3888
3889         return (status & mask) ? 1 : 0;
3890 }
3891
3892
3893 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3894 {
3895         int status;
3896
3897         if (hdspm->tco) {
3898                 switch (hdspm->io_type) {
3899                 case MADI:
3900                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3901                         if (status & HDSPM_tcoLockMadi) {
3902                                 if (status & HDSPM_tcoSync)
3903                                         return 2;
3904                                 else
3905                                         return 1;
3906                         }
3907                         return 0;
3908                         break;
3909                 case AES32:
3910                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3911                         if (status & HDSPM_tcoLockAes) {
3912                                 if (status & HDSPM_tcoSync)
3913                                         return 2;
3914                                 else
3915                                         return 1;
3916                         }
3917                         return 0;
3918
3919                         break;
3920
3921                 case RayDAT:
3922                 case AIO:
3923                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3924
3925                         if (status & 0x8000000)
3926                                 return 2; /* Sync */
3927                         if (status & 0x4000000)
3928                                 return 1; /* Lock */
3929                         return 0; /* No signal */
3930                         break;
3931
3932                 default:
3933                         break;
3934                 }
3935         }
3936
3937         return 3; /* N/A */
3938 }
3939
3940
3941 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3942                                     struct snd_ctl_elem_value *ucontrol)
3943 {
3944         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3945         int val = -1;
3946
3947         switch (hdspm->io_type) {
3948         case RayDAT:
3949                 switch (kcontrol->private_value) {
3950                 case 0: /* WC */
3951                         val = hdspm_wc_sync_check(hdspm); break;
3952                 case 7: /* TCO */
3953                         val = hdspm_tco_sync_check(hdspm); break;
3954                 case 8: /* SYNC IN */
3955                         val = hdspm_sync_in_sync_check(hdspm); break;
3956                 default:
3957                         val = hdspm_s1_sync_check(hdspm,
3958                                         kcontrol->private_value-1);
3959                 }
3960                 break;
3961
3962         case AIO:
3963                 switch (kcontrol->private_value) {
3964                 case 0: /* WC */
3965                         val = hdspm_wc_sync_check(hdspm); break;
3966                 case 4: /* TCO */
3967                         val = hdspm_tco_sync_check(hdspm); break;
3968                 case 5: /* SYNC IN */
3969                         val = hdspm_sync_in_sync_check(hdspm); break;
3970                 default:
3971                         val = hdspm_s1_sync_check(hdspm,
3972                                         kcontrol->private_value-1);
3973                 }
3974                 break;
3975
3976         case MADI:
3977                 switch (kcontrol->private_value) {
3978                 case 0: /* WC */
3979                         val = hdspm_wc_sync_check(hdspm); break;
3980                 case 1: /* MADI */
3981                         val = hdspm_madi_sync_check(hdspm); break;
3982                 case 2: /* TCO */
3983                         val = hdspm_tco_sync_check(hdspm); break;
3984                 case 3: /* SYNC_IN */
3985                         val = hdspm_sync_in_sync_check(hdspm); break;
3986                 }
3987                 break;
3988
3989         case MADIface:
3990                 val = hdspm_madi_sync_check(hdspm); /* MADI */
3991                 break;
3992
3993         case AES32:
3994                 switch (kcontrol->private_value) {
3995                 case 0: /* WC */
3996                         val = hdspm_wc_sync_check(hdspm); break;
3997                 case 9: /* TCO */
3998                         val = hdspm_tco_sync_check(hdspm); break;
3999                 case 10 /* SYNC IN */:
4000                         val = hdspm_sync_in_sync_check(hdspm); break;
4001                 default: /* AES1 to AES8 */
4002                          val = hdspm_aes_sync_check(hdspm,
4003                                          kcontrol->private_value-1);
4004                 }
4005                 break;
4006
4007         }
4008
4009         if (hdspm->tco) {
4010                 switch (kcontrol->private_value) {
4011                 case 11:
4012                         /* Check TCO for lock state of its current input */
4013                         val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
4014                         break;
4015                 case 12:
4016                         /* Check TCO for valid time code on LTC input. */
4017                         val = hdspm_tco_input_check(hdspm,
4018                                 HDSPM_TCO1_LTC_Input_valid);
4019                         break;
4020                 default:
4021                         break;
4022                 }
4023         }
4024
4025         if (-1 == val)
4026                 val = 3;
4027
4028         ucontrol->value.enumerated.item[0] = val;
4029         return 0;
4030 }
4031
4032
4033
4034 /**
4035  * TCO controls
4036  **/
4037 static void hdspm_tco_write(struct hdspm *hdspm)
4038 {
4039         unsigned int tc[4] = { 0, 0, 0, 0};
4040
4041         switch (hdspm->tco->input) {
4042         case 0:
4043                 tc[2] |= HDSPM_TCO2_set_input_MSB;
4044                 break;
4045         case 1:
4046                 tc[2] |= HDSPM_TCO2_set_input_LSB;
4047                 break;
4048         default:
4049                 break;
4050         }
4051
4052         switch (hdspm->tco->framerate) {
4053         case 1:
4054                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4055                 break;
4056         case 2:
4057                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4058                 break;
4059         case 3:
4060                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4061                         HDSPM_TCO1_set_drop_frame_flag;
4062                 break;
4063         case 4:
4064                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4065                         HDSPM_TCO1_LTC_Format_MSB;
4066                 break;
4067         case 5:
4068                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4069                         HDSPM_TCO1_LTC_Format_MSB +
4070                         HDSPM_TCO1_set_drop_frame_flag;
4071                 break;
4072         default:
4073                 break;
4074         }
4075
4076         switch (hdspm->tco->wordclock) {
4077         case 1:
4078                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4079                 break;
4080         case 2:
4081                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4082                 break;
4083         default:
4084                 break;
4085         }
4086
4087         switch (hdspm->tco->samplerate) {
4088         case 1:
4089                 tc[2] |= HDSPM_TCO2_set_freq;
4090                 break;
4091         case 2:
4092                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4093                 break;
4094         default:
4095                 break;
4096         }
4097
4098         switch (hdspm->tco->pull) {
4099         case 1:
4100                 tc[2] |= HDSPM_TCO2_set_pull_up;
4101                 break;
4102         case 2:
4103                 tc[2] |= HDSPM_TCO2_set_pull_down;
4104                 break;
4105         case 3:
4106                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4107                 break;
4108         case 4:
4109                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4110                 break;
4111         default:
4112                 break;
4113         }
4114
4115         if (1 == hdspm->tco->term) {
4116                 tc[2] |= HDSPM_TCO2_set_term_75R;
4117         }
4118
4119         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4120         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4121         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4122         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4123 }
4124
4125
4126 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4127 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4128         .name = xname, \
4129         .index = xindex, \
4130         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4131                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4132         .info = snd_hdspm_info_tco_sample_rate, \
4133         .get = snd_hdspm_get_tco_sample_rate, \
4134         .put = snd_hdspm_put_tco_sample_rate \
4135 }
4136
4137 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4138                                           struct snd_ctl_elem_info *uinfo)
4139 {
4140         static const char *const texts[] = { "44.1 kHz", "48 kHz" };
4141         ENUMERATED_CTL_INFO(uinfo, texts);
4142         return 0;
4143 }
4144
4145 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4146                                       struct snd_ctl_elem_value *ucontrol)
4147 {
4148         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4149
4150         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4151
4152         return 0;
4153 }
4154
4155 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4156                                          struct snd_ctl_elem_value *ucontrol)
4157 {
4158         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4159
4160         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4161                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4162
4163                 hdspm_tco_write(hdspm);
4164
4165                 return 1;
4166         }
4167
4168         return 0;
4169 }
4170
4171
4172 #define HDSPM_TCO_PULL(xname, xindex) \
4173 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4174         .name = xname, \
4175         .index = xindex, \
4176         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4177                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4178         .info = snd_hdspm_info_tco_pull, \
4179         .get = snd_hdspm_get_tco_pull, \
4180         .put = snd_hdspm_put_tco_pull \
4181 }
4182
4183 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4184                                    struct snd_ctl_elem_info *uinfo)
4185 {
4186         static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %",
4187                 "+ 4 %", "- 4 %" };
4188         ENUMERATED_CTL_INFO(uinfo, texts);
4189         return 0;
4190 }
4191
4192 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4193                                   struct snd_ctl_elem_value *ucontrol)
4194 {
4195         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4196
4197         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4198
4199         return 0;
4200 }
4201
4202 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4203                                   struct snd_ctl_elem_value *ucontrol)
4204 {
4205         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4206
4207         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4208                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4209
4210                 hdspm_tco_write(hdspm);
4211
4212                 return 1;
4213         }
4214
4215         return 0;
4216 }
4217
4218 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4219 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4220         .name = xname, \
4221         .index = xindex, \
4222         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4223                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4224         .info = snd_hdspm_info_tco_wck_conversion, \
4225         .get = snd_hdspm_get_tco_wck_conversion, \
4226         .put = snd_hdspm_put_tco_wck_conversion \
4227 }
4228
4229 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4230                                              struct snd_ctl_elem_info *uinfo)
4231 {
4232         static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4233         ENUMERATED_CTL_INFO(uinfo, texts);
4234         return 0;
4235 }
4236
4237 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4238                                             struct snd_ctl_elem_value *ucontrol)
4239 {
4240         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4241
4242         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4243
4244         return 0;
4245 }
4246
4247 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4248                                             struct snd_ctl_elem_value *ucontrol)
4249 {
4250         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4251
4252         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4253                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4254
4255                 hdspm_tco_write(hdspm);
4256
4257                 return 1;
4258         }
4259
4260         return 0;
4261 }
4262
4263
4264 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4265 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4266         .name = xname, \
4267         .index = xindex, \
4268         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4269                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4270         .info = snd_hdspm_info_tco_frame_rate, \
4271         .get = snd_hdspm_get_tco_frame_rate, \
4272         .put = snd_hdspm_put_tco_frame_rate \
4273 }
4274
4275 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4276                                           struct snd_ctl_elem_info *uinfo)
4277 {
4278         static const char *const texts[] = { "24 fps", "25 fps", "29.97fps",
4279                 "29.97 dfps", "30 fps", "30 dfps" };
4280         ENUMERATED_CTL_INFO(uinfo, texts);
4281         return 0;
4282 }
4283
4284 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4285                                         struct snd_ctl_elem_value *ucontrol)
4286 {
4287         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4288
4289         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4290
4291         return 0;
4292 }
4293
4294 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4295                                         struct snd_ctl_elem_value *ucontrol)
4296 {
4297         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4298
4299         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4300                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4301
4302                 hdspm_tco_write(hdspm);
4303
4304                 return 1;
4305         }
4306
4307         return 0;
4308 }
4309
4310
4311 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4312 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4313         .name = xname, \
4314         .index = xindex, \
4315         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4316                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4317         .info = snd_hdspm_info_tco_sync_source, \
4318         .get = snd_hdspm_get_tco_sync_source, \
4319         .put = snd_hdspm_put_tco_sync_source \
4320 }
4321
4322 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4323                                           struct snd_ctl_elem_info *uinfo)
4324 {
4325         static const char *const texts[] = { "LTC", "Video", "WCK" };
4326         ENUMERATED_CTL_INFO(uinfo, texts);
4327         return 0;
4328 }
4329
4330 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4331                                          struct snd_ctl_elem_value *ucontrol)
4332 {
4333         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4334
4335         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4336
4337         return 0;
4338 }
4339
4340 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4341                                          struct snd_ctl_elem_value *ucontrol)
4342 {
4343         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4344
4345         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4346                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4347
4348                 hdspm_tco_write(hdspm);
4349
4350                 return 1;
4351         }
4352
4353         return 0;
4354 }
4355
4356
4357 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4358 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4359         .name = xname, \
4360         .index = xindex, \
4361         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4362                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4363         .info = snd_hdspm_info_tco_word_term, \
4364         .get = snd_hdspm_get_tco_word_term, \
4365         .put = snd_hdspm_put_tco_word_term \
4366 }
4367
4368 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4369                                         struct snd_ctl_elem_info *uinfo)
4370 {
4371         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4372         uinfo->count = 1;
4373         uinfo->value.integer.min = 0;
4374         uinfo->value.integer.max = 1;
4375
4376         return 0;
4377 }
4378
4379
4380 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4381                                        struct snd_ctl_elem_value *ucontrol)
4382 {
4383         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4384
4385         ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4386
4387         return 0;
4388 }
4389
4390
4391 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4392                                        struct snd_ctl_elem_value *ucontrol)
4393 {
4394         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4395
4396         if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4397                 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4398
4399                 hdspm_tco_write(hdspm);
4400
4401                 return 1;
4402         }
4403
4404         return 0;
4405 }
4406
4407
4408
4409
4410 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4411         HDSPM_MIXER("Mixer", 0),
4412         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4413         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4414         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4415         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4416         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4417         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4418         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4419         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4420         HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4421         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4422         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4423         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4424         HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4425         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4426         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4427         HDSPM_INPUT_SELECT("Input Select", 0),
4428         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4429 };
4430
4431
4432 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4433         HDSPM_MIXER("Mixer", 0),
4434         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4435         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4436         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4437         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4438         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4439         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4440         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4441         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4442         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4443 };
4444
4445 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4446         HDSPM_MIXER("Mixer", 0),
4447         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4448         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4449         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4450         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4451         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4452         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4453         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4454         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4455         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4456         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4457         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4458         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4459         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4460         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4461         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4462         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4463         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
4464         HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0),
4465         HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt),
4466         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4467         HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1),
4468         HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db),
4469         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48),
4470         HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0),
4471         HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0),
4472         HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0)
4473
4474                 /*
4475                    HDSPM_INPUT_SELECT("Input Select", 0),
4476                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4477                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4478                    HDSPM_SPDIF_IN("SPDIF In", 0);
4479                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4480                    HDSPM_INPUT_LEVEL("Input Level", 0);
4481                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4482                    HDSPM_PHONES("Phones", 0);
4483                    */
4484 };
4485
4486 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4487         HDSPM_MIXER("Mixer", 0),
4488         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4489         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4490         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4491         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4492         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4493         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4494         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4495         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4496         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4497         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4498         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4499         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4500         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4501         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4502         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4503         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4504         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4505         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4506         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4507         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4508         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4509         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4510         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4511         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
4512 };
4513
4514 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4515         HDSPM_MIXER("Mixer", 0),
4516         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4517         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4518         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4519         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4520         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4521         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11),
4522         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4523         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4524         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4525         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4526         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4527         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4528         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4529         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4530         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4531         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4532         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4533         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4534         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4535         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4536         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4537         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4538         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4539         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4540         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4541         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4542         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4543         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4544         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4545         HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4546         HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4547         HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4548         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4549         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4550         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4551 };
4552
4553
4554
4555 /* Control elements for the optional TCO module */
4556 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4557         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4558         HDSPM_TCO_PULL("TCO Pull", 0),
4559         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4560         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4561         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4562         HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4563         HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4564         HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4565         HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4566         HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4567 };
4568
4569
4570 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4571
4572
4573 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4574 {
4575         int i;
4576
4577         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4578                 if (hdspm->system_sample_rate > 48000) {
4579                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4580                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4581                                 SNDRV_CTL_ELEM_ACCESS_READ |
4582                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4583                 } else {
4584                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4585                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4586                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4587                 }
4588                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4589                                 SNDRV_CTL_EVENT_MASK_INFO,
4590                                 &hdspm->playback_mixer_ctls[i]->id);
4591         }
4592
4593         return 0;
4594 }
4595
4596
4597 static int snd_hdspm_create_controls(struct snd_card *card,
4598                                         struct hdspm *hdspm)
4599 {
4600         unsigned int idx, limit;
4601         int err;
4602         struct snd_kcontrol *kctl;
4603         struct snd_kcontrol_new *list = NULL;
4604
4605         switch (hdspm->io_type) {
4606         case MADI:
4607                 list = snd_hdspm_controls_madi;
4608                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4609                 break;
4610         case MADIface:
4611                 list = snd_hdspm_controls_madiface;
4612                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4613                 break;
4614         case AIO:
4615                 list = snd_hdspm_controls_aio;
4616                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4617                 break;
4618         case RayDAT:
4619                 list = snd_hdspm_controls_raydat;
4620                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4621                 break;
4622         case AES32:
4623                 list = snd_hdspm_controls_aes32;
4624                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4625                 break;
4626         }
4627
4628         if (NULL != list) {
4629                 for (idx = 0; idx < limit; idx++) {
4630                         err = snd_ctl_add(card,
4631                                         snd_ctl_new1(&list[idx], hdspm));
4632                         if (err < 0)
4633                                 return err;
4634                 }
4635         }
4636
4637
4638         /* create simple 1:1 playback mixer controls */
4639         snd_hdspm_playback_mixer.name = "Chn";
4640         if (hdspm->system_sample_rate >= 128000) {
4641                 limit = hdspm->qs_out_channels;
4642         } else if (hdspm->system_sample_rate >= 64000) {
4643                 limit = hdspm->ds_out_channels;
4644         } else {
4645                 limit = hdspm->ss_out_channels;
4646         }
4647         for (idx = 0; idx < limit; ++idx) {
4648                 snd_hdspm_playback_mixer.index = idx + 1;
4649                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4650                 err = snd_ctl_add(card, kctl);
4651                 if (err < 0)
4652                         return err;
4653                 hdspm->playback_mixer_ctls[idx] = kctl;
4654         }
4655
4656
4657         if (hdspm->tco) {
4658                 /* add tco control elements */
4659                 list = snd_hdspm_controls_tco;
4660                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4661                 for (idx = 0; idx < limit; idx++) {
4662                         err = snd_ctl_add(card,
4663                                         snd_ctl_new1(&list[idx], hdspm));
4664                         if (err < 0)
4665                                 return err;
4666                 }
4667         }
4668
4669         return 0;
4670 }
4671
4672 /*------------------------------------------------------------
4673    /proc interface
4674  ------------------------------------------------------------*/
4675
4676 static void
4677 snd_hdspm_proc_read_tco(struct snd_info_entry *entry,
4678                                         struct snd_info_buffer *buffer)
4679 {
4680         struct hdspm *hdspm = entry->private_data;
4681         unsigned int status, control;
4682         int a, ltc, frames, seconds, minutes, hours;
4683         unsigned int period;
4684         u64 freq_const = 0;
4685         u32 rate;
4686
4687         snd_iprintf(buffer, "--- TCO ---\n");
4688
4689         status = hdspm_read(hdspm, HDSPM_statusRegister);
4690         control = hdspm->control_register;
4691
4692
4693         if (status & HDSPM_tco_detect) {
4694                 snd_iprintf(buffer, "TCO module detected.\n");
4695                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4696                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4697                         snd_iprintf(buffer, "  LTC valid, ");
4698                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4699                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4700                         case 0:
4701                                 snd_iprintf(buffer, "24 fps, ");
4702                                 break;
4703                         case HDSPM_TCO1_LTC_Format_LSB:
4704                                 snd_iprintf(buffer, "25 fps, ");
4705                                 break;
4706                         case HDSPM_TCO1_LTC_Format_MSB:
4707                                 snd_iprintf(buffer, "29.97 fps, ");
4708                                 break;
4709                         default:
4710                                 snd_iprintf(buffer, "30 fps, ");
4711                                 break;
4712                         }
4713                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4714                                 snd_iprintf(buffer, "drop frame\n");
4715                         } else {
4716                                 snd_iprintf(buffer, "full frame\n");
4717                         }
4718                 } else {
4719                         snd_iprintf(buffer, "  no LTC\n");
4720                 }
4721                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4722                         snd_iprintf(buffer, "  Video: NTSC\n");
4723                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4724                         snd_iprintf(buffer, "  Video: PAL\n");
4725                 } else {
4726                         snd_iprintf(buffer, "  No video\n");
4727                 }
4728                 if (a & HDSPM_TCO1_TCO_lock) {
4729                         snd_iprintf(buffer, "  Sync: lock\n");
4730                 } else {
4731                         snd_iprintf(buffer, "  Sync: no lock\n");
4732                 }
4733
4734                 switch (hdspm->io_type) {
4735                 case MADI:
4736                 case AES32:
4737                         freq_const = 110069313433624ULL;
4738                         break;
4739                 case RayDAT:
4740                 case AIO:
4741                         freq_const = 104857600000000ULL;
4742                         break;
4743                 case MADIface:
4744                         break; /* no TCO possible */
4745                 }
4746
4747                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4748                 snd_iprintf(buffer, "    period: %u\n", period);
4749
4750
4751                 /* rate = freq_const/period; */
4752                 rate = div_u64(freq_const, period);
4753
4754                 if (control & HDSPM_QuadSpeed) {
4755                         rate *= 4;
4756                 } else if (control & HDSPM_DoubleSpeed) {
4757                         rate *= 2;
4758                 }
4759
4760                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4761                                 (unsigned int) rate);
4762
4763                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4764                 frames = ltc & 0xF;
4765                 ltc >>= 4;
4766                 frames += (ltc & 0x3) * 10;
4767                 ltc >>= 4;
4768                 seconds = ltc & 0xF;
4769                 ltc >>= 4;
4770                 seconds += (ltc & 0x7) * 10;
4771                 ltc >>= 4;
4772                 minutes = ltc & 0xF;
4773                 ltc >>= 4;
4774                 minutes += (ltc & 0x7) * 10;
4775                 ltc >>= 4;
4776                 hours = ltc & 0xF;
4777                 ltc >>= 4;
4778                 hours += (ltc & 0x3) * 10;
4779                 snd_iprintf(buffer,
4780                         "  LTC In: %02d:%02d:%02d:%02d\n",
4781                         hours, minutes, seconds, frames);
4782
4783         } else {
4784                 snd_iprintf(buffer, "No TCO module detected.\n");
4785         }
4786 }
4787
4788 static void
4789 snd_hdspm_proc_read_madi(struct snd_info_entry *entry,
4790                          struct snd_info_buffer *buffer)
4791 {
4792         struct hdspm *hdspm = entry->private_data;
4793         unsigned int status, status2, control, freq;
4794
4795         char *pref_sync_ref;
4796         char *autosync_ref;
4797         char *system_clock_mode;
4798         char *insel;
4799         int x, x2;
4800
4801         status = hdspm_read(hdspm, HDSPM_statusRegister);
4802         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4803         control = hdspm->control_register;
4804         freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4805
4806         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4807                         hdspm->card_name, hdspm->card->number + 1,
4808                         hdspm->firmware_rev,
4809                         (status2 & HDSPM_version0) |
4810                         (status2 & HDSPM_version1) | (status2 &
4811                                 HDSPM_version2));
4812
4813         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4814                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4815                         hdspm->serial);
4816
4817         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4818                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4819
4820         snd_iprintf(buffer, "--- System ---\n");
4821
4822         snd_iprintf(buffer,
4823                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4824                 status & HDSPM_audioIRQPending,
4825                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4826                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4827                 hdspm->irq_count);
4828         snd_iprintf(buffer,
4829                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4830                 "estimated= %ld (bytes)\n",
4831                 ((status & HDSPM_BufferID) ? 1 : 0),
4832                 (status & HDSPM_BufferPositionMask),
4833                 (status & HDSPM_BufferPositionMask) %
4834                 (2 * (int)hdspm->period_bytes),
4835                 ((status & HDSPM_BufferPositionMask) - 64) %
4836                 (2 * (int)hdspm->period_bytes),
4837                 (long) hdspm_hw_pointer(hdspm) * 4);
4838
4839         snd_iprintf(buffer,
4840                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4841                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4842                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4843                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4844                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4845         snd_iprintf(buffer,
4846                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4847                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4848                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4849         snd_iprintf(buffer,
4850                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4851                 "status2=0x%x\n",
4852                 hdspm->control_register, hdspm->control2_register,
4853                 status, status2);
4854
4855
4856         snd_iprintf(buffer, "--- Settings ---\n");
4857
4858         x = hdspm_get_latency(hdspm);
4859
4860         snd_iprintf(buffer,
4861                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4862                 x, (unsigned long) hdspm->period_bytes);
4863
4864         snd_iprintf(buffer, "Line out: %s\n",
4865                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4866
4867         switch (hdspm->control_register & HDSPM_InputMask) {
4868         case HDSPM_InputOptical:
4869                 insel = "Optical";
4870                 break;
4871         case HDSPM_InputCoaxial:
4872                 insel = "Coaxial";
4873                 break;
4874         default:
4875                 insel = "Unknown";
4876         }
4877
4878         snd_iprintf(buffer,
4879                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4880                 "Auto Input %s\n",
4881                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4882                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4883                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4884
4885
4886         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4887                 system_clock_mode = "AutoSync";
4888         else
4889                 system_clock_mode = "Master";
4890         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4891
4892         switch (hdspm_pref_sync_ref(hdspm)) {
4893         case HDSPM_SYNC_FROM_WORD:
4894                 pref_sync_ref = "Word Clock";
4895                 break;
4896         case HDSPM_SYNC_FROM_MADI:
4897                 pref_sync_ref = "MADI Sync";
4898                 break;
4899         case HDSPM_SYNC_FROM_TCO:
4900                 pref_sync_ref = "TCO";
4901                 break;
4902         case HDSPM_SYNC_FROM_SYNC_IN:
4903                 pref_sync_ref = "Sync In";
4904                 break;
4905         default:
4906                 pref_sync_ref = "XXXX Clock";
4907                 break;
4908         }
4909         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4910                         pref_sync_ref);
4911
4912         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4913                         hdspm->system_sample_rate);
4914
4915
4916         snd_iprintf(buffer, "--- Status:\n");
4917
4918         x = status & HDSPM_madiSync;
4919         x2 = status2 & HDSPM_wcSync;
4920
4921         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4922                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4923                         "NoLock",
4924                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4925                         "NoLock");
4926
4927         switch (hdspm_autosync_ref(hdspm)) {
4928         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4929                 autosync_ref = "Sync In";
4930                 break;
4931         case HDSPM_AUTOSYNC_FROM_TCO:
4932                 autosync_ref = "TCO";
4933                 break;
4934         case HDSPM_AUTOSYNC_FROM_WORD:
4935                 autosync_ref = "Word Clock";
4936                 break;
4937         case HDSPM_AUTOSYNC_FROM_MADI:
4938                 autosync_ref = "MADI Sync";
4939                 break;
4940         case HDSPM_AUTOSYNC_FROM_NONE:
4941                 autosync_ref = "Input not valid";
4942                 break;
4943         default:
4944                 autosync_ref = "---";
4945                 break;
4946         }
4947         snd_iprintf(buffer,
4948                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4949                 autosync_ref, hdspm_external_sample_rate(hdspm),
4950                 (status & HDSPM_madiFreqMask) >> 22,
4951                 (status2 & HDSPM_wcFreqMask) >> 5);
4952
4953         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4954                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4955                 (status & HDSPM_RX_64ch) ? "64 channels" :
4956                 "56 channels");
4957
4958         /* call readout function for TCO specific status */
4959         snd_hdspm_proc_read_tco(entry, buffer);
4960
4961         snd_iprintf(buffer, "\n");
4962 }
4963
4964 static void
4965 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4966                           struct snd_info_buffer *buffer)
4967 {
4968         struct hdspm *hdspm = entry->private_data;
4969         unsigned int status;
4970         unsigned int status2;
4971         unsigned int timecode;
4972         unsigned int wcLock, wcSync;
4973         int pref_syncref;
4974         char *autosync_ref;
4975         int x;
4976
4977         status = hdspm_read(hdspm, HDSPM_statusRegister);
4978         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4979         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4980
4981         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4982                     hdspm->card_name, hdspm->card->number + 1,
4983                     hdspm->firmware_rev);
4984
4985         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4986                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4987
4988         snd_iprintf(buffer, "--- System ---\n");
4989
4990         snd_iprintf(buffer,
4991                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4992                     status & HDSPM_audioIRQPending,
4993                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
4994                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
4995                     hdspm->irq_count);
4996         snd_iprintf(buffer,
4997                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
4998                     "estimated= %ld (bytes)\n",
4999                     ((status & HDSPM_BufferID) ? 1 : 0),
5000                     (status & HDSPM_BufferPositionMask),
5001                     (status & HDSPM_BufferPositionMask) %
5002                     (2 * (int)hdspm->period_bytes),
5003                     ((status & HDSPM_BufferPositionMask) - 64) %
5004                     (2 * (int)hdspm->period_bytes),
5005                     (long) hdspm_hw_pointer(hdspm) * 4);
5006
5007         snd_iprintf(buffer,
5008                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5009                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5010                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5011                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5012                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5013         snd_iprintf(buffer,
5014                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5015                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5016                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5017         snd_iprintf(buffer,
5018                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5019                     "status2=0x%x\n",
5020                     hdspm->control_register, hdspm->control2_register,
5021                     status, status2);
5022
5023         snd_iprintf(buffer, "--- Settings ---\n");
5024
5025         x = hdspm_get_latency(hdspm);
5026
5027         snd_iprintf(buffer,
5028                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5029                     x, (unsigned long) hdspm->period_bytes);
5030
5031         snd_iprintf(buffer, "Line out: %s\n",
5032                     (hdspm->
5033                      control_register & HDSPM_LineOut) ? "on " : "off");
5034
5035         snd_iprintf(buffer,
5036                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5037                     (hdspm->
5038                      control_register & HDSPM_clr_tms) ? "on" : "off",
5039                     (hdspm->
5040                      control_register & HDSPM_Emphasis) ? "on" : "off",
5041                     (hdspm->
5042                      control_register & HDSPM_Dolby) ? "on" : "off");
5043
5044
5045         pref_syncref = hdspm_pref_sync_ref(hdspm);
5046         if (pref_syncref == 0)
5047                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5048         else
5049                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5050                                 pref_syncref);
5051
5052         snd_iprintf(buffer, "System Clock Frequency: %d\n",
5053                     hdspm->system_sample_rate);
5054
5055         snd_iprintf(buffer, "Double speed: %s\n",
5056                         hdspm->control_register & HDSPM_DS_DoubleWire?
5057                         "Double wire" : "Single wire");
5058         snd_iprintf(buffer, "Quad speed: %s\n",
5059                         hdspm->control_register & HDSPM_QS_DoubleWire?
5060                         "Double wire" :
5061                         hdspm->control_register & HDSPM_QS_QuadWire?
5062                         "Quad wire" : "Single wire");
5063
5064         snd_iprintf(buffer, "--- Status:\n");
5065
5066         wcLock = status & HDSPM_AES32_wcLock;
5067         wcSync = wcLock && (status & HDSPM_AES32_wcSync);
5068
5069         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
5070                     (wcLock) ? (wcSync ? "Sync   " : "Lock   ") : "No Lock",
5071                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5072
5073         for (x = 0; x < 8; x++) {
5074                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
5075                             x+1,
5076                             (status2 & (HDSPM_LockAES >> x)) ?
5077                             "Sync   " : "No Lock",
5078                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5079         }
5080
5081         switch (hdspm_autosync_ref(hdspm)) {
5082         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5083                 autosync_ref = "None"; break;
5084         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5085                 autosync_ref = "Word Clock"; break;
5086         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5087                 autosync_ref = "AES1"; break;
5088         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5089                 autosync_ref = "AES2"; break;
5090         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5091                 autosync_ref = "AES3"; break;
5092         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5093                 autosync_ref = "AES4"; break;
5094         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5095                 autosync_ref = "AES5"; break;
5096         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5097                 autosync_ref = "AES6"; break;
5098         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5099                 autosync_ref = "AES7"; break;
5100         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5101                 autosync_ref = "AES8"; break;
5102         case HDSPM_AES32_AUTOSYNC_FROM_TCO:
5103                 autosync_ref = "TCO"; break;
5104         case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN:
5105                 autosync_ref = "Sync In"; break;
5106         default:
5107                 autosync_ref = "---"; break;
5108         }
5109         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5110
5111         /* call readout function for TCO specific status */
5112         snd_hdspm_proc_read_tco(entry, buffer);
5113
5114         snd_iprintf(buffer, "\n");
5115 }
5116
5117 static void
5118 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5119                          struct snd_info_buffer *buffer)
5120 {
5121         struct hdspm *hdspm = entry->private_data;
5122         unsigned int status1, status2, status3, control, i;
5123         unsigned int lock, sync;
5124
5125         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5126         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5127         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5128
5129         control = hdspm->control_register;
5130
5131         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5132         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5133         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5134
5135
5136         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5137
5138         snd_iprintf(buffer, "Clock mode      : %s\n",
5139                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5140         snd_iprintf(buffer, "System frequency: %d Hz\n",
5141                 hdspm_get_system_sample_rate(hdspm));
5142
5143         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5144
5145         lock = 0x1;
5146         sync = 0x100;
5147
5148         for (i = 0; i < 8; i++) {
5149                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5150                                 i,
5151                                 (status1 & lock) ? 1 : 0,
5152                                 (status1 & sync) ? 1 : 0,
5153                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
5154
5155                 lock = lock<<1;
5156                 sync = sync<<1;
5157         }
5158
5159         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5160                         (status1 & 0x1000000) ? 1 : 0,
5161                         (status1 & 0x2000000) ? 1 : 0,
5162                         texts_freq[(status1 >> 16) & 0xF]);
5163
5164         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5165                         (status1 & 0x4000000) ? 1 : 0,
5166                         (status1 & 0x8000000) ? 1 : 0,
5167                         texts_freq[(status1 >> 20) & 0xF]);
5168
5169         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5170                         (status3 & 0x400) ? 1 : 0,
5171                         (status3 & 0x800) ? 1 : 0,
5172                         texts_freq[(status2 >> 12) & 0xF]);
5173
5174 }
5175
5176 #ifdef CONFIG_SND_DEBUG
5177 static void
5178 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5179                           struct snd_info_buffer *buffer)
5180 {
5181         struct hdspm *hdspm = entry->private_data;
5182
5183         int j,i;
5184
5185         for (i = 0; i < 256 /* 1024*64 */; i += j) {
5186                 snd_iprintf(buffer, "0x%08X: ", i);
5187                 for (j = 0; j < 16; j += 4)
5188                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5189                 snd_iprintf(buffer, "\n");
5190         }
5191 }
5192 #endif
5193
5194
5195 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5196                           struct snd_info_buffer *buffer)
5197 {
5198         struct hdspm *hdspm = entry->private_data;
5199         int i;
5200
5201         snd_iprintf(buffer, "# generated by hdspm\n");
5202
5203         for (i = 0; i < hdspm->max_channels_in; i++) {
5204                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5205         }
5206 }
5207
5208 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5209                           struct snd_info_buffer *buffer)
5210 {
5211         struct hdspm *hdspm = entry->private_data;
5212         int i;
5213
5214         snd_iprintf(buffer, "# generated by hdspm\n");
5215
5216         for (i = 0; i < hdspm->max_channels_out; i++) {
5217                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5218         }
5219 }
5220
5221
5222 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5223 {
5224         struct snd_info_entry *entry;
5225
5226         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5227                 switch (hdspm->io_type) {
5228                 case AES32:
5229                         snd_info_set_text_ops(entry, hdspm,
5230                                         snd_hdspm_proc_read_aes32);
5231                         break;
5232                 case MADI:
5233                         snd_info_set_text_ops(entry, hdspm,
5234                                         snd_hdspm_proc_read_madi);
5235                         break;
5236                 case MADIface:
5237                         /* snd_info_set_text_ops(entry, hdspm,
5238                          snd_hdspm_proc_read_madiface); */
5239                         break;
5240                 case RayDAT:
5241                         snd_info_set_text_ops(entry, hdspm,
5242                                         snd_hdspm_proc_read_raydat);
5243                         break;
5244                 case AIO:
5245                         break;
5246                 }
5247         }
5248
5249         if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5250                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5251         }
5252
5253         if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5254                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5255         }
5256
5257 #ifdef CONFIG_SND_DEBUG
5258         /* debug file to read all hdspm registers */
5259         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5260                 snd_info_set_text_ops(entry, hdspm,
5261                                 snd_hdspm_proc_read_debug);
5262 #endif
5263 }
5264
5265 /*------------------------------------------------------------
5266    hdspm intitialize
5267  ------------------------------------------------------------*/
5268
5269 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5270 {
5271         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5272            hold it (e.g. during module initialization).
5273            */
5274
5275         /* set defaults:       */
5276
5277         hdspm->settings_register = 0;
5278
5279         switch (hdspm->io_type) {
5280         case MADI:
5281         case MADIface:
5282                 hdspm->control_register =
5283                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5284                 break;
5285
5286         case RayDAT:
5287         case AIO:
5288                 hdspm->settings_register = 0x1 + 0x1000;
5289                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5290                  * line_out */
5291                 hdspm->control_register =
5292                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5293                 break;
5294
5295         case AES32:
5296                 hdspm->control_register =
5297                         HDSPM_ClockModeMaster | /* Master Clock Mode on */
5298                         hdspm_encode_latency(7) | /* latency max=8192samples */
5299                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5300                         HDSPM_LineOut | /* Analog output in */
5301                         HDSPM_Professional;  /* Professional mode */
5302                 break;
5303         }
5304
5305         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5306
5307         if (AES32 == hdspm->io_type) {
5308                 /* No control2 register for AES32 */
5309 #ifdef SNDRV_BIG_ENDIAN
5310                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5311 #else
5312                 hdspm->control2_register = 0;
5313 #endif
5314
5315                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5316         }
5317         hdspm_compute_period_size(hdspm);
5318
5319         /* silence everything */
5320
5321         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5322
5323         if (hdspm_is_raydat_or_aio(hdspm))
5324                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5325
5326         /* set a default rate so that the channel map is set up. */
5327         hdspm_set_rate(hdspm, 48000, 1);
5328
5329         return 0;
5330 }
5331
5332
5333 /*------------------------------------------------------------
5334    interrupt
5335  ------------------------------------------------------------*/
5336
5337 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5338 {
5339         struct hdspm *hdspm = (struct hdspm *) dev_id;
5340         unsigned int status;
5341         int i, audio, midi, schedule = 0;
5342         /* cycles_t now; */
5343
5344         status = hdspm_read(hdspm, HDSPM_statusRegister);
5345
5346         audio = status & HDSPM_audioIRQPending;
5347         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5348                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5349
5350         /* now = get_cycles(); */
5351         /**
5352          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5353          *          6       4096   ~256053425     ~514672358
5354          *          5       2048   ~128024983     ~257373821
5355          *          4       1024    ~64023706     ~128718089
5356          *          3        512    ~32005945      ~64385999
5357          *          2        256    ~16003039      ~32260176
5358          *          1        128     ~7998738      ~16194507
5359          *          0         64     ~3998231       ~8191558
5360          **/
5361         /*
5362            snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5363            now-hdspm->last_interrupt, status & 0xFFC0);
5364            hdspm->last_interrupt = now;
5365         */
5366
5367         if (!audio && !midi)
5368                 return IRQ_NONE;
5369
5370         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5371         hdspm->irq_count++;
5372
5373
5374         if (audio) {
5375                 if (hdspm->capture_substream)
5376                         snd_pcm_period_elapsed(hdspm->capture_substream);
5377
5378                 if (hdspm->playback_substream)
5379                         snd_pcm_period_elapsed(hdspm->playback_substream);
5380         }
5381
5382         if (midi) {
5383                 i = 0;
5384                 while (i < hdspm->midiPorts) {
5385                         if ((hdspm_read(hdspm,
5386                                 hdspm->midi[i].statusIn) & 0xff) &&
5387                                         (status & hdspm->midi[i].irq)) {
5388                                 /* we disable interrupts for this input until
5389                                  * processing is done
5390                                  */
5391                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5392                                 hdspm_write(hdspm, HDSPM_controlRegister,
5393                                                 hdspm->control_register);
5394                                 hdspm->midi[i].pending = 1;
5395                                 schedule = 1;
5396                         }
5397
5398                         i++;
5399                 }
5400
5401                 if (schedule)
5402                         tasklet_hi_schedule(&hdspm->midi_tasklet);
5403         }
5404
5405         return IRQ_HANDLED;
5406 }
5407
5408 /*------------------------------------------------------------
5409    pcm interface
5410   ------------------------------------------------------------*/
5411
5412
5413 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5414                                               *substream)
5415 {
5416         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5417         return hdspm_hw_pointer(hdspm);
5418 }
5419
5420
5421 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5422 {
5423         struct snd_pcm_runtime *runtime = substream->runtime;
5424         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5425         struct snd_pcm_substream *other;
5426
5427         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5428                 other = hdspm->capture_substream;
5429         else
5430                 other = hdspm->playback_substream;
5431
5432         if (hdspm->running)
5433                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5434         else
5435                 runtime->status->hw_ptr = 0;
5436         if (other) {
5437                 struct snd_pcm_substream *s;
5438                 struct snd_pcm_runtime *oruntime = other->runtime;
5439                 snd_pcm_group_for_each_entry(s, substream) {
5440                         if (s == other) {
5441                                 oruntime->status->hw_ptr =
5442                                         runtime->status->hw_ptr;
5443                                 break;
5444                         }
5445                 }
5446         }
5447         return 0;
5448 }
5449
5450 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5451                                struct snd_pcm_hw_params *params)
5452 {
5453         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5454         int err;
5455         int i;
5456         pid_t this_pid;
5457         pid_t other_pid;
5458
5459         spin_lock_irq(&hdspm->lock);
5460
5461         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5462                 this_pid = hdspm->playback_pid;
5463                 other_pid = hdspm->capture_pid;
5464         } else {
5465                 this_pid = hdspm->capture_pid;
5466                 other_pid = hdspm->playback_pid;
5467         }
5468
5469         if (other_pid > 0 && this_pid != other_pid) {
5470
5471                 /* The other stream is open, and not by the same
5472                    task as this one. Make sure that the parameters
5473                    that matter are the same.
5474                    */
5475
5476                 if (params_rate(params) != hdspm->system_sample_rate) {
5477                         spin_unlock_irq(&hdspm->lock);
5478                         _snd_pcm_hw_param_setempty(params,
5479                                         SNDRV_PCM_HW_PARAM_RATE);
5480                         return -EBUSY;
5481                 }
5482
5483                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5484                         spin_unlock_irq(&hdspm->lock);
5485                         _snd_pcm_hw_param_setempty(params,
5486                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5487                         return -EBUSY;
5488                 }
5489
5490         }
5491         /* We're fine. */
5492         spin_unlock_irq(&hdspm->lock);
5493
5494         /* how to make sure that the rate matches an externally-set one ?   */
5495
5496         spin_lock_irq(&hdspm->lock);
5497         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5498         if (err < 0) {
5499                 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5500                 spin_unlock_irq(&hdspm->lock);
5501                 _snd_pcm_hw_param_setempty(params,
5502                                 SNDRV_PCM_HW_PARAM_RATE);
5503                 return err;
5504         }
5505         spin_unlock_irq(&hdspm->lock);
5506
5507         err = hdspm_set_interrupt_interval(hdspm,
5508                         params_period_size(params));
5509         if (err < 0) {
5510                 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5511                 _snd_pcm_hw_param_setempty(params,
5512                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5513                 return err;
5514         }
5515
5516         /* Memory allocation, takashi's method, dont know if we should
5517          * spinlock
5518          */
5519         /* malloc all buffer even if not enabled to get sure */
5520         /* Update for MADI rev 204: we need to allocate for all channels,
5521          * otherwise it doesn't work at 96kHz */
5522
5523         err =
5524                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5525         if (err < 0) {
5526                 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5527                 return err;
5528         }
5529
5530         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5531
5532                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5533                                 params_channels(params));
5534
5535                 for (i = 0; i < params_channels(params); ++i)
5536                         snd_hdspm_enable_out(hdspm, i, 1);
5537
5538                 hdspm->playback_buffer =
5539                         (unsigned char *) substream->runtime->dma_area;
5540                 snd_printdd("Allocated sample buffer for playback at %p\n",
5541                                 hdspm->playback_buffer);
5542         } else {
5543                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5544                                 params_channels(params));
5545
5546                 for (i = 0; i < params_channels(params); ++i)
5547                         snd_hdspm_enable_in(hdspm, i, 1);
5548
5549                 hdspm->capture_buffer =
5550                         (unsigned char *) substream->runtime->dma_area;
5551                 snd_printdd("Allocated sample buffer for capture at %p\n",
5552                                 hdspm->capture_buffer);
5553         }
5554
5555         /*
5556            snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5557            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5558            "playback" : "capture",
5559            snd_pcm_sgbuf_get_addr(substream, 0));
5560            */
5561         /*
5562            snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5563            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5564            "playback" : "capture",
5565            params_rate(params), params_channels(params),
5566            params_buffer_size(params));
5567            */
5568
5569
5570         /*  For AES cards, the float format bit is the same as the
5571          *  preferred sync reference. Since we don't want to break
5572          *  sync settings, we have to skip the remaining part of this
5573          *  function.
5574          */
5575         if (hdspm->io_type == AES32) {
5576                 return 0;
5577         }
5578
5579
5580         /* Switch to native float format if requested */
5581         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5582                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5583                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5584
5585                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5586         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5587                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5588                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5589
5590                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5591         }
5592         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5593
5594         return 0;
5595 }
5596
5597 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5598 {
5599         int i;
5600         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5601
5602         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5603
5604                 /* params_channels(params) should be enough,
5605                    but to get sure in case of error */
5606                 for (i = 0; i < hdspm->max_channels_out; ++i)
5607                         snd_hdspm_enable_out(hdspm, i, 0);
5608
5609                 hdspm->playback_buffer = NULL;
5610         } else {
5611                 for (i = 0; i < hdspm->max_channels_in; ++i)
5612                         snd_hdspm_enable_in(hdspm, i, 0);
5613
5614                 hdspm->capture_buffer = NULL;
5615
5616         }
5617
5618         snd_pcm_lib_free_pages(substream);
5619
5620         return 0;
5621 }
5622
5623
5624 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5625                 struct snd_pcm_channel_info *info)
5626 {
5627         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5628
5629         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5630                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5631                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5632                         return -EINVAL;
5633                 }
5634
5635                 if (hdspm->channel_map_out[info->channel] < 0) {
5636                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5637                         return -EINVAL;
5638                 }
5639
5640                 info->offset = hdspm->channel_map_out[info->channel] *
5641                         HDSPM_CHANNEL_BUFFER_BYTES;
5642         } else {
5643                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5644                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5645                         return -EINVAL;
5646                 }
5647
5648                 if (hdspm->channel_map_in[info->channel] < 0) {
5649                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5650                         return -EINVAL;
5651                 }
5652
5653                 info->offset = hdspm->channel_map_in[info->channel] *
5654                         HDSPM_CHANNEL_BUFFER_BYTES;
5655         }
5656
5657         info->first = 0;
5658         info->step = 32;
5659         return 0;
5660 }
5661
5662
5663 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5664                 unsigned int cmd, void *arg)
5665 {
5666         switch (cmd) {
5667         case SNDRV_PCM_IOCTL1_RESET:
5668                 return snd_hdspm_reset(substream);
5669
5670         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5671                 {
5672                         struct snd_pcm_channel_info *info = arg;
5673                         return snd_hdspm_channel_info(substream, info);
5674                 }
5675         default:
5676                 break;
5677         }
5678
5679         return snd_pcm_lib_ioctl(substream, cmd, arg);
5680 }
5681
5682 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5683 {
5684         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5685         struct snd_pcm_substream *other;
5686         int running;
5687
5688         spin_lock(&hdspm->lock);
5689         running = hdspm->running;
5690         switch (cmd) {
5691         case SNDRV_PCM_TRIGGER_START:
5692                 running |= 1 << substream->stream;
5693                 break;
5694         case SNDRV_PCM_TRIGGER_STOP:
5695                 running &= ~(1 << substream->stream);
5696                 break;
5697         default:
5698                 snd_BUG();
5699                 spin_unlock(&hdspm->lock);
5700                 return -EINVAL;
5701         }
5702         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5703                 other = hdspm->capture_substream;
5704         else
5705                 other = hdspm->playback_substream;
5706
5707         if (other) {
5708                 struct snd_pcm_substream *s;
5709                 snd_pcm_group_for_each_entry(s, substream) {
5710                         if (s == other) {
5711                                 snd_pcm_trigger_done(s, substream);
5712                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5713                                         running |= 1 << s->stream;
5714                                 else
5715                                         running &= ~(1 << s->stream);
5716                                 goto _ok;
5717                         }
5718                 }
5719                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5720                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5721                                         && substream->stream ==
5722                                         SNDRV_PCM_STREAM_CAPTURE)
5723                                 hdspm_silence_playback(hdspm);
5724                 } else {
5725                         if (running &&
5726                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5727                                 hdspm_silence_playback(hdspm);
5728                 }
5729         } else {
5730                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5731                         hdspm_silence_playback(hdspm);
5732         }
5733 _ok:
5734         snd_pcm_trigger_done(substream, substream);
5735         if (!hdspm->running && running)
5736                 hdspm_start_audio(hdspm);
5737         else if (hdspm->running && !running)
5738                 hdspm_stop_audio(hdspm);
5739         hdspm->running = running;
5740         spin_unlock(&hdspm->lock);
5741
5742         return 0;
5743 }
5744
5745 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5746 {
5747         return 0;
5748 }
5749
5750 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5751         .info = (SNDRV_PCM_INFO_MMAP |
5752                  SNDRV_PCM_INFO_MMAP_VALID |
5753                  SNDRV_PCM_INFO_NONINTERLEAVED |
5754                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5755         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5756         .rates = (SNDRV_PCM_RATE_32000 |
5757                   SNDRV_PCM_RATE_44100 |
5758                   SNDRV_PCM_RATE_48000 |
5759                   SNDRV_PCM_RATE_64000 |
5760                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5761                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5762         .rate_min = 32000,
5763         .rate_max = 192000,
5764         .channels_min = 1,
5765         .channels_max = HDSPM_MAX_CHANNELS,
5766         .buffer_bytes_max =
5767             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5768         .period_bytes_min = (32 * 4),
5769         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5770         .periods_min = 2,
5771         .periods_max = 512,
5772         .fifo_size = 0
5773 };
5774
5775 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5776         .info = (SNDRV_PCM_INFO_MMAP |
5777                  SNDRV_PCM_INFO_MMAP_VALID |
5778                  SNDRV_PCM_INFO_NONINTERLEAVED |
5779                  SNDRV_PCM_INFO_SYNC_START),
5780         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5781         .rates = (SNDRV_PCM_RATE_32000 |
5782                   SNDRV_PCM_RATE_44100 |
5783                   SNDRV_PCM_RATE_48000 |
5784                   SNDRV_PCM_RATE_64000 |
5785                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5786                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5787         .rate_min = 32000,
5788         .rate_max = 192000,
5789         .channels_min = 1,
5790         .channels_max = HDSPM_MAX_CHANNELS,
5791         .buffer_bytes_max =
5792             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5793         .period_bytes_min = (32 * 4),
5794         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5795         .periods_min = 2,
5796         .periods_max = 512,
5797         .fifo_size = 0
5798 };
5799
5800 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5801                                            struct snd_pcm_hw_rule *rule)
5802 {
5803         struct hdspm *hdspm = rule->private;
5804         struct snd_interval *c =
5805             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5806         struct snd_interval *r =
5807             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5808
5809         if (r->min > 96000 && r->max <= 192000) {
5810                 struct snd_interval t = {
5811                         .min = hdspm->qs_in_channels,
5812                         .max = hdspm->qs_in_channels,
5813                         .integer = 1,
5814                 };
5815                 return snd_interval_refine(c, &t);
5816         } else if (r->min > 48000 && r->max <= 96000) {
5817                 struct snd_interval t = {
5818                         .min = hdspm->ds_in_channels,
5819                         .max = hdspm->ds_in_channels,
5820                         .integer = 1,
5821                 };
5822                 return snd_interval_refine(c, &t);
5823         } else if (r->max < 64000) {
5824                 struct snd_interval t = {
5825                         .min = hdspm->ss_in_channels,
5826                         .max = hdspm->ss_in_channels,
5827                         .integer = 1,
5828                 };
5829                 return snd_interval_refine(c, &t);
5830         }
5831
5832         return 0;
5833 }
5834
5835 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5836                                            struct snd_pcm_hw_rule * rule)
5837 {
5838         struct hdspm *hdspm = rule->private;
5839         struct snd_interval *c =
5840             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5841         struct snd_interval *r =
5842             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5843
5844         if (r->min > 96000 && r->max <= 192000) {
5845                 struct snd_interval t = {
5846                         .min = hdspm->qs_out_channels,
5847                         .max = hdspm->qs_out_channels,
5848                         .integer = 1,
5849                 };
5850                 return snd_interval_refine(c, &t);
5851         } else if (r->min > 48000 && r->max <= 96000) {
5852                 struct snd_interval t = {
5853                         .min = hdspm->ds_out_channels,
5854                         .max = hdspm->ds_out_channels,
5855                         .integer = 1,
5856                 };
5857                 return snd_interval_refine(c, &t);
5858         } else if (r->max < 64000) {
5859                 struct snd_interval t = {
5860                         .min = hdspm->ss_out_channels,
5861                         .max = hdspm->ss_out_channels,
5862                         .integer = 1,
5863                 };
5864                 return snd_interval_refine(c, &t);
5865         } else {
5866         }
5867         return 0;
5868 }
5869
5870 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5871                                            struct snd_pcm_hw_rule * rule)
5872 {
5873         struct hdspm *hdspm = rule->private;
5874         struct snd_interval *c =
5875             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5876         struct snd_interval *r =
5877             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5878
5879         if (c->min >= hdspm->ss_in_channels) {
5880                 struct snd_interval t = {
5881                         .min = 32000,
5882                         .max = 48000,
5883                         .integer = 1,
5884                 };
5885                 return snd_interval_refine(r, &t);
5886         } else if (c->max <= hdspm->qs_in_channels) {
5887                 struct snd_interval t = {
5888                         .min = 128000,
5889                         .max = 192000,
5890                         .integer = 1,
5891                 };
5892                 return snd_interval_refine(r, &t);
5893         } else if (c->max <= hdspm->ds_in_channels) {
5894                 struct snd_interval t = {
5895                         .min = 64000,
5896                         .max = 96000,
5897                         .integer = 1,
5898                 };
5899                 return snd_interval_refine(r, &t);
5900         }
5901
5902         return 0;
5903 }
5904 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5905                                            struct snd_pcm_hw_rule *rule)
5906 {
5907         struct hdspm *hdspm = rule->private;
5908         struct snd_interval *c =
5909             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5910         struct snd_interval *r =
5911             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5912
5913         if (c->min >= hdspm->ss_out_channels) {
5914                 struct snd_interval t = {
5915                         .min = 32000,
5916                         .max = 48000,
5917                         .integer = 1,
5918                 };
5919                 return snd_interval_refine(r, &t);
5920         } else if (c->max <= hdspm->qs_out_channels) {
5921                 struct snd_interval t = {
5922                         .min = 128000,
5923                         .max = 192000,
5924                         .integer = 1,
5925                 };
5926                 return snd_interval_refine(r, &t);
5927         } else if (c->max <= hdspm->ds_out_channels) {
5928                 struct snd_interval t = {
5929                         .min = 64000,
5930                         .max = 96000,
5931                         .integer = 1,
5932                 };
5933                 return snd_interval_refine(r, &t);
5934         }
5935
5936         return 0;
5937 }
5938
5939 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5940                                       struct snd_pcm_hw_rule *rule)
5941 {
5942         unsigned int list[3];
5943         struct hdspm *hdspm = rule->private;
5944         struct snd_interval *c = hw_param_interval(params,
5945                         SNDRV_PCM_HW_PARAM_CHANNELS);
5946
5947         list[0] = hdspm->qs_in_channels;
5948         list[1] = hdspm->ds_in_channels;
5949         list[2] = hdspm->ss_in_channels;
5950         return snd_interval_list(c, 3, list, 0);
5951 }
5952
5953 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5954                                       struct snd_pcm_hw_rule *rule)
5955 {
5956         unsigned int list[3];
5957         struct hdspm *hdspm = rule->private;
5958         struct snd_interval *c = hw_param_interval(params,
5959                         SNDRV_PCM_HW_PARAM_CHANNELS);
5960
5961         list[0] = hdspm->qs_out_channels;
5962         list[1] = hdspm->ds_out_channels;
5963         list[2] = hdspm->ss_out_channels;
5964         return snd_interval_list(c, 3, list, 0);
5965 }
5966
5967
5968 static unsigned int hdspm_aes32_sample_rates[] = {
5969         32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5970 };
5971
5972 static struct snd_pcm_hw_constraint_list
5973 hdspm_hw_constraints_aes32_sample_rates = {
5974         .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5975         .list = hdspm_aes32_sample_rates,
5976         .mask = 0
5977 };
5978
5979 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5980 {
5981         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5982         struct snd_pcm_runtime *runtime = substream->runtime;
5983
5984         spin_lock_irq(&hdspm->lock);
5985
5986         snd_pcm_set_sync(substream);
5987
5988
5989         runtime->hw = snd_hdspm_playback_subinfo;
5990
5991         if (hdspm->capture_substream == NULL)
5992                 hdspm_stop_audio(hdspm);
5993
5994         hdspm->playback_pid = current->pid;
5995         hdspm->playback_substream = substream;
5996
5997         spin_unlock_irq(&hdspm->lock);
5998
5999         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6000         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6001
6002         switch (hdspm->io_type) {
6003         case AIO:
6004         case RayDAT:
6005                 snd_pcm_hw_constraint_minmax(runtime,
6006                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6007                                              32, 4096);
6008                 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
6009                 snd_pcm_hw_constraint_minmax(runtime,
6010                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6011                                              16384, 16384);
6012                 break;
6013
6014         default:
6015                 snd_pcm_hw_constraint_minmax(runtime,
6016                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6017                                              64, 8192);
6018                 break;
6019         }
6020
6021         if (AES32 == hdspm->io_type) {
6022                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6023                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6024                                 &hdspm_hw_constraints_aes32_sample_rates);
6025         } else {
6026                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6027                                 snd_hdspm_hw_rule_rate_out_channels, hdspm,
6028                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6029         }
6030
6031         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6032                         snd_hdspm_hw_rule_out_channels, hdspm,
6033                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6034
6035         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6036                         snd_hdspm_hw_rule_out_channels_rate, hdspm,
6037                         SNDRV_PCM_HW_PARAM_RATE, -1);
6038
6039         return 0;
6040 }
6041
6042 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
6043 {
6044         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6045
6046         spin_lock_irq(&hdspm->lock);
6047
6048         hdspm->playback_pid = -1;
6049         hdspm->playback_substream = NULL;
6050
6051         spin_unlock_irq(&hdspm->lock);
6052
6053         return 0;
6054 }
6055
6056
6057 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6058 {
6059         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6060         struct snd_pcm_runtime *runtime = substream->runtime;
6061
6062         spin_lock_irq(&hdspm->lock);
6063         snd_pcm_set_sync(substream);
6064         runtime->hw = snd_hdspm_capture_subinfo;
6065
6066         if (hdspm->playback_substream == NULL)
6067                 hdspm_stop_audio(hdspm);
6068
6069         hdspm->capture_pid = current->pid;
6070         hdspm->capture_substream = substream;
6071
6072         spin_unlock_irq(&hdspm->lock);
6073
6074         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6075         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6076
6077         switch (hdspm->io_type) {
6078         case AIO:
6079         case RayDAT:
6080                 snd_pcm_hw_constraint_minmax(runtime,
6081                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6082                                              32, 4096);
6083                 snd_pcm_hw_constraint_minmax(runtime,
6084                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6085                                              16384, 16384);
6086                 break;
6087
6088         default:
6089                 snd_pcm_hw_constraint_minmax(runtime,
6090                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6091                                              64, 8192);
6092                 break;
6093         }
6094
6095         if (AES32 == hdspm->io_type) {
6096                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6097                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6098                                 &hdspm_hw_constraints_aes32_sample_rates);
6099         } else {
6100                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6101                                 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6102                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6103         }
6104
6105         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6106                         snd_hdspm_hw_rule_in_channels, hdspm,
6107                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6108
6109         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6110                         snd_hdspm_hw_rule_in_channels_rate, hdspm,
6111                         SNDRV_PCM_HW_PARAM_RATE, -1);
6112
6113         return 0;
6114 }
6115
6116 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6117 {
6118         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6119
6120         spin_lock_irq(&hdspm->lock);
6121
6122         hdspm->capture_pid = -1;
6123         hdspm->capture_substream = NULL;
6124
6125         spin_unlock_irq(&hdspm->lock);
6126         return 0;
6127 }
6128
6129 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6130 {
6131         /* we have nothing to initialize but the call is required */
6132         return 0;
6133 }
6134
6135 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6136 {
6137         u32 val = readl(src);
6138         return copy_to_user(dest, &val, 4);
6139 }
6140
6141 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6142                 unsigned int cmd, unsigned long arg)
6143 {
6144         void __user *argp = (void __user *)arg;
6145         struct hdspm *hdspm = hw->private_data;
6146         struct hdspm_mixer_ioctl mixer;
6147         struct hdspm_config info;
6148         struct hdspm_status status;
6149         struct hdspm_version hdspm_version;
6150         struct hdspm_peak_rms *levels;
6151         struct hdspm_ltc ltc;
6152         unsigned int statusregister;
6153         long unsigned int s;
6154         int i = 0;
6155
6156         switch (cmd) {
6157
6158         case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6159                 levels = &hdspm->peak_rms;
6160                 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6161                         levels->input_peaks[i] =
6162                                 readl(hdspm->iobase +
6163                                                 HDSPM_MADI_INPUT_PEAK + i*4);
6164                         levels->playback_peaks[i] =
6165                                 readl(hdspm->iobase +
6166                                                 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6167                         levels->output_peaks[i] =
6168                                 readl(hdspm->iobase +
6169                                                 HDSPM_MADI_OUTPUT_PEAK + i*4);
6170
6171                         levels->input_rms[i] =
6172                                 ((uint64_t) readl(hdspm->iobase +
6173                                         HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6174                                 (uint64_t) readl(hdspm->iobase +
6175                                                 HDSPM_MADI_INPUT_RMS_L + i*4);
6176                         levels->playback_rms[i] =
6177                                 ((uint64_t)readl(hdspm->iobase +
6178                                         HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6179                                 (uint64_t)readl(hdspm->iobase +
6180                                         HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6181                         levels->output_rms[i] =
6182                                 ((uint64_t)readl(hdspm->iobase +
6183                                         HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6184                                 (uint64_t)readl(hdspm->iobase +
6185                                                 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6186                 }
6187
6188                 if (hdspm->system_sample_rate > 96000) {
6189                         levels->speed = qs;
6190                 } else if (hdspm->system_sample_rate > 48000) {
6191                         levels->speed = ds;
6192                 } else {
6193                         levels->speed = ss;
6194                 }
6195                 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6196
6197                 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6198                 if (0 != s) {
6199                         /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6200                          [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6201                          */
6202                         return -EFAULT;
6203                 }
6204                 break;
6205
6206         case SNDRV_HDSPM_IOCTL_GET_LTC:
6207                 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6208                 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6209                 if (i & HDSPM_TCO1_LTC_Input_valid) {
6210                         switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6211                                 HDSPM_TCO1_LTC_Format_MSB)) {
6212                         case 0:
6213                                 ltc.format = fps_24;
6214                                 break;
6215                         case HDSPM_TCO1_LTC_Format_LSB:
6216                                 ltc.format = fps_25;
6217                                 break;
6218                         case HDSPM_TCO1_LTC_Format_MSB:
6219                                 ltc.format = fps_2997;
6220                                 break;
6221                         default:
6222                                 ltc.format = 30;
6223                                 break;
6224                         }
6225                         if (i & HDSPM_TCO1_set_drop_frame_flag) {
6226                                 ltc.frame = drop_frame;
6227                         } else {
6228                                 ltc.frame = full_frame;
6229                         }
6230                 } else {
6231                         ltc.format = format_invalid;
6232                         ltc.frame = frame_invalid;
6233                 }
6234                 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6235                         ltc.input_format = ntsc;
6236                 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6237                         ltc.input_format = pal;
6238                 } else {
6239                         ltc.input_format = no_video;
6240                 }
6241
6242                 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6243                 if (0 != s) {
6244                         /*
6245                          snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6246                         return -EFAULT;
6247                 }
6248
6249                 break;
6250
6251         case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6252
6253                 memset(&info, 0, sizeof(info));
6254                 spin_lock_irq(&hdspm->lock);
6255                 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6256                 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6257
6258                 info.system_sample_rate = hdspm->system_sample_rate;
6259                 info.autosync_sample_rate =
6260                         hdspm_external_sample_rate(hdspm);
6261                 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6262                 info.clock_source = hdspm_clock_source(hdspm);
6263                 info.autosync_ref = hdspm_autosync_ref(hdspm);
6264                 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut);
6265                 info.passthru = 0;
6266                 spin_unlock_irq(&hdspm->lock);
6267                 if (copy_to_user(argp, &info, sizeof(info)))
6268                         return -EFAULT;
6269                 break;
6270
6271         case SNDRV_HDSPM_IOCTL_GET_STATUS:
6272                 memset(&status, 0, sizeof(status));
6273
6274                 status.card_type = hdspm->io_type;
6275
6276                 status.autosync_source = hdspm_autosync_ref(hdspm);
6277
6278                 status.card_clock = 110069313433624ULL;
6279                 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6280
6281                 switch (hdspm->io_type) {
6282                 case MADI:
6283                 case MADIface:
6284                         status.card_specific.madi.sync_wc =
6285                                 hdspm_wc_sync_check(hdspm);
6286                         status.card_specific.madi.sync_madi =
6287                                 hdspm_madi_sync_check(hdspm);
6288                         status.card_specific.madi.sync_tco =
6289                                 hdspm_tco_sync_check(hdspm);
6290                         status.card_specific.madi.sync_in =
6291                                 hdspm_sync_in_sync_check(hdspm);
6292
6293                         statusregister =
6294                                 hdspm_read(hdspm, HDSPM_statusRegister);
6295                         status.card_specific.madi.madi_input =
6296                                 (statusregister & HDSPM_AB_int) ? 1 : 0;
6297                         status.card_specific.madi.channel_format =
6298                                 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6299                         /* TODO: Mac driver sets it when f_s>48kHz */
6300                         status.card_specific.madi.frame_format = 0;
6301
6302                 default:
6303                         break;
6304                 }
6305
6306                 if (copy_to_user(argp, &status, sizeof(status)))
6307                         return -EFAULT;
6308
6309
6310                 break;
6311
6312         case SNDRV_HDSPM_IOCTL_GET_VERSION:
6313                 memset(&hdspm_version, 0, sizeof(hdspm_version));
6314
6315                 hdspm_version.card_type = hdspm->io_type;
6316                 strncpy(hdspm_version.cardname, hdspm->card_name,
6317                                 sizeof(hdspm_version.cardname));
6318                 hdspm_version.serial = hdspm->serial;
6319                 hdspm_version.firmware_rev = hdspm->firmware_rev;
6320                 hdspm_version.addons = 0;
6321                 if (hdspm->tco)
6322                         hdspm_version.addons |= HDSPM_ADDON_TCO;
6323
6324                 if (copy_to_user(argp, &hdspm_version,
6325                                         sizeof(hdspm_version)))
6326                         return -EFAULT;
6327                 break;
6328
6329         case SNDRV_HDSPM_IOCTL_GET_MIXER:
6330                 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6331                         return -EFAULT;
6332                 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6333                                         sizeof(struct hdspm_mixer)))
6334                         return -EFAULT;
6335                 break;
6336
6337         default:
6338                 return -EINVAL;
6339         }
6340         return 0;
6341 }
6342
6343 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6344         .open = snd_hdspm_playback_open,
6345         .close = snd_hdspm_playback_release,
6346         .ioctl = snd_hdspm_ioctl,
6347         .hw_params = snd_hdspm_hw_params,
6348         .hw_free = snd_hdspm_hw_free,
6349         .prepare = snd_hdspm_prepare,
6350         .trigger = snd_hdspm_trigger,
6351         .pointer = snd_hdspm_hw_pointer,
6352         .page = snd_pcm_sgbuf_ops_page,
6353 };
6354
6355 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6356         .open = snd_hdspm_capture_open,
6357         .close = snd_hdspm_capture_release,
6358         .ioctl = snd_hdspm_ioctl,
6359         .hw_params = snd_hdspm_hw_params,
6360         .hw_free = snd_hdspm_hw_free,
6361         .prepare = snd_hdspm_prepare,
6362         .trigger = snd_hdspm_trigger,
6363         .pointer = snd_hdspm_hw_pointer,
6364         .page = snd_pcm_sgbuf_ops_page,
6365 };
6366
6367 static int snd_hdspm_create_hwdep(struct snd_card *card,
6368                                   struct hdspm *hdspm)
6369 {
6370         struct snd_hwdep *hw;
6371         int err;
6372
6373         err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6374         if (err < 0)
6375                 return err;
6376
6377         hdspm->hwdep = hw;
6378         hw->private_data = hdspm;
6379         strcpy(hw->name, "HDSPM hwdep interface");
6380
6381         hw->ops.open = snd_hdspm_hwdep_dummy_op;
6382         hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6383         hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6384         hw->ops.release = snd_hdspm_hwdep_dummy_op;
6385
6386         return 0;
6387 }
6388
6389
6390 /*------------------------------------------------------------
6391    memory interface
6392  ------------------------------------------------------------*/
6393 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6394 {
6395         int err;
6396         struct snd_pcm *pcm;
6397         size_t wanted;
6398
6399         pcm = hdspm->pcm;
6400
6401         wanted = HDSPM_DMA_AREA_BYTES;
6402
6403         err =
6404              snd_pcm_lib_preallocate_pages_for_all(pcm,
6405                                                    SNDRV_DMA_TYPE_DEV_SG,
6406                                                    snd_dma_pci_data(hdspm->pci),
6407                                                    wanted,
6408                                                    wanted);
6409         if (err < 0) {
6410                 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6411
6412                 return err;
6413         } else
6414                 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6415
6416         return 0;
6417 }
6418
6419
6420 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6421                             struct snd_pcm_substream *substream,
6422                              unsigned int reg, int channels)
6423 {
6424         int i;
6425
6426         /* continuous memory segment */
6427         for (i = 0; i < (channels * 16); i++)
6428                 hdspm_write(hdspm, reg + 4 * i,
6429                                 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6430 }
6431
6432
6433 /* ------------- ALSA Devices ---------------------------- */
6434 static int snd_hdspm_create_pcm(struct snd_card *card,
6435                                 struct hdspm *hdspm)
6436 {
6437         struct snd_pcm *pcm;
6438         int err;
6439
6440         err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6441         if (err < 0)
6442                 return err;
6443
6444         hdspm->pcm = pcm;
6445         pcm->private_data = hdspm;
6446         strcpy(pcm->name, hdspm->card_name);
6447
6448         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6449                         &snd_hdspm_playback_ops);
6450         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6451                         &snd_hdspm_capture_ops);
6452
6453         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6454
6455         err = snd_hdspm_preallocate_memory(hdspm);
6456         if (err < 0)
6457                 return err;
6458
6459         return 0;
6460 }
6461
6462 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6463 {
6464         int i;
6465
6466         for (i = 0; i < hdspm->midiPorts; i++)
6467                 snd_hdspm_flush_midi_input(hdspm, i);
6468 }
6469
6470 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
6471                                          struct hdspm *hdspm)
6472 {
6473         int err, i;
6474
6475         snd_printdd("Create card...\n");
6476         err = snd_hdspm_create_pcm(card, hdspm);
6477         if (err < 0)
6478                 return err;
6479
6480         i = 0;
6481         while (i < hdspm->midiPorts) {
6482                 err = snd_hdspm_create_midi(card, hdspm, i);
6483                 if (err < 0) {
6484                         return err;
6485                 }
6486                 i++;
6487         }
6488
6489         err = snd_hdspm_create_controls(card, hdspm);
6490         if (err < 0)
6491                 return err;
6492
6493         err = snd_hdspm_create_hwdep(card, hdspm);
6494         if (err < 0)
6495                 return err;
6496
6497         snd_printdd("proc init...\n");
6498         snd_hdspm_proc_init(hdspm);
6499
6500         hdspm->system_sample_rate = -1;
6501         hdspm->last_external_sample_rate = -1;
6502         hdspm->last_internal_sample_rate = -1;
6503         hdspm->playback_pid = -1;
6504         hdspm->capture_pid = -1;
6505         hdspm->capture_substream = NULL;
6506         hdspm->playback_substream = NULL;
6507
6508         snd_printdd("Set defaults...\n");
6509         err = snd_hdspm_set_defaults(hdspm);
6510         if (err < 0)
6511                 return err;
6512
6513         snd_printdd("Update mixer controls...\n");
6514         hdspm_update_simple_mixer_controls(hdspm);
6515
6516         snd_printdd("Initializeing complete ???\n");
6517
6518         err = snd_card_register(card);
6519         if (err < 0) {
6520                 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6521                 return err;
6522         }
6523
6524         snd_printdd("... yes now\n");
6525
6526         return 0;
6527 }
6528
6529 static int snd_hdspm_create(struct snd_card *card,
6530                             struct hdspm *hdspm)
6531 {
6532
6533         struct pci_dev *pci = hdspm->pci;
6534         int err;
6535         unsigned long io_extent;
6536
6537         hdspm->irq = -1;
6538         hdspm->card = card;
6539
6540         spin_lock_init(&hdspm->lock);
6541
6542         pci_read_config_word(hdspm->pci,
6543                         PCI_CLASS_REVISION, &hdspm->firmware_rev);
6544
6545         strcpy(card->mixername, "Xilinx FPGA");
6546         strcpy(card->driver, "HDSPM");
6547
6548         switch (hdspm->firmware_rev) {
6549         case HDSPM_RAYDAT_REV:
6550                 hdspm->io_type = RayDAT;
6551                 hdspm->card_name = "RME RayDAT";
6552                 hdspm->midiPorts = 2;
6553                 break;
6554         case HDSPM_AIO_REV:
6555                 hdspm->io_type = AIO;
6556                 hdspm->card_name = "RME AIO";
6557                 hdspm->midiPorts = 1;
6558                 break;
6559         case HDSPM_MADIFACE_REV:
6560                 hdspm->io_type = MADIface;
6561                 hdspm->card_name = "RME MADIface";
6562                 hdspm->midiPorts = 1;
6563                 break;
6564         default:
6565                 if ((hdspm->firmware_rev == 0xf0) ||
6566                         ((hdspm->firmware_rev >= 0xe6) &&
6567                                         (hdspm->firmware_rev <= 0xea))) {
6568                         hdspm->io_type = AES32;
6569                         hdspm->card_name = "RME AES32";
6570                         hdspm->midiPorts = 2;
6571                 } else if ((hdspm->firmware_rev == 0xd2) ||
6572                         ((hdspm->firmware_rev >= 0xc8)  &&
6573                                 (hdspm->firmware_rev <= 0xcf))) {
6574                         hdspm->io_type = MADI;
6575                         hdspm->card_name = "RME MADI";
6576                         hdspm->midiPorts = 3;
6577                 } else {
6578                         snd_printk(KERN_ERR
6579                                 "HDSPM: unknown firmware revision %x\n",
6580                                 hdspm->firmware_rev);
6581                         return -ENODEV;
6582                 }
6583         }
6584
6585         err = pci_enable_device(pci);
6586         if (err < 0)
6587                 return err;
6588
6589         pci_set_master(hdspm->pci);
6590
6591         err = pci_request_regions(pci, "hdspm");
6592         if (err < 0)
6593                 return err;
6594
6595         hdspm->port = pci_resource_start(pci, 0);
6596         io_extent = pci_resource_len(pci, 0);
6597
6598         snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6599                         hdspm->port, hdspm->port + io_extent - 1);
6600
6601         hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6602         if (!hdspm->iobase) {
6603                 snd_printk(KERN_ERR "HDSPM: "
6604                                 "unable to remap region 0x%lx-0x%lx\n",
6605                                 hdspm->port, hdspm->port + io_extent - 1);
6606                 return -EBUSY;
6607         }
6608         snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6609                         (unsigned long)hdspm->iobase, hdspm->port,
6610                         hdspm->port + io_extent - 1);
6611
6612         if (request_irq(pci->irq, snd_hdspm_interrupt,
6613                         IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6614                 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6615                 return -EBUSY;
6616         }
6617
6618         snd_printdd("use IRQ %d\n", pci->irq);
6619
6620         hdspm->irq = pci->irq;
6621
6622         snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6623                         sizeof(struct hdspm_mixer));
6624         hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6625         if (!hdspm->mixer) {
6626                 snd_printk(KERN_ERR "HDSPM: "
6627                                 "unable to kmalloc Mixer memory of %d Bytes\n",
6628                                 (int)sizeof(struct hdspm_mixer));
6629                 return -ENOMEM;
6630         }
6631
6632         hdspm->port_names_in = NULL;
6633         hdspm->port_names_out = NULL;
6634
6635         switch (hdspm->io_type) {
6636         case AES32:
6637                 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6638                 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6639                 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6640
6641                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6642                         channel_map_aes32;
6643                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6644                         channel_map_aes32;
6645                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6646                         channel_map_aes32;
6647                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6648                         texts_ports_aes32;
6649                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6650                         texts_ports_aes32;
6651                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6652                         texts_ports_aes32;
6653
6654                 hdspm->max_channels_out = hdspm->max_channels_in =
6655                         AES32_CHANNELS;
6656                 hdspm->port_names_in = hdspm->port_names_out =
6657                         texts_ports_aes32;
6658                 hdspm->channel_map_in = hdspm->channel_map_out =
6659                         channel_map_aes32;
6660
6661                 break;
6662
6663         case MADI:
6664         case MADIface:
6665                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6666                         MADI_SS_CHANNELS;
6667                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6668                         MADI_DS_CHANNELS;
6669                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6670                         MADI_QS_CHANNELS;
6671
6672                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6673                         channel_map_unity_ss;
6674                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6675                         channel_map_unity_ss;
6676                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6677                         channel_map_unity_ss;
6678
6679                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6680                         texts_ports_madi;
6681                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6682                         texts_ports_madi;
6683                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6684                         texts_ports_madi;
6685                 break;
6686
6687         case AIO:
6688                 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6689                 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6690                 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6691                 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6692                 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6693                 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6694
6695                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6696                         snd_printk(KERN_INFO "HDSPM: AEB input board found\n");
6697                         hdspm->ss_in_channels += 4;
6698                         hdspm->ds_in_channels += 4;
6699                         hdspm->qs_in_channels += 4;
6700                 }
6701
6702                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) {
6703                         snd_printk(KERN_INFO "HDSPM: AEB output board found\n");
6704                         hdspm->ss_out_channels += 4;
6705                         hdspm->ds_out_channels += 4;
6706                         hdspm->qs_out_channels += 4;
6707                 }
6708
6709                 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6710                 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6711                 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6712
6713                 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6714                 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6715                 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6716
6717                 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6718                 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6719                 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6720                 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6721                 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6722                 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6723
6724                 break;
6725
6726         case RayDAT:
6727                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6728                         RAYDAT_SS_CHANNELS;
6729                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6730                         RAYDAT_DS_CHANNELS;
6731                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6732                         RAYDAT_QS_CHANNELS;
6733
6734                 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6735                 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6736
6737                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6738                         channel_map_raydat_ss;
6739                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6740                         channel_map_raydat_ds;
6741                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6742                         channel_map_raydat_qs;
6743                 hdspm->channel_map_in = hdspm->channel_map_out =
6744                         channel_map_raydat_ss;
6745
6746                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6747                         texts_ports_raydat_ss;
6748                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6749                         texts_ports_raydat_ds;
6750                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6751                         texts_ports_raydat_qs;
6752
6753
6754                 break;
6755
6756         }
6757
6758         /* TCO detection */
6759         switch (hdspm->io_type) {
6760         case AIO:
6761         case RayDAT:
6762                 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6763                                 HDSPM_s2_tco_detect) {
6764                         hdspm->midiPorts++;
6765                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6766                                         GFP_KERNEL);
6767                         if (NULL != hdspm->tco) {
6768                                 hdspm_tco_write(hdspm);
6769                         }
6770                         snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6771                 } else {
6772                         hdspm->tco = NULL;
6773                 }
6774                 break;
6775
6776         case MADI:
6777         case AES32:
6778                 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6779                         hdspm->midiPorts++;
6780                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6781                                         GFP_KERNEL);
6782                         if (NULL != hdspm->tco) {
6783                                 hdspm_tco_write(hdspm);
6784                         }
6785                         snd_printk(KERN_INFO "HDSPM: MADI/AES TCO module found\n");
6786                 } else {
6787                         hdspm->tco = NULL;
6788                 }
6789                 break;
6790
6791         default:
6792                 hdspm->tco = NULL;
6793         }
6794
6795         /* texts */
6796         switch (hdspm->io_type) {
6797         case AES32:
6798                 if (hdspm->tco) {
6799                         hdspm->texts_autosync = texts_autosync_aes_tco;
6800                         hdspm->texts_autosync_items =
6801                                 ARRAY_SIZE(texts_autosync_aes_tco);
6802                 } else {
6803                         hdspm->texts_autosync = texts_autosync_aes;
6804                         hdspm->texts_autosync_items =
6805                                 ARRAY_SIZE(texts_autosync_aes);
6806                 }
6807                 break;
6808
6809         case MADI:
6810                 if (hdspm->tco) {
6811                         hdspm->texts_autosync = texts_autosync_madi_tco;
6812                         hdspm->texts_autosync_items = 4;
6813                 } else {
6814                         hdspm->texts_autosync = texts_autosync_madi;
6815                         hdspm->texts_autosync_items = 3;
6816                 }
6817                 break;
6818
6819         case MADIface:
6820
6821                 break;
6822
6823         case RayDAT:
6824                 if (hdspm->tco) {
6825                         hdspm->texts_autosync = texts_autosync_raydat_tco;
6826                         hdspm->texts_autosync_items = 9;
6827                 } else {
6828                         hdspm->texts_autosync = texts_autosync_raydat;
6829                         hdspm->texts_autosync_items = 8;
6830                 }
6831                 break;
6832
6833         case AIO:
6834                 if (hdspm->tco) {
6835                         hdspm->texts_autosync = texts_autosync_aio_tco;
6836                         hdspm->texts_autosync_items = 6;
6837                 } else {
6838                         hdspm->texts_autosync = texts_autosync_aio;
6839                         hdspm->texts_autosync_items = 5;
6840                 }
6841                 break;
6842
6843         }
6844
6845         tasklet_init(&hdspm->midi_tasklet,
6846                         hdspm_midi_tasklet, (unsigned long) hdspm);
6847
6848
6849         if (hdspm->io_type != MADIface) {
6850                 hdspm->serial = (hdspm_read(hdspm,
6851                                 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6852                 /* id contains either a user-provided value or the default
6853                  * NULL. If it's the default, we're safe to
6854                  * fill card->id with the serial number.
6855                  *
6856                  * If the serial number is 0xFFFFFF, then we're dealing with
6857                  * an old PCI revision that comes without a sane number. In
6858                  * this case, we don't set card->id to avoid collisions
6859                  * when running with multiple cards.
6860                  */
6861                 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6862                         sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6863                         snd_card_set_id(card, card->id);
6864                 }
6865         }
6866
6867         snd_printdd("create alsa devices.\n");
6868         err = snd_hdspm_create_alsa_devices(card, hdspm);
6869         if (err < 0)
6870                 return err;
6871
6872         snd_hdspm_initialize_midi_flush(hdspm);
6873
6874         return 0;
6875 }
6876
6877
6878 static int snd_hdspm_free(struct hdspm * hdspm)
6879 {
6880
6881         if (hdspm->port) {
6882
6883                 /* stop th audio, and cancel all interrupts */
6884                 hdspm->control_register &=
6885                     ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6886                       HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6887                       HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6888                 hdspm_write(hdspm, HDSPM_controlRegister,
6889                             hdspm->control_register);
6890         }
6891
6892         if (hdspm->irq >= 0)
6893                 free_irq(hdspm->irq, (void *) hdspm);
6894
6895         kfree(hdspm->mixer);
6896
6897         if (hdspm->iobase)
6898                 iounmap(hdspm->iobase);
6899
6900         if (hdspm->port)
6901                 pci_release_regions(hdspm->pci);
6902
6903         pci_disable_device(hdspm->pci);
6904         return 0;
6905 }
6906
6907
6908 static void snd_hdspm_card_free(struct snd_card *card)
6909 {
6910         struct hdspm *hdspm = card->private_data;
6911
6912         if (hdspm)
6913                 snd_hdspm_free(hdspm);
6914 }
6915
6916
6917 static int snd_hdspm_probe(struct pci_dev *pci,
6918                            const struct pci_device_id *pci_id)
6919 {
6920         static int dev;
6921         struct hdspm *hdspm;
6922         struct snd_card *card;
6923         int err;
6924
6925         if (dev >= SNDRV_CARDS)
6926                 return -ENODEV;
6927         if (!enable[dev]) {
6928                 dev++;
6929                 return -ENOENT;
6930         }
6931
6932         err = snd_card_create(index[dev], id[dev],
6933                         THIS_MODULE, sizeof(struct hdspm), &card);
6934         if (err < 0)
6935                 return err;
6936
6937         hdspm = card->private_data;
6938         card->private_free = snd_hdspm_card_free;
6939         hdspm->dev = dev;
6940         hdspm->pci = pci;
6941
6942         snd_card_set_dev(card, &pci->dev);
6943
6944         err = snd_hdspm_create(card, hdspm);
6945         if (err < 0) {
6946                 snd_card_free(card);
6947                 return err;
6948         }
6949
6950         if (hdspm->io_type != MADIface) {
6951                 sprintf(card->shortname, "%s_%x",
6952                         hdspm->card_name,
6953                         hdspm->serial);
6954                 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6955                         hdspm->card_name,
6956                         hdspm->serial,
6957                         hdspm->port, hdspm->irq);
6958         } else {
6959                 sprintf(card->shortname, "%s", hdspm->card_name);
6960                 sprintf(card->longname, "%s at 0x%lx, irq %d",
6961                                 hdspm->card_name, hdspm->port, hdspm->irq);
6962         }
6963
6964         err = snd_card_register(card);
6965         if (err < 0) {
6966                 snd_card_free(card);
6967                 return err;
6968         }
6969
6970         pci_set_drvdata(pci, card);
6971
6972         dev++;
6973         return 0;
6974 }
6975
6976 static void snd_hdspm_remove(struct pci_dev *pci)
6977 {
6978         snd_card_free(pci_get_drvdata(pci));
6979 }
6980
6981 static struct pci_driver hdspm_driver = {
6982         .name = KBUILD_MODNAME,
6983         .id_table = snd_hdspm_ids,
6984         .probe = snd_hdspm_probe,
6985         .remove = snd_hdspm_remove,
6986 };
6987
6988 module_pci_driver(hdspm_driver);