2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
4 * Copyright (c) 2003 Winfried Ritsch (IEM)
5 * code based on hdsp.c Paul Davis
8 * Modified 2006-06-01 for AES32 support by Remy Bruno
9 * <remy.bruno@trinnov.com>
11 * Modified 2009-04-13 for proper metering by Florian Faber
14 * Modified 2009-04-14 for native float support by Florian Faber
17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
20 * Modified 2009-04-30 added hw serial number support by Florian Faber
22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/moduleparam.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/math64.h>
50 #include <sound/core.h>
51 #include <sound/control.h>
52 #include <sound/pcm.h>
53 #include <sound/pcm_params.h>
54 #include <sound/info.h>
55 #include <sound/asoundef.h>
56 #include <sound/rawmidi.h>
57 #include <sound/hwdep.h>
58 #include <sound/initval.h>
60 #include <sound/hdspm.h>
62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
64 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
69 module_param_array(id, charp, NULL, 0444);
70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
78 "Winfried Ritsch <ritsch_AT_iem.at>, "
79 "Paul Davis <paul@linuxaudiosystems.com>, "
80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
81 "Remy Bruno <remy.bruno@trinnov.com>, "
82 "Florian Faber <faberman@linuxproaudio.org>, "
83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
85 MODULE_DESCRIPTION("RME HDSPM");
86 MODULE_LICENSE("GPL");
87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
89 /* --- Write registers. ---
90 These are defined as byte-offsets from the iobase value. */
92 #define HDSPM_WR_SETTINGS 0
93 #define HDSPM_outputBufferAddress 32
94 #define HDSPM_inputBufferAddress 36
95 #define HDSPM_controlRegister 64
96 #define HDSPM_interruptConfirmation 96
97 #define HDSPM_control2Reg 256 /* not in specs ???????? */
98 #define HDSPM_freqReg 256 /* for AES32 */
99 #define HDSPM_midiDataOut0 352 /* just believe in old code */
100 #define HDSPM_midiDataOut1 356
101 #define HDSPM_eeprom_wr 384 /* for AES32 */
103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut 8192
110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
116 /* --- Read registers. ---
117 These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister 0
119 /*#define HDSPM_statusRegister2 96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121 * offset 192, for AES32 *and* MADI
122 * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2 192
124 #define HDSPM_timecodeRegister 128
127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192
132 #define HDSPM_RD_TCO 256
133 #define HDSPM_RD_PLL_FREQ 512
134 #define HDSPM_WR_TCO 128
136 #define HDSPM_TCO1_TCO_lock 0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
144 #define HDSPM_TCO1_set_TC 0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800
149 #define HDSPM_TCO2_TC_run 0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
154 #define HDSPM_TCO2_set_jam_sync 0x00200000
155 #define HDSPM_TCO2_set_flywheel 0x00400000
157 #define HDSPM_TCO2_set_01_4 0x01000000
158 #define HDSPM_TCO2_set_pull_down 0x02000000
159 #define HDSPM_TCO2_set_pull_up 0x04000000
160 #define HDSPM_TCO2_set_freq 0x08000000
161 #define HDSPM_TCO2_set_term_75R 0x10000000
162 #define HDSPM_TCO2_set_input_LSB 0x20000000
163 #define HDSPM_TCO2_set_input_MSB 0x40000000
164 #define HDSPM_TCO2_set_freq_from_app 0x80000000
167 #define HDSPM_midiDataOut0 352
168 #define HDSPM_midiDataOut1 356
169 #define HDSPM_midiDataOut2 368
171 #define HDSPM_midiDataIn0 360
172 #define HDSPM_midiDataIn1 364
173 #define HDSPM_midiDataIn2 372
174 #define HDSPM_midiDataIn3 376
176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0 384
178 #define HDSPM_midiStatusOut1 388
179 #define HDSPM_midiStatusOut2 400
181 #define HDSPM_midiStatusIn0 392
182 #define HDSPM_midiStatusIn1 396
183 #define HDSPM_midiStatusIn2 404
184 #define HDSPM_midiStatusIn3 408
187 /* the meters are regular i/o-mapped registers, but offset
188 considerably from the rest. the peak registers are reset
189 when read; the least-significant 4 bits are full-scale counters;
190 the actual peak value is in the most-significant 24 bits.
193 #define HDSPM_MADI_INPUT_PEAK 4096
194 #define HDSPM_MADI_PLAYBACK_PEAK 4352
195 #define HDSPM_MADI_OUTPUT_PEAK 4608
197 #define HDSPM_MADI_INPUT_RMS_L 6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400
199 #define HDSPM_MADI_OUTPUT_RMS_L 6656
201 #define HDSPM_MADI_INPUT_RMS_H 7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424
203 #define HDSPM_MADI_OUTPUT_RMS_H 7680
205 /* --- Control Register bits --------- */
206 #define HDSPM_Start (1<<0) /* start engine */
208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1 (1<<2) /* where n is defined */
210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings
214 register [RayDAT, AIO] */
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
225 56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
229 0=off, 1=on */ /* MADI ONLY */
230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
237 #define HDSPM_SyncRef2 (1<<13)
238 #define HDSPM_SyncRef3 (1<<25)
240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
242 AES additional bits in
243 lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT 0x2000000
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
259 #define HDSPM_wclk_sel (1<<30)
261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical 0
267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269 HDSPM_SyncRef2|HDSPM_SyncRef3)
271 #define HDSPM_c0_SyncRef0 0x2
272 #define HDSPM_c0_SyncRef1 0x4
273 #define HDSPM_c0_SyncRef2 0x8
274 #define HDSPM_c0_SyncRef3 0x10
275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO 2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3
283 #define HDSPM_Frequency32KHz HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK 1
299 #define HDSPM_SYNC_CHECK_SYNC 2
301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD 0
303 #define HDSPM_AUTOSYNC_FROM_MADI 1
304 #define HDSPM_AUTOSYNC_FROM_TCO 2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
306 #define HDSPM_AUTOSYNC_FROM_NONE 4
308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0 /* optical */
310 #define HDSPM_COAXIAL 1 /* BNC */
312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
318 /* --- control2 register bits --- */
319 #define HDSPM_TMS (1<<0)
320 #define HDSPM_TCK (1<<1)
321 #define HDSPM_TDI (1<<2)
322 #define HDSPM_JTAG (1<<3)
323 #define HDSPM_PWDN (1<<4)
324 #define HDSPM_PROGRAM (1<<5)
325 #define HDSPM_CONFIG_MODE_0 (1<<6)
326 #define HDSPM_CONFIG_MODE_1 (1<<7)
327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE (1<<9)
329 #define HDSPM_RD_MULTIPLE (1<<10)
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332 that do not conflict with specific bits for AES32 seem to be valid also
335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */
344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351 /* since 64byte accurate, last 6 bits are not used */
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
365 #define HDSPM_tco_detect 0x08000000
366 #define HDSPM_tco_lock 0x20000000
368 #define HDSPM_s2_tco_detect 0x00000040
369 #define HDSPM_s2_AEBO_D 0x00000080
370 #define HDSPM_s2_AEBI_D 0x00000100
373 #define HDSPM_midi0IRQPending 0x40000000
374 #define HDSPM_midi1IRQPending 0x80000000
375 #define HDSPM_midi2IRQPending 0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending 0x00200000
379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381 HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
392 /* Status2 Register bits */ /* MADI ONLY */
394 #define HDSPM_version0 (1<<0) /* not really defined but I guess */
395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2)
398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */
404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */
406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000
409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0)
417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2)
420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
423 #define HDSPM_status1_F_0 0x0400000
424 #define HDSPM_status1_F_1 0x0800000
425 #define HDSPM_status1_F_2 0x1000000
426 #define HDSPM_status1_F_3 0x2000000
427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
432 #define HDSPM_SelSyncRef_WORD 0
433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
440 For AES32, bits for status, status2 and timecode are different
443 #define HDSPM_AES32_wcLock 0x0200000
444 #define HDSPM_AES32_wcFreq_bit 22
445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
447 #define HDSPM_AES32_syncref_bit 16
448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
463 #define HDSPM_LockAES 0x80
464 #define HDSPM_LockAES1 0x80
465 #define HDSPM_LockAES2 0x40
466 #define HDSPM_LockAES3 0x20
467 #define HDSPM_LockAES4 0x10
468 #define HDSPM_LockAES5 0x8
469 #define HDSPM_LockAES6 0x4
470 #define HDSPM_LockAES7 0x2
471 #define HDSPM_LockAES8 0x1
474 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
486 NB: Timecode register doesn't seem to work on AES32 card revision 230
490 #define UNITY_GAIN 32768 /* = 65536/2 */
491 #define MINUS_INFINITY_GAIN 0
493 /* Number of channels for different Speed Modes */
494 #define MADI_SS_CHANNELS 64
495 #define MADI_DS_CHANNELS 32
496 #define MADI_QS_CHANNELS 16
498 #define RAYDAT_SS_CHANNELS 36
499 #define RAYDAT_DS_CHANNELS 20
500 #define RAYDAT_QS_CHANNELS 12
502 #define AIO_IN_SS_CHANNELS 14
503 #define AIO_IN_DS_CHANNELS 10
504 #define AIO_IN_QS_CHANNELS 8
505 #define AIO_OUT_SS_CHANNELS 16
506 #define AIO_OUT_DS_CHANNELS 12
507 #define AIO_OUT_QS_CHANNELS 10
509 #define AES32_CHANNELS 16
511 /* the size of a substream (1 mono data stream) */
512 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
513 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
515 /* the size of the area we need to allocate for DMA transfers. the
516 size is the same regardless of the number of channels, and
517 also the latency to use.
518 for one direction !!!
520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
523 /* revisions >= 230 indicate AES32 card */
524 #define HDSPM_MADI_OLD_REV 207
525 #define HDSPM_MADI_REV 210
526 #define HDSPM_RAYDAT_REV 211
527 #define HDSPM_AIO_REV 212
528 #define HDSPM_MADIFACE_REV 213
529 #define HDSPM_AES_REV 240
530 #define HDSPM_AES32_REV 234
531 #define HDSPM_AES32_OLD_REV 233
533 /* speed factor modes */
534 #define HDSPM_SPEED_SINGLE 0
535 #define HDSPM_SPEED_DOUBLE 1
536 #define HDSPM_SPEED_QUAD 2
538 /* names for speed modes */
539 static char *hdspm_speed_names[] = { "single", "double", "quad" };
541 static char *texts_autosync_aes_tco[] = { "Word Clock",
542 "AES1", "AES2", "AES3", "AES4",
543 "AES5", "AES6", "AES7", "AES8",
545 static char *texts_autosync_aes[] = { "Word Clock",
546 "AES1", "AES2", "AES3", "AES4",
547 "AES5", "AES6", "AES7", "AES8" };
548 static char *texts_autosync_madi_tco[] = { "Word Clock",
549 "MADI", "TCO", "Sync In" };
550 static char *texts_autosync_madi[] = { "Word Clock",
553 static char *texts_autosync_raydat_tco[] = {
555 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
556 "AES", "SPDIF", "TCO", "Sync In"
558 static char *texts_autosync_raydat[] = {
560 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
561 "AES", "SPDIF", "Sync In"
563 static char *texts_autosync_aio_tco[] = {
565 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
567 static char *texts_autosync_aio[] = { "Word Clock",
568 "ADAT", "AES", "SPDIF", "Sync In" };
570 static char *texts_freq[] = {
583 static char *texts_ports_madi[] = {
584 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
585 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
586 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
587 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
588 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
589 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
590 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
591 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
592 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
593 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
594 "MADI.61", "MADI.62", "MADI.63", "MADI.64",
598 static char *texts_ports_raydat_ss[] = {
599 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
600 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
601 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
602 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
603 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
604 "ADAT4.7", "ADAT4.8",
609 static char *texts_ports_raydat_ds[] = {
610 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
611 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
612 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
613 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
618 static char *texts_ports_raydat_qs[] = {
619 "ADAT1.1", "ADAT1.2",
620 "ADAT2.1", "ADAT2.2",
621 "ADAT3.1", "ADAT3.2",
622 "ADAT4.1", "ADAT4.2",
628 static char *texts_ports_aio_in_ss[] = {
629 "Analogue.L", "Analogue.R",
631 "SPDIF.L", "SPDIF.R",
632 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
636 static char *texts_ports_aio_out_ss[] = {
637 "Analogue.L", "Analogue.R",
639 "SPDIF.L", "SPDIF.R",
640 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
645 static char *texts_ports_aio_in_ds[] = {
646 "Analogue.L", "Analogue.R",
648 "SPDIF.L", "SPDIF.R",
649 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
652 static char *texts_ports_aio_out_ds[] = {
653 "Analogue.L", "Analogue.R",
655 "SPDIF.L", "SPDIF.R",
656 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
660 static char *texts_ports_aio_in_qs[] = {
661 "Analogue.L", "Analogue.R",
663 "SPDIF.L", "SPDIF.R",
664 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
667 static char *texts_ports_aio_out_qs[] = {
668 "Analogue.L", "Analogue.R",
670 "SPDIF.L", "SPDIF.R",
671 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
675 static char *texts_ports_aes32[] = {
676 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
677 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
681 /* These tables map the ALSA channels 1..N to the channels that we
682 need to use in order to find the relevant channel buffer. RME
683 refers to this kind of mapping as between "the ADAT channel and
684 the DMA channel." We index it using the logical audio channel,
685 and the value is the DMA channel (i.e. channel buffer number)
686 where the data for that channel can be read/written from/to.
689 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
690 0, 1, 2, 3, 4, 5, 6, 7,
691 8, 9, 10, 11, 12, 13, 14, 15,
692 16, 17, 18, 19, 20, 21, 22, 23,
693 24, 25, 26, 27, 28, 29, 30, 31,
694 32, 33, 34, 35, 36, 37, 38, 39,
695 40, 41, 42, 43, 44, 45, 46, 47,
696 48, 49, 50, 51, 52, 53, 54, 55,
697 56, 57, 58, 59, 60, 61, 62, 63
700 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
701 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
702 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
703 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
704 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
708 -1, -1, -1, -1, -1, -1, -1, -1,
709 -1, -1, -1, -1, -1, -1, -1, -1,
710 -1, -1, -1, -1, -1, -1, -1, -1,
713 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
714 4, 5, 6, 7, /* ADAT 1 */
715 8, 9, 10, 11, /* ADAT 2 */
716 12, 13, 14, 15, /* ADAT 3 */
717 16, 17, 18, 19, /* ADAT 4 */
721 -1, -1, -1, -1, -1, -1, -1, -1,
722 -1, -1, -1, -1, -1, -1, -1, -1,
723 -1, -1, -1, -1, -1, -1, -1, -1,
724 -1, -1, -1, -1, -1, -1, -1, -1,
725 -1, -1, -1, -1, -1, -1, -1, -1,
728 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
736 -1, -1, -1, -1, -1, -1, -1, -1,
737 -1, -1, -1, -1, -1, -1, -1, -1,
738 -1, -1, -1, -1, -1, -1, -1, -1,
739 -1, -1, -1, -1, -1, -1, -1, -1,
740 -1, -1, -1, -1, -1, -1, -1, -1,
741 -1, -1, -1, -1, -1, -1, -1, -1,
744 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
747 10, 11, /* spdif in */
748 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
750 -1, -1, -1, -1, -1, -1, -1, -1,
751 -1, -1, -1, -1, -1, -1, -1, -1,
752 -1, -1, -1, -1, -1, -1, -1, -1,
753 -1, -1, -1, -1, -1, -1, -1, -1,
754 -1, -1, -1, -1, -1, -1, -1, -1,
755 -1, -1, -1, -1, -1, -1, -1, -1,
758 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
761 10, 11, /* spdif out */
762 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
763 6, 7, /* phone out */
764 -1, -1, -1, -1, -1, -1, -1, -1,
765 -1, -1, -1, -1, -1, -1, -1, -1,
766 -1, -1, -1, -1, -1, -1, -1, -1,
767 -1, -1, -1, -1, -1, -1, -1, -1,
768 -1, -1, -1, -1, -1, -1, -1, -1,
769 -1, -1, -1, -1, -1, -1, -1, -1,
772 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
775 10, 11, /* spdif in */
776 12, 14, 16, 18, /* adat in */
777 -1, -1, -1, -1, -1, -1,
778 -1, -1, -1, -1, -1, -1, -1, -1,
779 -1, -1, -1, -1, -1, -1, -1, -1,
780 -1, -1, -1, -1, -1, -1, -1, -1,
781 -1, -1, -1, -1, -1, -1, -1, -1,
782 -1, -1, -1, -1, -1, -1, -1, -1,
783 -1, -1, -1, -1, -1, -1, -1, -1
786 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
789 10, 11, /* spdif out */
790 12, 14, 16, 18, /* adat out */
791 6, 7, /* phone out */
793 -1, -1, -1, -1, -1, -1, -1, -1,
794 -1, -1, -1, -1, -1, -1, -1, -1,
795 -1, -1, -1, -1, -1, -1, -1, -1,
796 -1, -1, -1, -1, -1, -1, -1, -1,
797 -1, -1, -1, -1, -1, -1, -1, -1,
798 -1, -1, -1, -1, -1, -1, -1, -1
801 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
804 10, 11, /* spdif in */
805 12, 16, /* adat in */
806 -1, -1, -1, -1, -1, -1, -1, -1,
807 -1, -1, -1, -1, -1, -1, -1, -1,
808 -1, -1, -1, -1, -1, -1, -1, -1,
809 -1, -1, -1, -1, -1, -1, -1, -1,
810 -1, -1, -1, -1, -1, -1, -1, -1,
811 -1, -1, -1, -1, -1, -1, -1, -1,
812 -1, -1, -1, -1, -1, -1, -1, -1
815 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
818 10, 11, /* spdif out */
819 12, 16, /* adat out */
820 6, 7, /* phone out */
821 -1, -1, -1, -1, -1, -1,
822 -1, -1, -1, -1, -1, -1, -1, -1,
823 -1, -1, -1, -1, -1, -1, -1, -1,
824 -1, -1, -1, -1, -1, -1, -1, -1,
825 -1, -1, -1, -1, -1, -1, -1, -1,
826 -1, -1, -1, -1, -1, -1, -1, -1,
827 -1, -1, -1, -1, -1, -1, -1, -1
830 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
831 0, 1, 2, 3, 4, 5, 6, 7,
832 8, 9, 10, 11, 12, 13, 14, 15,
833 -1, -1, -1, -1, -1, -1, -1, -1,
834 -1, -1, -1, -1, -1, -1, -1, -1,
835 -1, -1, -1, -1, -1, -1, -1, -1,
836 -1, -1, -1, -1, -1, -1, -1, -1,
837 -1, -1, -1, -1, -1, -1, -1, -1,
838 -1, -1, -1, -1, -1, -1, -1, -1
844 struct snd_rawmidi *rmidi;
845 struct snd_rawmidi_substream *input;
846 struct snd_rawmidi_substream *output;
847 char istimer; /* timer in use */
848 struct timer_list timer;
865 int term; /* 0 = off, 1 = on */
870 /* only one playback and/or capture stream */
871 struct snd_pcm_substream *capture_substream;
872 struct snd_pcm_substream *playback_substream;
874 char *card_name; /* for procinfo */
875 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
879 int monitor_outs; /* set up monitoring outs init flag */
881 u32 control_register; /* cached value */
882 u32 control2_register; /* cached value */
883 u32 settings_register;
885 struct hdspm_midi midi[4];
886 struct tasklet_struct midi_tasklet;
889 unsigned char ss_in_channels;
890 unsigned char ds_in_channels;
891 unsigned char qs_in_channels;
892 unsigned char ss_out_channels;
893 unsigned char ds_out_channels;
894 unsigned char qs_out_channels;
896 unsigned char max_channels_in;
897 unsigned char max_channels_out;
899 signed char *channel_map_in;
900 signed char *channel_map_out;
902 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
903 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
905 char **port_names_in;
906 char **port_names_out;
908 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
909 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
911 unsigned char *playback_buffer; /* suitably aligned address */
912 unsigned char *capture_buffer; /* suitably aligned address */
914 pid_t capture_pid; /* process id which uses capture */
915 pid_t playback_pid; /* process id which uses capture */
916 int running; /* running status */
918 int last_external_sample_rate; /* samplerate mystic ... */
919 int last_internal_sample_rate;
920 int system_sample_rate;
922 int dev; /* Hardware vars... */
925 void __iomem *iobase;
927 int irq_count; /* for debug */
930 struct snd_card *card; /* one card */
931 struct snd_pcm *pcm; /* has one pcm */
932 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
933 struct pci_dev *pci; /* and an pci info */
936 /* fast alsa mixer */
937 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
938 /* but input to much, so not used */
939 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
940 /* full mixer accessible over mixer ioctl or hwdep-device */
941 struct hdspm_mixer *mixer;
943 struct hdspm_tco *tco; /* NULL if no TCO detected */
945 char **texts_autosync;
946 int texts_autosync_items;
948 cycles_t last_interrupt;
950 struct hdspm_peak_rms peak_rms;
954 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
956 .vendor = PCI_VENDOR_ID_XILINX,
957 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
958 .subvendor = PCI_ANY_ID,
959 .subdevice = PCI_ANY_ID,
966 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
969 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
970 struct hdspm * hdspm);
971 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
972 struct hdspm * hdspm);
974 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
975 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
976 static int hdspm_autosync_ref(struct hdspm *hdspm);
977 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
978 static void hdspm_set_sgbuf(struct hdspm *hdspm,
979 struct snd_pcm_substream *substream,
980 unsigned int reg, int channels);
982 static inline int HDSPM_bit2freq(int n)
984 static const int bit2freq_tab[] = {
985 0, 32000, 44100, 48000, 64000, 88200,
986 96000, 128000, 176400, 192000 };
989 return bit2freq_tab[n];
992 /* Write/read to/from HDSPM with Adresses in Bytes
993 not words but only 32Bit writes are allowed */
995 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
998 writel(val, hdspm->iobase + reg);
1001 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1003 return readl(hdspm->iobase + reg);
1006 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1007 mixer is write only on hardware so we have to cache him for read
1008 each fader is a u32, but uses only the first 16 bit */
1010 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1013 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1016 return hdspm->mixer->ch[chan].in[in];
1019 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1022 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1024 return hdspm->mixer->ch[chan].pb[pb];
1027 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1028 unsigned int in, unsigned short data)
1030 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1034 HDSPM_MADI_mixerBase +
1035 ((in + 128 * chan) * sizeof(u32)),
1036 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1040 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1041 unsigned int pb, unsigned short data)
1043 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1047 HDSPM_MADI_mixerBase +
1048 ((64 + pb + 128 * chan) * sizeof(u32)),
1049 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1054 /* enable DMA for specific channels, now available for DSP-MADI */
1055 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1057 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1060 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1062 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1065 /* check if same process is writing and reading */
1066 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1068 unsigned long flags;
1071 spin_lock_irqsave(&hdspm->lock, flags);
1072 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1073 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1076 spin_unlock_irqrestore(&hdspm->lock, flags);
1080 /* check for external sample rate */
1081 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1083 unsigned int status, status2, timecode;
1084 int syncref, rate = 0, rate_bits;
1086 switch (hdspm->io_type) {
1088 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1089 status = hdspm_read(hdspm, HDSPM_statusRegister);
1090 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1092 syncref = hdspm_autosync_ref(hdspm);
1094 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1095 status & HDSPM_AES32_wcLock)
1096 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1098 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1099 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1100 status2 & (HDSPM_LockAES >>
1101 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1102 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1107 status = hdspm_read(hdspm, HDSPM_statusRegister);
1109 if (!(status & HDSPM_madiLock)) {
1110 rate = 0; /* no lock */
1112 switch (status & (HDSPM_status1_freqMask)) {
1113 case HDSPM_status1_F_0*1:
1114 rate = 32000; break;
1115 case HDSPM_status1_F_0*2:
1116 rate = 44100; break;
1117 case HDSPM_status1_F_0*3:
1118 rate = 48000; break;
1119 case HDSPM_status1_F_0*4:
1120 rate = 64000; break;
1121 case HDSPM_status1_F_0*5:
1122 rate = 88200; break;
1123 case HDSPM_status1_F_0*6:
1124 rate = 96000; break;
1125 case HDSPM_status1_F_0*7:
1126 rate = 128000; break;
1127 case HDSPM_status1_F_0*8:
1128 rate = 176400; break;
1129 case HDSPM_status1_F_0*9:
1130 rate = 192000; break;
1141 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1142 status = hdspm_read(hdspm, HDSPM_statusRegister);
1145 /* if wordclock has synced freq and wordclock is valid */
1146 if ((status2 & HDSPM_wcLock) != 0 &&
1147 (status2 & HDSPM_SelSyncRef0) == 0) {
1149 rate_bits = status2 & HDSPM_wcFreqMask;
1152 switch (rate_bits) {
1153 case HDSPM_wcFreq32:
1156 case HDSPM_wcFreq44_1:
1159 case HDSPM_wcFreq48:
1162 case HDSPM_wcFreq64:
1165 case HDSPM_wcFreq88_2:
1168 case HDSPM_wcFreq96:
1177 /* if rate detected and Syncref is Word than have it,
1178 * word has priority to MADI
1181 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1184 /* maybe a madi input (which is taken if sel sync is madi) */
1185 if (status & HDSPM_madiLock) {
1186 rate_bits = status & HDSPM_madiFreqMask;
1188 switch (rate_bits) {
1189 case HDSPM_madiFreq32:
1192 case HDSPM_madiFreq44_1:
1195 case HDSPM_madiFreq48:
1198 case HDSPM_madiFreq64:
1201 case HDSPM_madiFreq88_2:
1204 case HDSPM_madiFreq96:
1207 case HDSPM_madiFreq128:
1210 case HDSPM_madiFreq176_4:
1213 case HDSPM_madiFreq192:
1227 /* Latency function */
1228 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1230 hdspm->period_bytes = 1 << ((hdspm_decode_latency(hdspm->control_register) + 8));
1234 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1238 position = hdspm_read(hdspm, HDSPM_statusRegister);
1240 switch (hdspm->io_type) {
1243 position &= HDSPM_BufferPositionMask;
1244 position /= 4; /* Bytes per sample */
1247 position = (position & HDSPM_BufferID) ?
1248 (hdspm->period_bytes / 4) : 0;
1255 static inline void hdspm_start_audio(struct hdspm * s)
1257 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1258 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1261 static inline void hdspm_stop_audio(struct hdspm * s)
1263 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1264 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1267 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1268 static void hdspm_silence_playback(struct hdspm *hdspm)
1271 int n = hdspm->period_bytes;
1272 void *buf = hdspm->playback_buffer;
1277 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1279 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1283 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1287 spin_lock_irq(&s->lock);
1295 s->control_register &= ~HDSPM_LatencyMask;
1296 s->control_register |= hdspm_encode_latency(n);
1298 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1300 hdspm_compute_period_size(s);
1302 spin_unlock_irq(&s->lock);
1307 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1314 switch (hdspm->io_type) {
1317 freq_const = 110069313433624ULL;
1321 freq_const = 104857600000000ULL;
1324 freq_const = 131072000000000ULL;
1327 return div_u64(freq_const, period);
1331 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1337 else if (rate >= 56000)
1340 switch (hdspm->io_type) {
1342 n = 131072000000000ULL; /* 125 MHz */
1346 n = 110069313433624ULL; /* 105 MHz */
1350 n = 104857600000000ULL; /* 100 MHz */
1354 n = div_u64(n, rate);
1355 /* n should be less than 2^32 for being written to FREQ register */
1356 snd_BUG_ON(n >> 32);
1357 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1360 /* dummy set rate lets see what happens */
1361 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1366 int current_speed, target_speed;
1368 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1369 it (e.g. during module initialization).
1372 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1375 if (called_internally) {
1377 /* request from ctl or card initialization
1378 just make a warning an remember setting
1379 for future master mode switching */
1381 snd_printk(KERN_WARNING "HDSPM: "
1382 "Warning: device is not running "
1383 "as a clock master.\n");
1387 /* hw_param request while in AutoSync mode */
1389 hdspm_external_sample_rate(hdspm);
1391 if (hdspm_autosync_ref(hdspm) ==
1392 HDSPM_AUTOSYNC_FROM_NONE) {
1394 snd_printk(KERN_WARNING "HDSPM: "
1395 "Detected no Externel Sync \n");
1398 } else if (rate != external_freq) {
1400 snd_printk(KERN_WARNING "HDSPM: "
1401 "Warning: No AutoSync source for "
1402 "requested rate\n");
1408 current_rate = hdspm->system_sample_rate;
1410 /* Changing between Singe, Double and Quad speed is not
1411 allowed if any substreams are open. This is because such a change
1412 causes a shift in the location of the DMA buffers and a reduction
1413 in the number of available buffers.
1415 Note that a similar but essentially insoluble problem exists for
1416 externally-driven rate changes. All we can do is to flag rate
1417 changes in the read/write routines.
1420 if (current_rate <= 48000)
1421 current_speed = HDSPM_SPEED_SINGLE;
1422 else if (current_rate <= 96000)
1423 current_speed = HDSPM_SPEED_DOUBLE;
1425 current_speed = HDSPM_SPEED_QUAD;
1428 target_speed = HDSPM_SPEED_SINGLE;
1429 else if (rate <= 96000)
1430 target_speed = HDSPM_SPEED_DOUBLE;
1432 target_speed = HDSPM_SPEED_QUAD;
1436 rate_bits = HDSPM_Frequency32KHz;
1439 rate_bits = HDSPM_Frequency44_1KHz;
1442 rate_bits = HDSPM_Frequency48KHz;
1445 rate_bits = HDSPM_Frequency64KHz;
1448 rate_bits = HDSPM_Frequency88_2KHz;
1451 rate_bits = HDSPM_Frequency96KHz;
1454 rate_bits = HDSPM_Frequency128KHz;
1457 rate_bits = HDSPM_Frequency176_4KHz;
1460 rate_bits = HDSPM_Frequency192KHz;
1466 if (current_speed != target_speed
1467 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1470 "cannot change from %s speed to %s speed mode "
1471 "(capture PID = %d, playback PID = %d)\n",
1472 hdspm_speed_names[current_speed],
1473 hdspm_speed_names[target_speed],
1474 hdspm->capture_pid, hdspm->playback_pid);
1478 hdspm->control_register &= ~HDSPM_FrequencyMask;
1479 hdspm->control_register |= rate_bits;
1480 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1482 /* For AES32, need to set DDS value in FREQ register
1483 For MADI, also apparently */
1484 hdspm_set_dds_value(hdspm, rate);
1486 if (AES32 == hdspm->io_type && rate != current_rate)
1487 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1489 hdspm->system_sample_rate = rate;
1491 if (rate <= 48000) {
1492 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1493 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1494 hdspm->max_channels_in = hdspm->ss_in_channels;
1495 hdspm->max_channels_out = hdspm->ss_out_channels;
1496 hdspm->port_names_in = hdspm->port_names_in_ss;
1497 hdspm->port_names_out = hdspm->port_names_out_ss;
1498 } else if (rate <= 96000) {
1499 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1500 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1501 hdspm->max_channels_in = hdspm->ds_in_channels;
1502 hdspm->max_channels_out = hdspm->ds_out_channels;
1503 hdspm->port_names_in = hdspm->port_names_in_ds;
1504 hdspm->port_names_out = hdspm->port_names_out_ds;
1506 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1507 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1508 hdspm->max_channels_in = hdspm->qs_in_channels;
1509 hdspm->max_channels_out = hdspm->qs_out_channels;
1510 hdspm->port_names_in = hdspm->port_names_in_qs;
1511 hdspm->port_names_out = hdspm->port_names_out_qs;
1520 /* mainly for init to 0 on load */
1521 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1526 if (sgain > UNITY_GAIN)
1533 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1534 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1535 hdspm_write_in_gain(hdspm, i, j, gain);
1536 hdspm_write_pb_gain(hdspm, i, j, gain);
1540 /*----------------------------------------------------------------------------
1542 ----------------------------------------------------------------------------*/
1544 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1547 /* the hardware already does the relevant bit-mask with 0xff */
1548 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1551 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1554 /* the hardware already does the relevant bit-mask with 0xff */
1555 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1558 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1560 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1563 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1565 int fifo_bytes_used;
1567 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1569 if (fifo_bytes_used < 128)
1570 return 128 - fifo_bytes_used;
1575 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1577 while (snd_hdspm_midi_input_available (hdspm, id))
1578 snd_hdspm_midi_read_byte (hdspm, id);
1581 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1583 unsigned long flags;
1587 unsigned char buf[128];
1589 /* Output is not interrupt driven */
1591 spin_lock_irqsave (&hmidi->lock, flags);
1592 if (hmidi->output &&
1593 !snd_rawmidi_transmit_empty (hmidi->output)) {
1594 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1596 if (n_pending > 0) {
1597 if (n_pending > (int)sizeof (buf))
1598 n_pending = sizeof (buf);
1600 to_write = snd_rawmidi_transmit (hmidi->output, buf,
1603 for (i = 0; i < to_write; ++i)
1604 snd_hdspm_midi_write_byte (hmidi->hdspm,
1610 spin_unlock_irqrestore (&hmidi->lock, flags);
1614 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1616 unsigned char buf[128]; /* this buffer is designed to match the MIDI
1619 unsigned long flags;
1623 spin_lock_irqsave (&hmidi->lock, flags);
1624 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1625 if (n_pending > 0) {
1627 if (n_pending > (int)sizeof (buf))
1628 n_pending = sizeof (buf);
1629 for (i = 0; i < n_pending; ++i)
1630 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1633 snd_rawmidi_receive (hmidi->input, buf,
1636 /* flush the MIDI input FIFO */
1638 snd_hdspm_midi_read_byte (hmidi->hdspm,
1643 spin_unlock_irqrestore(&hmidi->lock, flags);
1645 spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1646 hmidi->hdspm->control_register |= hmidi->ie;
1647 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1648 hmidi->hdspm->control_register);
1649 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1651 return snd_hdspm_midi_output_write (hmidi);
1655 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1657 struct hdspm *hdspm;
1658 struct hdspm_midi *hmidi;
1659 unsigned long flags;
1661 hmidi = substream->rmidi->private_data;
1662 hdspm = hmidi->hdspm;
1664 spin_lock_irqsave (&hdspm->lock, flags);
1666 if (!(hdspm->control_register & hmidi->ie)) {
1667 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1668 hdspm->control_register |= hmidi->ie;
1671 hdspm->control_register &= ~hmidi->ie;
1674 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1675 spin_unlock_irqrestore (&hdspm->lock, flags);
1678 static void snd_hdspm_midi_output_timer(unsigned long data)
1680 struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1681 unsigned long flags;
1683 snd_hdspm_midi_output_write(hmidi);
1684 spin_lock_irqsave (&hmidi->lock, flags);
1686 /* this does not bump hmidi->istimer, because the
1687 kernel automatically removed the timer when it
1688 expired, and we are now adding it back, thus
1689 leaving istimer wherever it was set before.
1692 if (hmidi->istimer) {
1693 hmidi->timer.expires = 1 + jiffies;
1694 add_timer(&hmidi->timer);
1697 spin_unlock_irqrestore (&hmidi->lock, flags);
1701 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1703 struct hdspm_midi *hmidi;
1704 unsigned long flags;
1706 hmidi = substream->rmidi->private_data;
1707 spin_lock_irqsave (&hmidi->lock, flags);
1709 if (!hmidi->istimer) {
1710 init_timer(&hmidi->timer);
1711 hmidi->timer.function = snd_hdspm_midi_output_timer;
1712 hmidi->timer.data = (unsigned long) hmidi;
1713 hmidi->timer.expires = 1 + jiffies;
1714 add_timer(&hmidi->timer);
1718 if (hmidi->istimer && --hmidi->istimer <= 0)
1719 del_timer (&hmidi->timer);
1721 spin_unlock_irqrestore (&hmidi->lock, flags);
1723 snd_hdspm_midi_output_write(hmidi);
1726 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1728 struct hdspm_midi *hmidi;
1730 hmidi = substream->rmidi->private_data;
1731 spin_lock_irq (&hmidi->lock);
1732 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1733 hmidi->input = substream;
1734 spin_unlock_irq (&hmidi->lock);
1739 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1741 struct hdspm_midi *hmidi;
1743 hmidi = substream->rmidi->private_data;
1744 spin_lock_irq (&hmidi->lock);
1745 hmidi->output = substream;
1746 spin_unlock_irq (&hmidi->lock);
1751 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1753 struct hdspm_midi *hmidi;
1755 snd_hdspm_midi_input_trigger (substream, 0);
1757 hmidi = substream->rmidi->private_data;
1758 spin_lock_irq (&hmidi->lock);
1759 hmidi->input = NULL;
1760 spin_unlock_irq (&hmidi->lock);
1765 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1767 struct hdspm_midi *hmidi;
1769 snd_hdspm_midi_output_trigger (substream, 0);
1771 hmidi = substream->rmidi->private_data;
1772 spin_lock_irq (&hmidi->lock);
1773 hmidi->output = NULL;
1774 spin_unlock_irq (&hmidi->lock);
1779 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1781 .open = snd_hdspm_midi_output_open,
1782 .close = snd_hdspm_midi_output_close,
1783 .trigger = snd_hdspm_midi_output_trigger,
1786 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1788 .open = snd_hdspm_midi_input_open,
1789 .close = snd_hdspm_midi_input_close,
1790 .trigger = snd_hdspm_midi_input_trigger,
1793 static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1794 struct hdspm *hdspm, int id)
1799 hdspm->midi[id].id = id;
1800 hdspm->midi[id].hdspm = hdspm;
1801 spin_lock_init (&hdspm->midi[id].lock);
1804 if (MADIface == hdspm->io_type) {
1805 /* MIDI-over-MADI on HDSPe MADIface */
1806 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1807 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1808 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1809 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1810 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1811 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1813 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1814 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1815 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1816 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1817 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1818 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1820 } else if (1 == id) {
1821 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1822 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1823 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1824 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1825 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1826 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1827 } else if ((2 == id) && (MADI == hdspm->io_type)) {
1828 /* MIDI-over-MADI on HDSPe MADI */
1829 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1830 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1831 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1832 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1833 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1834 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1835 } else if (2 == id) {
1836 /* TCO MTC, read only */
1837 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1838 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1839 hdspm->midi[2].dataOut = -1;
1840 hdspm->midi[2].statusOut = -1;
1841 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1842 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1843 } else if (3 == id) {
1844 /* TCO MTC on HDSPe MADI */
1845 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1846 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1847 hdspm->midi[3].dataOut = -1;
1848 hdspm->midi[3].statusOut = -1;
1849 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1850 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1853 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1854 (MADIface == hdspm->io_type)))) {
1855 if ((id == 0) && (MADIface == hdspm->io_type)) {
1856 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1857 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1858 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1860 sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1862 err = snd_rawmidi_new(card, buf, id, 1, 1,
1863 &hdspm->midi[id].rmidi);
1867 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1869 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1871 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1872 SNDRV_RAWMIDI_STREAM_OUTPUT,
1873 &snd_hdspm_midi_output);
1874 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1875 SNDRV_RAWMIDI_STREAM_INPUT,
1876 &snd_hdspm_midi_input);
1878 hdspm->midi[id].rmidi->info_flags |=
1879 SNDRV_RAWMIDI_INFO_OUTPUT |
1880 SNDRV_RAWMIDI_INFO_INPUT |
1881 SNDRV_RAWMIDI_INFO_DUPLEX;
1883 /* TCO MTC, read only */
1884 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1885 err = snd_rawmidi_new(card, buf, id, 1, 1,
1886 &hdspm->midi[id].rmidi);
1890 sprintf(hdspm->midi[id].rmidi->name,
1891 "%s MTC %d", card->id, id+1);
1892 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1894 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1895 SNDRV_RAWMIDI_STREAM_INPUT,
1896 &snd_hdspm_midi_input);
1898 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1905 static void hdspm_midi_tasklet(unsigned long arg)
1907 struct hdspm *hdspm = (struct hdspm *)arg;
1910 while (i < hdspm->midiPorts) {
1911 if (hdspm->midi[i].pending)
1912 snd_hdspm_midi_input_read(&hdspm->midi[i]);
1919 /*-----------------------------------------------------------------------------
1921 ----------------------------------------------------------------------------*/
1923 /* get the system sample rate which is set */
1927 * Calculate the real sample rate from the
1928 * current DDS value.
1930 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
1932 unsigned int period, rate;
1934 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
1935 rate = hdspm_calc_dds_value(hdspm, period);
1941 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
1942 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1945 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1946 .info = snd_hdspm_info_system_sample_rate, \
1947 .get = snd_hdspm_get_system_sample_rate \
1950 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
1951 struct snd_ctl_elem_info *uinfo)
1953 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1955 uinfo->value.integer.min = 27000;
1956 uinfo->value.integer.max = 207000;
1957 uinfo->value.integer.step = 1;
1962 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
1963 struct snd_ctl_elem_value *
1966 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1968 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
1974 * Returns the WordClock sample rate class for the given card.
1976 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
1980 switch (hdspm->io_type) {
1983 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
1984 return (status >> 16) & 0xF;
1996 * Returns the TCO sample rate class for the given card.
1998 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2003 switch (hdspm->io_type) {
2006 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2007 return (status >> 20) & 0xF;
2019 * Returns the SYNC_IN sample rate class for the given card.
2021 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2026 switch (hdspm->io_type) {
2029 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2030 return (status >> 12) & 0xF;
2042 * Returns the sample rate class for input source <idx> for
2043 * 'new style' cards like the AIO and RayDAT.
2045 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2047 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2049 return (status >> (idx*4)) & 0xF;
2054 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2055 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2057 .private_value = xindex, \
2058 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2059 .info = snd_hdspm_info_autosync_sample_rate, \
2060 .get = snd_hdspm_get_autosync_sample_rate \
2064 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2065 struct snd_ctl_elem_info *uinfo)
2067 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2069 uinfo->value.enumerated.items = 10;
2071 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2072 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2073 strcpy(uinfo->value.enumerated.name,
2074 texts_freq[uinfo->value.enumerated.item]);
2079 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2080 struct snd_ctl_elem_value *
2083 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2085 switch (hdspm->io_type) {
2087 switch (kcontrol->private_value) {
2089 ucontrol->value.enumerated.item[0] =
2090 hdspm_get_wc_sample_rate(hdspm);
2093 ucontrol->value.enumerated.item[0] =
2094 hdspm_get_tco_sample_rate(hdspm);
2097 ucontrol->value.enumerated.item[0] =
2098 hdspm_get_sync_in_sample_rate(hdspm);
2101 ucontrol->value.enumerated.item[0] =
2102 hdspm_get_s1_sample_rate(hdspm,
2103 kcontrol->private_value-1);
2107 switch (kcontrol->private_value) {
2109 ucontrol->value.enumerated.item[0] =
2110 hdspm_get_wc_sample_rate(hdspm);
2113 ucontrol->value.enumerated.item[0] =
2114 hdspm_get_tco_sample_rate(hdspm);
2116 case 5: /* SYNC_IN */
2117 ucontrol->value.enumerated.item[0] =
2118 hdspm_get_sync_in_sample_rate(hdspm);
2121 ucontrol->value.enumerated.item[0] =
2122 hdspm_get_s1_sample_rate(hdspm,
2123 ucontrol->id.index-1);
2128 switch (kcontrol->private_value) {
2130 ucontrol->value.enumerated.item[0] =
2131 hdspm_get_wc_sample_rate(hdspm);
2134 ucontrol->value.enumerated.item[0] =
2135 hdspm_get_tco_sample_rate(hdspm);
2137 case 10: /* SYNC_IN */
2138 ucontrol->value.enumerated.item[0] =
2139 hdspm_get_sync_in_sample_rate(hdspm);
2141 default: /* AES1 to AES8 */
2142 ucontrol->value.enumerated.item[0] =
2143 hdspm_get_s1_sample_rate(hdspm,
2144 kcontrol->private_value-1);
2156 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2157 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2160 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2161 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2162 .info = snd_hdspm_info_system_clock_mode, \
2163 .get = snd_hdspm_get_system_clock_mode, \
2164 .put = snd_hdspm_put_system_clock_mode, \
2169 * Returns the system clock mode for the given card.
2170 * @returns 0 - master, 1 - slave
2172 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2174 switch (hdspm->io_type) {
2177 if (hdspm->settings_register & HDSPM_c0Master)
2182 if (hdspm->control_register & HDSPM_ClockModeMaster)
2191 * Sets the system clock mode.
2192 * @param mode 0 - master, 1 - slave
2194 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2196 switch (hdspm->io_type) {
2200 hdspm->settings_register |= HDSPM_c0Master;
2202 hdspm->settings_register &= ~HDSPM_c0Master;
2204 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2209 hdspm->control_register |= HDSPM_ClockModeMaster;
2211 hdspm->control_register &= ~HDSPM_ClockModeMaster;
2213 hdspm_write(hdspm, HDSPM_controlRegister,
2214 hdspm->control_register);
2219 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2220 struct snd_ctl_elem_info *uinfo)
2222 static char *texts[] = { "Master", "AutoSync" };
2224 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2226 uinfo->value.enumerated.items = 2;
2227 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2228 uinfo->value.enumerated.item =
2229 uinfo->value.enumerated.items - 1;
2230 strcpy(uinfo->value.enumerated.name,
2231 texts[uinfo->value.enumerated.item]);
2235 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2236 struct snd_ctl_elem_value *ucontrol)
2238 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2240 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2244 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2245 struct snd_ctl_elem_value *ucontrol)
2247 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2250 if (!snd_hdspm_use_is_exclusive(hdspm))
2253 val = ucontrol->value.enumerated.item[0];
2259 hdspm_set_system_clock_mode(hdspm, val);
2265 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2266 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2269 .info = snd_hdspm_info_clock_source, \
2270 .get = snd_hdspm_get_clock_source, \
2271 .put = snd_hdspm_put_clock_source \
2275 static int hdspm_clock_source(struct hdspm * hdspm)
2277 switch (hdspm->system_sample_rate) {
2278 case 32000: return 0;
2279 case 44100: return 1;
2280 case 48000: return 2;
2281 case 64000: return 3;
2282 case 88200: return 4;
2283 case 96000: return 5;
2284 case 128000: return 6;
2285 case 176400: return 7;
2286 case 192000: return 8;
2292 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2297 rate = 32000; break;
2299 rate = 44100; break;
2301 rate = 48000; break;
2303 rate = 64000; break;
2305 rate = 88200; break;
2307 rate = 96000; break;
2309 rate = 128000; break;
2311 rate = 176400; break;
2313 rate = 192000; break;
2317 hdspm_set_rate(hdspm, rate, 1);
2321 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2322 struct snd_ctl_elem_info *uinfo)
2324 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2326 uinfo->value.enumerated.items = 9;
2328 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2329 uinfo->value.enumerated.item =
2330 uinfo->value.enumerated.items - 1;
2332 strcpy(uinfo->value.enumerated.name,
2333 texts_freq[uinfo->value.enumerated.item+1]);
2338 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2339 struct snd_ctl_elem_value *ucontrol)
2341 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2343 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2347 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2348 struct snd_ctl_elem_value *ucontrol)
2350 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2354 if (!snd_hdspm_use_is_exclusive(hdspm))
2356 val = ucontrol->value.enumerated.item[0];
2361 spin_lock_irq(&hdspm->lock);
2362 if (val != hdspm_clock_source(hdspm))
2363 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2366 spin_unlock_irq(&hdspm->lock);
2371 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2372 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2375 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2376 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2377 .info = snd_hdspm_info_pref_sync_ref, \
2378 .get = snd_hdspm_get_pref_sync_ref, \
2379 .put = snd_hdspm_put_pref_sync_ref \
2384 * Returns the current preferred sync reference setting.
2385 * The semantics of the return value are depending on the
2386 * card, please see the comments for clarification.
2388 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2390 switch (hdspm->io_type) {
2392 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2393 case 0: return 0; /* WC */
2394 case HDSPM_SyncRef0: return 1; /* AES 1 */
2395 case HDSPM_SyncRef1: return 2; /* AES 2 */
2396 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2397 case HDSPM_SyncRef2: return 4; /* AES 4 */
2398 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2399 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2400 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2401 return 7; /* AES 7 */
2402 case HDSPM_SyncRef3: return 8; /* AES 8 */
2403 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2410 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2411 case 0: return 0; /* WC */
2412 case HDSPM_SyncRef0: return 1; /* MADI */
2413 case HDSPM_SyncRef1: return 2; /* TCO */
2414 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2415 return 3; /* SYNC_IN */
2418 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2419 case 0: return 0; /* WC */
2420 case HDSPM_SyncRef0: return 1; /* MADI */
2421 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2422 return 2; /* SYNC_IN */
2429 switch ((hdspm->settings_register &
2430 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2431 case 0: return 0; /* WC */
2432 case 3: return 1; /* ADAT 1 */
2433 case 4: return 2; /* ADAT 2 */
2434 case 5: return 3; /* ADAT 3 */
2435 case 6: return 4; /* ADAT 4 */
2436 case 1: return 5; /* AES */
2437 case 2: return 6; /* SPDIF */
2438 case 9: return 7; /* TCO */
2439 case 10: return 8; /* SYNC_IN */
2442 switch ((hdspm->settings_register &
2443 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2444 case 0: return 0; /* WC */
2445 case 3: return 1; /* ADAT 1 */
2446 case 4: return 2; /* ADAT 2 */
2447 case 5: return 3; /* ADAT 3 */
2448 case 6: return 4; /* ADAT 4 */
2449 case 1: return 5; /* AES */
2450 case 2: return 6; /* SPDIF */
2451 case 10: return 7; /* SYNC_IN */
2459 switch ((hdspm->settings_register &
2460 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2461 case 0: return 0; /* WC */
2462 case 3: return 1; /* ADAT */
2463 case 1: return 2; /* AES */
2464 case 2: return 3; /* SPDIF */
2465 case 9: return 4; /* TCO */
2466 case 10: return 5; /* SYNC_IN */
2469 switch ((hdspm->settings_register &
2470 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2471 case 0: return 0; /* WC */
2472 case 3: return 1; /* ADAT */
2473 case 1: return 2; /* AES */
2474 case 2: return 3; /* SPDIF */
2475 case 10: return 4; /* SYNC_IN */
2487 * Set the preferred sync reference to <pref>. The semantics
2488 * of <pref> are depending on the card type, see the comments
2489 * for clarification.
2491 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2495 switch (hdspm->io_type) {
2497 hdspm->control_register &= ~HDSPM_SyncRefMask;
2502 hdspm->control_register |= HDSPM_SyncRef0;
2505 hdspm->control_register |= HDSPM_SyncRef1;
2508 hdspm->control_register |=
2509 HDSPM_SyncRef1+HDSPM_SyncRef0;
2512 hdspm->control_register |= HDSPM_SyncRef2;
2515 hdspm->control_register |=
2516 HDSPM_SyncRef2+HDSPM_SyncRef0;
2519 hdspm->control_register |=
2520 HDSPM_SyncRef2+HDSPM_SyncRef1;
2523 hdspm->control_register |=
2524 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2527 hdspm->control_register |= HDSPM_SyncRef3;
2530 hdspm->control_register |=
2531 HDSPM_SyncRef3+HDSPM_SyncRef0;
2541 hdspm->control_register &= ~HDSPM_SyncRefMask;
2547 hdspm->control_register |= HDSPM_SyncRef0;
2550 hdspm->control_register |= HDSPM_SyncRef1;
2552 case 3: /* SYNC_IN */
2553 hdspm->control_register |=
2554 HDSPM_SyncRef0+HDSPM_SyncRef1;
2564 hdspm->control_register |= HDSPM_SyncRef0;
2566 case 2: /* SYNC_IN */
2567 hdspm->control_register |=
2568 HDSPM_SyncRef0+HDSPM_SyncRef1;
2580 case 0: p = 0; break; /* WC */
2581 case 1: p = 3; break; /* ADAT 1 */
2582 case 2: p = 4; break; /* ADAT 2 */
2583 case 3: p = 5; break; /* ADAT 3 */
2584 case 4: p = 6; break; /* ADAT 4 */
2585 case 5: p = 1; break; /* AES */
2586 case 6: p = 2; break; /* SPDIF */
2587 case 7: p = 9; break; /* TCO */
2588 case 8: p = 10; break; /* SYNC_IN */
2593 case 0: p = 0; break; /* WC */
2594 case 1: p = 3; break; /* ADAT 1 */
2595 case 2: p = 4; break; /* ADAT 2 */
2596 case 3: p = 5; break; /* ADAT 3 */
2597 case 4: p = 6; break; /* ADAT 4 */
2598 case 5: p = 1; break; /* AES */
2599 case 6: p = 2; break; /* SPDIF */
2600 case 7: p = 10; break; /* SYNC_IN */
2609 case 0: p = 0; break; /* WC */
2610 case 1: p = 3; break; /* ADAT */
2611 case 2: p = 1; break; /* AES */
2612 case 3: p = 2; break; /* SPDIF */
2613 case 4: p = 9; break; /* TCO */
2614 case 5: p = 10; break; /* SYNC_IN */
2619 case 0: p = 0; break; /* WC */
2620 case 1: p = 3; break; /* ADAT */
2621 case 2: p = 1; break; /* AES */
2622 case 3: p = 2; break; /* SPDIF */
2623 case 4: p = 10; break; /* SYNC_IN */
2630 switch (hdspm->io_type) {
2633 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2634 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2635 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2641 hdspm_write(hdspm, HDSPM_controlRegister,
2642 hdspm->control_register);
2649 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2650 struct snd_ctl_elem_info *uinfo)
2652 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2654 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2656 uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2658 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2659 uinfo->value.enumerated.item =
2660 uinfo->value.enumerated.items - 1;
2662 strcpy(uinfo->value.enumerated.name,
2663 hdspm->texts_autosync[uinfo->value.enumerated.item]);
2668 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2669 struct snd_ctl_elem_value *ucontrol)
2671 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2672 int psf = hdspm_pref_sync_ref(hdspm);
2675 ucontrol->value.enumerated.item[0] = psf;
2682 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2683 struct snd_ctl_elem_value *ucontrol)
2685 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2686 int val, change = 0;
2688 if (!snd_hdspm_use_is_exclusive(hdspm))
2691 val = ucontrol->value.enumerated.item[0];
2695 else if (val >= hdspm->texts_autosync_items)
2696 val = hdspm->texts_autosync_items-1;
2698 spin_lock_irq(&hdspm->lock);
2699 if (val != hdspm_pref_sync_ref(hdspm))
2700 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2702 spin_unlock_irq(&hdspm->lock);
2707 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2708 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2711 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2712 .info = snd_hdspm_info_autosync_ref, \
2713 .get = snd_hdspm_get_autosync_ref, \
2716 static int hdspm_autosync_ref(struct hdspm *hdspm)
2718 if (AES32 == hdspm->io_type) {
2719 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2720 unsigned int syncref =
2721 (status >> HDSPM_AES32_syncref_bit) & 0xF;
2723 return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2726 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2727 } else if (MADI == hdspm->io_type) {
2728 /* This looks at the autosync selected sync reference */
2729 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2731 switch (status2 & HDSPM_SelSyncRefMask) {
2732 case HDSPM_SelSyncRef_WORD:
2733 return HDSPM_AUTOSYNC_FROM_WORD;
2734 case HDSPM_SelSyncRef_MADI:
2735 return HDSPM_AUTOSYNC_FROM_MADI;
2736 case HDSPM_SelSyncRef_TCO:
2737 return HDSPM_AUTOSYNC_FROM_TCO;
2738 case HDSPM_SelSyncRef_SyncIn:
2739 return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2740 case HDSPM_SelSyncRef_NVALID:
2741 return HDSPM_AUTOSYNC_FROM_NONE;
2751 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2752 struct snd_ctl_elem_info *uinfo)
2754 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2756 if (AES32 == hdspm->io_type) {
2757 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2758 "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2760 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2762 uinfo->value.enumerated.items = 10;
2763 if (uinfo->value.enumerated.item >=
2764 uinfo->value.enumerated.items)
2765 uinfo->value.enumerated.item =
2766 uinfo->value.enumerated.items - 1;
2767 strcpy(uinfo->value.enumerated.name,
2768 texts[uinfo->value.enumerated.item]);
2769 } else if (MADI == hdspm->io_type) {
2770 static char *texts[] = {"Word Clock", "MADI", "TCO",
2771 "Sync In", "None" };
2773 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2775 uinfo->value.enumerated.items = 5;
2776 if (uinfo->value.enumerated.item >=
2777 uinfo->value.enumerated.items)
2778 uinfo->value.enumerated.item =
2779 uinfo->value.enumerated.items - 1;
2780 strcpy(uinfo->value.enumerated.name,
2781 texts[uinfo->value.enumerated.item]);
2786 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2787 struct snd_ctl_elem_value *ucontrol)
2789 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2791 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2796 #define HDSPM_LINE_OUT(xname, xindex) \
2797 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2800 .info = snd_hdspm_info_line_out, \
2801 .get = snd_hdspm_get_line_out, \
2802 .put = snd_hdspm_put_line_out \
2805 static int hdspm_line_out(struct hdspm * hdspm)
2807 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
2811 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
2814 hdspm->control_register |= HDSPM_LineOut;
2816 hdspm->control_register &= ~HDSPM_LineOut;
2817 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2822 #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info
2824 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
2825 struct snd_ctl_elem_value *ucontrol)
2827 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2829 spin_lock_irq(&hdspm->lock);
2830 ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
2831 spin_unlock_irq(&hdspm->lock);
2835 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
2836 struct snd_ctl_elem_value *ucontrol)
2838 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2842 if (!snd_hdspm_use_is_exclusive(hdspm))
2844 val = ucontrol->value.integer.value[0] & 1;
2845 spin_lock_irq(&hdspm->lock);
2846 change = (int) val != hdspm_line_out(hdspm);
2847 hdspm_set_line_output(hdspm, val);
2848 spin_unlock_irq(&hdspm->lock);
2853 #define HDSPM_TX_64(xname, xindex) \
2854 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2857 .info = snd_hdspm_info_tx_64, \
2858 .get = snd_hdspm_get_tx_64, \
2859 .put = snd_hdspm_put_tx_64 \
2862 static int hdspm_tx_64(struct hdspm * hdspm)
2864 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
2867 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
2870 hdspm->control_register |= HDSPM_TX_64ch;
2872 hdspm->control_register &= ~HDSPM_TX_64ch;
2873 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2878 #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info
2880 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
2881 struct snd_ctl_elem_value *ucontrol)
2883 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2885 spin_lock_irq(&hdspm->lock);
2886 ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
2887 spin_unlock_irq(&hdspm->lock);
2891 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
2892 struct snd_ctl_elem_value *ucontrol)
2894 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2898 if (!snd_hdspm_use_is_exclusive(hdspm))
2900 val = ucontrol->value.integer.value[0] & 1;
2901 spin_lock_irq(&hdspm->lock);
2902 change = (int) val != hdspm_tx_64(hdspm);
2903 hdspm_set_tx_64(hdspm, val);
2904 spin_unlock_irq(&hdspm->lock);
2909 #define HDSPM_C_TMS(xname, xindex) \
2910 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2913 .info = snd_hdspm_info_c_tms, \
2914 .get = snd_hdspm_get_c_tms, \
2915 .put = snd_hdspm_put_c_tms \
2918 static int hdspm_c_tms(struct hdspm * hdspm)
2920 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
2923 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
2926 hdspm->control_register |= HDSPM_clr_tms;
2928 hdspm->control_register &= ~HDSPM_clr_tms;
2929 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2934 #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info
2936 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
2937 struct snd_ctl_elem_value *ucontrol)
2939 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2941 spin_lock_irq(&hdspm->lock);
2942 ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
2943 spin_unlock_irq(&hdspm->lock);
2947 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
2948 struct snd_ctl_elem_value *ucontrol)
2950 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2954 if (!snd_hdspm_use_is_exclusive(hdspm))
2956 val = ucontrol->value.integer.value[0] & 1;
2957 spin_lock_irq(&hdspm->lock);
2958 change = (int) val != hdspm_c_tms(hdspm);
2959 hdspm_set_c_tms(hdspm, val);
2960 spin_unlock_irq(&hdspm->lock);
2965 #define HDSPM_SAFE_MODE(xname, xindex) \
2966 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2969 .info = snd_hdspm_info_safe_mode, \
2970 .get = snd_hdspm_get_safe_mode, \
2971 .put = snd_hdspm_put_safe_mode \
2974 static int hdspm_safe_mode(struct hdspm * hdspm)
2976 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
2979 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
2982 hdspm->control_register |= HDSPM_AutoInp;
2984 hdspm->control_register &= ~HDSPM_AutoInp;
2985 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2990 #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info
2992 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
2993 struct snd_ctl_elem_value *ucontrol)
2995 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2997 spin_lock_irq(&hdspm->lock);
2998 ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
2999 spin_unlock_irq(&hdspm->lock);
3003 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
3004 struct snd_ctl_elem_value *ucontrol)
3006 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3010 if (!snd_hdspm_use_is_exclusive(hdspm))
3012 val = ucontrol->value.integer.value[0] & 1;
3013 spin_lock_irq(&hdspm->lock);
3014 change = (int) val != hdspm_safe_mode(hdspm);
3015 hdspm_set_safe_mode(hdspm, val);
3016 spin_unlock_irq(&hdspm->lock);
3021 #define HDSPM_EMPHASIS(xname, xindex) \
3022 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3025 .info = snd_hdspm_info_emphasis, \
3026 .get = snd_hdspm_get_emphasis, \
3027 .put = snd_hdspm_put_emphasis \
3030 static int hdspm_emphasis(struct hdspm * hdspm)
3032 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
3035 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
3038 hdspm->control_register |= HDSPM_Emphasis;
3040 hdspm->control_register &= ~HDSPM_Emphasis;
3041 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3046 #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info
3048 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
3049 struct snd_ctl_elem_value *ucontrol)
3051 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3053 spin_lock_irq(&hdspm->lock);
3054 ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
3055 spin_unlock_irq(&hdspm->lock);
3059 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
3060 struct snd_ctl_elem_value *ucontrol)
3062 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3066 if (!snd_hdspm_use_is_exclusive(hdspm))
3068 val = ucontrol->value.integer.value[0] & 1;
3069 spin_lock_irq(&hdspm->lock);
3070 change = (int) val != hdspm_emphasis(hdspm);
3071 hdspm_set_emphasis(hdspm, val);
3072 spin_unlock_irq(&hdspm->lock);
3077 #define HDSPM_DOLBY(xname, xindex) \
3078 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3081 .info = snd_hdspm_info_dolby, \
3082 .get = snd_hdspm_get_dolby, \
3083 .put = snd_hdspm_put_dolby \
3086 static int hdspm_dolby(struct hdspm * hdspm)
3088 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
3091 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
3094 hdspm->control_register |= HDSPM_Dolby;
3096 hdspm->control_register &= ~HDSPM_Dolby;
3097 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3102 #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info
3104 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
3105 struct snd_ctl_elem_value *ucontrol)
3107 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3109 spin_lock_irq(&hdspm->lock);
3110 ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
3111 spin_unlock_irq(&hdspm->lock);
3115 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
3116 struct snd_ctl_elem_value *ucontrol)
3118 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3122 if (!snd_hdspm_use_is_exclusive(hdspm))
3124 val = ucontrol->value.integer.value[0] & 1;
3125 spin_lock_irq(&hdspm->lock);
3126 change = (int) val != hdspm_dolby(hdspm);
3127 hdspm_set_dolby(hdspm, val);
3128 spin_unlock_irq(&hdspm->lock);
3133 #define HDSPM_PROFESSIONAL(xname, xindex) \
3134 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3137 .info = snd_hdspm_info_professional, \
3138 .get = snd_hdspm_get_professional, \
3139 .put = snd_hdspm_put_professional \
3142 static int hdspm_professional(struct hdspm * hdspm)
3144 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
3147 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
3150 hdspm->control_register |= HDSPM_Professional;
3152 hdspm->control_register &= ~HDSPM_Professional;
3153 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3158 #define snd_hdspm_info_professional snd_ctl_boolean_mono_info
3160 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
3161 struct snd_ctl_elem_value *ucontrol)
3163 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3165 spin_lock_irq(&hdspm->lock);
3166 ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
3167 spin_unlock_irq(&hdspm->lock);
3171 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
3172 struct snd_ctl_elem_value *ucontrol)
3174 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3178 if (!snd_hdspm_use_is_exclusive(hdspm))
3180 val = ucontrol->value.integer.value[0] & 1;
3181 spin_lock_irq(&hdspm->lock);
3182 change = (int) val != hdspm_professional(hdspm);
3183 hdspm_set_professional(hdspm, val);
3184 spin_unlock_irq(&hdspm->lock);
3188 #define HDSPM_INPUT_SELECT(xname, xindex) \
3189 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3192 .info = snd_hdspm_info_input_select, \
3193 .get = snd_hdspm_get_input_select, \
3194 .put = snd_hdspm_put_input_select \
3197 static int hdspm_input_select(struct hdspm * hdspm)
3199 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3202 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3205 hdspm->control_register |= HDSPM_InputSelect0;
3207 hdspm->control_register &= ~HDSPM_InputSelect0;
3208 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3213 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3214 struct snd_ctl_elem_info *uinfo)
3216 static char *texts[] = { "optical", "coaxial" };
3218 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3220 uinfo->value.enumerated.items = 2;
3222 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3223 uinfo->value.enumerated.item =
3224 uinfo->value.enumerated.items - 1;
3225 strcpy(uinfo->value.enumerated.name,
3226 texts[uinfo->value.enumerated.item]);
3231 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3232 struct snd_ctl_elem_value *ucontrol)
3234 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3236 spin_lock_irq(&hdspm->lock);
3237 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3238 spin_unlock_irq(&hdspm->lock);
3242 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3243 struct snd_ctl_elem_value *ucontrol)
3245 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3249 if (!snd_hdspm_use_is_exclusive(hdspm))
3251 val = ucontrol->value.integer.value[0] & 1;
3252 spin_lock_irq(&hdspm->lock);
3253 change = (int) val != hdspm_input_select(hdspm);
3254 hdspm_set_input_select(hdspm, val);
3255 spin_unlock_irq(&hdspm->lock);
3260 #define HDSPM_DS_WIRE(xname, xindex) \
3261 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3264 .info = snd_hdspm_info_ds_wire, \
3265 .get = snd_hdspm_get_ds_wire, \
3266 .put = snd_hdspm_put_ds_wire \
3269 static int hdspm_ds_wire(struct hdspm * hdspm)
3271 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3274 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3277 hdspm->control_register |= HDSPM_DS_DoubleWire;
3279 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3280 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3285 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3286 struct snd_ctl_elem_info *uinfo)
3288 static char *texts[] = { "Single", "Double" };
3290 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3292 uinfo->value.enumerated.items = 2;
3294 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3295 uinfo->value.enumerated.item =
3296 uinfo->value.enumerated.items - 1;
3297 strcpy(uinfo->value.enumerated.name,
3298 texts[uinfo->value.enumerated.item]);
3303 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3304 struct snd_ctl_elem_value *ucontrol)
3306 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3308 spin_lock_irq(&hdspm->lock);
3309 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3310 spin_unlock_irq(&hdspm->lock);
3314 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3315 struct snd_ctl_elem_value *ucontrol)
3317 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3321 if (!snd_hdspm_use_is_exclusive(hdspm))
3323 val = ucontrol->value.integer.value[0] & 1;
3324 spin_lock_irq(&hdspm->lock);
3325 change = (int) val != hdspm_ds_wire(hdspm);
3326 hdspm_set_ds_wire(hdspm, val);
3327 spin_unlock_irq(&hdspm->lock);
3332 #define HDSPM_QS_WIRE(xname, xindex) \
3333 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3336 .info = snd_hdspm_info_qs_wire, \
3337 .get = snd_hdspm_get_qs_wire, \
3338 .put = snd_hdspm_put_qs_wire \
3341 static int hdspm_qs_wire(struct hdspm * hdspm)
3343 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3345 if (hdspm->control_register & HDSPM_QS_QuadWire)
3350 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3352 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3357 hdspm->control_register |= HDSPM_QS_DoubleWire;
3360 hdspm->control_register |= HDSPM_QS_QuadWire;
3363 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3368 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3369 struct snd_ctl_elem_info *uinfo)
3371 static char *texts[] = { "Single", "Double", "Quad" };
3373 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3375 uinfo->value.enumerated.items = 3;
3377 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3378 uinfo->value.enumerated.item =
3379 uinfo->value.enumerated.items - 1;
3380 strcpy(uinfo->value.enumerated.name,
3381 texts[uinfo->value.enumerated.item]);
3386 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3387 struct snd_ctl_elem_value *ucontrol)
3389 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3391 spin_lock_irq(&hdspm->lock);
3392 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3393 spin_unlock_irq(&hdspm->lock);
3397 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3398 struct snd_ctl_elem_value *ucontrol)
3400 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3404 if (!snd_hdspm_use_is_exclusive(hdspm))
3406 val = ucontrol->value.integer.value[0];
3411 spin_lock_irq(&hdspm->lock);
3412 change = val != hdspm_qs_wire(hdspm);
3413 hdspm_set_qs_wire(hdspm, val);
3414 spin_unlock_irq(&hdspm->lock);
3418 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3419 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3422 .info = snd_hdspm_info_madi_speedmode, \
3423 .get = snd_hdspm_get_madi_speedmode, \
3424 .put = snd_hdspm_put_madi_speedmode \
3427 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3429 if (hdspm->control_register & HDSPM_QuadSpeed)
3431 if (hdspm->control_register & HDSPM_DoubleSpeed)
3436 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3438 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3443 hdspm->control_register |= HDSPM_DoubleSpeed;
3446 hdspm->control_register |= HDSPM_QuadSpeed;
3449 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3454 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3455 struct snd_ctl_elem_info *uinfo)
3457 static char *texts[] = { "Single", "Double", "Quad" };
3459 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3461 uinfo->value.enumerated.items = 3;
3463 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3464 uinfo->value.enumerated.item =
3465 uinfo->value.enumerated.items - 1;
3466 strcpy(uinfo->value.enumerated.name,
3467 texts[uinfo->value.enumerated.item]);
3472 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3473 struct snd_ctl_elem_value *ucontrol)
3475 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3477 spin_lock_irq(&hdspm->lock);
3478 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3479 spin_unlock_irq(&hdspm->lock);
3483 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3484 struct snd_ctl_elem_value *ucontrol)
3486 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3490 if (!snd_hdspm_use_is_exclusive(hdspm))
3492 val = ucontrol->value.integer.value[0];
3497 spin_lock_irq(&hdspm->lock);
3498 change = val != hdspm_madi_speedmode(hdspm);
3499 hdspm_set_madi_speedmode(hdspm, val);
3500 spin_unlock_irq(&hdspm->lock);
3504 #define HDSPM_MIXER(xname, xindex) \
3505 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3509 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3510 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3511 .info = snd_hdspm_info_mixer, \
3512 .get = snd_hdspm_get_mixer, \
3513 .put = snd_hdspm_put_mixer \
3516 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3517 struct snd_ctl_elem_info *uinfo)
3519 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3521 uinfo->value.integer.min = 0;
3522 uinfo->value.integer.max = 65535;
3523 uinfo->value.integer.step = 1;
3527 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3528 struct snd_ctl_elem_value *ucontrol)
3530 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3534 source = ucontrol->value.integer.value[0];
3537 else if (source >= 2 * HDSPM_MAX_CHANNELS)
3538 source = 2 * HDSPM_MAX_CHANNELS - 1;
3540 destination = ucontrol->value.integer.value[1];
3541 if (destination < 0)
3543 else if (destination >= HDSPM_MAX_CHANNELS)
3544 destination = HDSPM_MAX_CHANNELS - 1;
3546 spin_lock_irq(&hdspm->lock);
3547 if (source >= HDSPM_MAX_CHANNELS)
3548 ucontrol->value.integer.value[2] =
3549 hdspm_read_pb_gain(hdspm, destination,
3550 source - HDSPM_MAX_CHANNELS);
3552 ucontrol->value.integer.value[2] =
3553 hdspm_read_in_gain(hdspm, destination, source);
3555 spin_unlock_irq(&hdspm->lock);
3560 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3561 struct snd_ctl_elem_value *ucontrol)
3563 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3569 if (!snd_hdspm_use_is_exclusive(hdspm))
3572 source = ucontrol->value.integer.value[0];
3573 destination = ucontrol->value.integer.value[1];
3575 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3577 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3580 gain = ucontrol->value.integer.value[2];
3582 spin_lock_irq(&hdspm->lock);
3584 if (source >= HDSPM_MAX_CHANNELS)
3585 change = gain != hdspm_read_pb_gain(hdspm, destination,
3587 HDSPM_MAX_CHANNELS);
3589 change = gain != hdspm_read_in_gain(hdspm, destination,
3593 if (source >= HDSPM_MAX_CHANNELS)
3594 hdspm_write_pb_gain(hdspm, destination,
3595 source - HDSPM_MAX_CHANNELS,
3598 hdspm_write_in_gain(hdspm, destination, source,
3601 spin_unlock_irq(&hdspm->lock);
3606 /* The simple mixer control(s) provide gain control for the
3607 basic 1:1 mappings of playback streams to output
3611 #define HDSPM_PLAYBACK_MIXER \
3612 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3613 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3614 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3615 .info = snd_hdspm_info_playback_mixer, \
3616 .get = snd_hdspm_get_playback_mixer, \
3617 .put = snd_hdspm_put_playback_mixer \
3620 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3621 struct snd_ctl_elem_info *uinfo)
3623 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3625 uinfo->value.integer.min = 0;
3626 uinfo->value.integer.max = 64;
3627 uinfo->value.integer.step = 1;
3631 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3632 struct snd_ctl_elem_value *ucontrol)
3634 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3637 channel = ucontrol->id.index - 1;
3639 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3642 spin_lock_irq(&hdspm->lock);
3643 ucontrol->value.integer.value[0] =
3644 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3645 spin_unlock_irq(&hdspm->lock);
3650 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3651 struct snd_ctl_elem_value *ucontrol)
3653 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3658 if (!snd_hdspm_use_is_exclusive(hdspm))
3661 channel = ucontrol->id.index - 1;
3663 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3666 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3668 spin_lock_irq(&hdspm->lock);
3670 gain != hdspm_read_pb_gain(hdspm, channel,
3673 hdspm_write_pb_gain(hdspm, channel, channel,
3675 spin_unlock_irq(&hdspm->lock);
3679 #define HDSPM_SYNC_CHECK(xname, xindex) \
3680 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3682 .private_value = xindex, \
3683 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3684 .info = snd_hdspm_info_sync_check, \
3685 .get = snd_hdspm_get_sync_check \
3689 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3690 struct snd_ctl_elem_info *uinfo)
3692 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3693 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3695 uinfo->value.enumerated.items = 4;
3696 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3697 uinfo->value.enumerated.item =
3698 uinfo->value.enumerated.items - 1;
3699 strcpy(uinfo->value.enumerated.name,
3700 texts[uinfo->value.enumerated.item]);
3704 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3706 int status, status2;
3708 switch (hdspm->io_type) {
3710 status = hdspm_read(hdspm, HDSPM_statusRegister);
3711 if (status & HDSPM_wcSync)
3713 else if (status & HDSPM_wcLock)
3719 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3720 if (status2 & HDSPM_wcLock) {
3721 if (status2 & HDSPM_wcSync)
3731 status = hdspm_read(hdspm, HDSPM_statusRegister);
3733 if (status & 0x2000000)
3735 else if (status & 0x1000000)
3750 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3752 int status = hdspm_read(hdspm, HDSPM_statusRegister);
3753 if (status & HDSPM_madiLock) {
3754 if (status & HDSPM_madiSync)
3763 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3765 int status, lock, sync;
3767 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3769 lock = (status & (0x1<<idx)) ? 1 : 0;
3770 sync = (status & (0x100<<idx)) ? 1 : 0;
3780 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3782 int status, lock = 0, sync = 0;
3784 switch (hdspm->io_type) {
3787 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3788 lock = (status & 0x400) ? 1 : 0;
3789 sync = (status & 0x800) ? 1 : 0;
3794 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3795 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3796 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3811 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3813 int status2, lock, sync;
3814 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3816 lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3817 sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3827 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3832 switch (hdspm->io_type) {
3835 status = hdspm_read(hdspm, HDSPM_statusRegister);
3836 if (status & HDSPM_tcoLock) {
3837 if (status & HDSPM_tcoSync)
3848 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3850 if (status & 0x8000000)
3851 return 2; /* Sync */
3852 if (status & 0x4000000)
3853 return 1; /* Lock */
3854 return 0; /* No signal */
3866 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3867 struct snd_ctl_elem_value *ucontrol)
3869 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3872 switch (hdspm->io_type) {
3874 switch (kcontrol->private_value) {
3876 val = hdspm_wc_sync_check(hdspm); break;
3878 val = hdspm_tco_sync_check(hdspm); break;
3879 case 8: /* SYNC IN */
3880 val = hdspm_sync_in_sync_check(hdspm); break;
3882 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3886 switch (kcontrol->private_value) {
3888 val = hdspm_wc_sync_check(hdspm); break;
3890 val = hdspm_tco_sync_check(hdspm); break;
3891 case 5: /* SYNC IN */
3892 val = hdspm_sync_in_sync_check(hdspm); break;
3894 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3898 switch (kcontrol->private_value) {
3900 val = hdspm_wc_sync_check(hdspm); break;
3902 val = hdspm_madi_sync_check(hdspm); break;
3904 val = hdspm_tco_sync_check(hdspm); break;
3905 case 3: /* SYNC_IN */
3906 val = hdspm_sync_in_sync_check(hdspm); break;
3910 val = hdspm_madi_sync_check(hdspm); /* MADI */
3914 switch (kcontrol->private_value) {
3916 val = hdspm_wc_sync_check(hdspm); break;
3918 val = hdspm_tco_sync_check(hdspm); break;
3919 case 10 /* SYNC IN */:
3920 val = hdspm_sync_in_sync_check(hdspm); break;
3921 default: /* AES1 to AES8 */
3922 val = hdspm_aes_sync_check(hdspm,
3923 kcontrol->private_value-1);
3931 ucontrol->value.enumerated.item[0] = val;
3940 static void hdspm_tco_write(struct hdspm *hdspm)
3942 unsigned int tc[4] = { 0, 0, 0, 0};
3944 switch (hdspm->tco->input) {
3946 tc[2] |= HDSPM_TCO2_set_input_MSB;
3949 tc[2] |= HDSPM_TCO2_set_input_LSB;
3955 switch (hdspm->tco->framerate) {
3957 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
3960 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
3963 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
3964 HDSPM_TCO1_set_drop_frame_flag;
3967 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3968 HDSPM_TCO1_LTC_Format_MSB;
3971 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3972 HDSPM_TCO1_LTC_Format_MSB +
3973 HDSPM_TCO1_set_drop_frame_flag;
3979 switch (hdspm->tco->wordclock) {
3981 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
3984 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
3990 switch (hdspm->tco->samplerate) {
3992 tc[2] |= HDSPM_TCO2_set_freq;
3995 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4001 switch (hdspm->tco->pull) {
4003 tc[2] |= HDSPM_TCO2_set_pull_up;
4006 tc[2] |= HDSPM_TCO2_set_pull_down;
4009 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4012 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4018 if (1 == hdspm->tco->term) {
4019 tc[2] |= HDSPM_TCO2_set_term_75R;
4022 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4023 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4024 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4025 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4029 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4030 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4033 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4034 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4035 .info = snd_hdspm_info_tco_sample_rate, \
4036 .get = snd_hdspm_get_tco_sample_rate, \
4037 .put = snd_hdspm_put_tco_sample_rate \
4040 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4041 struct snd_ctl_elem_info *uinfo)
4043 static char *texts[] = { "44.1 kHz", "48 kHz" };
4044 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4046 uinfo->value.enumerated.items = 2;
4048 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4049 uinfo->value.enumerated.item =
4050 uinfo->value.enumerated.items - 1;
4052 strcpy(uinfo->value.enumerated.name,
4053 texts[uinfo->value.enumerated.item]);
4058 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4059 struct snd_ctl_elem_value *ucontrol)
4061 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4063 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4068 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4069 struct snd_ctl_elem_value *ucontrol)
4071 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4073 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4074 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4076 hdspm_tco_write(hdspm);
4085 #define HDSPM_TCO_PULL(xname, xindex) \
4086 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4089 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4090 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4091 .info = snd_hdspm_info_tco_pull, \
4092 .get = snd_hdspm_get_tco_pull, \
4093 .put = snd_hdspm_put_tco_pull \
4096 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4097 struct snd_ctl_elem_info *uinfo)
4099 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4100 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4102 uinfo->value.enumerated.items = 5;
4104 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4105 uinfo->value.enumerated.item =
4106 uinfo->value.enumerated.items - 1;
4108 strcpy(uinfo->value.enumerated.name,
4109 texts[uinfo->value.enumerated.item]);
4114 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4115 struct snd_ctl_elem_value *ucontrol)
4117 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4119 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4124 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4125 struct snd_ctl_elem_value *ucontrol)
4127 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4129 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4130 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4132 hdspm_tco_write(hdspm);
4140 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4141 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4144 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4145 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4146 .info = snd_hdspm_info_tco_wck_conversion, \
4147 .get = snd_hdspm_get_tco_wck_conversion, \
4148 .put = snd_hdspm_put_tco_wck_conversion \
4151 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4152 struct snd_ctl_elem_info *uinfo)
4154 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4155 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4157 uinfo->value.enumerated.items = 3;
4159 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4160 uinfo->value.enumerated.item =
4161 uinfo->value.enumerated.items - 1;
4163 strcpy(uinfo->value.enumerated.name,
4164 texts[uinfo->value.enumerated.item]);
4169 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4170 struct snd_ctl_elem_value *ucontrol)
4172 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4174 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4179 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4180 struct snd_ctl_elem_value *ucontrol)
4182 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4184 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4185 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4187 hdspm_tco_write(hdspm);
4196 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4197 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4200 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4201 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4202 .info = snd_hdspm_info_tco_frame_rate, \
4203 .get = snd_hdspm_get_tco_frame_rate, \
4204 .put = snd_hdspm_put_tco_frame_rate \
4207 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4208 struct snd_ctl_elem_info *uinfo)
4210 static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4211 "29.97 dfps", "30 fps", "30 dfps" };
4212 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4214 uinfo->value.enumerated.items = 6;
4216 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4217 uinfo->value.enumerated.item =
4218 uinfo->value.enumerated.items - 1;
4220 strcpy(uinfo->value.enumerated.name,
4221 texts[uinfo->value.enumerated.item]);
4226 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4227 struct snd_ctl_elem_value *ucontrol)
4229 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4231 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4236 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4237 struct snd_ctl_elem_value *ucontrol)
4239 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4241 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4242 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4244 hdspm_tco_write(hdspm);
4253 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4254 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4257 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4258 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4259 .info = snd_hdspm_info_tco_sync_source, \
4260 .get = snd_hdspm_get_tco_sync_source, \
4261 .put = snd_hdspm_put_tco_sync_source \
4264 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4265 struct snd_ctl_elem_info *uinfo)
4267 static char *texts[] = { "LTC", "Video", "WCK" };
4268 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4270 uinfo->value.enumerated.items = 3;
4272 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4273 uinfo->value.enumerated.item =
4274 uinfo->value.enumerated.items - 1;
4276 strcpy(uinfo->value.enumerated.name,
4277 texts[uinfo->value.enumerated.item]);
4282 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4283 struct snd_ctl_elem_value *ucontrol)
4285 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4287 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4292 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4293 struct snd_ctl_elem_value *ucontrol)
4295 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4297 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4298 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4300 hdspm_tco_write(hdspm);
4309 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4310 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4313 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4314 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4315 .info = snd_hdspm_info_tco_word_term, \
4316 .get = snd_hdspm_get_tco_word_term, \
4317 .put = snd_hdspm_put_tco_word_term \
4320 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4321 struct snd_ctl_elem_info *uinfo)
4323 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4325 uinfo->value.integer.min = 0;
4326 uinfo->value.integer.max = 1;
4332 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4333 struct snd_ctl_elem_value *ucontrol)
4335 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4337 ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4343 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4344 struct snd_ctl_elem_value *ucontrol)
4346 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4348 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4349 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4351 hdspm_tco_write(hdspm);
4362 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4363 HDSPM_MIXER("Mixer", 0),
4364 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4365 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4366 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4367 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4368 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4369 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4370 HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4371 HDSPM_SYNC_CHECK("TCO SyncCHeck", 2),
4372 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4373 HDSPM_LINE_OUT("Line Out", 0),
4374 HDSPM_TX_64("TX 64 channels mode", 0),
4375 HDSPM_C_TMS("Clear Track Marker", 0),
4376 HDSPM_SAFE_MODE("Safe Mode", 0),
4377 HDSPM_INPUT_SELECT("Input Select", 0),
4378 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4382 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4383 HDSPM_MIXER("Mixer", 0),
4384 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4385 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4386 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4387 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4388 HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4389 HDSPM_TX_64("TX 64 channels mode", 0),
4390 HDSPM_C_TMS("Clear Track Marker", 0),
4391 HDSPM_SAFE_MODE("Safe Mode", 0),
4392 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4395 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4396 HDSPM_MIXER("Mixer", 0),
4397 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4398 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4399 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4400 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4401 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4402 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4403 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4404 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4405 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4406 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4407 HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4408 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4409 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4410 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4411 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4412 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4413 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4414 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4417 HDSPM_INPUT_SELECT("Input Select", 0),
4418 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4419 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4420 HDSPM_SPDIF_IN("SPDIF In", 0);
4421 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4422 HDSPM_INPUT_LEVEL("Input Level", 0);
4423 HDSPM_OUTPUT_LEVEL("Output Level", 0);
4424 HDSPM_PHONES("Phones", 0);
4428 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4429 HDSPM_MIXER("Mixer", 0),
4430 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4431 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4432 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4433 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4434 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4435 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4436 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4437 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4438 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4439 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4440 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4441 HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4442 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4443 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4444 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4445 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4446 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4447 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4448 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4449 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4450 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4451 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4454 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4455 HDSPM_MIXER("Mixer", 0),
4456 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4457 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4458 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4459 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4460 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4461 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4462 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4463 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4464 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4465 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4466 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4467 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4468 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4469 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4470 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4471 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4472 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4473 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4474 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4475 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4476 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4477 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4478 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4479 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4480 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4481 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4482 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4483 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4484 HDSPM_LINE_OUT("Line Out", 0),
4485 HDSPM_EMPHASIS("Emphasis", 0),
4486 HDSPM_DOLBY("Non Audio", 0),
4487 HDSPM_PROFESSIONAL("Professional", 0),
4488 HDSPM_C_TMS("Clear Track Marker", 0),
4489 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4490 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4495 /* Control elements for the optional TCO module */
4496 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4497 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4498 HDSPM_TCO_PULL("TCO Pull", 0),
4499 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4500 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4501 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4502 HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
4506 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4509 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4513 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4514 if (hdspm->system_sample_rate > 48000) {
4515 hdspm->playback_mixer_ctls[i]->vd[0].access =
4516 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4517 SNDRV_CTL_ELEM_ACCESS_READ |
4518 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4520 hdspm->playback_mixer_ctls[i]->vd[0].access =
4521 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4522 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4524 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4525 SNDRV_CTL_EVENT_MASK_INFO,
4526 &hdspm->playback_mixer_ctls[i]->id);
4533 static int snd_hdspm_create_controls(struct snd_card *card,
4534 struct hdspm *hdspm)
4536 unsigned int idx, limit;
4538 struct snd_kcontrol *kctl;
4539 struct snd_kcontrol_new *list = NULL;
4541 switch (hdspm->io_type) {
4543 list = snd_hdspm_controls_madi;
4544 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4547 list = snd_hdspm_controls_madiface;
4548 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4551 list = snd_hdspm_controls_aio;
4552 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4555 list = snd_hdspm_controls_raydat;
4556 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4559 list = snd_hdspm_controls_aes32;
4560 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4565 for (idx = 0; idx < limit; idx++) {
4566 err = snd_ctl_add(card,
4567 snd_ctl_new1(&list[idx], hdspm));
4574 /* create simple 1:1 playback mixer controls */
4575 snd_hdspm_playback_mixer.name = "Chn";
4576 if (hdspm->system_sample_rate >= 128000) {
4577 limit = hdspm->qs_out_channels;
4578 } else if (hdspm->system_sample_rate >= 64000) {
4579 limit = hdspm->ds_out_channels;
4581 limit = hdspm->ss_out_channels;
4583 for (idx = 0; idx < limit; ++idx) {
4584 snd_hdspm_playback_mixer.index = idx + 1;
4585 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4586 err = snd_ctl_add(card, kctl);
4589 hdspm->playback_mixer_ctls[idx] = kctl;
4594 /* add tco control elements */
4595 list = snd_hdspm_controls_tco;
4596 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4597 for (idx = 0; idx < limit; idx++) {
4598 err = snd_ctl_add(card,
4599 snd_ctl_new1(&list[idx], hdspm));
4608 /*------------------------------------------------------------
4610 ------------------------------------------------------------*/
4613 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4614 struct snd_info_buffer *buffer)
4616 struct hdspm *hdspm = entry->private_data;
4617 unsigned int status, status2, control, freq;
4619 char *pref_sync_ref;
4621 char *system_clock_mode;
4626 int a, ltc, frames, seconds, minutes, hours;
4627 unsigned int period;
4631 status = hdspm_read(hdspm, HDSPM_statusRegister);
4632 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4633 control = hdspm->control_register;
4634 freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4636 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4637 hdspm->card_name, hdspm->card->number + 1,
4638 hdspm->firmware_rev,
4639 (status2 & HDSPM_version0) |
4640 (status2 & HDSPM_version1) | (status2 &
4643 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4644 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4645 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
4647 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4648 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4650 snd_iprintf(buffer, "--- System ---\n");
4653 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4654 status & HDSPM_audioIRQPending,
4655 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4656 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4659 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4660 "estimated= %ld (bytes)\n",
4661 ((status & HDSPM_BufferID) ? 1 : 0),
4662 (status & HDSPM_BufferPositionMask),
4663 (status & HDSPM_BufferPositionMask) %
4664 (2 * (int)hdspm->period_bytes),
4665 ((status & HDSPM_BufferPositionMask) - 64) %
4666 (2 * (int)hdspm->period_bytes),
4667 (long) hdspm_hw_pointer(hdspm) * 4);
4670 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4671 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4672 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4673 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4674 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4676 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4677 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4678 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4680 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4682 hdspm->control_register, hdspm->control2_register,
4684 if (status & HDSPM_tco_detect) {
4685 snd_iprintf(buffer, "TCO module detected.\n");
4686 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4687 if (a & HDSPM_TCO1_LTC_Input_valid) {
4688 snd_iprintf(buffer, " LTC valid, ");
4689 switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4690 HDSPM_TCO1_LTC_Format_MSB)) {
4692 snd_iprintf(buffer, "24 fps, ");
4694 case HDSPM_TCO1_LTC_Format_LSB:
4695 snd_iprintf(buffer, "25 fps, ");
4697 case HDSPM_TCO1_LTC_Format_MSB:
4698 snd_iprintf(buffer, "29.97 fps, ");
4701 snd_iprintf(buffer, "30 fps, ");
4704 if (a & HDSPM_TCO1_set_drop_frame_flag) {
4705 snd_iprintf(buffer, "drop frame\n");
4707 snd_iprintf(buffer, "full frame\n");
4710 snd_iprintf(buffer, " no LTC\n");
4712 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4713 snd_iprintf(buffer, " Video: NTSC\n");
4714 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4715 snd_iprintf(buffer, " Video: PAL\n");
4717 snd_iprintf(buffer, " No video\n");
4719 if (a & HDSPM_TCO1_TCO_lock) {
4720 snd_iprintf(buffer, " Sync: lock\n");
4722 snd_iprintf(buffer, " Sync: no lock\n");
4725 switch (hdspm->io_type) {
4728 freq_const = 110069313433624ULL;
4732 freq_const = 104857600000000ULL;
4735 break; /* no TCO possible */
4738 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4739 snd_iprintf(buffer, " period: %u\n", period);
4742 /* rate = freq_const/period; */
4743 rate = div_u64(freq_const, period);
4745 if (control & HDSPM_QuadSpeed) {
4747 } else if (control & HDSPM_DoubleSpeed) {
4751 snd_iprintf(buffer, " Frequency: %u Hz\n",
4752 (unsigned int) rate);
4754 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4757 frames += (ltc & 0x3) * 10;
4759 seconds = ltc & 0xF;
4761 seconds += (ltc & 0x7) * 10;
4763 minutes = ltc & 0xF;
4765 minutes += (ltc & 0x7) * 10;
4769 hours += (ltc & 0x3) * 10;
4771 " LTC In: %02d:%02d:%02d:%02d\n",
4772 hours, minutes, seconds, frames);
4775 snd_iprintf(buffer, "No TCO module detected.\n");
4778 snd_iprintf(buffer, "--- Settings ---\n");
4780 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4781 HDSPM_LatencyMask));
4784 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4785 x, (unsigned long) hdspm->period_bytes);
4787 snd_iprintf(buffer, "Line out: %s\n",
4788 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4790 switch (hdspm->control_register & HDSPM_InputMask) {
4791 case HDSPM_InputOptical:
4794 case HDSPM_InputCoaxial:
4802 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4804 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4805 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4806 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4809 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4810 system_clock_mode = "AutoSync";
4812 system_clock_mode = "Master";
4813 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4815 switch (hdspm_pref_sync_ref(hdspm)) {
4816 case HDSPM_SYNC_FROM_WORD:
4817 pref_sync_ref = "Word Clock";
4819 case HDSPM_SYNC_FROM_MADI:
4820 pref_sync_ref = "MADI Sync";
4822 case HDSPM_SYNC_FROM_TCO:
4823 pref_sync_ref = "TCO";
4825 case HDSPM_SYNC_FROM_SYNC_IN:
4826 pref_sync_ref = "Sync In";
4829 pref_sync_ref = "XXXX Clock";
4832 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4835 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4836 hdspm->system_sample_rate);
4839 snd_iprintf(buffer, "--- Status:\n");
4841 x = status & HDSPM_madiSync;
4842 x2 = status2 & HDSPM_wcSync;
4844 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4845 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4847 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4850 switch (hdspm_autosync_ref(hdspm)) {
4851 case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4852 autosync_ref = "Sync In";
4854 case HDSPM_AUTOSYNC_FROM_TCO:
4855 autosync_ref = "TCO";
4857 case HDSPM_AUTOSYNC_FROM_WORD:
4858 autosync_ref = "Word Clock";
4860 case HDSPM_AUTOSYNC_FROM_MADI:
4861 autosync_ref = "MADI Sync";
4863 case HDSPM_AUTOSYNC_FROM_NONE:
4864 autosync_ref = "Input not valid";
4867 autosync_ref = "---";
4871 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4872 autosync_ref, hdspm_external_sample_rate(hdspm),
4873 (status & HDSPM_madiFreqMask) >> 22,
4874 (status2 & HDSPM_wcFreqMask) >> 5);
4876 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4877 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4878 (status & HDSPM_RX_64ch) ? "64 channels" :
4881 snd_iprintf(buffer, "\n");
4885 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4886 struct snd_info_buffer *buffer)
4888 struct hdspm *hdspm = entry->private_data;
4889 unsigned int status;
4890 unsigned int status2;
4891 unsigned int timecode;
4896 status = hdspm_read(hdspm, HDSPM_statusRegister);
4897 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4898 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4900 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4901 hdspm->card_name, hdspm->card->number + 1,
4902 hdspm->firmware_rev);
4904 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4905 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4907 snd_iprintf(buffer, "--- System ---\n");
4910 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4911 status & HDSPM_audioIRQPending,
4912 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4913 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4916 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4917 "estimated= %ld (bytes)\n",
4918 ((status & HDSPM_BufferID) ? 1 : 0),
4919 (status & HDSPM_BufferPositionMask),
4920 (status & HDSPM_BufferPositionMask) %
4921 (2 * (int)hdspm->period_bytes),
4922 ((status & HDSPM_BufferPositionMask) - 64) %
4923 (2 * (int)hdspm->period_bytes),
4924 (long) hdspm_hw_pointer(hdspm) * 4);
4927 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4928 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4929 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4930 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4931 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4933 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4934 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4935 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4937 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4939 hdspm->control_register, hdspm->control2_register,
4942 snd_iprintf(buffer, "--- Settings ---\n");
4944 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4945 HDSPM_LatencyMask));
4948 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4949 x, (unsigned long) hdspm->period_bytes);
4951 snd_iprintf(buffer, "Line out: %s\n",
4953 control_register & HDSPM_LineOut) ? "on " : "off");
4956 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
4958 control_register & HDSPM_clr_tms) ? "on" : "off",
4960 control_register & HDSPM_Emphasis) ? "on" : "off",
4962 control_register & HDSPM_Dolby) ? "on" : "off");
4965 pref_syncref = hdspm_pref_sync_ref(hdspm);
4966 if (pref_syncref == 0)
4967 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
4969 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
4972 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4973 hdspm->system_sample_rate);
4975 snd_iprintf(buffer, "Double speed: %s\n",
4976 hdspm->control_register & HDSPM_DS_DoubleWire?
4977 "Double wire" : "Single wire");
4978 snd_iprintf(buffer, "Quad speed: %s\n",
4979 hdspm->control_register & HDSPM_QS_DoubleWire?
4981 hdspm->control_register & HDSPM_QS_QuadWire?
4982 "Quad wire" : "Single wire");
4984 snd_iprintf(buffer, "--- Status:\n");
4986 snd_iprintf(buffer, "Word: %s Frequency: %d\n",
4987 (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock",
4988 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
4990 for (x = 0; x < 8; x++) {
4991 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
4993 (status2 & (HDSPM_LockAES >> x)) ?
4994 "Sync " : "No Lock",
4995 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
4998 switch (hdspm_autosync_ref(hdspm)) {
4999 case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5000 autosync_ref = "None"; break;
5001 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5002 autosync_ref = "Word Clock"; break;
5003 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5004 autosync_ref = "AES1"; break;
5005 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5006 autosync_ref = "AES2"; break;
5007 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5008 autosync_ref = "AES3"; break;
5009 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5010 autosync_ref = "AES4"; break;
5011 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5012 autosync_ref = "AES5"; break;
5013 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5014 autosync_ref = "AES6"; break;
5015 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5016 autosync_ref = "AES7"; break;
5017 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5018 autosync_ref = "AES8"; break;
5020 autosync_ref = "---"; break;
5022 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5024 snd_iprintf(buffer, "\n");
5028 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5029 struct snd_info_buffer *buffer)
5031 struct hdspm *hdspm = entry->private_data;
5032 unsigned int status1, status2, status3, control, i;
5033 unsigned int lock, sync;
5035 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5036 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5037 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5039 control = hdspm->control_register;
5041 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5042 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5043 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5046 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5048 snd_iprintf(buffer, "Clock mode : %s\n",
5049 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5050 snd_iprintf(buffer, "System frequency: %d Hz\n",
5051 hdspm_get_system_sample_rate(hdspm));
5053 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5058 for (i = 0; i < 8; i++) {
5059 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5061 (status1 & lock) ? 1 : 0,
5062 (status1 & sync) ? 1 : 0,
5063 texts_freq[(status2 >> (i * 4)) & 0xF]);
5069 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5070 (status1 & 0x1000000) ? 1 : 0,
5071 (status1 & 0x2000000) ? 1 : 0,
5072 texts_freq[(status1 >> 16) & 0xF]);
5074 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5075 (status1 & 0x4000000) ? 1 : 0,
5076 (status1 & 0x8000000) ? 1 : 0,
5077 texts_freq[(status1 >> 20) & 0xF]);
5079 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5080 (status3 & 0x400) ? 1 : 0,
5081 (status3 & 0x800) ? 1 : 0,
5082 texts_freq[(status2 >> 12) & 0xF]);
5086 #ifdef CONFIG_SND_DEBUG
5088 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5089 struct snd_info_buffer *buffer)
5091 struct hdspm *hdspm = entry->private_data;
5095 for (i = 0; i < 256 /* 1024*64 */; i += j) {
5096 snd_iprintf(buffer, "0x%08X: ", i);
5097 for (j = 0; j < 16; j += 4)
5098 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5099 snd_iprintf(buffer, "\n");
5105 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5106 struct snd_info_buffer *buffer)
5108 struct hdspm *hdspm = entry->private_data;
5111 snd_iprintf(buffer, "# generated by hdspm\n");
5113 for (i = 0; i < hdspm->max_channels_in; i++) {
5114 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5118 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5119 struct snd_info_buffer *buffer)
5121 struct hdspm *hdspm = entry->private_data;
5124 snd_iprintf(buffer, "# generated by hdspm\n");
5126 for (i = 0; i < hdspm->max_channels_out; i++) {
5127 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5132 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
5134 struct snd_info_entry *entry;
5136 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5137 switch (hdspm->io_type) {
5139 snd_info_set_text_ops(entry, hdspm,
5140 snd_hdspm_proc_read_aes32);
5143 snd_info_set_text_ops(entry, hdspm,
5144 snd_hdspm_proc_read_madi);
5147 /* snd_info_set_text_ops(entry, hdspm,
5148 snd_hdspm_proc_read_madiface); */
5151 snd_info_set_text_ops(entry, hdspm,
5152 snd_hdspm_proc_read_raydat);
5159 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5160 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5163 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5164 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5167 #ifdef CONFIG_SND_DEBUG
5168 /* debug file to read all hdspm registers */
5169 if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5170 snd_info_set_text_ops(entry, hdspm,
5171 snd_hdspm_proc_read_debug);
5175 /*------------------------------------------------------------
5177 ------------------------------------------------------------*/
5179 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5181 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5182 hold it (e.g. during module initialization).
5187 hdspm->settings_register = 0;
5189 switch (hdspm->io_type) {
5192 hdspm->control_register =
5193 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5198 hdspm->settings_register = 0x1 + 0x1000;
5199 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5201 hdspm->control_register =
5202 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5206 hdspm->control_register =
5207 HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5208 hdspm_encode_latency(7) | /* latency max=8192samples */
5209 HDSPM_SyncRef0 | /* AES1 is syncclock */
5210 HDSPM_LineOut | /* Analog output in */
5211 HDSPM_Professional; /* Professional mode */
5215 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5217 if (AES32 == hdspm->io_type) {
5218 /* No control2 register for AES32 */
5219 #ifdef SNDRV_BIG_ENDIAN
5220 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5222 hdspm->control2_register = 0;
5225 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5227 hdspm_compute_period_size(hdspm);
5229 /* silence everything */
5231 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5233 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5234 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5237 /* set a default rate so that the channel map is set up. */
5238 hdspm_set_rate(hdspm, 48000, 1);
5244 /*------------------------------------------------------------
5246 ------------------------------------------------------------*/
5248 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5250 struct hdspm *hdspm = (struct hdspm *) dev_id;
5251 unsigned int status;
5252 int i, audio, midi, schedule = 0;
5255 status = hdspm_read(hdspm, HDSPM_statusRegister);
5257 audio = status & HDSPM_audioIRQPending;
5258 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5259 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5261 /* now = get_cycles(); */
5263 * LAT_2..LAT_0 period counter (win) counter (mac)
5264 * 6 4096 ~256053425 ~514672358
5265 * 5 2048 ~128024983 ~257373821
5266 * 4 1024 ~64023706 ~128718089
5267 * 3 512 ~32005945 ~64385999
5268 * 2 256 ~16003039 ~32260176
5269 * 1 128 ~7998738 ~16194507
5270 * 0 64 ~3998231 ~8191558
5273 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5274 now-hdspm->last_interrupt, status & 0xFFC0);
5275 hdspm->last_interrupt = now;
5278 if (!audio && !midi)
5281 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5286 if (hdspm->capture_substream)
5287 snd_pcm_period_elapsed(hdspm->capture_substream);
5289 if (hdspm->playback_substream)
5290 snd_pcm_period_elapsed(hdspm->playback_substream);
5295 while (i < hdspm->midiPorts) {
5296 if ((hdspm_read(hdspm,
5297 hdspm->midi[i].statusIn) & 0xff) &&
5298 (status & hdspm->midi[i].irq)) {
5299 /* we disable interrupts for this input until
5300 * processing is done
5302 hdspm->control_register &= ~hdspm->midi[i].ie;
5303 hdspm_write(hdspm, HDSPM_controlRegister,
5304 hdspm->control_register);
5305 hdspm->midi[i].pending = 1;
5313 tasklet_hi_schedule(&hdspm->midi_tasklet);
5319 /*------------------------------------------------------------
5321 ------------------------------------------------------------*/
5324 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5327 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5328 return hdspm_hw_pointer(hdspm);
5332 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5334 struct snd_pcm_runtime *runtime = substream->runtime;
5335 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5336 struct snd_pcm_substream *other;
5338 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5339 other = hdspm->capture_substream;
5341 other = hdspm->playback_substream;
5344 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5346 runtime->status->hw_ptr = 0;
5348 struct snd_pcm_substream *s;
5349 struct snd_pcm_runtime *oruntime = other->runtime;
5350 snd_pcm_group_for_each_entry(s, substream) {
5352 oruntime->status->hw_ptr =
5353 runtime->status->hw_ptr;
5361 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5362 struct snd_pcm_hw_params *params)
5364 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5370 spin_lock_irq(&hdspm->lock);
5372 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5373 this_pid = hdspm->playback_pid;
5374 other_pid = hdspm->capture_pid;
5376 this_pid = hdspm->capture_pid;
5377 other_pid = hdspm->playback_pid;
5380 if (other_pid > 0 && this_pid != other_pid) {
5382 /* The other stream is open, and not by the same
5383 task as this one. Make sure that the parameters
5384 that matter are the same.
5387 if (params_rate(params) != hdspm->system_sample_rate) {
5388 spin_unlock_irq(&hdspm->lock);
5389 _snd_pcm_hw_param_setempty(params,
5390 SNDRV_PCM_HW_PARAM_RATE);
5394 if (params_period_size(params) != hdspm->period_bytes / 4) {
5395 spin_unlock_irq(&hdspm->lock);
5396 _snd_pcm_hw_param_setempty(params,
5397 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5403 spin_unlock_irq(&hdspm->lock);
5405 /* how to make sure that the rate matches an externally-set one ? */
5407 spin_lock_irq(&hdspm->lock);
5408 err = hdspm_set_rate(hdspm, params_rate(params), 0);
5410 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5411 spin_unlock_irq(&hdspm->lock);
5412 _snd_pcm_hw_param_setempty(params,
5413 SNDRV_PCM_HW_PARAM_RATE);
5416 spin_unlock_irq(&hdspm->lock);
5418 err = hdspm_set_interrupt_interval(hdspm,
5419 params_period_size(params));
5421 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5422 _snd_pcm_hw_param_setempty(params,
5423 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5427 /* Memory allocation, takashi's method, dont know if we should
5430 /* malloc all buffer even if not enabled to get sure */
5431 /* Update for MADI rev 204: we need to allocate for all channels,
5432 * otherwise it doesn't work at 96kHz */
5435 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5437 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5441 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5443 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5444 params_channels(params));
5446 for (i = 0; i < params_channels(params); ++i)
5447 snd_hdspm_enable_out(hdspm, i, 1);
5449 hdspm->playback_buffer =
5450 (unsigned char *) substream->runtime->dma_area;
5451 snd_printdd("Allocated sample buffer for playback at %p\n",
5452 hdspm->playback_buffer);
5454 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5455 params_channels(params));
5457 for (i = 0; i < params_channels(params); ++i)
5458 snd_hdspm_enable_in(hdspm, i, 1);
5460 hdspm->capture_buffer =
5461 (unsigned char *) substream->runtime->dma_area;
5462 snd_printdd("Allocated sample buffer for capture at %p\n",
5463 hdspm->capture_buffer);
5467 snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5468 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5469 "playback" : "capture",
5470 snd_pcm_sgbuf_get_addr(substream, 0));
5473 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5474 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5475 "playback" : "capture",
5476 params_rate(params), params_channels(params),
5477 params_buffer_size(params));
5481 /* Switch to native float format if requested */
5482 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5483 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5484 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5486 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5487 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5488 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5489 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5491 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5493 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5498 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5501 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5503 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5505 /* params_channels(params) should be enough,
5506 but to get sure in case of error */
5507 for (i = 0; i < hdspm->max_channels_out; ++i)
5508 snd_hdspm_enable_out(hdspm, i, 0);
5510 hdspm->playback_buffer = NULL;
5512 for (i = 0; i < hdspm->max_channels_in; ++i)
5513 snd_hdspm_enable_in(hdspm, i, 0);
5515 hdspm->capture_buffer = NULL;
5519 snd_pcm_lib_free_pages(substream);
5525 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5526 struct snd_pcm_channel_info *info)
5528 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5530 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5531 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5532 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5536 if (hdspm->channel_map_out[info->channel] < 0) {
5537 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5541 info->offset = hdspm->channel_map_out[info->channel] *
5542 HDSPM_CHANNEL_BUFFER_BYTES;
5544 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5545 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5549 if (hdspm->channel_map_in[info->channel] < 0) {
5550 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5554 info->offset = hdspm->channel_map_in[info->channel] *
5555 HDSPM_CHANNEL_BUFFER_BYTES;
5564 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5565 unsigned int cmd, void *arg)
5568 case SNDRV_PCM_IOCTL1_RESET:
5569 return snd_hdspm_reset(substream);
5571 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5573 struct snd_pcm_channel_info *info = arg;
5574 return snd_hdspm_channel_info(substream, info);
5580 return snd_pcm_lib_ioctl(substream, cmd, arg);
5583 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5585 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5586 struct snd_pcm_substream *other;
5589 spin_lock(&hdspm->lock);
5590 running = hdspm->running;
5592 case SNDRV_PCM_TRIGGER_START:
5593 running |= 1 << substream->stream;
5595 case SNDRV_PCM_TRIGGER_STOP:
5596 running &= ~(1 << substream->stream);
5600 spin_unlock(&hdspm->lock);
5603 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5604 other = hdspm->capture_substream;
5606 other = hdspm->playback_substream;
5609 struct snd_pcm_substream *s;
5610 snd_pcm_group_for_each_entry(s, substream) {
5612 snd_pcm_trigger_done(s, substream);
5613 if (cmd == SNDRV_PCM_TRIGGER_START)
5614 running |= 1 << s->stream;
5616 running &= ~(1 << s->stream);
5620 if (cmd == SNDRV_PCM_TRIGGER_START) {
5621 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5622 && substream->stream ==
5623 SNDRV_PCM_STREAM_CAPTURE)
5624 hdspm_silence_playback(hdspm);
5627 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5628 hdspm_silence_playback(hdspm);
5631 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5632 hdspm_silence_playback(hdspm);
5635 snd_pcm_trigger_done(substream, substream);
5636 if (!hdspm->running && running)
5637 hdspm_start_audio(hdspm);
5638 else if (hdspm->running && !running)
5639 hdspm_stop_audio(hdspm);
5640 hdspm->running = running;
5641 spin_unlock(&hdspm->lock);
5646 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5651 static unsigned int period_sizes_old[] = {
5652 64, 128, 256, 512, 1024, 2048, 4096
5655 static unsigned int period_sizes_new[] = {
5656 32, 64, 128, 256, 512, 1024, 2048, 4096
5659 /* RayDAT and AIO always have a buffer of 16384 samples per channel */
5660 static unsigned int raydat_aio_buffer_sizes[] = {
5664 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5665 .info = (SNDRV_PCM_INFO_MMAP |
5666 SNDRV_PCM_INFO_MMAP_VALID |
5667 SNDRV_PCM_INFO_NONINTERLEAVED |
5668 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5669 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5670 .rates = (SNDRV_PCM_RATE_32000 |
5671 SNDRV_PCM_RATE_44100 |
5672 SNDRV_PCM_RATE_48000 |
5673 SNDRV_PCM_RATE_64000 |
5674 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5675 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5679 .channels_max = HDSPM_MAX_CHANNELS,
5681 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5682 .period_bytes_min = (64 * 4),
5683 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5689 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5690 .info = (SNDRV_PCM_INFO_MMAP |
5691 SNDRV_PCM_INFO_MMAP_VALID |
5692 SNDRV_PCM_INFO_NONINTERLEAVED |
5693 SNDRV_PCM_INFO_SYNC_START),
5694 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5695 .rates = (SNDRV_PCM_RATE_32000 |
5696 SNDRV_PCM_RATE_44100 |
5697 SNDRV_PCM_RATE_48000 |
5698 SNDRV_PCM_RATE_64000 |
5699 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5700 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5704 .channels_max = HDSPM_MAX_CHANNELS,
5706 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5707 .period_bytes_min = (64 * 4),
5708 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5714 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_old = {
5715 .count = ARRAY_SIZE(period_sizes_old),
5716 .list = period_sizes_old,
5720 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_new = {
5721 .count = ARRAY_SIZE(period_sizes_new),
5722 .list = period_sizes_new,
5726 static struct snd_pcm_hw_constraint_list hw_constraints_raydat_io_buffer = {
5727 .count = ARRAY_SIZE(raydat_aio_buffer_sizes),
5728 .list = raydat_aio_buffer_sizes,
5732 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5733 struct snd_pcm_hw_rule *rule)
5735 struct hdspm *hdspm = rule->private;
5736 struct snd_interval *c =
5737 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5738 struct snd_interval *r =
5739 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5741 if (r->min > 96000 && r->max <= 192000) {
5742 struct snd_interval t = {
5743 .min = hdspm->qs_in_channels,
5744 .max = hdspm->qs_in_channels,
5747 return snd_interval_refine(c, &t);
5748 } else if (r->min > 48000 && r->max <= 96000) {
5749 struct snd_interval t = {
5750 .min = hdspm->ds_in_channels,
5751 .max = hdspm->ds_in_channels,
5754 return snd_interval_refine(c, &t);
5755 } else if (r->max < 64000) {
5756 struct snd_interval t = {
5757 .min = hdspm->ss_in_channels,
5758 .max = hdspm->ss_in_channels,
5761 return snd_interval_refine(c, &t);
5767 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5768 struct snd_pcm_hw_rule * rule)
5770 struct hdspm *hdspm = rule->private;
5771 struct snd_interval *c =
5772 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5773 struct snd_interval *r =
5774 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5776 if (r->min > 96000 && r->max <= 192000) {
5777 struct snd_interval t = {
5778 .min = hdspm->qs_out_channels,
5779 .max = hdspm->qs_out_channels,
5782 return snd_interval_refine(c, &t);
5783 } else if (r->min > 48000 && r->max <= 96000) {
5784 struct snd_interval t = {
5785 .min = hdspm->ds_out_channels,
5786 .max = hdspm->ds_out_channels,
5789 return snd_interval_refine(c, &t);
5790 } else if (r->max < 64000) {
5791 struct snd_interval t = {
5792 .min = hdspm->ss_out_channels,
5793 .max = hdspm->ss_out_channels,
5796 return snd_interval_refine(c, &t);
5802 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5803 struct snd_pcm_hw_rule * rule)
5805 struct hdspm *hdspm = rule->private;
5806 struct snd_interval *c =
5807 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5808 struct snd_interval *r =
5809 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5811 if (c->min >= hdspm->ss_in_channels) {
5812 struct snd_interval t = {
5817 return snd_interval_refine(r, &t);
5818 } else if (c->max <= hdspm->qs_in_channels) {
5819 struct snd_interval t = {
5824 return snd_interval_refine(r, &t);
5825 } else if (c->max <= hdspm->ds_in_channels) {
5826 struct snd_interval t = {
5831 return snd_interval_refine(r, &t);
5836 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5837 struct snd_pcm_hw_rule *rule)
5839 struct hdspm *hdspm = rule->private;
5840 struct snd_interval *c =
5841 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5842 struct snd_interval *r =
5843 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5845 if (c->min >= hdspm->ss_out_channels) {
5846 struct snd_interval t = {
5851 return snd_interval_refine(r, &t);
5852 } else if (c->max <= hdspm->qs_out_channels) {
5853 struct snd_interval t = {
5858 return snd_interval_refine(r, &t);
5859 } else if (c->max <= hdspm->ds_out_channels) {
5860 struct snd_interval t = {
5865 return snd_interval_refine(r, &t);
5871 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5872 struct snd_pcm_hw_rule *rule)
5874 unsigned int list[3];
5875 struct hdspm *hdspm = rule->private;
5876 struct snd_interval *c = hw_param_interval(params,
5877 SNDRV_PCM_HW_PARAM_CHANNELS);
5879 list[0] = hdspm->qs_in_channels;
5880 list[1] = hdspm->ds_in_channels;
5881 list[2] = hdspm->ss_in_channels;
5882 return snd_interval_list(c, 3, list, 0);
5885 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5886 struct snd_pcm_hw_rule *rule)
5888 unsigned int list[3];
5889 struct hdspm *hdspm = rule->private;
5890 struct snd_interval *c = hw_param_interval(params,
5891 SNDRV_PCM_HW_PARAM_CHANNELS);
5893 list[0] = hdspm->qs_out_channels;
5894 list[1] = hdspm->ds_out_channels;
5895 list[2] = hdspm->ss_out_channels;
5896 return snd_interval_list(c, 3, list, 0);
5900 static unsigned int hdspm_aes32_sample_rates[] = {
5901 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5904 static struct snd_pcm_hw_constraint_list
5905 hdspm_hw_constraints_aes32_sample_rates = {
5906 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5907 .list = hdspm_aes32_sample_rates,
5911 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5913 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5914 struct snd_pcm_runtime *runtime = substream->runtime;
5916 spin_lock_irq(&hdspm->lock);
5918 snd_pcm_set_sync(substream);
5921 runtime->hw = snd_hdspm_playback_subinfo;
5923 if (hdspm->capture_substream == NULL)
5924 hdspm_stop_audio(hdspm);
5926 hdspm->playback_pid = current->pid;
5927 hdspm->playback_substream = substream;
5929 spin_unlock_irq(&hdspm->lock);
5931 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5933 switch (hdspm->io_type) {
5936 snd_pcm_hw_constraint_list(runtime, 0,
5937 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5938 &hw_constraints_period_sizes_new);
5939 snd_pcm_hw_constraint_list(runtime, 0,
5940 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5941 &hw_constraints_raydat_io_buffer);
5946 snd_pcm_hw_constraint_list(runtime, 0,
5947 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5948 &hw_constraints_period_sizes_old);
5951 if (AES32 == hdspm->io_type) {
5952 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5953 &hdspm_hw_constraints_aes32_sample_rates);
5955 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5956 snd_hdspm_hw_rule_rate_out_channels, hdspm,
5957 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5960 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5961 snd_hdspm_hw_rule_out_channels, hdspm,
5962 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5964 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5965 snd_hdspm_hw_rule_out_channels_rate, hdspm,
5966 SNDRV_PCM_HW_PARAM_RATE, -1);
5971 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
5973 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5975 spin_lock_irq(&hdspm->lock);
5977 hdspm->playback_pid = -1;
5978 hdspm->playback_substream = NULL;
5980 spin_unlock_irq(&hdspm->lock);
5986 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
5988 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5989 struct snd_pcm_runtime *runtime = substream->runtime;
5991 spin_lock_irq(&hdspm->lock);
5992 snd_pcm_set_sync(substream);
5993 runtime->hw = snd_hdspm_capture_subinfo;
5995 if (hdspm->playback_substream == NULL)
5996 hdspm_stop_audio(hdspm);
5998 hdspm->capture_pid = current->pid;
5999 hdspm->capture_substream = substream;
6001 spin_unlock_irq(&hdspm->lock);
6003 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6004 switch (hdspm->io_type) {
6007 snd_pcm_hw_constraint_list(runtime, 0,
6008 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6009 &hw_constraints_period_sizes_new);
6010 snd_pcm_hw_constraint_list(runtime, 0,
6011 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6012 &hw_constraints_raydat_io_buffer);
6016 snd_pcm_hw_constraint_list(runtime, 0,
6017 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6018 &hw_constraints_period_sizes_old);
6021 if (AES32 == hdspm->io_type) {
6022 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6023 &hdspm_hw_constraints_aes32_sample_rates);
6025 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6026 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6027 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6030 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6031 snd_hdspm_hw_rule_in_channels, hdspm,
6032 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6034 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6035 snd_hdspm_hw_rule_in_channels_rate, hdspm,
6036 SNDRV_PCM_HW_PARAM_RATE, -1);
6041 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6043 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6045 spin_lock_irq(&hdspm->lock);
6047 hdspm->capture_pid = -1;
6048 hdspm->capture_substream = NULL;
6050 spin_unlock_irq(&hdspm->lock);
6054 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6056 /* we have nothing to initialize but the call is required */
6060 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6062 u32 val = readl(src);
6063 return copy_to_user(dest, &val, 4);
6066 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6067 unsigned int cmd, unsigned long __user arg)
6069 void __user *argp = (void __user *)arg;
6070 struct hdspm *hdspm = hw->private_data;
6071 struct hdspm_mixer_ioctl mixer;
6072 struct hdspm_config info;
6073 struct hdspm_status status;
6074 struct hdspm_version hdspm_version;
6075 struct hdspm_peak_rms *levels;
6076 struct hdspm_ltc ltc;
6077 unsigned int statusregister;
6078 long unsigned int s;
6083 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6084 levels = &hdspm->peak_rms;
6085 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6086 levels->input_peaks[i] =
6087 readl(hdspm->iobase +
6088 HDSPM_MADI_INPUT_PEAK + i*4);
6089 levels->playback_peaks[i] =
6090 readl(hdspm->iobase +
6091 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6092 levels->output_peaks[i] =
6093 readl(hdspm->iobase +
6094 HDSPM_MADI_OUTPUT_PEAK + i*4);
6096 levels->input_rms[i] =
6097 ((uint64_t) readl(hdspm->iobase +
6098 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6099 (uint64_t) readl(hdspm->iobase +
6100 HDSPM_MADI_INPUT_RMS_L + i*4);
6101 levels->playback_rms[i] =
6102 ((uint64_t)readl(hdspm->iobase +
6103 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6104 (uint64_t)readl(hdspm->iobase +
6105 HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6106 levels->output_rms[i] =
6107 ((uint64_t)readl(hdspm->iobase +
6108 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6109 (uint64_t)readl(hdspm->iobase +
6110 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6113 if (hdspm->system_sample_rate > 96000) {
6115 } else if (hdspm->system_sample_rate > 48000) {
6120 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6122 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6124 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6125 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6131 case SNDRV_HDSPM_IOCTL_GET_LTC:
6132 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6133 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6134 if (i & HDSPM_TCO1_LTC_Input_valid) {
6135 switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6136 HDSPM_TCO1_LTC_Format_MSB)) {
6138 ltc.format = fps_24;
6140 case HDSPM_TCO1_LTC_Format_LSB:
6141 ltc.format = fps_25;
6143 case HDSPM_TCO1_LTC_Format_MSB:
6144 ltc.format = fps_2997;
6150 if (i & HDSPM_TCO1_set_drop_frame_flag) {
6151 ltc.frame = drop_frame;
6153 ltc.frame = full_frame;
6156 ltc.format = format_invalid;
6157 ltc.frame = frame_invalid;
6159 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6160 ltc.input_format = ntsc;
6161 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6162 ltc.input_format = pal;
6164 ltc.input_format = no_video;
6167 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc));
6170 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6176 case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6178 memset(&info, 0, sizeof(info));
6179 spin_lock_irq(&hdspm->lock);
6180 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6181 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6183 info.system_sample_rate = hdspm->system_sample_rate;
6184 info.autosync_sample_rate =
6185 hdspm_external_sample_rate(hdspm);
6186 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6187 info.clock_source = hdspm_clock_source(hdspm);
6188 info.autosync_ref = hdspm_autosync_ref(hdspm);
6189 info.line_out = hdspm_line_out(hdspm);
6191 spin_unlock_irq(&hdspm->lock);
6192 if (copy_to_user((void __user *) arg, &info, sizeof(info)))
6196 case SNDRV_HDSPM_IOCTL_GET_STATUS:
6197 status.card_type = hdspm->io_type;
6199 status.autosync_source = hdspm_autosync_ref(hdspm);
6201 status.card_clock = 110069313433624ULL;
6202 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6204 switch (hdspm->io_type) {
6207 status.card_specific.madi.sync_wc =
6208 hdspm_wc_sync_check(hdspm);
6209 status.card_specific.madi.sync_madi =
6210 hdspm_madi_sync_check(hdspm);
6211 status.card_specific.madi.sync_tco =
6212 hdspm_tco_sync_check(hdspm);
6213 status.card_specific.madi.sync_in =
6214 hdspm_sync_in_sync_check(hdspm);
6217 hdspm_read(hdspm, HDSPM_statusRegister);
6218 status.card_specific.madi.madi_input =
6219 (statusregister & HDSPM_AB_int) ? 1 : 0;
6220 status.card_specific.madi.channel_format =
6221 (statusregister & HDSPM_TX_64ch) ? 1 : 0;
6222 /* TODO: Mac driver sets it when f_s>48kHz */
6223 status.card_specific.madi.frame_format = 0;
6229 if (copy_to_user((void __user *) arg, &status, sizeof(status)))
6235 case SNDRV_HDSPM_IOCTL_GET_VERSION:
6236 hdspm_version.card_type = hdspm->io_type;
6237 strncpy(hdspm_version.cardname, hdspm->card_name,
6238 sizeof(hdspm_version.cardname));
6239 hdspm_version.serial = (hdspm_read(hdspm,
6240 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6241 hdspm_version.firmware_rev = hdspm->firmware_rev;
6242 hdspm_version.addons = 0;
6244 hdspm_version.addons |= HDSPM_ADDON_TCO;
6246 if (copy_to_user((void __user *) arg, &hdspm_version,
6247 sizeof(hdspm_version)))
6251 case SNDRV_HDSPM_IOCTL_GET_MIXER:
6252 if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer)))
6254 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6255 sizeof(struct hdspm_mixer)))
6265 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6266 .open = snd_hdspm_playback_open,
6267 .close = snd_hdspm_playback_release,
6268 .ioctl = snd_hdspm_ioctl,
6269 .hw_params = snd_hdspm_hw_params,
6270 .hw_free = snd_hdspm_hw_free,
6271 .prepare = snd_hdspm_prepare,
6272 .trigger = snd_hdspm_trigger,
6273 .pointer = snd_hdspm_hw_pointer,
6274 .page = snd_pcm_sgbuf_ops_page,
6277 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6278 .open = snd_hdspm_capture_open,
6279 .close = snd_hdspm_capture_release,
6280 .ioctl = snd_hdspm_ioctl,
6281 .hw_params = snd_hdspm_hw_params,
6282 .hw_free = snd_hdspm_hw_free,
6283 .prepare = snd_hdspm_prepare,
6284 .trigger = snd_hdspm_trigger,
6285 .pointer = snd_hdspm_hw_pointer,
6286 .page = snd_pcm_sgbuf_ops_page,
6289 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
6290 struct hdspm * hdspm)
6292 struct snd_hwdep *hw;
6295 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6300 hw->private_data = hdspm;
6301 strcpy(hw->name, "HDSPM hwdep interface");
6303 hw->ops.open = snd_hdspm_hwdep_dummy_op;
6304 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6305 hw->ops.release = snd_hdspm_hwdep_dummy_op;
6311 /*------------------------------------------------------------
6313 ------------------------------------------------------------*/
6314 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6317 struct snd_pcm *pcm;
6322 wanted = HDSPM_DMA_AREA_BYTES;
6325 snd_pcm_lib_preallocate_pages_for_all(pcm,
6326 SNDRV_DMA_TYPE_DEV_SG,
6327 snd_dma_pci_data(hdspm->pci),
6331 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6335 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6341 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6342 struct snd_pcm_substream *substream,
6343 unsigned int reg, int channels)
6347 /* continuous memory segment */
6348 for (i = 0; i < (channels * 16); i++)
6349 hdspm_write(hdspm, reg + 4 * i,
6350 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6354 /* ------------- ALSA Devices ---------------------------- */
6355 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
6356 struct hdspm *hdspm)
6358 struct snd_pcm *pcm;
6361 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6366 pcm->private_data = hdspm;
6367 strcpy(pcm->name, hdspm->card_name);
6369 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6370 &snd_hdspm_playback_ops);
6371 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6372 &snd_hdspm_capture_ops);
6374 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6376 err = snd_hdspm_preallocate_memory(hdspm);
6383 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6387 for (i = 0; i < hdspm->midiPorts; i++)
6388 snd_hdspm_flush_midi_input(hdspm, i);
6391 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
6392 struct hdspm * hdspm)
6396 snd_printdd("Create card...\n");
6397 err = snd_hdspm_create_pcm(card, hdspm);
6402 while (i < hdspm->midiPorts) {
6403 err = snd_hdspm_create_midi(card, hdspm, i);
6410 err = snd_hdspm_create_controls(card, hdspm);
6414 err = snd_hdspm_create_hwdep(card, hdspm);
6418 snd_printdd("proc init...\n");
6419 snd_hdspm_proc_init(hdspm);
6421 hdspm->system_sample_rate = -1;
6422 hdspm->last_external_sample_rate = -1;
6423 hdspm->last_internal_sample_rate = -1;
6424 hdspm->playback_pid = -1;
6425 hdspm->capture_pid = -1;
6426 hdspm->capture_substream = NULL;
6427 hdspm->playback_substream = NULL;
6429 snd_printdd("Set defaults...\n");
6430 err = snd_hdspm_set_defaults(hdspm);
6434 snd_printdd("Update mixer controls...\n");
6435 hdspm_update_simple_mixer_controls(hdspm);
6437 snd_printdd("Initializeing complete ???\n");
6439 err = snd_card_register(card);
6441 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6445 snd_printdd("... yes now\n");
6450 static int __devinit snd_hdspm_create(struct snd_card *card,
6451 struct hdspm *hdspm) {
6453 struct pci_dev *pci = hdspm->pci;
6455 unsigned long io_extent;
6460 spin_lock_init(&hdspm->lock);
6462 pci_read_config_word(hdspm->pci,
6463 PCI_CLASS_REVISION, &hdspm->firmware_rev);
6465 strcpy(card->mixername, "Xilinx FPGA");
6466 strcpy(card->driver, "HDSPM");
6468 switch (hdspm->firmware_rev) {
6469 case HDSPM_MADI_REV:
6470 case HDSPM_MADI_OLD_REV:
6471 hdspm->io_type = MADI;
6472 hdspm->card_name = "RME MADI";
6473 hdspm->midiPorts = 3;
6475 case HDSPM_RAYDAT_REV:
6476 hdspm->io_type = RayDAT;
6477 hdspm->card_name = "RME RayDAT";
6478 hdspm->midiPorts = 2;
6481 hdspm->io_type = AIO;
6482 hdspm->card_name = "RME AIO";
6483 hdspm->midiPorts = 1;
6485 case HDSPM_MADIFACE_REV:
6486 hdspm->io_type = MADIface;
6487 hdspm->card_name = "RME MADIface";
6488 hdspm->midiPorts = 1;
6491 case HDSPM_AES32_REV:
6492 case HDSPM_AES32_OLD_REV:
6493 hdspm->io_type = AES32;
6494 hdspm->card_name = "RME AES32";
6495 hdspm->midiPorts = 2;
6498 snd_printk(KERN_ERR "HDSPM: unknown firmware revision %x\n",
6499 hdspm->firmware_rev);
6503 err = pci_enable_device(pci);
6507 pci_set_master(hdspm->pci);
6509 err = pci_request_regions(pci, "hdspm");
6513 hdspm->port = pci_resource_start(pci, 0);
6514 io_extent = pci_resource_len(pci, 0);
6516 snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6517 hdspm->port, hdspm->port + io_extent - 1);
6519 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6520 if (!hdspm->iobase) {
6521 snd_printk(KERN_ERR "HDSPM: "
6522 "unable to remap region 0x%lx-0x%lx\n",
6523 hdspm->port, hdspm->port + io_extent - 1);
6526 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6527 (unsigned long)hdspm->iobase, hdspm->port,
6528 hdspm->port + io_extent - 1);
6530 if (request_irq(pci->irq, snd_hdspm_interrupt,
6531 IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6532 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6536 snd_printdd("use IRQ %d\n", pci->irq);
6538 hdspm->irq = pci->irq;
6540 snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6541 sizeof(struct hdspm_mixer));
6542 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6543 if (!hdspm->mixer) {
6544 snd_printk(KERN_ERR "HDSPM: "
6545 "unable to kmalloc Mixer memory of %d Bytes\n",
6546 (int)sizeof(struct hdspm_mixer));
6550 hdspm->port_names_in = NULL;
6551 hdspm->port_names_out = NULL;
6553 switch (hdspm->io_type) {
6555 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6556 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6557 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6559 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6561 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6563 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6565 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6567 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6569 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6572 hdspm->max_channels_out = hdspm->max_channels_in =
6574 hdspm->port_names_in = hdspm->port_names_out =
6576 hdspm->channel_map_in = hdspm->channel_map_out =
6583 hdspm->ss_in_channels = hdspm->ss_out_channels =
6585 hdspm->ds_in_channels = hdspm->ds_out_channels =
6587 hdspm->qs_in_channels = hdspm->qs_out_channels =
6590 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6591 channel_map_unity_ss;
6592 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6593 channel_map_unity_ss;
6594 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6595 channel_map_unity_ss;
6597 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6599 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6601 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6606 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6607 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6610 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6611 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6612 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6613 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6614 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6615 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6617 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6618 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6619 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6621 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6622 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6623 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6625 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6626 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6627 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6628 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6629 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6630 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6635 hdspm->ss_in_channels = hdspm->ss_out_channels =
6637 hdspm->ds_in_channels = hdspm->ds_out_channels =
6639 hdspm->qs_in_channels = hdspm->qs_out_channels =
6642 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6643 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6645 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6646 channel_map_raydat_ss;
6647 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6648 channel_map_raydat_ds;
6649 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6650 channel_map_raydat_qs;
6651 hdspm->channel_map_in = hdspm->channel_map_out =
6652 channel_map_raydat_ss;
6654 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6655 texts_ports_raydat_ss;
6656 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6657 texts_ports_raydat_ds;
6658 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6659 texts_ports_raydat_qs;
6667 switch (hdspm->io_type) {
6670 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6671 HDSPM_s2_tco_detect) {
6673 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6675 if (NULL != hdspm->tco) {
6676 hdspm_tco_write(hdspm);
6678 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6685 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6687 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6689 if (NULL != hdspm->tco) {
6690 hdspm_tco_write(hdspm);
6692 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6703 switch (hdspm->io_type) {
6706 hdspm->texts_autosync = texts_autosync_aes_tco;
6707 hdspm->texts_autosync_items = 10;
6709 hdspm->texts_autosync = texts_autosync_aes;
6710 hdspm->texts_autosync_items = 9;
6716 hdspm->texts_autosync = texts_autosync_madi_tco;
6717 hdspm->texts_autosync_items = 4;
6719 hdspm->texts_autosync = texts_autosync_madi;
6720 hdspm->texts_autosync_items = 3;
6730 hdspm->texts_autosync = texts_autosync_raydat_tco;
6731 hdspm->texts_autosync_items = 9;
6733 hdspm->texts_autosync = texts_autosync_raydat;
6734 hdspm->texts_autosync_items = 8;
6740 hdspm->texts_autosync = texts_autosync_aio_tco;
6741 hdspm->texts_autosync_items = 6;
6743 hdspm->texts_autosync = texts_autosync_aio;
6744 hdspm->texts_autosync_items = 5;
6750 tasklet_init(&hdspm->midi_tasklet,
6751 hdspm_midi_tasklet, (unsigned long) hdspm);
6753 snd_printdd("create alsa devices.\n");
6754 err = snd_hdspm_create_alsa_devices(card, hdspm);
6758 snd_hdspm_initialize_midi_flush(hdspm);
6764 static int snd_hdspm_free(struct hdspm * hdspm)
6769 /* stop th audio, and cancel all interrupts */
6770 hdspm->control_register &=
6771 ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6772 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6773 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6774 hdspm_write(hdspm, HDSPM_controlRegister,
6775 hdspm->control_register);
6778 if (hdspm->irq >= 0)
6779 free_irq(hdspm->irq, (void *) hdspm);
6781 kfree(hdspm->mixer);
6784 iounmap(hdspm->iobase);
6787 pci_release_regions(hdspm->pci);
6789 pci_disable_device(hdspm->pci);
6794 static void snd_hdspm_card_free(struct snd_card *card)
6796 struct hdspm *hdspm = card->private_data;
6799 snd_hdspm_free(hdspm);
6803 static int __devinit snd_hdspm_probe(struct pci_dev *pci,
6804 const struct pci_device_id *pci_id)
6807 struct hdspm *hdspm;
6808 struct snd_card *card;
6811 if (dev >= SNDRV_CARDS)
6818 err = snd_card_create(index[dev], id[dev],
6819 THIS_MODULE, sizeof(struct hdspm), &card);
6823 hdspm = card->private_data;
6824 card->private_free = snd_hdspm_card_free;
6828 snd_card_set_dev(card, &pci->dev);
6830 err = snd_hdspm_create(card, hdspm);
6832 snd_card_free(card);
6836 if (hdspm->io_type != MADIface) {
6837 sprintf(card->shortname, "%s_%x",
6839 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
6840 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6842 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF,
6843 hdspm->port, hdspm->irq);
6845 sprintf(card->shortname, "%s", hdspm->card_name);
6846 sprintf(card->longname, "%s at 0x%lx, irq %d",
6847 hdspm->card_name, hdspm->port, hdspm->irq);
6850 err = snd_card_register(card);
6852 snd_card_free(card);
6856 pci_set_drvdata(pci, card);
6862 static void __devexit snd_hdspm_remove(struct pci_dev *pci)
6864 snd_card_free(pci_get_drvdata(pci));
6865 pci_set_drvdata(pci, NULL);
6868 static struct pci_driver driver = {
6869 .name = KBUILD_MODNAME,
6870 .id_table = snd_hdspm_ids,
6871 .probe = snd_hdspm_probe,
6872 .remove = __devexit_p(snd_hdspm_remove),
6876 static int __init alsa_card_hdspm_init(void)
6878 return pci_register_driver(&driver);
6881 static void __exit alsa_card_hdspm_exit(void)
6883 pci_unregister_driver(&driver);
6886 module_init(alsa_card_hdspm_init)
6887 module_exit(alsa_card_hdspm_exit)