d21964994168cce0f81c4546156174f6490e2487
[firefly-linux-kernel-4.4.55.git] / sound / pci / rme9652 / hdspm.c
1 /*
2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
3  *
4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
5  *      code based on hdsp.c   Paul Davis
6  *                             Marcus Andersson
7  *                             Thomas Charbonnel
8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
9  *                                               <remy.bruno@trinnov.com>
10  *
11  *      Modified 2009-04-13 for proper metering by Florian Faber
12  *                                               <faber@faberman.de>
13  *
14  *      Modified 2009-04-14 for native float support by Florian Faber
15  *                                               <faber@faberman.de>
16  *
17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
18  *                                               <faber@faberman.de>
19  *
20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
21  *
22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
23  *
24  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
25  *
26  *   This program is free software; you can redistribute it and/or modify
27  *   it under the terms of the GNU General Public License as published by
28  *   the Free Software Foundation; either version 2 of the License, or
29  *   (at your option) any later version.
30  *
31  *   This program is distributed in the hope that it will be useful,
32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
34  *   GNU General Public License for more details.
35  *
36  *   You should have received a copy of the GNU General Public License
37  *   along with this program; if not, write to the Free Software
38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
39  *
40  */
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/moduleparam.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/math64.h>
48 #include <asm/io.h>
49
50 #include <sound/core.h>
51 #include <sound/control.h>
52 #include <sound/pcm.h>
53 #include <sound/pcm_params.h>
54 #include <sound/info.h>
55 #include <sound/asoundef.h>
56 #include <sound/rawmidi.h>
57 #include <sound/hwdep.h>
58 #include <sound/initval.h>
59
60 #include <sound/hdspm.h>
61
62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
64 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
65
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
68
69 module_param_array(id, charp, NULL, 0444);
70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
71
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
74
75
76 MODULE_AUTHOR
77 (
78         "Winfried Ritsch <ritsch_AT_iem.at>, "
79         "Paul Davis <paul@linuxaudiosystems.com>, "
80         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
81         "Remy Bruno <remy.bruno@trinnov.com>, "
82         "Florian Faber <faberman@linuxproaudio.org>, "
83         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
84 );
85 MODULE_DESCRIPTION("RME HDSPM");
86 MODULE_LICENSE("GPL");
87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
88
89 /* --- Write registers. ---
90   These are defined as byte-offsets from the iobase value.  */
91
92 #define HDSPM_WR_SETTINGS             0
93 #define HDSPM_outputBufferAddress    32
94 #define HDSPM_inputBufferAddress     36
95 #define HDSPM_controlRegister        64
96 #define HDSPM_interruptConfirmation  96
97 #define HDSPM_control2Reg            256  /* not in specs ???????? */
98 #define HDSPM_freqReg                256  /* for AES32 */
99 #define HDSPM_midiDataOut0           352  /* just believe in old code */
100 #define HDSPM_midiDataOut1           356
101 #define HDSPM_eeprom_wr              384  /* for AES32 */
102
103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
105 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
106
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut       8192
110 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
111
112 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
113
114 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
115
116 /* --- Read registers. ---
117    These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister    0
119 /*#define HDSPM_statusRegister2  96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121  * offset 192, for AES32 *and* MADI
122  * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2  192
124 #define HDSPM_timecodeRegister 128
125
126 /* AIO, RayDAT */
127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192
131
132 #define HDSPM_RD_TCO           256
133 #define HDSPM_RD_PLL_FREQ      512
134 #define HDSPM_WR_TCO           128
135
136 #define HDSPM_TCO1_TCO_lock                     0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
143
144 #define HDSPM_TCO1_set_TC                       0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
148
149 #define HDSPM_TCO2_TC_run                       0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
154 #define HDSPM_TCO2_set_jam_sync                 0x00200000
155 #define HDSPM_TCO2_set_flywheel                 0x00400000
156
157 #define HDSPM_TCO2_set_01_4                     0x01000000
158 #define HDSPM_TCO2_set_pull_down                0x02000000
159 #define HDSPM_TCO2_set_pull_up                  0x04000000
160 #define HDSPM_TCO2_set_freq                     0x08000000
161 #define HDSPM_TCO2_set_term_75R                 0x10000000
162 #define HDSPM_TCO2_set_input_LSB                0x20000000
163 #define HDSPM_TCO2_set_input_MSB                0x40000000
164 #define HDSPM_TCO2_set_freq_from_app            0x80000000
165
166
167 #define HDSPM_midiDataOut0    352
168 #define HDSPM_midiDataOut1    356
169 #define HDSPM_midiDataOut2    368
170
171 #define HDSPM_midiDataIn0     360
172 #define HDSPM_midiDataIn1     364
173 #define HDSPM_midiDataIn2     372
174 #define HDSPM_midiDataIn3     376
175
176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0  384
178 #define HDSPM_midiStatusOut1  388
179 #define HDSPM_midiStatusOut2  400
180
181 #define HDSPM_midiStatusIn0   392
182 #define HDSPM_midiStatusIn1   396
183 #define HDSPM_midiStatusIn2   404
184 #define HDSPM_midiStatusIn3   408
185
186
187 /* the meters are regular i/o-mapped registers, but offset
188    considerably from the rest. the peak registers are reset
189    when read; the least-significant 4 bits are full-scale counters;
190    the actual peak value is in the most-significant 24 bits.
191 */
192
193 #define HDSPM_MADI_INPUT_PEAK           4096
194 #define HDSPM_MADI_PLAYBACK_PEAK        4352
195 #define HDSPM_MADI_OUTPUT_PEAK          4608
196
197 #define HDSPM_MADI_INPUT_RMS_L          6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
199 #define HDSPM_MADI_OUTPUT_RMS_L         6656
200
201 #define HDSPM_MADI_INPUT_RMS_H          7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
203 #define HDSPM_MADI_OUTPUT_RMS_H         7680
204
205 /* --- Control Register bits --------- */
206 #define HDSPM_Start                (1<<0) /* start engine */
207
208 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1             (1<<2) /* where n is defined */
210 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
211
212 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
214                                           register [RayDAT, AIO] */
215
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
217
218 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
222
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
225                                      56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
227
228 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
229                                      0=off, 1=on  */ /* MADI ONLY */
230 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
231
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
233                                     * -- MADI ONLY
234                                     */
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
236
237 #define HDSPM_SyncRef2     (1<<13)
238 #define HDSPM_SyncRef3     (1<<25)
239
240 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
242                                       AES additional bits in
243                                       lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
246
247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000
251
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT         0x2000000
254
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
258
259 #define HDSPM_wclk_sel (1<<30)
260
261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
264                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical   0
267 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269                               HDSPM_SyncRef2|HDSPM_SyncRef3)
270
271 #define HDSPM_c0_SyncRef0      0x2
272 #define HDSPM_c0_SyncRef1      0x4
273 #define HDSPM_c0_SyncRef2      0x8
274 #define HDSPM_c0_SyncRef3      0x10
275 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
277
278 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO     2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3
282
283 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
289                                 HDSPM_Frequency0)
290 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
293                                  HDSPM_Frequency0)
294
295
296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK    1
299 #define HDSPM_SYNC_CHECK_SYNC    2
300
301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD      0
303 #define HDSPM_AUTOSYNC_FROM_MADI      1
304 #define HDSPM_AUTOSYNC_FROM_TCO       2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
306 #define HDSPM_AUTOSYNC_FROM_NONE      4
307
308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0         /* optical   */
310 #define HDSPM_COAXIAL 1         /* BNC */
311
312 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
314
315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
317
318 /* --- control2 register bits --- */
319 #define HDSPM_TMS             (1<<0)
320 #define HDSPM_TCK             (1<<1)
321 #define HDSPM_TDI             (1<<2)
322 #define HDSPM_JTAG            (1<<3)
323 #define HDSPM_PWDN            (1<<4)
324 #define HDSPM_PROGRAM         (1<<5)
325 #define HDSPM_CONFIG_MODE_0   (1<<6)
326 #define HDSPM_CONFIG_MODE_1   (1<<7)
327 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE  (1<<9)
329 #define HDSPM_RD_MULTIPLE     (1<<10)
330
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332      that do not conflict with specific bits for AES32 seem to be valid also
333      for the AES32
334  */
335 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
338                                          * (like inp0)
339                                          */
340
341 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
343
344 #define HDSPM_tcoLock    0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status */
346
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
349
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351                         /* since 64byte accurate, last 6 bits are not used */
352
353
354
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
356
357 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
361
362 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
363                                          * Interrupt
364                                          */
365 #define HDSPM_tco_detect         0x08000000
366 #define HDSPM_tco_lock           0x20000000
367
368 #define HDSPM_s2_tco_detect      0x00000040
369 #define HDSPM_s2_AEBO_D          0x00000080
370 #define HDSPM_s2_AEBI_D          0x00000100
371
372
373 #define HDSPM_midi0IRQPending    0x40000000
374 #define HDSPM_midi1IRQPending    0x80000000
375 #define HDSPM_midi2IRQPending    0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending    0x00200000
378
379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381                              HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
391
392 /* Status2 Register bits */ /* MADI ONLY */
393
394 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
395 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2)
397
398 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
400
401 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
402 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, */
404 /* missing Bit   for               111=128, 1000=176.4, 1001=192 */
405
406 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000
408
409 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
412
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
414
415 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
417 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
418 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
419 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
420 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
421 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
422
423 #define HDSPM_status1_F_0 0x0400000
424 #define HDSPM_status1_F_1 0x0800000
425 #define HDSPM_status1_F_2 0x1000000
426 #define HDSPM_status1_F_3 0x2000000
427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
428
429
430 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
431                                     HDSPM_SelSyncRef2)
432 #define HDSPM_SelSyncRef_WORD      0
433 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
434 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
435 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
437                                     HDSPM_SelSyncRef2)
438
439 /*
440    For AES32, bits for status, status2 and timecode are different
441 */
442 /* status */
443 #define HDSPM_AES32_wcLock      0x0200000
444 #define HDSPM_AES32_wcFreq_bit  22
445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
446   HDSPM_bit2freq */
447 #define HDSPM_AES32_syncref_bit  16
448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
449
450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
460
461 /*  status2 */
462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
463 #define HDSPM_LockAES   0x80
464 #define HDSPM_LockAES1  0x80
465 #define HDSPM_LockAES2  0x40
466 #define HDSPM_LockAES3  0x20
467 #define HDSPM_LockAES4  0x10
468 #define HDSPM_LockAES5  0x8
469 #define HDSPM_LockAES6  0x4
470 #define HDSPM_LockAES7  0x2
471 #define HDSPM_LockAES8  0x1
472 /*
473    Timecode
474    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
475    AES i+1
476  bits 3210
477       0001  32kHz
478       0010  44.1kHz
479       0011  48kHz
480       0100  64kHz
481       0101  88.2kHz
482       0110  96kHz
483       0111  128kHz
484       1000  176.4kHz
485       1001  192kHz
486   NB: Timecode register doesn't seem to work on AES32 card revision 230
487 */
488
489 /* Mixer Values */
490 #define UNITY_GAIN          32768       /* = 65536/2 */
491 #define MINUS_INFINITY_GAIN 0
492
493 /* Number of channels for different Speed Modes */
494 #define MADI_SS_CHANNELS       64
495 #define MADI_DS_CHANNELS       32
496 #define MADI_QS_CHANNELS       16
497
498 #define RAYDAT_SS_CHANNELS     36
499 #define RAYDAT_DS_CHANNELS     20
500 #define RAYDAT_QS_CHANNELS     12
501
502 #define AIO_IN_SS_CHANNELS        14
503 #define AIO_IN_DS_CHANNELS        10
504 #define AIO_IN_QS_CHANNELS        8
505 #define AIO_OUT_SS_CHANNELS        16
506 #define AIO_OUT_DS_CHANNELS        12
507 #define AIO_OUT_QS_CHANNELS        10
508
509 #define AES32_CHANNELS          16
510
511 /* the size of a substream (1 mono data stream) */
512 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
513 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
514
515 /* the size of the area we need to allocate for DMA transfers. the
516    size is the same regardless of the number of channels, and
517    also the latency to use.
518    for one direction !!!
519 */
520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
522
523 /* revisions >= 230 indicate AES32 card */
524 #define HDSPM_MADI_OLD_REV      207
525 #define HDSPM_MADI_REV          210
526 #define HDSPM_RAYDAT_REV        211
527 #define HDSPM_AIO_REV           212
528 #define HDSPM_MADIFACE_REV      213
529 #define HDSPM_AES_REV           240
530 #define HDSPM_AES32_REV         234
531 #define HDSPM_AES32_OLD_REV     233
532
533 /* speed factor modes */
534 #define HDSPM_SPEED_SINGLE 0
535 #define HDSPM_SPEED_DOUBLE 1
536 #define HDSPM_SPEED_QUAD   2
537
538 /* names for speed modes */
539 static char *hdspm_speed_names[] = { "single", "double", "quad" };
540
541 static char *texts_autosync_aes_tco[] = { "Word Clock",
542                                           "AES1", "AES2", "AES3", "AES4",
543                                           "AES5", "AES6", "AES7", "AES8",
544                                           "TCO" };
545 static char *texts_autosync_aes[] = { "Word Clock",
546                                       "AES1", "AES2", "AES3", "AES4",
547                                       "AES5", "AES6", "AES7", "AES8" };
548 static char *texts_autosync_madi_tco[] = { "Word Clock",
549                                            "MADI", "TCO", "Sync In" };
550 static char *texts_autosync_madi[] = { "Word Clock",
551                                        "MADI", "Sync In" };
552
553 static char *texts_autosync_raydat_tco[] = {
554         "Word Clock",
555         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
556         "AES", "SPDIF", "TCO", "Sync In"
557 };
558 static char *texts_autosync_raydat[] = {
559         "Word Clock",
560         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
561         "AES", "SPDIF", "Sync In"
562 };
563 static char *texts_autosync_aio_tco[] = {
564         "Word Clock",
565         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
566 };
567 static char *texts_autosync_aio[] = { "Word Clock",
568                                       "ADAT", "AES", "SPDIF", "Sync In" };
569
570 static char *texts_freq[] = {
571         "No Lock",
572         "32 kHz",
573         "44.1 kHz",
574         "48 kHz",
575         "64 kHz",
576         "88.2 kHz",
577         "96 kHz",
578         "128 kHz",
579         "176.4 kHz",
580         "192 kHz"
581 };
582
583 static char *texts_ports_madi[] = {
584         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
585         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
586         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
587         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
588         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
589         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
590         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
591         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
592         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
593         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
594         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
595 };
596
597
598 static char *texts_ports_raydat_ss[] = {
599         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
600         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
601         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
602         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
603         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
604         "ADAT4.7", "ADAT4.8",
605         "AES.L", "AES.R",
606         "SPDIF.L", "SPDIF.R"
607 };
608
609 static char *texts_ports_raydat_ds[] = {
610         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
611         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
612         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
613         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
614         "AES.L", "AES.R",
615         "SPDIF.L", "SPDIF.R"
616 };
617
618 static char *texts_ports_raydat_qs[] = {
619         "ADAT1.1", "ADAT1.2",
620         "ADAT2.1", "ADAT2.2",
621         "ADAT3.1", "ADAT3.2",
622         "ADAT4.1", "ADAT4.2",
623         "AES.L", "AES.R",
624         "SPDIF.L", "SPDIF.R"
625 };
626
627
628 static char *texts_ports_aio_in_ss[] = {
629         "Analogue.L", "Analogue.R",
630         "AES.L", "AES.R",
631         "SPDIF.L", "SPDIF.R",
632         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
633         "ADAT.7", "ADAT.8"
634 };
635
636 static char *texts_ports_aio_out_ss[] = {
637         "Analogue.L", "Analogue.R",
638         "AES.L", "AES.R",
639         "SPDIF.L", "SPDIF.R",
640         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
641         "ADAT.7", "ADAT.8",
642         "Phone.L", "Phone.R"
643 };
644
645 static char *texts_ports_aio_in_ds[] = {
646         "Analogue.L", "Analogue.R",
647         "AES.L", "AES.R",
648         "SPDIF.L", "SPDIF.R",
649         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
650 };
651
652 static char *texts_ports_aio_out_ds[] = {
653         "Analogue.L", "Analogue.R",
654         "AES.L", "AES.R",
655         "SPDIF.L", "SPDIF.R",
656         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
657         "Phone.L", "Phone.R"
658 };
659
660 static char *texts_ports_aio_in_qs[] = {
661         "Analogue.L", "Analogue.R",
662         "AES.L", "AES.R",
663         "SPDIF.L", "SPDIF.R",
664         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
665 };
666
667 static char *texts_ports_aio_out_qs[] = {
668         "Analogue.L", "Analogue.R",
669         "AES.L", "AES.R",
670         "SPDIF.L", "SPDIF.R",
671         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
672         "Phone.L", "Phone.R"
673 };
674
675 static char *texts_ports_aes32[] = {
676         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
677         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
678         "AES.15", "AES.16"
679 };
680
681 /* These tables map the ALSA channels 1..N to the channels that we
682    need to use in order to find the relevant channel buffer. RME
683    refers to this kind of mapping as between "the ADAT channel and
684    the DMA channel." We index it using the logical audio channel,
685    and the value is the DMA channel (i.e. channel buffer number)
686    where the data for that channel can be read/written from/to.
687 */
688
689 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
690         0, 1, 2, 3, 4, 5, 6, 7,
691         8, 9, 10, 11, 12, 13, 14, 15,
692         16, 17, 18, 19, 20, 21, 22, 23,
693         24, 25, 26, 27, 28, 29, 30, 31,
694         32, 33, 34, 35, 36, 37, 38, 39,
695         40, 41, 42, 43, 44, 45, 46, 47,
696         48, 49, 50, 51, 52, 53, 54, 55,
697         56, 57, 58, 59, 60, 61, 62, 63
698 };
699
700 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
701         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
702         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
703         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
704         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
705         0, 1,                   /* AES */
706         2, 3,                   /* SPDIF */
707         -1, -1, -1, -1,
708         -1, -1, -1, -1, -1, -1, -1, -1,
709         -1, -1, -1, -1, -1, -1, -1, -1,
710         -1, -1, -1, -1, -1, -1, -1, -1,
711 };
712
713 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
714         4, 5, 6, 7,             /* ADAT 1 */
715         8, 9, 10, 11,           /* ADAT 2 */
716         12, 13, 14, 15,         /* ADAT 3 */
717         16, 17, 18, 19,         /* ADAT 4 */
718         0, 1,                   /* AES */
719         2, 3,                   /* SPDIF */
720         -1, -1, -1, -1,
721         -1, -1, -1, -1, -1, -1, -1, -1,
722         -1, -1, -1, -1, -1, -1, -1, -1,
723         -1, -1, -1, -1, -1, -1, -1, -1,
724         -1, -1, -1, -1, -1, -1, -1, -1,
725         -1, -1, -1, -1, -1, -1, -1, -1,
726 };
727
728 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
729         4, 5,                   /* ADAT 1 */
730         6, 7,                   /* ADAT 2 */
731         8, 9,                   /* ADAT 3 */
732         10, 11,                 /* ADAT 4 */
733         0, 1,                   /* AES */
734         2, 3,                   /* SPDIF */
735         -1, -1, -1, -1,
736         -1, -1, -1, -1, -1, -1, -1, -1,
737         -1, -1, -1, -1, -1, -1, -1, -1,
738         -1, -1, -1, -1, -1, -1, -1, -1,
739         -1, -1, -1, -1, -1, -1, -1, -1,
740         -1, -1, -1, -1, -1, -1, -1, -1,
741         -1, -1, -1, -1, -1, -1, -1, -1,
742 };
743
744 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
745         0, 1,                   /* line in */
746         8, 9,                   /* aes in, */
747         10, 11,                 /* spdif in */
748         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
749         -1, -1,
750         -1, -1, -1, -1, -1, -1, -1, -1,
751         -1, -1, -1, -1, -1, -1, -1, -1,
752         -1, -1, -1, -1, -1, -1, -1, -1,
753         -1, -1, -1, -1, -1, -1, -1, -1,
754         -1, -1, -1, -1, -1, -1, -1, -1,
755         -1, -1, -1, -1, -1, -1, -1, -1,
756 };
757
758 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
759         0, 1,                   /* line out */
760         8, 9,                   /* aes out */
761         10, 11,                 /* spdif out */
762         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
763         6, 7,                   /* phone out */
764         -1, -1, -1, -1, -1, -1, -1, -1,
765         -1, -1, -1, -1, -1, -1, -1, -1,
766         -1, -1, -1, -1, -1, -1, -1, -1,
767         -1, -1, -1, -1, -1, -1, -1, -1,
768         -1, -1, -1, -1, -1, -1, -1, -1,
769         -1, -1, -1, -1, -1, -1, -1, -1,
770 };
771
772 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
773         0, 1,                   /* line in */
774         8, 9,                   /* aes in */
775         10, 11,                 /* spdif in */
776         12, 14, 16, 18,         /* adat in */
777         -1, -1, -1, -1, -1, -1,
778         -1, -1, -1, -1, -1, -1, -1, -1,
779         -1, -1, -1, -1, -1, -1, -1, -1,
780         -1, -1, -1, -1, -1, -1, -1, -1,
781         -1, -1, -1, -1, -1, -1, -1, -1,
782         -1, -1, -1, -1, -1, -1, -1, -1,
783         -1, -1, -1, -1, -1, -1, -1, -1
784 };
785
786 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
787         0, 1,                   /* line out */
788         8, 9,                   /* aes out */
789         10, 11,                 /* spdif out */
790         12, 14, 16, 18,         /* adat out */
791         6, 7,                   /* phone out */
792         -1, -1, -1, -1,
793         -1, -1, -1, -1, -1, -1, -1, -1,
794         -1, -1, -1, -1, -1, -1, -1, -1,
795         -1, -1, -1, -1, -1, -1, -1, -1,
796         -1, -1, -1, -1, -1, -1, -1, -1,
797         -1, -1, -1, -1, -1, -1, -1, -1,
798         -1, -1, -1, -1, -1, -1, -1, -1
799 };
800
801 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
802         0, 1,                   /* line in */
803         8, 9,                   /* aes in */
804         10, 11,                 /* spdif in */
805         12, 16,                 /* adat in */
806         -1, -1, -1, -1, -1, -1, -1, -1,
807         -1, -1, -1, -1, -1, -1, -1, -1,
808         -1, -1, -1, -1, -1, -1, -1, -1,
809         -1, -1, -1, -1, -1, -1, -1, -1,
810         -1, -1, -1, -1, -1, -1, -1, -1,
811         -1, -1, -1, -1, -1, -1, -1, -1,
812         -1, -1, -1, -1, -1, -1, -1, -1
813 };
814
815 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
816         0, 1,                   /* line out */
817         8, 9,                   /* aes out */
818         10, 11,                 /* spdif out */
819         12, 16,                 /* adat out */
820         6, 7,                   /* phone out */
821         -1, -1, -1, -1, -1, -1,
822         -1, -1, -1, -1, -1, -1, -1, -1,
823         -1, -1, -1, -1, -1, -1, -1, -1,
824         -1, -1, -1, -1, -1, -1, -1, -1,
825         -1, -1, -1, -1, -1, -1, -1, -1,
826         -1, -1, -1, -1, -1, -1, -1, -1,
827         -1, -1, -1, -1, -1, -1, -1, -1
828 };
829
830 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
831         0, 1, 2, 3, 4, 5, 6, 7,
832         8, 9, 10, 11, 12, 13, 14, 15,
833         -1, -1, -1, -1, -1, -1, -1, -1,
834         -1, -1, -1, -1, -1, -1, -1, -1,
835         -1, -1, -1, -1, -1, -1, -1, -1,
836         -1, -1, -1, -1, -1, -1, -1, -1,
837         -1, -1, -1, -1, -1, -1, -1, -1,
838         -1, -1, -1, -1, -1, -1, -1, -1
839 };
840
841 struct hdspm_midi {
842         struct hdspm *hdspm;
843         int id;
844         struct snd_rawmidi *rmidi;
845         struct snd_rawmidi_substream *input;
846         struct snd_rawmidi_substream *output;
847         char istimer;           /* timer in use */
848         struct timer_list timer;
849         spinlock_t lock;
850         int pending;
851         int dataIn;
852         int statusIn;
853         int dataOut;
854         int statusOut;
855         int ie;
856         int irq;
857 };
858
859 struct hdspm_tco {
860         int input;
861         int framerate;
862         int wordclock;
863         int samplerate;
864         int pull;
865         int term; /* 0 = off, 1 = on */
866 };
867
868 struct hdspm {
869         spinlock_t lock;
870         /* only one playback and/or capture stream */
871         struct snd_pcm_substream *capture_substream;
872         struct snd_pcm_substream *playback_substream;
873
874         char *card_name;             /* for procinfo */
875         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
876
877         uint8_t io_type;
878
879         int monitor_outs;       /* set up monitoring outs init flag */
880
881         u32 control_register;   /* cached value */
882         u32 control2_register;  /* cached value */
883         u32 settings_register;
884
885         struct hdspm_midi midi[4];
886         struct tasklet_struct midi_tasklet;
887
888         size_t period_bytes;
889         unsigned char ss_in_channels;
890         unsigned char ds_in_channels;
891         unsigned char qs_in_channels;
892         unsigned char ss_out_channels;
893         unsigned char ds_out_channels;
894         unsigned char qs_out_channels;
895
896         unsigned char max_channels_in;
897         unsigned char max_channels_out;
898
899         signed char *channel_map_in;
900         signed char *channel_map_out;
901
902         signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
903         signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
904
905         char **port_names_in;
906         char **port_names_out;
907
908         char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
909         char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
910
911         unsigned char *playback_buffer; /* suitably aligned address */
912         unsigned char *capture_buffer;  /* suitably aligned address */
913
914         pid_t capture_pid;      /* process id which uses capture */
915         pid_t playback_pid;     /* process id which uses capture */
916         int running;            /* running status */
917
918         int last_external_sample_rate;  /* samplerate mystic ... */
919         int last_internal_sample_rate;
920         int system_sample_rate;
921
922         int dev;                /* Hardware vars... */
923         int irq;
924         unsigned long port;
925         void __iomem *iobase;
926
927         int irq_count;          /* for debug */
928         int midiPorts;
929
930         struct snd_card *card;  /* one card */
931         struct snd_pcm *pcm;            /* has one pcm */
932         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
933         struct pci_dev *pci;    /* and an pci info */
934
935         /* Mixer vars */
936         /* fast alsa mixer */
937         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
938         /* but input to much, so not used */
939         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
940         /* full mixer accessible over mixer ioctl or hwdep-device */
941         struct hdspm_mixer *mixer;
942
943         struct hdspm_tco *tco;  /* NULL if no TCO detected */
944
945         char **texts_autosync;
946         int texts_autosync_items;
947
948         cycles_t last_interrupt;
949
950         struct hdspm_peak_rms peak_rms;
951 };
952
953
954 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
955         {
956          .vendor = PCI_VENDOR_ID_XILINX,
957          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
958          .subvendor = PCI_ANY_ID,
959          .subdevice = PCI_ANY_ID,
960          .class = 0,
961          .class_mask = 0,
962          .driver_data = 0},
963         {0,}
964 };
965
966 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
967
968 /* prototypes */
969 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
970                                                    struct hdspm * hdspm);
971 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
972                                           struct hdspm * hdspm);
973
974 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
975 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
976 static int hdspm_autosync_ref(struct hdspm *hdspm);
977 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
978 static void hdspm_set_sgbuf(struct hdspm *hdspm,
979                             struct snd_pcm_substream *substream,
980                              unsigned int reg, int channels);
981
982 static inline int HDSPM_bit2freq(int n)
983 {
984         static const int bit2freq_tab[] = {
985                 0, 32000, 44100, 48000, 64000, 88200,
986                 96000, 128000, 176400, 192000 };
987         if (n < 1 || n > 9)
988                 return 0;
989         return bit2freq_tab[n];
990 }
991
992 /* Write/read to/from HDSPM with Adresses in Bytes
993    not words but only 32Bit writes are allowed */
994
995 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
996                                unsigned int val)
997 {
998         writel(val, hdspm->iobase + reg);
999 }
1000
1001 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1002 {
1003         return readl(hdspm->iobase + reg);
1004 }
1005
1006 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1007    mixer is write only on hardware so we have to cache him for read
1008    each fader is a u32, but uses only the first 16 bit */
1009
1010 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1011                                      unsigned int in)
1012 {
1013         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1014                 return 0;
1015
1016         return hdspm->mixer->ch[chan].in[in];
1017 }
1018
1019 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1020                                      unsigned int pb)
1021 {
1022         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1023                 return 0;
1024         return hdspm->mixer->ch[chan].pb[pb];
1025 }
1026
1027 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1028                                       unsigned int in, unsigned short data)
1029 {
1030         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1031                 return -1;
1032
1033         hdspm_write(hdspm,
1034                     HDSPM_MADI_mixerBase +
1035                     ((in + 128 * chan) * sizeof(u32)),
1036                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1037         return 0;
1038 }
1039
1040 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1041                                       unsigned int pb, unsigned short data)
1042 {
1043         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1044                 return -1;
1045
1046         hdspm_write(hdspm,
1047                     HDSPM_MADI_mixerBase +
1048                     ((64 + pb + 128 * chan) * sizeof(u32)),
1049                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1050         return 0;
1051 }
1052
1053
1054 /* enable DMA for specific channels, now available for DSP-MADI */
1055 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1056 {
1057         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1058 }
1059
1060 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1061 {
1062         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1063 }
1064
1065 /* check if same process is writing and reading */
1066 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1067 {
1068         unsigned long flags;
1069         int ret = 1;
1070
1071         spin_lock_irqsave(&hdspm->lock, flags);
1072         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1073             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1074                 ret = 0;
1075         }
1076         spin_unlock_irqrestore(&hdspm->lock, flags);
1077         return ret;
1078 }
1079
1080 /* check for external sample rate */
1081 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1082 {
1083         unsigned int status, status2, timecode;
1084         int syncref, rate = 0, rate_bits;
1085
1086         switch (hdspm->io_type) {
1087         case AES32:
1088                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1089                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1090                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1091
1092                 syncref = hdspm_autosync_ref(hdspm);
1093
1094                 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1095                                 status & HDSPM_AES32_wcLock)
1096                         return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1097
1098                 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1099                                 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1100                                 status2 & (HDSPM_LockAES >>
1101                                 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1102                         return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1103                 return 0;
1104                 break;
1105
1106         case MADIface:
1107                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1108
1109                 if (!(status & HDSPM_madiLock)) {
1110                         rate = 0;  /* no lock */
1111                 } else {
1112                         switch (status & (HDSPM_status1_freqMask)) {
1113                         case HDSPM_status1_F_0*1:
1114                                 rate = 32000; break;
1115                         case HDSPM_status1_F_0*2:
1116                                 rate = 44100; break;
1117                         case HDSPM_status1_F_0*3:
1118                                 rate = 48000; break;
1119                         case HDSPM_status1_F_0*4:
1120                                 rate = 64000; break;
1121                         case HDSPM_status1_F_0*5:
1122                                 rate = 88200; break;
1123                         case HDSPM_status1_F_0*6:
1124                                 rate = 96000; break;
1125                         case HDSPM_status1_F_0*7:
1126                                 rate = 128000; break;
1127                         case HDSPM_status1_F_0*8:
1128                                 rate = 176400; break;
1129                         case HDSPM_status1_F_0*9:
1130                                 rate = 192000; break;
1131                         default:
1132                                 rate = 0; break;
1133                         }
1134                 }
1135
1136                 break;
1137
1138         case MADI:
1139         case AIO:
1140         case RayDAT:
1141                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1142                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1143                 rate = 0;
1144
1145                 /* if wordclock has synced freq and wordclock is valid */
1146                 if ((status2 & HDSPM_wcLock) != 0 &&
1147                                 (status2 & HDSPM_SelSyncRef0) == 0) {
1148
1149                         rate_bits = status2 & HDSPM_wcFreqMask;
1150
1151
1152                         switch (rate_bits) {
1153                         case HDSPM_wcFreq32:
1154                                 rate = 32000;
1155                                 break;
1156                         case HDSPM_wcFreq44_1:
1157                                 rate = 44100;
1158                                 break;
1159                         case HDSPM_wcFreq48:
1160                                 rate = 48000;
1161                                 break;
1162                         case HDSPM_wcFreq64:
1163                                 rate = 64000;
1164                                 break;
1165                         case HDSPM_wcFreq88_2:
1166                                 rate = 88200;
1167                                 break;
1168                         case HDSPM_wcFreq96:
1169                                 rate = 96000;
1170                                 break;
1171                         default:
1172                                 rate = 0;
1173                                 break;
1174                         }
1175                 }
1176
1177                 /* if rate detected and Syncref is Word than have it,
1178                  * word has priority to MADI
1179                  */
1180                 if (rate != 0 &&
1181                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1182                         return rate;
1183
1184                 /* maybe a madi input (which is taken if sel sync is madi) */
1185                 if (status & HDSPM_madiLock) {
1186                         rate_bits = status & HDSPM_madiFreqMask;
1187
1188                         switch (rate_bits) {
1189                         case HDSPM_madiFreq32:
1190                                 rate = 32000;
1191                                 break;
1192                         case HDSPM_madiFreq44_1:
1193                                 rate = 44100;
1194                                 break;
1195                         case HDSPM_madiFreq48:
1196                                 rate = 48000;
1197                                 break;
1198                         case HDSPM_madiFreq64:
1199                                 rate = 64000;
1200                                 break;
1201                         case HDSPM_madiFreq88_2:
1202                                 rate = 88200;
1203                                 break;
1204                         case HDSPM_madiFreq96:
1205                                 rate = 96000;
1206                                 break;
1207                         case HDSPM_madiFreq128:
1208                                 rate = 128000;
1209                                 break;
1210                         case HDSPM_madiFreq176_4:
1211                                 rate = 176400;
1212                                 break;
1213                         case HDSPM_madiFreq192:
1214                                 rate = 192000;
1215                                 break;
1216                         default:
1217                                 rate = 0;
1218                                 break;
1219                         }
1220                 }
1221                 break;
1222         }
1223
1224         return rate;
1225 }
1226
1227 /* Latency function */
1228 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1229 {
1230         hdspm->period_bytes = 1 << ((hdspm_decode_latency(hdspm->control_register) + 8));
1231 }
1232
1233
1234 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1235 {
1236         int position;
1237
1238         position = hdspm_read(hdspm, HDSPM_statusRegister);
1239
1240         switch (hdspm->io_type) {
1241         case RayDAT:
1242         case AIO:
1243                 position &= HDSPM_BufferPositionMask;
1244                 position /= 4; /* Bytes per sample */
1245                 break;
1246         default:
1247                 position = (position & HDSPM_BufferID) ?
1248                         (hdspm->period_bytes / 4) : 0;
1249         }
1250
1251         return position;
1252 }
1253
1254
1255 static inline void hdspm_start_audio(struct hdspm * s)
1256 {
1257         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1258         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1259 }
1260
1261 static inline void hdspm_stop_audio(struct hdspm * s)
1262 {
1263         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1264         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1265 }
1266
1267 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1268 static void hdspm_silence_playback(struct hdspm *hdspm)
1269 {
1270         int i;
1271         int n = hdspm->period_bytes;
1272         void *buf = hdspm->playback_buffer;
1273
1274         if (buf == NULL)
1275                 return;
1276
1277         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1278                 memset(buf, 0, n);
1279                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1280         }
1281 }
1282
1283 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1284 {
1285         int n;
1286
1287         spin_lock_irq(&s->lock);
1288
1289         frames >>= 7;
1290         n = 0;
1291         while (frames) {
1292                 n++;
1293                 frames >>= 1;
1294         }
1295         s->control_register &= ~HDSPM_LatencyMask;
1296         s->control_register |= hdspm_encode_latency(n);
1297
1298         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1299
1300         hdspm_compute_period_size(s);
1301
1302         spin_unlock_irq(&s->lock);
1303
1304         return 0;
1305 }
1306
1307 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1308 {
1309         u64 freq_const;
1310
1311         if (period == 0)
1312                 return 0;
1313
1314         switch (hdspm->io_type) {
1315         case MADI:
1316         case AES32:
1317                 freq_const = 110069313433624ULL;
1318                 break;
1319         case RayDAT:
1320         case AIO:
1321                 freq_const = 104857600000000ULL;
1322                 break;
1323         case MADIface:
1324                 freq_const = 131072000000000ULL;
1325         }
1326
1327         return div_u64(freq_const, period);
1328 }
1329
1330
1331 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1332 {
1333         u64 n;
1334
1335         if (rate >= 112000)
1336                 rate /= 4;
1337         else if (rate >= 56000)
1338                 rate /= 2;
1339
1340         switch (hdspm->io_type) {
1341         case MADIface:
1342           n = 131072000000000ULL;  /* 125 MHz */
1343           break;
1344         case MADI:
1345         case AES32:
1346           n = 110069313433624ULL;  /* 105 MHz */
1347           break;
1348         case RayDAT:
1349         case AIO:
1350           n = 104857600000000ULL;  /* 100 MHz */
1351           break;
1352         }
1353
1354         n = div_u64(n, rate);
1355         /* n should be less than 2^32 for being written to FREQ register */
1356         snd_BUG_ON(n >> 32);
1357         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1358 }
1359
1360 /* dummy set rate lets see what happens */
1361 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1362 {
1363         int current_rate;
1364         int rate_bits;
1365         int not_set = 0;
1366         int current_speed, target_speed;
1367
1368         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1369            it (e.g. during module initialization).
1370          */
1371
1372         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1373
1374                 /* SLAVE --- */
1375                 if (called_internally) {
1376
1377                         /* request from ctl or card initialization
1378                            just make a warning an remember setting
1379                            for future master mode switching */
1380
1381                         snd_printk(KERN_WARNING "HDSPM: "
1382                                    "Warning: device is not running "
1383                                    "as a clock master.\n");
1384                         not_set = 1;
1385                 } else {
1386
1387                         /* hw_param request while in AutoSync mode */
1388                         int external_freq =
1389                             hdspm_external_sample_rate(hdspm);
1390
1391                         if (hdspm_autosync_ref(hdspm) ==
1392                             HDSPM_AUTOSYNC_FROM_NONE) {
1393
1394                                 snd_printk(KERN_WARNING "HDSPM: "
1395                                            "Detected no Externel Sync \n");
1396                                 not_set = 1;
1397
1398                         } else if (rate != external_freq) {
1399
1400                                 snd_printk(KERN_WARNING "HDSPM: "
1401                                            "Warning: No AutoSync source for "
1402                                            "requested rate\n");
1403                                 not_set = 1;
1404                         }
1405                 }
1406         }
1407
1408         current_rate = hdspm->system_sample_rate;
1409
1410         /* Changing between Singe, Double and Quad speed is not
1411            allowed if any substreams are open. This is because such a change
1412            causes a shift in the location of the DMA buffers and a reduction
1413            in the number of available buffers.
1414
1415            Note that a similar but essentially insoluble problem exists for
1416            externally-driven rate changes. All we can do is to flag rate
1417            changes in the read/write routines.
1418          */
1419
1420         if (current_rate <= 48000)
1421                 current_speed = HDSPM_SPEED_SINGLE;
1422         else if (current_rate <= 96000)
1423                 current_speed = HDSPM_SPEED_DOUBLE;
1424         else
1425                 current_speed = HDSPM_SPEED_QUAD;
1426
1427         if (rate <= 48000)
1428                 target_speed = HDSPM_SPEED_SINGLE;
1429         else if (rate <= 96000)
1430                 target_speed = HDSPM_SPEED_DOUBLE;
1431         else
1432                 target_speed = HDSPM_SPEED_QUAD;
1433
1434         switch (rate) {
1435         case 32000:
1436                 rate_bits = HDSPM_Frequency32KHz;
1437                 break;
1438         case 44100:
1439                 rate_bits = HDSPM_Frequency44_1KHz;
1440                 break;
1441         case 48000:
1442                 rate_bits = HDSPM_Frequency48KHz;
1443                 break;
1444         case 64000:
1445                 rate_bits = HDSPM_Frequency64KHz;
1446                 break;
1447         case 88200:
1448                 rate_bits = HDSPM_Frequency88_2KHz;
1449                 break;
1450         case 96000:
1451                 rate_bits = HDSPM_Frequency96KHz;
1452                 break;
1453         case 128000:
1454                 rate_bits = HDSPM_Frequency128KHz;
1455                 break;
1456         case 176400:
1457                 rate_bits = HDSPM_Frequency176_4KHz;
1458                 break;
1459         case 192000:
1460                 rate_bits = HDSPM_Frequency192KHz;
1461                 break;
1462         default:
1463                 return -EINVAL;
1464         }
1465
1466         if (current_speed != target_speed
1467             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1468                 snd_printk
1469                     (KERN_ERR "HDSPM: "
1470                      "cannot change from %s speed to %s speed mode "
1471                      "(capture PID = %d, playback PID = %d)\n",
1472                      hdspm_speed_names[current_speed],
1473                      hdspm_speed_names[target_speed],
1474                      hdspm->capture_pid, hdspm->playback_pid);
1475                 return -EBUSY;
1476         }
1477
1478         hdspm->control_register &= ~HDSPM_FrequencyMask;
1479         hdspm->control_register |= rate_bits;
1480         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1481
1482         /* For AES32, need to set DDS value in FREQ register
1483            For MADI, also apparently */
1484         hdspm_set_dds_value(hdspm, rate);
1485
1486         if (AES32 == hdspm->io_type && rate != current_rate)
1487                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1488
1489         hdspm->system_sample_rate = rate;
1490
1491         if (rate <= 48000) {
1492                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1493                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1494                 hdspm->max_channels_in = hdspm->ss_in_channels;
1495                 hdspm->max_channels_out = hdspm->ss_out_channels;
1496                 hdspm->port_names_in = hdspm->port_names_in_ss;
1497                 hdspm->port_names_out = hdspm->port_names_out_ss;
1498         } else if (rate <= 96000) {
1499                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1500                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1501                 hdspm->max_channels_in = hdspm->ds_in_channels;
1502                 hdspm->max_channels_out = hdspm->ds_out_channels;
1503                 hdspm->port_names_in = hdspm->port_names_in_ds;
1504                 hdspm->port_names_out = hdspm->port_names_out_ds;
1505         } else {
1506                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1507                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1508                 hdspm->max_channels_in = hdspm->qs_in_channels;
1509                 hdspm->max_channels_out = hdspm->qs_out_channels;
1510                 hdspm->port_names_in = hdspm->port_names_in_qs;
1511                 hdspm->port_names_out = hdspm->port_names_out_qs;
1512         }
1513
1514         if (not_set != 0)
1515                 return -1;
1516
1517         return 0;
1518 }
1519
1520 /* mainly for init to 0 on load */
1521 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1522 {
1523         int i, j;
1524         unsigned int gain;
1525
1526         if (sgain > UNITY_GAIN)
1527                 gain = UNITY_GAIN;
1528         else if (sgain < 0)
1529                 gain = 0;
1530         else
1531                 gain = sgain;
1532
1533         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1534                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1535                         hdspm_write_in_gain(hdspm, i, j, gain);
1536                         hdspm_write_pb_gain(hdspm, i, j, gain);
1537                 }
1538 }
1539
1540 /*----------------------------------------------------------------------------
1541    MIDI
1542   ----------------------------------------------------------------------------*/
1543
1544 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1545                                                       int id)
1546 {
1547         /* the hardware already does the relevant bit-mask with 0xff */
1548         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1549 }
1550
1551 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1552                                               int val)
1553 {
1554         /* the hardware already does the relevant bit-mask with 0xff */
1555         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1556 }
1557
1558 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1559 {
1560         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1561 }
1562
1563 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1564 {
1565         int fifo_bytes_used;
1566
1567         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1568
1569         if (fifo_bytes_used < 128)
1570                 return  128 - fifo_bytes_used;
1571         else
1572                 return 0;
1573 }
1574
1575 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1576 {
1577         while (snd_hdspm_midi_input_available (hdspm, id))
1578                 snd_hdspm_midi_read_byte (hdspm, id);
1579 }
1580
1581 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1582 {
1583         unsigned long flags;
1584         int n_pending;
1585         int to_write;
1586         int i;
1587         unsigned char buf[128];
1588
1589         /* Output is not interrupt driven */
1590
1591         spin_lock_irqsave (&hmidi->lock, flags);
1592         if (hmidi->output &&
1593             !snd_rawmidi_transmit_empty (hmidi->output)) {
1594                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1595                                                             hmidi->id);
1596                 if (n_pending > 0) {
1597                         if (n_pending > (int)sizeof (buf))
1598                                 n_pending = sizeof (buf);
1599
1600                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1601                                                          n_pending);
1602                         if (to_write > 0) {
1603                                 for (i = 0; i < to_write; ++i)
1604                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1605                                                                    hmidi->id,
1606                                                                    buf[i]);
1607                         }
1608                 }
1609         }
1610         spin_unlock_irqrestore (&hmidi->lock, flags);
1611         return 0;
1612 }
1613
1614 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1615 {
1616         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1617                                  * input FIFO size
1618                                  */
1619         unsigned long flags;
1620         int n_pending;
1621         int i;
1622
1623         spin_lock_irqsave (&hmidi->lock, flags);
1624         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1625         if (n_pending > 0) {
1626                 if (hmidi->input) {
1627                         if (n_pending > (int)sizeof (buf))
1628                                 n_pending = sizeof (buf);
1629                         for (i = 0; i < n_pending; ++i)
1630                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1631                                                                    hmidi->id);
1632                         if (n_pending)
1633                                 snd_rawmidi_receive (hmidi->input, buf,
1634                                                      n_pending);
1635                 } else {
1636                         /* flush the MIDI input FIFO */
1637                         while (n_pending--)
1638                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1639                                                           hmidi->id);
1640                 }
1641         }
1642         hmidi->pending = 0;
1643         spin_unlock_irqrestore(&hmidi->lock, flags);
1644
1645         spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1646         hmidi->hdspm->control_register |= hmidi->ie;
1647         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1648                     hmidi->hdspm->control_register);
1649         spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1650
1651         return snd_hdspm_midi_output_write (hmidi);
1652 }
1653
1654 static void
1655 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1656 {
1657         struct hdspm *hdspm;
1658         struct hdspm_midi *hmidi;
1659         unsigned long flags;
1660
1661         hmidi = substream->rmidi->private_data;
1662         hdspm = hmidi->hdspm;
1663
1664         spin_lock_irqsave (&hdspm->lock, flags);
1665         if (up) {
1666                 if (!(hdspm->control_register & hmidi->ie)) {
1667                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1668                         hdspm->control_register |= hmidi->ie;
1669                 }
1670         } else {
1671                 hdspm->control_register &= ~hmidi->ie;
1672         }
1673
1674         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1675         spin_unlock_irqrestore (&hdspm->lock, flags);
1676 }
1677
1678 static void snd_hdspm_midi_output_timer(unsigned long data)
1679 {
1680         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1681         unsigned long flags;
1682
1683         snd_hdspm_midi_output_write(hmidi);
1684         spin_lock_irqsave (&hmidi->lock, flags);
1685
1686         /* this does not bump hmidi->istimer, because the
1687            kernel automatically removed the timer when it
1688            expired, and we are now adding it back, thus
1689            leaving istimer wherever it was set before.
1690         */
1691
1692         if (hmidi->istimer) {
1693                 hmidi->timer.expires = 1 + jiffies;
1694                 add_timer(&hmidi->timer);
1695         }
1696
1697         spin_unlock_irqrestore (&hmidi->lock, flags);
1698 }
1699
1700 static void
1701 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1702 {
1703         struct hdspm_midi *hmidi;
1704         unsigned long flags;
1705
1706         hmidi = substream->rmidi->private_data;
1707         spin_lock_irqsave (&hmidi->lock, flags);
1708         if (up) {
1709                 if (!hmidi->istimer) {
1710                         init_timer(&hmidi->timer);
1711                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1712                         hmidi->timer.data = (unsigned long) hmidi;
1713                         hmidi->timer.expires = 1 + jiffies;
1714                         add_timer(&hmidi->timer);
1715                         hmidi->istimer++;
1716                 }
1717         } else {
1718                 if (hmidi->istimer && --hmidi->istimer <= 0)
1719                         del_timer (&hmidi->timer);
1720         }
1721         spin_unlock_irqrestore (&hmidi->lock, flags);
1722         if (up)
1723                 snd_hdspm_midi_output_write(hmidi);
1724 }
1725
1726 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1727 {
1728         struct hdspm_midi *hmidi;
1729
1730         hmidi = substream->rmidi->private_data;
1731         spin_lock_irq (&hmidi->lock);
1732         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1733         hmidi->input = substream;
1734         spin_unlock_irq (&hmidi->lock);
1735
1736         return 0;
1737 }
1738
1739 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1740 {
1741         struct hdspm_midi *hmidi;
1742
1743         hmidi = substream->rmidi->private_data;
1744         spin_lock_irq (&hmidi->lock);
1745         hmidi->output = substream;
1746         spin_unlock_irq (&hmidi->lock);
1747
1748         return 0;
1749 }
1750
1751 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1752 {
1753         struct hdspm_midi *hmidi;
1754
1755         snd_hdspm_midi_input_trigger (substream, 0);
1756
1757         hmidi = substream->rmidi->private_data;
1758         spin_lock_irq (&hmidi->lock);
1759         hmidi->input = NULL;
1760         spin_unlock_irq (&hmidi->lock);
1761
1762         return 0;
1763 }
1764
1765 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1766 {
1767         struct hdspm_midi *hmidi;
1768
1769         snd_hdspm_midi_output_trigger (substream, 0);
1770
1771         hmidi = substream->rmidi->private_data;
1772         spin_lock_irq (&hmidi->lock);
1773         hmidi->output = NULL;
1774         spin_unlock_irq (&hmidi->lock);
1775
1776         return 0;
1777 }
1778
1779 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1780 {
1781         .open =         snd_hdspm_midi_output_open,
1782         .close =        snd_hdspm_midi_output_close,
1783         .trigger =      snd_hdspm_midi_output_trigger,
1784 };
1785
1786 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1787 {
1788         .open =         snd_hdspm_midi_input_open,
1789         .close =        snd_hdspm_midi_input_close,
1790         .trigger =      snd_hdspm_midi_input_trigger,
1791 };
1792
1793 static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1794                                             struct hdspm *hdspm, int id)
1795 {
1796         int err;
1797         char buf[32];
1798
1799         hdspm->midi[id].id = id;
1800         hdspm->midi[id].hdspm = hdspm;
1801         spin_lock_init (&hdspm->midi[id].lock);
1802
1803         if (0 == id) {
1804                 if (MADIface == hdspm->io_type) {
1805                         /* MIDI-over-MADI on HDSPe MADIface */
1806                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1807                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1808                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1809                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1810                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1811                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1812                 } else {
1813                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1814                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1815                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1816                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1817                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1818                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1819                 }
1820         } else if (1 == id) {
1821                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1822                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1823                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1824                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1825                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1826                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1827         } else if ((2 == id) && (MADI == hdspm->io_type)) {
1828                 /* MIDI-over-MADI on HDSPe MADI */
1829                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1830                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1831                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1832                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1833                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1834                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1835         } else if (2 == id) {
1836                 /* TCO MTC, read only */
1837                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1838                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1839                 hdspm->midi[2].dataOut = -1;
1840                 hdspm->midi[2].statusOut = -1;
1841                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1842                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1843         } else if (3 == id) {
1844                 /* TCO MTC on HDSPe MADI */
1845                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1846                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1847                 hdspm->midi[3].dataOut = -1;
1848                 hdspm->midi[3].statusOut = -1;
1849                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1850                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1851         }
1852
1853         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1854                                         (MADIface == hdspm->io_type)))) {
1855                 if ((id == 0) && (MADIface == hdspm->io_type)) {
1856                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1857                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1858                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1859                 } else {
1860                         sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1861                 }
1862                 err = snd_rawmidi_new(card, buf, id, 1, 1,
1863                                 &hdspm->midi[id].rmidi);
1864                 if (err < 0)
1865                         return err;
1866
1867                 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1868                                 card->id, id+1);
1869                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1870
1871                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1872                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
1873                                 &snd_hdspm_midi_output);
1874                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1875                                 SNDRV_RAWMIDI_STREAM_INPUT,
1876                                 &snd_hdspm_midi_input);
1877
1878                 hdspm->midi[id].rmidi->info_flags |=
1879                         SNDRV_RAWMIDI_INFO_OUTPUT |
1880                         SNDRV_RAWMIDI_INFO_INPUT |
1881                         SNDRV_RAWMIDI_INFO_DUPLEX;
1882         } else {
1883                 /* TCO MTC, read only */
1884                 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1885                 err = snd_rawmidi_new(card, buf, id, 1, 1,
1886                                 &hdspm->midi[id].rmidi);
1887                 if (err < 0)
1888                         return err;
1889
1890                 sprintf(hdspm->midi[id].rmidi->name,
1891                                 "%s MTC %d", card->id, id+1);
1892                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1893
1894                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1895                                 SNDRV_RAWMIDI_STREAM_INPUT,
1896                                 &snd_hdspm_midi_input);
1897
1898                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1899         }
1900
1901         return 0;
1902 }
1903
1904
1905 static void hdspm_midi_tasklet(unsigned long arg)
1906 {
1907         struct hdspm *hdspm = (struct hdspm *)arg;
1908         int i = 0;
1909
1910         while (i < hdspm->midiPorts) {
1911                 if (hdspm->midi[i].pending)
1912                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
1913
1914                 i++;
1915         }
1916 }
1917
1918
1919 /*-----------------------------------------------------------------------------
1920   Status Interface
1921   ----------------------------------------------------------------------------*/
1922
1923 /* get the system sample rate which is set */
1924
1925
1926 /**
1927  * Calculate the real sample rate from the
1928  * current DDS value.
1929  **/
1930 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
1931 {
1932         unsigned int period, rate;
1933
1934         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
1935         rate = hdspm_calc_dds_value(hdspm, period);
1936
1937         return rate;
1938 }
1939
1940
1941 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
1942 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1943   .name = xname, \
1944   .index = xindex, \
1945   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1946   .info = snd_hdspm_info_system_sample_rate, \
1947   .get = snd_hdspm_get_system_sample_rate \
1948 }
1949
1950 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
1951                                              struct snd_ctl_elem_info *uinfo)
1952 {
1953         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1954         uinfo->count = 1;
1955         uinfo->value.integer.min = 27000;
1956         uinfo->value.integer.max = 207000;
1957         uinfo->value.integer.step = 1;
1958         return 0;
1959 }
1960
1961
1962 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
1963                                             struct snd_ctl_elem_value *
1964                                             ucontrol)
1965 {
1966         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1967
1968         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
1969         return 0;
1970 }
1971
1972
1973 /**
1974  * Returns the WordClock sample rate class for the given card.
1975  **/
1976 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
1977 {
1978         int status;
1979
1980         switch (hdspm->io_type) {
1981         case RayDAT:
1982         case AIO:
1983                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
1984                 return (status >> 16) & 0xF;
1985                 break;
1986         default:
1987                 break;
1988         }
1989
1990
1991         return 0;
1992 }
1993
1994
1995 /**
1996  * Returns the TCO sample rate class for the given card.
1997  **/
1998 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
1999 {
2000         int status;
2001
2002         if (hdspm->tco) {
2003                 switch (hdspm->io_type) {
2004                 case RayDAT:
2005                 case AIO:
2006                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2007                         return (status >> 20) & 0xF;
2008                         break;
2009                 default:
2010                         break;
2011                 }
2012         }
2013
2014         return 0;
2015 }
2016
2017
2018 /**
2019  * Returns the SYNC_IN sample rate class for the given card.
2020  **/
2021 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2022 {
2023         int status;
2024
2025         if (hdspm->tco) {
2026                 switch (hdspm->io_type) {
2027                 case RayDAT:
2028                 case AIO:
2029                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2030                         return (status >> 12) & 0xF;
2031                         break;
2032                 default:
2033                         break;
2034                 }
2035         }
2036
2037         return 0;
2038 }
2039
2040
2041 /**
2042  * Returns the sample rate class for input source <idx> for
2043  * 'new style' cards like the AIO and RayDAT.
2044  **/
2045 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2046 {
2047         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2048
2049         return (status >> (idx*4)) & 0xF;
2050 }
2051
2052
2053
2054 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2055 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2056         .name = xname, \
2057         .private_value = xindex, \
2058         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2059         .info = snd_hdspm_info_autosync_sample_rate, \
2060         .get = snd_hdspm_get_autosync_sample_rate \
2061 }
2062
2063
2064 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2065                                                struct snd_ctl_elem_info *uinfo)
2066 {
2067         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2068         uinfo->count = 1;
2069         uinfo->value.enumerated.items = 10;
2070
2071         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2072                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2073         strcpy(uinfo->value.enumerated.name,
2074                         texts_freq[uinfo->value.enumerated.item]);
2075         return 0;
2076 }
2077
2078
2079 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2080                                               struct snd_ctl_elem_value *
2081                                               ucontrol)
2082 {
2083         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2084
2085         switch (hdspm->io_type) {
2086         case RayDAT:
2087                 switch (kcontrol->private_value) {
2088                 case 0:
2089                         ucontrol->value.enumerated.item[0] =
2090                                 hdspm_get_wc_sample_rate(hdspm);
2091                         break;
2092                 case 7:
2093                         ucontrol->value.enumerated.item[0] =
2094                                 hdspm_get_tco_sample_rate(hdspm);
2095                         break;
2096                 case 8:
2097                         ucontrol->value.enumerated.item[0] =
2098                                 hdspm_get_sync_in_sample_rate(hdspm);
2099                         break;
2100                 default:
2101                         ucontrol->value.enumerated.item[0] =
2102                                 hdspm_get_s1_sample_rate(hdspm,
2103                                                 kcontrol->private_value-1);
2104                 }
2105
2106         case AIO:
2107                 switch (kcontrol->private_value) {
2108                 case 0: /* WC */
2109                         ucontrol->value.enumerated.item[0] =
2110                                 hdspm_get_wc_sample_rate(hdspm);
2111                         break;
2112                 case 4: /* TCO */
2113                         ucontrol->value.enumerated.item[0] =
2114                                 hdspm_get_tco_sample_rate(hdspm);
2115                         break;
2116                 case 5: /* SYNC_IN */
2117                         ucontrol->value.enumerated.item[0] =
2118                                 hdspm_get_sync_in_sample_rate(hdspm);
2119                         break;
2120                 default:
2121                         ucontrol->value.enumerated.item[0] =
2122                                 hdspm_get_s1_sample_rate(hdspm,
2123                                                 ucontrol->id.index-1);
2124                 }
2125
2126         case AES32:
2127
2128                 switch (kcontrol->private_value) {
2129                 case 0: /* WC */
2130                         ucontrol->value.enumerated.item[0] =
2131                                 hdspm_get_wc_sample_rate(hdspm);
2132                         break;
2133                 case 9: /* TCO */
2134                         ucontrol->value.enumerated.item[0] =
2135                                 hdspm_get_tco_sample_rate(hdspm);
2136                         break;
2137                 case 10: /* SYNC_IN */
2138                         ucontrol->value.enumerated.item[0] =
2139                                 hdspm_get_sync_in_sample_rate(hdspm);
2140                         break;
2141                 default: /* AES1 to AES8 */
2142                         ucontrol->value.enumerated.item[0] =
2143                                 hdspm_get_s1_sample_rate(hdspm,
2144                                                 kcontrol->private_value-1);
2145                         break;
2146
2147                 }
2148         default:
2149                 break;
2150         }
2151
2152         return 0;
2153 }
2154
2155
2156 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2157 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2158         .name = xname, \
2159         .index = xindex, \
2160         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2161                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2162         .info = snd_hdspm_info_system_clock_mode, \
2163         .get = snd_hdspm_get_system_clock_mode, \
2164         .put = snd_hdspm_put_system_clock_mode, \
2165 }
2166
2167
2168 /**
2169  * Returns the system clock mode for the given card.
2170  * @returns 0 - master, 1 - slave
2171  **/
2172 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2173 {
2174         switch (hdspm->io_type) {
2175         case AIO:
2176         case RayDAT:
2177                 if (hdspm->settings_register & HDSPM_c0Master)
2178                         return 0;
2179                 break;
2180
2181         default:
2182                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2183                         return 0;
2184         }
2185
2186         return 1;
2187 }
2188
2189
2190 /**
2191  * Sets the system clock mode.
2192  * @param mode 0 - master, 1 - slave
2193  **/
2194 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2195 {
2196         switch (hdspm->io_type) {
2197         case AIO:
2198         case RayDAT:
2199                 if (0 == mode)
2200                         hdspm->settings_register |= HDSPM_c0Master;
2201                 else
2202                         hdspm->settings_register &= ~HDSPM_c0Master;
2203
2204                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2205                 break;
2206
2207         default:
2208                 if (0 == mode)
2209                         hdspm->control_register |= HDSPM_ClockModeMaster;
2210                 else
2211                         hdspm->control_register &= ~HDSPM_ClockModeMaster;
2212
2213                 hdspm_write(hdspm, HDSPM_controlRegister,
2214                                 hdspm->control_register);
2215         }
2216 }
2217
2218
2219 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2220                                             struct snd_ctl_elem_info *uinfo)
2221 {
2222         static char *texts[] = { "Master", "AutoSync" };
2223
2224         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2225         uinfo->count = 1;
2226         uinfo->value.enumerated.items = 2;
2227         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2228                 uinfo->value.enumerated.item =
2229                     uinfo->value.enumerated.items - 1;
2230         strcpy(uinfo->value.enumerated.name,
2231                texts[uinfo->value.enumerated.item]);
2232         return 0;
2233 }
2234
2235 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2236                                            struct snd_ctl_elem_value *ucontrol)
2237 {
2238         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2239
2240         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2241         return 0;
2242 }
2243
2244 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2245                                            struct snd_ctl_elem_value *ucontrol)
2246 {
2247         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2248         int val;
2249
2250         if (!snd_hdspm_use_is_exclusive(hdspm))
2251                 return -EBUSY;
2252
2253         val = ucontrol->value.enumerated.item[0];
2254         if (val < 0)
2255                 val = 0;
2256         else if (val > 1)
2257                 val = 1;
2258
2259         hdspm_set_system_clock_mode(hdspm, val);
2260
2261         return 0;
2262 }
2263
2264
2265 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2266 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2267         .name = xname, \
2268         .index = xindex, \
2269         .info = snd_hdspm_info_clock_source, \
2270         .get = snd_hdspm_get_clock_source, \
2271         .put = snd_hdspm_put_clock_source \
2272 }
2273
2274
2275 static int hdspm_clock_source(struct hdspm * hdspm)
2276 {
2277         switch (hdspm->system_sample_rate) {
2278         case 32000: return 0;
2279         case 44100: return 1;
2280         case 48000: return 2;
2281         case 64000: return 3;
2282         case 88200: return 4;
2283         case 96000: return 5;
2284         case 128000: return 6;
2285         case 176400: return 7;
2286         case 192000: return 8;
2287         }
2288
2289         return -1;
2290 }
2291
2292 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2293 {
2294         int rate;
2295         switch (mode) {
2296         case 0:
2297                 rate = 32000; break;
2298         case 1:
2299                 rate = 44100; break;
2300         case 2:
2301                 rate = 48000; break;
2302         case 3:
2303                 rate = 64000; break;
2304         case 4:
2305                 rate = 88200; break;
2306         case 5:
2307                 rate = 96000; break;
2308         case 6:
2309                 rate = 128000; break;
2310         case 7:
2311                 rate = 176400; break;
2312         case 8:
2313                 rate = 192000; break;
2314         default:
2315                 rate = 48000;
2316         }
2317         hdspm_set_rate(hdspm, rate, 1);
2318         return 0;
2319 }
2320
2321 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2322                                        struct snd_ctl_elem_info *uinfo)
2323 {
2324         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2325         uinfo->count = 1;
2326         uinfo->value.enumerated.items = 9;
2327
2328         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2329                 uinfo->value.enumerated.item =
2330                     uinfo->value.enumerated.items - 1;
2331
2332         strcpy(uinfo->value.enumerated.name,
2333                texts_freq[uinfo->value.enumerated.item+1]);
2334
2335         return 0;
2336 }
2337
2338 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2339                                       struct snd_ctl_elem_value *ucontrol)
2340 {
2341         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2342
2343         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2344         return 0;
2345 }
2346
2347 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2348                                       struct snd_ctl_elem_value *ucontrol)
2349 {
2350         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2351         int change;
2352         int val;
2353
2354         if (!snd_hdspm_use_is_exclusive(hdspm))
2355                 return -EBUSY;
2356         val = ucontrol->value.enumerated.item[0];
2357         if (val < 0)
2358                 val = 0;
2359         if (val > 9)
2360                 val = 9;
2361         spin_lock_irq(&hdspm->lock);
2362         if (val != hdspm_clock_source(hdspm))
2363                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2364         else
2365                 change = 0;
2366         spin_unlock_irq(&hdspm->lock);
2367         return change;
2368 }
2369
2370
2371 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2372 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2373         .name = xname, \
2374         .index = xindex, \
2375         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2376                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2377         .info = snd_hdspm_info_pref_sync_ref, \
2378         .get = snd_hdspm_get_pref_sync_ref, \
2379         .put = snd_hdspm_put_pref_sync_ref \
2380 }
2381
2382
2383 /**
2384  * Returns the current preferred sync reference setting.
2385  * The semantics of the return value are depending on the
2386  * card, please see the comments for clarification.
2387  **/
2388 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2389 {
2390         switch (hdspm->io_type) {
2391         case AES32:
2392                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2393                 case 0: return 0;  /* WC */
2394                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2395                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2396                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2397                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2398                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2399                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2400                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2401                                                     return 7; /* AES 7 */
2402                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2403                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2404                 }
2405                 break;
2406
2407         case MADI:
2408         case MADIface:
2409                 if (hdspm->tco) {
2410                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2411                         case 0: return 0;  /* WC */
2412                         case HDSPM_SyncRef0: return 1;  /* MADI */
2413                         case HDSPM_SyncRef1: return 2;  /* TCO */
2414                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2415                                              return 3;  /* SYNC_IN */
2416                         }
2417                 } else {
2418                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2419                         case 0: return 0;  /* WC */
2420                         case HDSPM_SyncRef0: return 1;  /* MADI */
2421                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2422                                              return 2;  /* SYNC_IN */
2423                         }
2424                 }
2425                 break;
2426
2427         case RayDAT:
2428                 if (hdspm->tco) {
2429                         switch ((hdspm->settings_register &
2430                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2431                         case 0: return 0;  /* WC */
2432                         case 3: return 1;  /* ADAT 1 */
2433                         case 4: return 2;  /* ADAT 2 */
2434                         case 5: return 3;  /* ADAT 3 */
2435                         case 6: return 4;  /* ADAT 4 */
2436                         case 1: return 5;  /* AES */
2437                         case 2: return 6;  /* SPDIF */
2438                         case 9: return 7;  /* TCO */
2439                         case 10: return 8; /* SYNC_IN */
2440                         }
2441                 } else {
2442                         switch ((hdspm->settings_register &
2443                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2444                         case 0: return 0;  /* WC */
2445                         case 3: return 1;  /* ADAT 1 */
2446                         case 4: return 2;  /* ADAT 2 */
2447                         case 5: return 3;  /* ADAT 3 */
2448                         case 6: return 4;  /* ADAT 4 */
2449                         case 1: return 5;  /* AES */
2450                         case 2: return 6;  /* SPDIF */
2451                         case 10: return 7; /* SYNC_IN */
2452                         }
2453                 }
2454
2455                 break;
2456
2457         case AIO:
2458                 if (hdspm->tco) {
2459                         switch ((hdspm->settings_register &
2460                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2461                         case 0: return 0;  /* WC */
2462                         case 3: return 1;  /* ADAT */
2463                         case 1: return 2;  /* AES */
2464                         case 2: return 3;  /* SPDIF */
2465                         case 9: return 4;  /* TCO */
2466                         case 10: return 5; /* SYNC_IN */
2467                         }
2468                 } else {
2469                         switch ((hdspm->settings_register &
2470                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2471                         case 0: return 0;  /* WC */
2472                         case 3: return 1;  /* ADAT */
2473                         case 1: return 2;  /* AES */
2474                         case 2: return 3;  /* SPDIF */
2475                         case 10: return 4; /* SYNC_IN */
2476                         }
2477                 }
2478
2479                 break;
2480         }
2481
2482         return -1;
2483 }
2484
2485
2486 /**
2487  * Set the preferred sync reference to <pref>. The semantics
2488  * of <pref> are depending on the card type, see the comments
2489  * for clarification.
2490  **/
2491 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2492 {
2493         int p = 0;
2494
2495         switch (hdspm->io_type) {
2496         case AES32:
2497                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2498                 switch (pref) {
2499                 case 0: /* WC  */
2500                         break;
2501                 case 1: /* AES 1 */
2502                         hdspm->control_register |= HDSPM_SyncRef0;
2503                         break;
2504                 case 2: /* AES 2 */
2505                         hdspm->control_register |= HDSPM_SyncRef1;
2506                         break;
2507                 case 3: /* AES 3 */
2508                         hdspm->control_register |=
2509                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2510                         break;
2511                 case 4: /* AES 4 */
2512                         hdspm->control_register |= HDSPM_SyncRef2;
2513                         break;
2514                 case 5: /* AES 5 */
2515                         hdspm->control_register |=
2516                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2517                         break;
2518                 case 6: /* AES 6 */
2519                         hdspm->control_register |=
2520                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2521                         break;
2522                 case 7: /* AES 7 */
2523                         hdspm->control_register |=
2524                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2525                         break;
2526                 case 8: /* AES 8 */
2527                         hdspm->control_register |= HDSPM_SyncRef3;
2528                         break;
2529                 case 9: /* TCO */
2530                         hdspm->control_register |=
2531                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2532                         break;
2533                 default:
2534                         return -1;
2535                 }
2536
2537                 break;
2538
2539         case MADI:
2540         case MADIface:
2541                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2542                 if (hdspm->tco) {
2543                         switch (pref) {
2544                         case 0: /* WC */
2545                                 break;
2546                         case 1: /* MADI */
2547                                 hdspm->control_register |= HDSPM_SyncRef0;
2548                                 break;
2549                         case 2: /* TCO */
2550                                 hdspm->control_register |= HDSPM_SyncRef1;
2551                                 break;
2552                         case 3: /* SYNC_IN */
2553                                 hdspm->control_register |=
2554                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2555                                 break;
2556                         default:
2557                                 return -1;
2558                         }
2559                 } else {
2560                         switch (pref) {
2561                         case 0: /* WC */
2562                                 break;
2563                         case 1: /* MADI */
2564                                 hdspm->control_register |= HDSPM_SyncRef0;
2565                                 break;
2566                         case 2: /* SYNC_IN */
2567                                 hdspm->control_register |=
2568                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2569                                 break;
2570                         default:
2571                                 return -1;
2572                         }
2573                 }
2574
2575                 break;
2576
2577         case RayDAT:
2578                 if (hdspm->tco) {
2579                         switch (pref) {
2580                         case 0: p = 0; break;  /* WC */
2581                         case 1: p = 3; break;  /* ADAT 1 */
2582                         case 2: p = 4; break;  /* ADAT 2 */
2583                         case 3: p = 5; break;  /* ADAT 3 */
2584                         case 4: p = 6; break;  /* ADAT 4 */
2585                         case 5: p = 1; break;  /* AES */
2586                         case 6: p = 2; break;  /* SPDIF */
2587                         case 7: p = 9; break;  /* TCO */
2588                         case 8: p = 10; break; /* SYNC_IN */
2589                         default: return -1;
2590                         }
2591                 } else {
2592                         switch (pref) {
2593                         case 0: p = 0; break;  /* WC */
2594                         case 1: p = 3; break;  /* ADAT 1 */
2595                         case 2: p = 4; break;  /* ADAT 2 */
2596                         case 3: p = 5; break;  /* ADAT 3 */
2597                         case 4: p = 6; break;  /* ADAT 4 */
2598                         case 5: p = 1; break;  /* AES */
2599                         case 6: p = 2; break;  /* SPDIF */
2600                         case 7: p = 10; break; /* SYNC_IN */
2601                         default: return -1;
2602                         }
2603                 }
2604                 break;
2605
2606         case AIO:
2607                 if (hdspm->tco) {
2608                         switch (pref) {
2609                         case 0: p = 0; break;  /* WC */
2610                         case 1: p = 3; break;  /* ADAT */
2611                         case 2: p = 1; break;  /* AES */
2612                         case 3: p = 2; break;  /* SPDIF */
2613                         case 4: p = 9; break;  /* TCO */
2614                         case 5: p = 10; break; /* SYNC_IN */
2615                         default: return -1;
2616                         }
2617                 } else {
2618                         switch (pref) {
2619                         case 0: p = 0; break;  /* WC */
2620                         case 1: p = 3; break;  /* ADAT */
2621                         case 2: p = 1; break;  /* AES */
2622                         case 3: p = 2; break;  /* SPDIF */
2623                         case 4: p = 10; break; /* SYNC_IN */
2624                         default: return -1;
2625                         }
2626                 }
2627                 break;
2628         }
2629
2630         switch (hdspm->io_type) {
2631         case RayDAT:
2632         case AIO:
2633                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2634                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2635                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2636                 break;
2637
2638         case MADI:
2639         case MADIface:
2640         case AES32:
2641                 hdspm_write(hdspm, HDSPM_controlRegister,
2642                                 hdspm->control_register);
2643         }
2644
2645         return 0;
2646 }
2647
2648
2649 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2650                                         struct snd_ctl_elem_info *uinfo)
2651 {
2652         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2653
2654         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2655         uinfo->count = 1;
2656         uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2657
2658         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2659                 uinfo->value.enumerated.item =
2660                         uinfo->value.enumerated.items - 1;
2661
2662         strcpy(uinfo->value.enumerated.name,
2663                         hdspm->texts_autosync[uinfo->value.enumerated.item]);
2664
2665         return 0;
2666 }
2667
2668 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2669                                        struct snd_ctl_elem_value *ucontrol)
2670 {
2671         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2672         int psf = hdspm_pref_sync_ref(hdspm);
2673
2674         if (psf >= 0) {
2675                 ucontrol->value.enumerated.item[0] = psf;
2676                 return 0;
2677         }
2678
2679         return -1;
2680 }
2681
2682 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2683                                        struct snd_ctl_elem_value *ucontrol)
2684 {
2685         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2686         int val, change = 0;
2687
2688         if (!snd_hdspm_use_is_exclusive(hdspm))
2689                 return -EBUSY;
2690
2691         val = ucontrol->value.enumerated.item[0];
2692
2693         if (val < 0)
2694                 val = 0;
2695         else if (val >= hdspm->texts_autosync_items)
2696                 val = hdspm->texts_autosync_items-1;
2697
2698         spin_lock_irq(&hdspm->lock);
2699         if (val != hdspm_pref_sync_ref(hdspm))
2700                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2701
2702         spin_unlock_irq(&hdspm->lock);
2703         return change;
2704 }
2705
2706
2707 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2708 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2709   .name = xname, \
2710   .index = xindex, \
2711   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2712   .info = snd_hdspm_info_autosync_ref, \
2713   .get = snd_hdspm_get_autosync_ref, \
2714 }
2715
2716 static int hdspm_autosync_ref(struct hdspm *hdspm)
2717 {
2718         if (AES32 == hdspm->io_type) {
2719                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2720                 unsigned int syncref =
2721                         (status >> HDSPM_AES32_syncref_bit) & 0xF;
2722                 if (syncref == 0)
2723                         return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2724                 if (syncref <= 8)
2725                         return syncref;
2726                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2727         } else if (MADI == hdspm->io_type) {
2728                 /* This looks at the autosync selected sync reference */
2729                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2730
2731                 switch (status2 & HDSPM_SelSyncRefMask) {
2732                 case HDSPM_SelSyncRef_WORD:
2733                         return HDSPM_AUTOSYNC_FROM_WORD;
2734                 case HDSPM_SelSyncRef_MADI:
2735                         return HDSPM_AUTOSYNC_FROM_MADI;
2736                 case HDSPM_SelSyncRef_TCO:
2737                         return HDSPM_AUTOSYNC_FROM_TCO;
2738                 case HDSPM_SelSyncRef_SyncIn:
2739                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2740                 case HDSPM_SelSyncRef_NVALID:
2741                         return HDSPM_AUTOSYNC_FROM_NONE;
2742                 default:
2743                         return 0;
2744                 }
2745
2746         }
2747         return 0;
2748 }
2749
2750
2751 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2752                                        struct snd_ctl_elem_info *uinfo)
2753 {
2754         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2755
2756         if (AES32 == hdspm->io_type) {
2757                 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2758                         "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2759
2760                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2761                 uinfo->count = 1;
2762                 uinfo->value.enumerated.items = 10;
2763                 if (uinfo->value.enumerated.item >=
2764                     uinfo->value.enumerated.items)
2765                         uinfo->value.enumerated.item =
2766                                 uinfo->value.enumerated.items - 1;
2767                 strcpy(uinfo->value.enumerated.name,
2768                                 texts[uinfo->value.enumerated.item]);
2769         } else if (MADI == hdspm->io_type) {
2770                 static char *texts[] = {"Word Clock", "MADI", "TCO",
2771                         "Sync In", "None" };
2772
2773                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2774                 uinfo->count = 1;
2775                 uinfo->value.enumerated.items = 5;
2776                 if (uinfo->value.enumerated.item >=
2777                                 uinfo->value.enumerated.items)
2778                         uinfo->value.enumerated.item =
2779                                 uinfo->value.enumerated.items - 1;
2780                 strcpy(uinfo->value.enumerated.name,
2781                                 texts[uinfo->value.enumerated.item]);
2782         }
2783         return 0;
2784 }
2785
2786 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2787                                       struct snd_ctl_elem_value *ucontrol)
2788 {
2789         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2790
2791         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2792         return 0;
2793 }
2794
2795
2796 #define HDSPM_LINE_OUT(xname, xindex) \
2797 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2798   .name = xname, \
2799   .index = xindex, \
2800   .info = snd_hdspm_info_line_out, \
2801   .get = snd_hdspm_get_line_out, \
2802   .put = snd_hdspm_put_line_out \
2803 }
2804
2805 static int hdspm_line_out(struct hdspm * hdspm)
2806 {
2807         return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
2808 }
2809
2810
2811 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
2812 {
2813         if (out)
2814                 hdspm->control_register |= HDSPM_LineOut;
2815         else
2816                 hdspm->control_register &= ~HDSPM_LineOut;
2817         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2818
2819         return 0;
2820 }
2821
2822 #define snd_hdspm_info_line_out         snd_ctl_boolean_mono_info
2823
2824 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
2825                                   struct snd_ctl_elem_value *ucontrol)
2826 {
2827         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2828
2829         spin_lock_irq(&hdspm->lock);
2830         ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
2831         spin_unlock_irq(&hdspm->lock);
2832         return 0;
2833 }
2834
2835 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
2836                                   struct snd_ctl_elem_value *ucontrol)
2837 {
2838         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2839         int change;
2840         unsigned int val;
2841
2842         if (!snd_hdspm_use_is_exclusive(hdspm))
2843                 return -EBUSY;
2844         val = ucontrol->value.integer.value[0] & 1;
2845         spin_lock_irq(&hdspm->lock);
2846         change = (int) val != hdspm_line_out(hdspm);
2847         hdspm_set_line_output(hdspm, val);
2848         spin_unlock_irq(&hdspm->lock);
2849         return change;
2850 }
2851
2852
2853 #define HDSPM_TX_64(xname, xindex) \
2854 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2855   .name = xname, \
2856   .index = xindex, \
2857   .info = snd_hdspm_info_tx_64, \
2858   .get = snd_hdspm_get_tx_64, \
2859   .put = snd_hdspm_put_tx_64 \
2860 }
2861
2862 static int hdspm_tx_64(struct hdspm * hdspm)
2863 {
2864         return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
2865 }
2866
2867 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
2868 {
2869         if (out)
2870                 hdspm->control_register |= HDSPM_TX_64ch;
2871         else
2872                 hdspm->control_register &= ~HDSPM_TX_64ch;
2873         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2874
2875         return 0;
2876 }
2877
2878 #define snd_hdspm_info_tx_64            snd_ctl_boolean_mono_info
2879
2880 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
2881                                struct snd_ctl_elem_value *ucontrol)
2882 {
2883         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2884
2885         spin_lock_irq(&hdspm->lock);
2886         ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
2887         spin_unlock_irq(&hdspm->lock);
2888         return 0;
2889 }
2890
2891 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
2892                                struct snd_ctl_elem_value *ucontrol)
2893 {
2894         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2895         int change;
2896         unsigned int val;
2897
2898         if (!snd_hdspm_use_is_exclusive(hdspm))
2899                 return -EBUSY;
2900         val = ucontrol->value.integer.value[0] & 1;
2901         spin_lock_irq(&hdspm->lock);
2902         change = (int) val != hdspm_tx_64(hdspm);
2903         hdspm_set_tx_64(hdspm, val);
2904         spin_unlock_irq(&hdspm->lock);
2905         return change;
2906 }
2907
2908
2909 #define HDSPM_C_TMS(xname, xindex) \
2910 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2911   .name = xname, \
2912   .index = xindex, \
2913   .info = snd_hdspm_info_c_tms, \
2914   .get = snd_hdspm_get_c_tms, \
2915   .put = snd_hdspm_put_c_tms \
2916 }
2917
2918 static int hdspm_c_tms(struct hdspm * hdspm)
2919 {
2920         return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
2921 }
2922
2923 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
2924 {
2925         if (out)
2926                 hdspm->control_register |= HDSPM_clr_tms;
2927         else
2928                 hdspm->control_register &= ~HDSPM_clr_tms;
2929         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2930
2931         return 0;
2932 }
2933
2934 #define snd_hdspm_info_c_tms            snd_ctl_boolean_mono_info
2935
2936 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
2937                                struct snd_ctl_elem_value *ucontrol)
2938 {
2939         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2940
2941         spin_lock_irq(&hdspm->lock);
2942         ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
2943         spin_unlock_irq(&hdspm->lock);
2944         return 0;
2945 }
2946
2947 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
2948                                struct snd_ctl_elem_value *ucontrol)
2949 {
2950         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2951         int change;
2952         unsigned int val;
2953
2954         if (!snd_hdspm_use_is_exclusive(hdspm))
2955                 return -EBUSY;
2956         val = ucontrol->value.integer.value[0] & 1;
2957         spin_lock_irq(&hdspm->lock);
2958         change = (int) val != hdspm_c_tms(hdspm);
2959         hdspm_set_c_tms(hdspm, val);
2960         spin_unlock_irq(&hdspm->lock);
2961         return change;
2962 }
2963
2964
2965 #define HDSPM_SAFE_MODE(xname, xindex) \
2966 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2967   .name = xname, \
2968   .index = xindex, \
2969   .info = snd_hdspm_info_safe_mode, \
2970   .get = snd_hdspm_get_safe_mode, \
2971   .put = snd_hdspm_put_safe_mode \
2972 }
2973
2974 static int hdspm_safe_mode(struct hdspm * hdspm)
2975 {
2976         return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
2977 }
2978
2979 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
2980 {
2981         if (out)
2982                 hdspm->control_register |= HDSPM_AutoInp;
2983         else
2984                 hdspm->control_register &= ~HDSPM_AutoInp;
2985         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2986
2987         return 0;
2988 }
2989
2990 #define snd_hdspm_info_safe_mode        snd_ctl_boolean_mono_info
2991
2992 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
2993                                    struct snd_ctl_elem_value *ucontrol)
2994 {
2995         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2996
2997         spin_lock_irq(&hdspm->lock);
2998         ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
2999         spin_unlock_irq(&hdspm->lock);
3000         return 0;
3001 }
3002
3003 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
3004                                    struct snd_ctl_elem_value *ucontrol)
3005 {
3006         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3007         int change;
3008         unsigned int val;
3009
3010         if (!snd_hdspm_use_is_exclusive(hdspm))
3011                 return -EBUSY;
3012         val = ucontrol->value.integer.value[0] & 1;
3013         spin_lock_irq(&hdspm->lock);
3014         change = (int) val != hdspm_safe_mode(hdspm);
3015         hdspm_set_safe_mode(hdspm, val);
3016         spin_unlock_irq(&hdspm->lock);
3017         return change;
3018 }
3019
3020
3021 #define HDSPM_EMPHASIS(xname, xindex) \
3022 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3023   .name = xname, \
3024   .index = xindex, \
3025   .info = snd_hdspm_info_emphasis, \
3026   .get = snd_hdspm_get_emphasis, \
3027   .put = snd_hdspm_put_emphasis \
3028 }
3029
3030 static int hdspm_emphasis(struct hdspm * hdspm)
3031 {
3032         return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
3033 }
3034
3035 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
3036 {
3037         if (emp)
3038                 hdspm->control_register |= HDSPM_Emphasis;
3039         else
3040                 hdspm->control_register &= ~HDSPM_Emphasis;
3041         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3042
3043         return 0;
3044 }
3045
3046 #define snd_hdspm_info_emphasis         snd_ctl_boolean_mono_info
3047
3048 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
3049                                   struct snd_ctl_elem_value *ucontrol)
3050 {
3051         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3052
3053         spin_lock_irq(&hdspm->lock);
3054         ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
3055         spin_unlock_irq(&hdspm->lock);
3056         return 0;
3057 }
3058
3059 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
3060                                   struct snd_ctl_elem_value *ucontrol)
3061 {
3062         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3063         int change;
3064         unsigned int val;
3065
3066         if (!snd_hdspm_use_is_exclusive(hdspm))
3067                 return -EBUSY;
3068         val = ucontrol->value.integer.value[0] & 1;
3069         spin_lock_irq(&hdspm->lock);
3070         change = (int) val != hdspm_emphasis(hdspm);
3071         hdspm_set_emphasis(hdspm, val);
3072         spin_unlock_irq(&hdspm->lock);
3073         return change;
3074 }
3075
3076
3077 #define HDSPM_DOLBY(xname, xindex) \
3078 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3079   .name = xname, \
3080   .index = xindex, \
3081   .info = snd_hdspm_info_dolby, \
3082   .get = snd_hdspm_get_dolby, \
3083   .put = snd_hdspm_put_dolby \
3084 }
3085
3086 static int hdspm_dolby(struct hdspm * hdspm)
3087 {
3088         return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
3089 }
3090
3091 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
3092 {
3093         if (dol)
3094                 hdspm->control_register |= HDSPM_Dolby;
3095         else
3096                 hdspm->control_register &= ~HDSPM_Dolby;
3097         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3098
3099         return 0;
3100 }
3101
3102 #define snd_hdspm_info_dolby            snd_ctl_boolean_mono_info
3103
3104 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
3105                                struct snd_ctl_elem_value *ucontrol)
3106 {
3107         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3108
3109         spin_lock_irq(&hdspm->lock);
3110         ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
3111         spin_unlock_irq(&hdspm->lock);
3112         return 0;
3113 }
3114
3115 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
3116                                struct snd_ctl_elem_value *ucontrol)
3117 {
3118         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3119         int change;
3120         unsigned int val;
3121
3122         if (!snd_hdspm_use_is_exclusive(hdspm))
3123                 return -EBUSY;
3124         val = ucontrol->value.integer.value[0] & 1;
3125         spin_lock_irq(&hdspm->lock);
3126         change = (int) val != hdspm_dolby(hdspm);
3127         hdspm_set_dolby(hdspm, val);
3128         spin_unlock_irq(&hdspm->lock);
3129         return change;
3130 }
3131
3132
3133 #define HDSPM_PROFESSIONAL(xname, xindex) \
3134 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3135   .name = xname, \
3136   .index = xindex, \
3137   .info = snd_hdspm_info_professional, \
3138   .get = snd_hdspm_get_professional, \
3139   .put = snd_hdspm_put_professional \
3140 }
3141
3142 static int hdspm_professional(struct hdspm * hdspm)
3143 {
3144         return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
3145 }
3146
3147 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
3148 {
3149         if (dol)
3150                 hdspm->control_register |= HDSPM_Professional;
3151         else
3152                 hdspm->control_register &= ~HDSPM_Professional;
3153         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3154
3155         return 0;
3156 }
3157
3158 #define snd_hdspm_info_professional     snd_ctl_boolean_mono_info
3159
3160 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
3161                                       struct snd_ctl_elem_value *ucontrol)
3162 {
3163         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3164
3165         spin_lock_irq(&hdspm->lock);
3166         ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
3167         spin_unlock_irq(&hdspm->lock);
3168         return 0;
3169 }
3170
3171 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
3172                                       struct snd_ctl_elem_value *ucontrol)
3173 {
3174         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3175         int change;
3176         unsigned int val;
3177
3178         if (!snd_hdspm_use_is_exclusive(hdspm))
3179                 return -EBUSY;
3180         val = ucontrol->value.integer.value[0] & 1;
3181         spin_lock_irq(&hdspm->lock);
3182         change = (int) val != hdspm_professional(hdspm);
3183         hdspm_set_professional(hdspm, val);
3184         spin_unlock_irq(&hdspm->lock);
3185         return change;
3186 }
3187
3188 #define HDSPM_INPUT_SELECT(xname, xindex) \
3189 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3190   .name = xname, \
3191   .index = xindex, \
3192   .info = snd_hdspm_info_input_select, \
3193   .get = snd_hdspm_get_input_select, \
3194   .put = snd_hdspm_put_input_select \
3195 }
3196
3197 static int hdspm_input_select(struct hdspm * hdspm)
3198 {
3199         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3200 }
3201
3202 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3203 {
3204         if (out)
3205                 hdspm->control_register |= HDSPM_InputSelect0;
3206         else
3207                 hdspm->control_register &= ~HDSPM_InputSelect0;
3208         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3209
3210         return 0;
3211 }
3212
3213 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3214                                        struct snd_ctl_elem_info *uinfo)
3215 {
3216         static char *texts[] = { "optical", "coaxial" };
3217
3218         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3219         uinfo->count = 1;
3220         uinfo->value.enumerated.items = 2;
3221
3222         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3223                 uinfo->value.enumerated.item =
3224                     uinfo->value.enumerated.items - 1;
3225         strcpy(uinfo->value.enumerated.name,
3226                texts[uinfo->value.enumerated.item]);
3227
3228         return 0;
3229 }
3230
3231 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3232                                       struct snd_ctl_elem_value *ucontrol)
3233 {
3234         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3235
3236         spin_lock_irq(&hdspm->lock);
3237         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3238         spin_unlock_irq(&hdspm->lock);
3239         return 0;
3240 }
3241
3242 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3243                                       struct snd_ctl_elem_value *ucontrol)
3244 {
3245         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3246         int change;
3247         unsigned int val;
3248
3249         if (!snd_hdspm_use_is_exclusive(hdspm))
3250                 return -EBUSY;
3251         val = ucontrol->value.integer.value[0] & 1;
3252         spin_lock_irq(&hdspm->lock);
3253         change = (int) val != hdspm_input_select(hdspm);
3254         hdspm_set_input_select(hdspm, val);
3255         spin_unlock_irq(&hdspm->lock);
3256         return change;
3257 }
3258
3259
3260 #define HDSPM_DS_WIRE(xname, xindex) \
3261 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3262   .name = xname, \
3263   .index = xindex, \
3264   .info = snd_hdspm_info_ds_wire, \
3265   .get = snd_hdspm_get_ds_wire, \
3266   .put = snd_hdspm_put_ds_wire \
3267 }
3268
3269 static int hdspm_ds_wire(struct hdspm * hdspm)
3270 {
3271         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3272 }
3273
3274 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3275 {
3276         if (ds)
3277                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3278         else
3279                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3280         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3281
3282         return 0;
3283 }
3284
3285 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3286                                   struct snd_ctl_elem_info *uinfo)
3287 {
3288         static char *texts[] = { "Single", "Double" };
3289
3290         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3291         uinfo->count = 1;
3292         uinfo->value.enumerated.items = 2;
3293
3294         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3295                 uinfo->value.enumerated.item =
3296                     uinfo->value.enumerated.items - 1;
3297         strcpy(uinfo->value.enumerated.name,
3298                texts[uinfo->value.enumerated.item]);
3299
3300         return 0;
3301 }
3302
3303 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3304                                  struct snd_ctl_elem_value *ucontrol)
3305 {
3306         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3307
3308         spin_lock_irq(&hdspm->lock);
3309         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3310         spin_unlock_irq(&hdspm->lock);
3311         return 0;
3312 }
3313
3314 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3315                                  struct snd_ctl_elem_value *ucontrol)
3316 {
3317         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3318         int change;
3319         unsigned int val;
3320
3321         if (!snd_hdspm_use_is_exclusive(hdspm))
3322                 return -EBUSY;
3323         val = ucontrol->value.integer.value[0] & 1;
3324         spin_lock_irq(&hdspm->lock);
3325         change = (int) val != hdspm_ds_wire(hdspm);
3326         hdspm_set_ds_wire(hdspm, val);
3327         spin_unlock_irq(&hdspm->lock);
3328         return change;
3329 }
3330
3331
3332 #define HDSPM_QS_WIRE(xname, xindex) \
3333 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3334   .name = xname, \
3335   .index = xindex, \
3336   .info = snd_hdspm_info_qs_wire, \
3337   .get = snd_hdspm_get_qs_wire, \
3338   .put = snd_hdspm_put_qs_wire \
3339 }
3340
3341 static int hdspm_qs_wire(struct hdspm * hdspm)
3342 {
3343         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3344                 return 1;
3345         if (hdspm->control_register & HDSPM_QS_QuadWire)
3346                 return 2;
3347         return 0;
3348 }
3349
3350 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3351 {
3352         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3353         switch (mode) {
3354         case 0:
3355                 break;
3356         case 1:
3357                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3358                 break;
3359         case 2:
3360                 hdspm->control_register |= HDSPM_QS_QuadWire;
3361                 break;
3362         }
3363         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3364
3365         return 0;
3366 }
3367
3368 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3369                                        struct snd_ctl_elem_info *uinfo)
3370 {
3371         static char *texts[] = { "Single", "Double", "Quad" };
3372
3373         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3374         uinfo->count = 1;
3375         uinfo->value.enumerated.items = 3;
3376
3377         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3378                 uinfo->value.enumerated.item =
3379                     uinfo->value.enumerated.items - 1;
3380         strcpy(uinfo->value.enumerated.name,
3381                texts[uinfo->value.enumerated.item]);
3382
3383         return 0;
3384 }
3385
3386 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3387                                       struct snd_ctl_elem_value *ucontrol)
3388 {
3389         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3390
3391         spin_lock_irq(&hdspm->lock);
3392         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3393         spin_unlock_irq(&hdspm->lock);
3394         return 0;
3395 }
3396
3397 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3398                                       struct snd_ctl_elem_value *ucontrol)
3399 {
3400         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3401         int change;
3402         int val;
3403
3404         if (!snd_hdspm_use_is_exclusive(hdspm))
3405                 return -EBUSY;
3406         val = ucontrol->value.integer.value[0];
3407         if (val < 0)
3408                 val = 0;
3409         if (val > 2)
3410                 val = 2;
3411         spin_lock_irq(&hdspm->lock);
3412         change = val != hdspm_qs_wire(hdspm);
3413         hdspm_set_qs_wire(hdspm, val);
3414         spin_unlock_irq(&hdspm->lock);
3415         return change;
3416 }
3417
3418 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3419 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3420         .name = xname, \
3421         .index = xindex, \
3422         .info = snd_hdspm_info_madi_speedmode, \
3423         .get = snd_hdspm_get_madi_speedmode, \
3424         .put = snd_hdspm_put_madi_speedmode \
3425 }
3426
3427 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3428 {
3429         if (hdspm->control_register & HDSPM_QuadSpeed)
3430                 return 2;
3431         if (hdspm->control_register & HDSPM_DoubleSpeed)
3432                 return 1;
3433         return 0;
3434 }
3435
3436 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3437 {
3438         hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3439         switch (mode) {
3440         case 0:
3441                 break;
3442         case 1:
3443                 hdspm->control_register |= HDSPM_DoubleSpeed;
3444                 break;
3445         case 2:
3446                 hdspm->control_register |= HDSPM_QuadSpeed;
3447                 break;
3448         }
3449         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3450
3451         return 0;
3452 }
3453
3454 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3455                                        struct snd_ctl_elem_info *uinfo)
3456 {
3457         static char *texts[] = { "Single", "Double", "Quad" };
3458
3459         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3460         uinfo->count = 1;
3461         uinfo->value.enumerated.items = 3;
3462
3463         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3464                 uinfo->value.enumerated.item =
3465                     uinfo->value.enumerated.items - 1;
3466         strcpy(uinfo->value.enumerated.name,
3467                texts[uinfo->value.enumerated.item]);
3468
3469         return 0;
3470 }
3471
3472 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3473                                       struct snd_ctl_elem_value *ucontrol)
3474 {
3475         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3476
3477         spin_lock_irq(&hdspm->lock);
3478         ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3479         spin_unlock_irq(&hdspm->lock);
3480         return 0;
3481 }
3482
3483 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3484                                       struct snd_ctl_elem_value *ucontrol)
3485 {
3486         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3487         int change;
3488         int val;
3489
3490         if (!snd_hdspm_use_is_exclusive(hdspm))
3491                 return -EBUSY;
3492         val = ucontrol->value.integer.value[0];
3493         if (val < 0)
3494                 val = 0;
3495         if (val > 2)
3496                 val = 2;
3497         spin_lock_irq(&hdspm->lock);
3498         change = val != hdspm_madi_speedmode(hdspm);
3499         hdspm_set_madi_speedmode(hdspm, val);
3500         spin_unlock_irq(&hdspm->lock);
3501         return change;
3502 }
3503
3504 #define HDSPM_MIXER(xname, xindex) \
3505 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3506   .name = xname, \
3507   .index = xindex, \
3508   .device = 0, \
3509   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3510                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3511   .info = snd_hdspm_info_mixer, \
3512   .get = snd_hdspm_get_mixer, \
3513   .put = snd_hdspm_put_mixer \
3514 }
3515
3516 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3517                                 struct snd_ctl_elem_info *uinfo)
3518 {
3519         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3520         uinfo->count = 3;
3521         uinfo->value.integer.min = 0;
3522         uinfo->value.integer.max = 65535;
3523         uinfo->value.integer.step = 1;
3524         return 0;
3525 }
3526
3527 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3528                                struct snd_ctl_elem_value *ucontrol)
3529 {
3530         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3531         int source;
3532         int destination;
3533
3534         source = ucontrol->value.integer.value[0];
3535         if (source < 0)
3536                 source = 0;
3537         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3538                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3539
3540         destination = ucontrol->value.integer.value[1];
3541         if (destination < 0)
3542                 destination = 0;
3543         else if (destination >= HDSPM_MAX_CHANNELS)
3544                 destination = HDSPM_MAX_CHANNELS - 1;
3545
3546         spin_lock_irq(&hdspm->lock);
3547         if (source >= HDSPM_MAX_CHANNELS)
3548                 ucontrol->value.integer.value[2] =
3549                     hdspm_read_pb_gain(hdspm, destination,
3550                                        source - HDSPM_MAX_CHANNELS);
3551         else
3552                 ucontrol->value.integer.value[2] =
3553                     hdspm_read_in_gain(hdspm, destination, source);
3554
3555         spin_unlock_irq(&hdspm->lock);
3556
3557         return 0;
3558 }
3559
3560 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3561                                struct snd_ctl_elem_value *ucontrol)
3562 {
3563         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3564         int change;
3565         int source;
3566         int destination;
3567         int gain;
3568
3569         if (!snd_hdspm_use_is_exclusive(hdspm))
3570                 return -EBUSY;
3571
3572         source = ucontrol->value.integer.value[0];
3573         destination = ucontrol->value.integer.value[1];
3574
3575         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3576                 return -1;
3577         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3578                 return -1;
3579
3580         gain = ucontrol->value.integer.value[2];
3581
3582         spin_lock_irq(&hdspm->lock);
3583
3584         if (source >= HDSPM_MAX_CHANNELS)
3585                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3586                                                     source -
3587                                                     HDSPM_MAX_CHANNELS);
3588         else
3589                 change = gain != hdspm_read_in_gain(hdspm, destination,
3590                                                     source);
3591
3592         if (change) {
3593                 if (source >= HDSPM_MAX_CHANNELS)
3594                         hdspm_write_pb_gain(hdspm, destination,
3595                                             source - HDSPM_MAX_CHANNELS,
3596                                             gain);
3597                 else
3598                         hdspm_write_in_gain(hdspm, destination, source,
3599                                             gain);
3600         }
3601         spin_unlock_irq(&hdspm->lock);
3602
3603         return change;
3604 }
3605
3606 /* The simple mixer control(s) provide gain control for the
3607    basic 1:1 mappings of playback streams to output
3608    streams.
3609 */
3610
3611 #define HDSPM_PLAYBACK_MIXER \
3612 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3613   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3614                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3615   .info = snd_hdspm_info_playback_mixer, \
3616   .get = snd_hdspm_get_playback_mixer, \
3617   .put = snd_hdspm_put_playback_mixer \
3618 }
3619
3620 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3621                                          struct snd_ctl_elem_info *uinfo)
3622 {
3623         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3624         uinfo->count = 1;
3625         uinfo->value.integer.min = 0;
3626         uinfo->value.integer.max = 64;
3627         uinfo->value.integer.step = 1;
3628         return 0;
3629 }
3630
3631 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3632                                         struct snd_ctl_elem_value *ucontrol)
3633 {
3634         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3635         int channel;
3636
3637         channel = ucontrol->id.index - 1;
3638
3639         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3640                 return -EINVAL;
3641
3642         spin_lock_irq(&hdspm->lock);
3643         ucontrol->value.integer.value[0] =
3644           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3645         spin_unlock_irq(&hdspm->lock);
3646
3647         return 0;
3648 }
3649
3650 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3651                                         struct snd_ctl_elem_value *ucontrol)
3652 {
3653         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3654         int change;
3655         int channel;
3656         int gain;
3657
3658         if (!snd_hdspm_use_is_exclusive(hdspm))
3659                 return -EBUSY;
3660
3661         channel = ucontrol->id.index - 1;
3662
3663         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3664                 return -EINVAL;
3665
3666         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3667
3668         spin_lock_irq(&hdspm->lock);
3669         change =
3670             gain != hdspm_read_pb_gain(hdspm, channel,
3671                                        channel);
3672         if (change)
3673                 hdspm_write_pb_gain(hdspm, channel, channel,
3674                                     gain);
3675         spin_unlock_irq(&hdspm->lock);
3676         return change;
3677 }
3678
3679 #define HDSPM_SYNC_CHECK(xname, xindex) \
3680 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3681         .name = xname, \
3682         .private_value = xindex, \
3683         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3684         .info = snd_hdspm_info_sync_check, \
3685         .get = snd_hdspm_get_sync_check \
3686 }
3687
3688
3689 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3690                                      struct snd_ctl_elem_info *uinfo)
3691 {
3692         static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3693         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3694         uinfo->count = 1;
3695         uinfo->value.enumerated.items = 4;
3696         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3697                 uinfo->value.enumerated.item =
3698                         uinfo->value.enumerated.items - 1;
3699         strcpy(uinfo->value.enumerated.name,
3700                         texts[uinfo->value.enumerated.item]);
3701         return 0;
3702 }
3703
3704 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3705 {
3706         int status, status2;
3707
3708         switch (hdspm->io_type) {
3709         case AES32:
3710                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3711                 if (status & HDSPM_wcSync)
3712                         return 2;
3713                 else if (status & HDSPM_wcLock)
3714                         return 1;
3715                 return 0;
3716                 break;
3717
3718         case MADI:
3719                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3720                 if (status2 & HDSPM_wcLock) {
3721                         if (status2 & HDSPM_wcSync)
3722                                 return 2;
3723                         else
3724                                 return 1;
3725                 }
3726                 return 0;
3727                 break;
3728
3729         case RayDAT:
3730         case AIO:
3731                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3732
3733                 if (status & 0x2000000)
3734                         return 2;
3735                 else if (status & 0x1000000)
3736                         return 1;
3737                 return 0;
3738
3739                 break;
3740
3741         case MADIface:
3742                 break;
3743         }
3744
3745
3746         return 3;
3747 }
3748
3749
3750 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3751 {
3752         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3753         if (status & HDSPM_madiLock) {
3754                 if (status & HDSPM_madiSync)
3755                         return 2;
3756                 else
3757                         return 1;
3758         }
3759         return 0;
3760 }
3761
3762
3763 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3764 {
3765         int status, lock, sync;
3766
3767         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3768
3769         lock = (status & (0x1<<idx)) ? 1 : 0;
3770         sync = (status & (0x100<<idx)) ? 1 : 0;
3771
3772         if (lock && sync)
3773                 return 2;
3774         else if (lock)
3775                 return 1;
3776         return 0;
3777 }
3778
3779
3780 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3781 {
3782         int status, lock = 0, sync = 0;
3783
3784         switch (hdspm->io_type) {
3785         case RayDAT:
3786         case AIO:
3787                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3788                 lock = (status & 0x400) ? 1 : 0;
3789                 sync = (status & 0x800) ? 1 : 0;
3790                 break;
3791
3792         case MADI:
3793         case AES32:
3794                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3795                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3796                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3797                 break;
3798
3799         case MADIface:
3800                 break;
3801         }
3802
3803         if (lock && sync)
3804                 return 2;
3805         else if (lock)
3806                 return 1;
3807
3808         return 0;
3809 }
3810
3811 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3812 {
3813         int status2, lock, sync;
3814         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3815
3816         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3817         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3818
3819         if (sync)
3820                 return 2;
3821         else if (lock)
3822                 return 1;
3823         return 0;
3824 }
3825
3826
3827 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3828 {
3829         int status;
3830
3831         if (hdspm->tco) {
3832                 switch (hdspm->io_type) {
3833                 case MADI:
3834                 case AES32:
3835                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3836                         if (status & HDSPM_tcoLock) {
3837                                 if (status & HDSPM_tcoSync)
3838                                         return 2;
3839                                 else
3840                                         return 1;
3841                         }
3842                         return 0;
3843
3844                         break;
3845
3846                 case RayDAT:
3847                 case AIO:
3848                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3849
3850                         if (status & 0x8000000)
3851                                 return 2; /* Sync */
3852                         if (status & 0x4000000)
3853                                 return 1; /* Lock */
3854                         return 0; /* No signal */
3855                         break;
3856
3857                 default:
3858                         break;
3859                 }
3860         }
3861
3862         return 3; /* N/A */
3863 }
3864
3865
3866 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3867                                     struct snd_ctl_elem_value *ucontrol)
3868 {
3869         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3870         int val = -1;
3871
3872         switch (hdspm->io_type) {
3873         case RayDAT:
3874                 switch (kcontrol->private_value) {
3875                 case 0: /* WC */
3876                         val = hdspm_wc_sync_check(hdspm); break;
3877                 case 7: /* TCO */
3878                         val = hdspm_tco_sync_check(hdspm); break;
3879                 case 8: /* SYNC IN */
3880                         val = hdspm_sync_in_sync_check(hdspm); break;
3881                 default:
3882                         val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3883                 }
3884
3885         case AIO:
3886                 switch (kcontrol->private_value) {
3887                 case 0: /* WC */
3888                         val = hdspm_wc_sync_check(hdspm); break;
3889                 case 4: /* TCO */
3890                         val = hdspm_tco_sync_check(hdspm); break;
3891                 case 5: /* SYNC IN */
3892                         val = hdspm_sync_in_sync_check(hdspm); break;
3893                 default:
3894                         val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3895                 }
3896
3897         case MADI:
3898                 switch (kcontrol->private_value) {
3899                 case 0: /* WC */
3900                         val = hdspm_wc_sync_check(hdspm); break;
3901                 case 1: /* MADI */
3902                         val = hdspm_madi_sync_check(hdspm); break;
3903                 case 2: /* TCO */
3904                         val = hdspm_tco_sync_check(hdspm); break;
3905                 case 3: /* SYNC_IN */
3906                         val = hdspm_sync_in_sync_check(hdspm); break;
3907                 }
3908
3909         case MADIface:
3910                 val = hdspm_madi_sync_check(hdspm); /* MADI */
3911                 break;
3912
3913         case AES32:
3914                 switch (kcontrol->private_value) {
3915                 case 0: /* WC */
3916                         val = hdspm_wc_sync_check(hdspm); break;
3917                 case 9: /* TCO */
3918                         val = hdspm_tco_sync_check(hdspm); break;
3919                 case 10 /* SYNC IN */:
3920                         val = hdspm_sync_in_sync_check(hdspm); break;
3921                 default: /* AES1 to AES8 */
3922                          val = hdspm_aes_sync_check(hdspm,
3923                                          kcontrol->private_value-1);
3924                 }
3925
3926         }
3927
3928         if (-1 == val)
3929                 val = 3;
3930
3931         ucontrol->value.enumerated.item[0] = val;
3932         return 0;
3933 }
3934
3935
3936
3937 /**
3938  * TCO controls
3939  **/
3940 static void hdspm_tco_write(struct hdspm *hdspm)
3941 {
3942         unsigned int tc[4] = { 0, 0, 0, 0};
3943
3944         switch (hdspm->tco->input) {
3945         case 0:
3946                 tc[2] |= HDSPM_TCO2_set_input_MSB;
3947                 break;
3948         case 1:
3949                 tc[2] |= HDSPM_TCO2_set_input_LSB;
3950                 break;
3951         default:
3952                 break;
3953         }
3954
3955         switch (hdspm->tco->framerate) {
3956         case 1:
3957                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
3958                 break;
3959         case 2:
3960                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
3961                 break;
3962         case 3:
3963                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
3964                         HDSPM_TCO1_set_drop_frame_flag;
3965                 break;
3966         case 4:
3967                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3968                         HDSPM_TCO1_LTC_Format_MSB;
3969                 break;
3970         case 5:
3971                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3972                         HDSPM_TCO1_LTC_Format_MSB +
3973                         HDSPM_TCO1_set_drop_frame_flag;
3974                 break;
3975         default:
3976                 break;
3977         }
3978
3979         switch (hdspm->tco->wordclock) {
3980         case 1:
3981                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
3982                 break;
3983         case 2:
3984                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
3985                 break;
3986         default:
3987                 break;
3988         }
3989
3990         switch (hdspm->tco->samplerate) {
3991         case 1:
3992                 tc[2] |= HDSPM_TCO2_set_freq;
3993                 break;
3994         case 2:
3995                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
3996                 break;
3997         default:
3998                 break;
3999         }
4000
4001         switch (hdspm->tco->pull) {
4002         case 1:
4003                 tc[2] |= HDSPM_TCO2_set_pull_up;
4004                 break;
4005         case 2:
4006                 tc[2] |= HDSPM_TCO2_set_pull_down;
4007                 break;
4008         case 3:
4009                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4010                 break;
4011         case 4:
4012                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4013                 break;
4014         default:
4015                 break;
4016         }
4017
4018         if (1 == hdspm->tco->term) {
4019                 tc[2] |= HDSPM_TCO2_set_term_75R;
4020         }
4021
4022         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4023         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4024         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4025         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4026 }
4027
4028
4029 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4030 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4031         .name = xname, \
4032         .index = xindex, \
4033         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4034                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4035         .info = snd_hdspm_info_tco_sample_rate, \
4036         .get = snd_hdspm_get_tco_sample_rate, \
4037         .put = snd_hdspm_put_tco_sample_rate \
4038 }
4039
4040 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4041                                           struct snd_ctl_elem_info *uinfo)
4042 {
4043         static char *texts[] = { "44.1 kHz", "48 kHz" };
4044         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4045         uinfo->count = 1;
4046         uinfo->value.enumerated.items = 2;
4047
4048         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4049                 uinfo->value.enumerated.item =
4050                         uinfo->value.enumerated.items - 1;
4051
4052         strcpy(uinfo->value.enumerated.name,
4053                         texts[uinfo->value.enumerated.item]);
4054
4055         return 0;
4056 }
4057
4058 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4059                                       struct snd_ctl_elem_value *ucontrol)
4060 {
4061         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4062
4063         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4064
4065         return 0;
4066 }
4067
4068 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4069                                          struct snd_ctl_elem_value *ucontrol)
4070 {
4071         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4072
4073         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4074                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4075
4076                 hdspm_tco_write(hdspm);
4077
4078                 return 1;
4079         }
4080
4081         return 0;
4082 }
4083
4084
4085 #define HDSPM_TCO_PULL(xname, xindex) \
4086 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4087         .name = xname, \
4088         .index = xindex, \
4089         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4090                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4091         .info = snd_hdspm_info_tco_pull, \
4092         .get = snd_hdspm_get_tco_pull, \
4093         .put = snd_hdspm_put_tco_pull \
4094 }
4095
4096 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4097                                    struct snd_ctl_elem_info *uinfo)
4098 {
4099         static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4100         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4101         uinfo->count = 1;
4102         uinfo->value.enumerated.items = 5;
4103
4104         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4105                 uinfo->value.enumerated.item =
4106                         uinfo->value.enumerated.items - 1;
4107
4108         strcpy(uinfo->value.enumerated.name,
4109                         texts[uinfo->value.enumerated.item]);
4110
4111         return 0;
4112 }
4113
4114 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4115                                   struct snd_ctl_elem_value *ucontrol)
4116 {
4117         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4118
4119         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4120
4121         return 0;
4122 }
4123
4124 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4125                                   struct snd_ctl_elem_value *ucontrol)
4126 {
4127         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4128
4129         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4130                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4131
4132                 hdspm_tco_write(hdspm);
4133
4134                 return 1;
4135         }
4136
4137         return 0;
4138 }
4139
4140 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4141 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4142         .name = xname, \
4143         .index = xindex, \
4144         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4145                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4146         .info = snd_hdspm_info_tco_wck_conversion, \
4147         .get = snd_hdspm_get_tco_wck_conversion, \
4148         .put = snd_hdspm_put_tco_wck_conversion \
4149 }
4150
4151 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4152                                              struct snd_ctl_elem_info *uinfo)
4153 {
4154         static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4155         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4156         uinfo->count = 1;
4157         uinfo->value.enumerated.items = 3;
4158
4159         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4160                 uinfo->value.enumerated.item =
4161                         uinfo->value.enumerated.items - 1;
4162
4163         strcpy(uinfo->value.enumerated.name,
4164                         texts[uinfo->value.enumerated.item]);
4165
4166         return 0;
4167 }
4168
4169 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4170                                             struct snd_ctl_elem_value *ucontrol)
4171 {
4172         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4173
4174         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4175
4176         return 0;
4177 }
4178
4179 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4180                                             struct snd_ctl_elem_value *ucontrol)
4181 {
4182         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4183
4184         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4185                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4186
4187                 hdspm_tco_write(hdspm);
4188
4189                 return 1;
4190         }
4191
4192         return 0;
4193 }
4194
4195
4196 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4197 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4198         .name = xname, \
4199         .index = xindex, \
4200         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4201                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4202         .info = snd_hdspm_info_tco_frame_rate, \
4203         .get = snd_hdspm_get_tco_frame_rate, \
4204         .put = snd_hdspm_put_tco_frame_rate \
4205 }
4206
4207 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4208                                           struct snd_ctl_elem_info *uinfo)
4209 {
4210         static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4211                 "29.97 dfps", "30 fps", "30 dfps" };
4212         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4213         uinfo->count = 1;
4214         uinfo->value.enumerated.items = 6;
4215
4216         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4217                 uinfo->value.enumerated.item =
4218                         uinfo->value.enumerated.items - 1;
4219
4220         strcpy(uinfo->value.enumerated.name,
4221                         texts[uinfo->value.enumerated.item]);
4222
4223         return 0;
4224 }
4225
4226 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4227                                         struct snd_ctl_elem_value *ucontrol)
4228 {
4229         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4230
4231         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4232
4233         return 0;
4234 }
4235
4236 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4237                                         struct snd_ctl_elem_value *ucontrol)
4238 {
4239         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4240
4241         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4242                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4243
4244                 hdspm_tco_write(hdspm);
4245
4246                 return 1;
4247         }
4248
4249         return 0;
4250 }
4251
4252
4253 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4254 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4255         .name = xname, \
4256         .index = xindex, \
4257         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4258                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4259         .info = snd_hdspm_info_tco_sync_source, \
4260         .get = snd_hdspm_get_tco_sync_source, \
4261         .put = snd_hdspm_put_tco_sync_source \
4262 }
4263
4264 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4265                                           struct snd_ctl_elem_info *uinfo)
4266 {
4267         static char *texts[] = { "LTC", "Video", "WCK" };
4268         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4269         uinfo->count = 1;
4270         uinfo->value.enumerated.items = 3;
4271
4272         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4273                 uinfo->value.enumerated.item =
4274                         uinfo->value.enumerated.items - 1;
4275
4276         strcpy(uinfo->value.enumerated.name,
4277                         texts[uinfo->value.enumerated.item]);
4278
4279         return 0;
4280 }
4281
4282 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4283                                          struct snd_ctl_elem_value *ucontrol)
4284 {
4285         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4286
4287         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4288
4289         return 0;
4290 }
4291
4292 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4293                                          struct snd_ctl_elem_value *ucontrol)
4294 {
4295         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4296
4297         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4298                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4299
4300                 hdspm_tco_write(hdspm);
4301
4302                 return 1;
4303         }
4304
4305         return 0;
4306 }
4307
4308
4309 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4310 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4311         .name = xname, \
4312         .index = xindex, \
4313         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4314                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4315         .info = snd_hdspm_info_tco_word_term, \
4316         .get = snd_hdspm_get_tco_word_term, \
4317         .put = snd_hdspm_put_tco_word_term \
4318 }
4319
4320 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4321                                         struct snd_ctl_elem_info *uinfo)
4322 {
4323         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4324         uinfo->count = 1;
4325         uinfo->value.integer.min = 0;
4326         uinfo->value.integer.max = 1;
4327
4328         return 0;
4329 }
4330
4331
4332 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4333                                        struct snd_ctl_elem_value *ucontrol)
4334 {
4335         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4336
4337         ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4338
4339         return 0;
4340 }
4341
4342
4343 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4344                                        struct snd_ctl_elem_value *ucontrol)
4345 {
4346         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4347
4348         if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4349                 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4350
4351                 hdspm_tco_write(hdspm);
4352
4353                 return 1;
4354         }
4355
4356         return 0;
4357 }
4358
4359
4360
4361
4362 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4363         HDSPM_MIXER("Mixer", 0),
4364         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4365         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4366         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4367         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4368         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4369         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4370         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4371         HDSPM_SYNC_CHECK("TCO SyncCHeck", 2),
4372         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4373         HDSPM_LINE_OUT("Line Out", 0),
4374         HDSPM_TX_64("TX 64 channels mode", 0),
4375         HDSPM_C_TMS("Clear Track Marker", 0),
4376         HDSPM_SAFE_MODE("Safe Mode", 0),
4377         HDSPM_INPUT_SELECT("Input Select", 0),
4378         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4379 };
4380
4381
4382 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4383         HDSPM_MIXER("Mixer", 0),
4384         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4385         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4386         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4387         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4388         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4389         HDSPM_TX_64("TX 64 channels mode", 0),
4390         HDSPM_C_TMS("Clear Track Marker", 0),
4391         HDSPM_SAFE_MODE("Safe Mode", 0),
4392         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4393 };
4394
4395 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4396         HDSPM_MIXER("Mixer", 0),
4397         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4398         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4399         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4400         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4401         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4402         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4403         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4404         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4405         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4406         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4407         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4408         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4409         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4410         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4411         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4412         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4413         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4414         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4415
4416                 /*
4417                    HDSPM_INPUT_SELECT("Input Select", 0),
4418                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4419                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4420                    HDSPM_SPDIF_IN("SPDIF In", 0);
4421                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4422                    HDSPM_INPUT_LEVEL("Input Level", 0);
4423                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4424                    HDSPM_PHONES("Phones", 0);
4425                    */
4426 };
4427
4428 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4429         HDSPM_MIXER("Mixer", 0),
4430         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4431         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4432         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4433         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4434         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4435         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4436         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4437         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4438         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4439         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4440         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4441         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4442         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4443         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4444         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4445         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4446         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4447         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4448         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4449         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4450         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4451         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4452 };
4453
4454 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4455         HDSPM_MIXER("Mixer", 0),
4456         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4457         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4458         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4459         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4460         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4461         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4462         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4463         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4464         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4465         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4466         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4467         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4468         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4469         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4470         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4471         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4472         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4473         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4474         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4475         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4476         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4477         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4478         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4479         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4480         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4481         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4482         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4483         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4484         HDSPM_LINE_OUT("Line Out", 0),
4485         HDSPM_EMPHASIS("Emphasis", 0),
4486         HDSPM_DOLBY("Non Audio", 0),
4487         HDSPM_PROFESSIONAL("Professional", 0),
4488         HDSPM_C_TMS("Clear Track Marker", 0),
4489         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4490         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4491 };
4492
4493
4494
4495 /* Control elements for the optional TCO module */
4496 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4497         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4498         HDSPM_TCO_PULL("TCO Pull", 0),
4499         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4500         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4501         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4502         HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
4503 };
4504
4505
4506 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4507
4508
4509 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4510 {
4511         int i;
4512
4513         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4514                 if (hdspm->system_sample_rate > 48000) {
4515                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4516                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4517                                 SNDRV_CTL_ELEM_ACCESS_READ |
4518                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4519                 } else {
4520                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4521                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4522                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4523                 }
4524                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4525                                 SNDRV_CTL_EVENT_MASK_INFO,
4526                                 &hdspm->playback_mixer_ctls[i]->id);
4527         }
4528
4529         return 0;
4530 }
4531
4532
4533 static int snd_hdspm_create_controls(struct snd_card *card,
4534                                         struct hdspm *hdspm)
4535 {
4536         unsigned int idx, limit;
4537         int err;
4538         struct snd_kcontrol *kctl;
4539         struct snd_kcontrol_new *list = NULL;
4540
4541         switch (hdspm->io_type) {
4542         case MADI:
4543                 list = snd_hdspm_controls_madi;
4544                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4545                 break;
4546         case MADIface:
4547                 list = snd_hdspm_controls_madiface;
4548                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4549                 break;
4550         case AIO:
4551                 list = snd_hdspm_controls_aio;
4552                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4553                 break;
4554         case RayDAT:
4555                 list = snd_hdspm_controls_raydat;
4556                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4557                 break;
4558         case AES32:
4559                 list = snd_hdspm_controls_aes32;
4560                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4561                 break;
4562         }
4563
4564         if (NULL != list) {
4565                 for (idx = 0; idx < limit; idx++) {
4566                         err = snd_ctl_add(card,
4567                                         snd_ctl_new1(&list[idx], hdspm));
4568                         if (err < 0)
4569                                 return err;
4570                 }
4571         }
4572
4573
4574         /* create simple 1:1 playback mixer controls */
4575         snd_hdspm_playback_mixer.name = "Chn";
4576         if (hdspm->system_sample_rate >= 128000) {
4577                 limit = hdspm->qs_out_channels;
4578         } else if (hdspm->system_sample_rate >= 64000) {
4579                 limit = hdspm->ds_out_channels;
4580         } else {
4581                 limit = hdspm->ss_out_channels;
4582         }
4583         for (idx = 0; idx < limit; ++idx) {
4584                 snd_hdspm_playback_mixer.index = idx + 1;
4585                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4586                 err = snd_ctl_add(card, kctl);
4587                 if (err < 0)
4588                         return err;
4589                 hdspm->playback_mixer_ctls[idx] = kctl;
4590         }
4591
4592
4593         if (hdspm->tco) {
4594                 /* add tco control elements */
4595                 list = snd_hdspm_controls_tco;
4596                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4597                 for (idx = 0; idx < limit; idx++) {
4598                         err = snd_ctl_add(card,
4599                                         snd_ctl_new1(&list[idx], hdspm));
4600                         if (err < 0)
4601                                 return err;
4602                 }
4603         }
4604
4605         return 0;
4606 }
4607
4608 /*------------------------------------------------------------
4609    /proc interface
4610  ------------------------------------------------------------*/
4611
4612 static void
4613 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4614                          struct snd_info_buffer *buffer)
4615 {
4616         struct hdspm *hdspm = entry->private_data;
4617         unsigned int status, status2, control, freq;
4618
4619         char *pref_sync_ref;
4620         char *autosync_ref;
4621         char *system_clock_mode;
4622         char *insel;
4623         int x, x2;
4624
4625         /* TCO stuff */
4626         int a, ltc, frames, seconds, minutes, hours;
4627         unsigned int period;
4628         u64 freq_const = 0;
4629         u32 rate;
4630
4631         status = hdspm_read(hdspm, HDSPM_statusRegister);
4632         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4633         control = hdspm->control_register;
4634         freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4635
4636         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4637                         hdspm->card_name, hdspm->card->number + 1,
4638                         hdspm->firmware_rev,
4639                         (status2 & HDSPM_version0) |
4640                         (status2 & HDSPM_version1) | (status2 &
4641                                 HDSPM_version2));
4642
4643         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4644                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4645                         (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
4646
4647         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4648                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4649
4650         snd_iprintf(buffer, "--- System ---\n");
4651
4652         snd_iprintf(buffer,
4653                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4654                 status & HDSPM_audioIRQPending,
4655                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4656                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4657                 hdspm->irq_count);
4658         snd_iprintf(buffer,
4659                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4660                 "estimated= %ld (bytes)\n",
4661                 ((status & HDSPM_BufferID) ? 1 : 0),
4662                 (status & HDSPM_BufferPositionMask),
4663                 (status & HDSPM_BufferPositionMask) %
4664                 (2 * (int)hdspm->period_bytes),
4665                 ((status & HDSPM_BufferPositionMask) - 64) %
4666                 (2 * (int)hdspm->period_bytes),
4667                 (long) hdspm_hw_pointer(hdspm) * 4);
4668
4669         snd_iprintf(buffer,
4670                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4671                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4672                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4673                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4674                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4675         snd_iprintf(buffer,
4676                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4677                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4678                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4679         snd_iprintf(buffer,
4680                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4681                 "status2=0x%x\n",
4682                 hdspm->control_register, hdspm->control2_register,
4683                 status, status2);
4684         if (status & HDSPM_tco_detect) {
4685                 snd_iprintf(buffer, "TCO module detected.\n");
4686                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4687                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4688                         snd_iprintf(buffer, "  LTC valid, ");
4689                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4690                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4691                         case 0:
4692                                 snd_iprintf(buffer, "24 fps, ");
4693                                 break;
4694                         case HDSPM_TCO1_LTC_Format_LSB:
4695                                 snd_iprintf(buffer, "25 fps, ");
4696                                 break;
4697                         case HDSPM_TCO1_LTC_Format_MSB:
4698                                 snd_iprintf(buffer, "29.97 fps, ");
4699                                 break;
4700                         default:
4701                                 snd_iprintf(buffer, "30 fps, ");
4702                                 break;
4703                         }
4704                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4705                                 snd_iprintf(buffer, "drop frame\n");
4706                         } else {
4707                                 snd_iprintf(buffer, "full frame\n");
4708                         }
4709                 } else {
4710                         snd_iprintf(buffer, "  no LTC\n");
4711                 }
4712                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4713                         snd_iprintf(buffer, "  Video: NTSC\n");
4714                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4715                         snd_iprintf(buffer, "  Video: PAL\n");
4716                 } else {
4717                         snd_iprintf(buffer, "  No video\n");
4718                 }
4719                 if (a & HDSPM_TCO1_TCO_lock) {
4720                         snd_iprintf(buffer, "  Sync: lock\n");
4721                 } else {
4722                         snd_iprintf(buffer, "  Sync: no lock\n");
4723                 }
4724
4725                 switch (hdspm->io_type) {
4726                 case MADI:
4727                 case AES32:
4728                         freq_const = 110069313433624ULL;
4729                         break;
4730                 case RayDAT:
4731                 case AIO:
4732                         freq_const = 104857600000000ULL;
4733                         break;
4734                 case MADIface:
4735                         break; /* no TCO possible */
4736                 }
4737
4738                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4739                 snd_iprintf(buffer, "    period: %u\n", period);
4740
4741
4742                 /* rate = freq_const/period; */
4743                 rate = div_u64(freq_const, period);
4744
4745                 if (control & HDSPM_QuadSpeed) {
4746                         rate *= 4;
4747                 } else if (control & HDSPM_DoubleSpeed) {
4748                         rate *= 2;
4749                 }
4750
4751                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4752                                 (unsigned int) rate);
4753
4754                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4755                 frames = ltc & 0xF;
4756                 ltc >>= 4;
4757                 frames += (ltc & 0x3) * 10;
4758                 ltc >>= 4;
4759                 seconds = ltc & 0xF;
4760                 ltc >>= 4;
4761                 seconds += (ltc & 0x7) * 10;
4762                 ltc >>= 4;
4763                 minutes = ltc & 0xF;
4764                 ltc >>= 4;
4765                 minutes += (ltc & 0x7) * 10;
4766                 ltc >>= 4;
4767                 hours = ltc & 0xF;
4768                 ltc >>= 4;
4769                 hours += (ltc & 0x3) * 10;
4770                 snd_iprintf(buffer,
4771                         "  LTC In: %02d:%02d:%02d:%02d\n",
4772                         hours, minutes, seconds, frames);
4773
4774         } else {
4775                 snd_iprintf(buffer, "No TCO module detected.\n");
4776         }
4777
4778         snd_iprintf(buffer, "--- Settings ---\n");
4779
4780         x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4781                                                         HDSPM_LatencyMask));
4782
4783         snd_iprintf(buffer,
4784                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4785                 x, (unsigned long) hdspm->period_bytes);
4786
4787         snd_iprintf(buffer, "Line out: %s\n",
4788                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4789
4790         switch (hdspm->control_register & HDSPM_InputMask) {
4791         case HDSPM_InputOptical:
4792                 insel = "Optical";
4793                 break;
4794         case HDSPM_InputCoaxial:
4795                 insel = "Coaxial";
4796                 break;
4797         default:
4798                 insel = "Unkown";
4799         }
4800
4801         snd_iprintf(buffer,
4802                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4803                 "Auto Input %s\n",
4804                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4805                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4806                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4807
4808
4809         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4810                 system_clock_mode = "AutoSync";
4811         else
4812                 system_clock_mode = "Master";
4813         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4814
4815         switch (hdspm_pref_sync_ref(hdspm)) {
4816         case HDSPM_SYNC_FROM_WORD:
4817                 pref_sync_ref = "Word Clock";
4818                 break;
4819         case HDSPM_SYNC_FROM_MADI:
4820                 pref_sync_ref = "MADI Sync";
4821                 break;
4822         case HDSPM_SYNC_FROM_TCO:
4823                 pref_sync_ref = "TCO";
4824                 break;
4825         case HDSPM_SYNC_FROM_SYNC_IN:
4826                 pref_sync_ref = "Sync In";
4827                 break;
4828         default:
4829                 pref_sync_ref = "XXXX Clock";
4830                 break;
4831         }
4832         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4833                         pref_sync_ref);
4834
4835         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4836                         hdspm->system_sample_rate);
4837
4838
4839         snd_iprintf(buffer, "--- Status:\n");
4840
4841         x = status & HDSPM_madiSync;
4842         x2 = status2 & HDSPM_wcSync;
4843
4844         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4845                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4846                         "NoLock",
4847                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4848                         "NoLock");
4849
4850         switch (hdspm_autosync_ref(hdspm)) {
4851         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4852                 autosync_ref = "Sync In";
4853                 break;
4854         case HDSPM_AUTOSYNC_FROM_TCO:
4855                 autosync_ref = "TCO";
4856                 break;
4857         case HDSPM_AUTOSYNC_FROM_WORD:
4858                 autosync_ref = "Word Clock";
4859                 break;
4860         case HDSPM_AUTOSYNC_FROM_MADI:
4861                 autosync_ref = "MADI Sync";
4862                 break;
4863         case HDSPM_AUTOSYNC_FROM_NONE:
4864                 autosync_ref = "Input not valid";
4865                 break;
4866         default:
4867                 autosync_ref = "---";
4868                 break;
4869         }
4870         snd_iprintf(buffer,
4871                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4872                 autosync_ref, hdspm_external_sample_rate(hdspm),
4873                 (status & HDSPM_madiFreqMask) >> 22,
4874                 (status2 & HDSPM_wcFreqMask) >> 5);
4875
4876         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4877                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4878                 (status & HDSPM_RX_64ch) ? "64 channels" :
4879                 "56 channels");
4880
4881         snd_iprintf(buffer, "\n");
4882 }
4883
4884 static void
4885 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4886                           struct snd_info_buffer *buffer)
4887 {
4888         struct hdspm *hdspm = entry->private_data;
4889         unsigned int status;
4890         unsigned int status2;
4891         unsigned int timecode;
4892         int pref_syncref;
4893         char *autosync_ref;
4894         int x;
4895
4896         status = hdspm_read(hdspm, HDSPM_statusRegister);
4897         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4898         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4899
4900         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4901                     hdspm->card_name, hdspm->card->number + 1,
4902                     hdspm->firmware_rev);
4903
4904         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4905                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4906
4907         snd_iprintf(buffer, "--- System ---\n");
4908
4909         snd_iprintf(buffer,
4910                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4911                     status & HDSPM_audioIRQPending,
4912                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
4913                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
4914                     hdspm->irq_count);
4915         snd_iprintf(buffer,
4916                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
4917                     "estimated= %ld (bytes)\n",
4918                     ((status & HDSPM_BufferID) ? 1 : 0),
4919                     (status & HDSPM_BufferPositionMask),
4920                     (status & HDSPM_BufferPositionMask) %
4921                     (2 * (int)hdspm->period_bytes),
4922                     ((status & HDSPM_BufferPositionMask) - 64) %
4923                     (2 * (int)hdspm->period_bytes),
4924                     (long) hdspm_hw_pointer(hdspm) * 4);
4925
4926         snd_iprintf(buffer,
4927                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4928                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4929                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4930                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4931                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4932         snd_iprintf(buffer,
4933                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4934                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4935                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4936         snd_iprintf(buffer,
4937                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4938                     "status2=0x%x\n",
4939                     hdspm->control_register, hdspm->control2_register,
4940                     status, status2);
4941
4942         snd_iprintf(buffer, "--- Settings ---\n");
4943
4944         x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4945                                 HDSPM_LatencyMask));
4946
4947         snd_iprintf(buffer,
4948                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4949                     x, (unsigned long) hdspm->period_bytes);
4950
4951         snd_iprintf(buffer, "Line out: %s\n",
4952                     (hdspm->
4953                      control_register & HDSPM_LineOut) ? "on " : "off");
4954
4955         snd_iprintf(buffer,
4956                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
4957                     (hdspm->
4958                      control_register & HDSPM_clr_tms) ? "on" : "off",
4959                     (hdspm->
4960                      control_register & HDSPM_Emphasis) ? "on" : "off",
4961                     (hdspm->
4962                      control_register & HDSPM_Dolby) ? "on" : "off");
4963
4964
4965         pref_syncref = hdspm_pref_sync_ref(hdspm);
4966         if (pref_syncref == 0)
4967                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
4968         else
4969                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
4970                                 pref_syncref);
4971
4972         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4973                     hdspm->system_sample_rate);
4974
4975         snd_iprintf(buffer, "Double speed: %s\n",
4976                         hdspm->control_register & HDSPM_DS_DoubleWire?
4977                         "Double wire" : "Single wire");
4978         snd_iprintf(buffer, "Quad speed: %s\n",
4979                         hdspm->control_register & HDSPM_QS_DoubleWire?
4980                         "Double wire" :
4981                         hdspm->control_register & HDSPM_QS_QuadWire?
4982                         "Quad wire" : "Single wire");
4983
4984         snd_iprintf(buffer, "--- Status:\n");
4985
4986         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
4987                     (status & HDSPM_AES32_wcLock) ? "Sync   " : "No Lock",
4988                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
4989
4990         for (x = 0; x < 8; x++) {
4991                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
4992                             x+1,
4993                             (status2 & (HDSPM_LockAES >> x)) ?
4994                             "Sync   " : "No Lock",
4995                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
4996         }
4997
4998         switch (hdspm_autosync_ref(hdspm)) {
4999         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5000                 autosync_ref = "None"; break;
5001         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5002                 autosync_ref = "Word Clock"; break;
5003         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5004                 autosync_ref = "AES1"; break;
5005         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5006                 autosync_ref = "AES2"; break;
5007         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5008                 autosync_ref = "AES3"; break;
5009         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5010                 autosync_ref = "AES4"; break;
5011         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5012                 autosync_ref = "AES5"; break;
5013         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5014                 autosync_ref = "AES6"; break;
5015         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5016                 autosync_ref = "AES7"; break;
5017         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5018                 autosync_ref = "AES8"; break;
5019         default:
5020                 autosync_ref = "---"; break;
5021         }
5022         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5023
5024         snd_iprintf(buffer, "\n");
5025 }
5026
5027 static void
5028 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5029                          struct snd_info_buffer *buffer)
5030 {
5031         struct hdspm *hdspm = entry->private_data;
5032         unsigned int status1, status2, status3, control, i;
5033         unsigned int lock, sync;
5034
5035         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5036         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5037         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5038
5039         control = hdspm->control_register;
5040
5041         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5042         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5043         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5044
5045
5046         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5047
5048         snd_iprintf(buffer, "Clock mode      : %s\n",
5049                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5050         snd_iprintf(buffer, "System frequency: %d Hz\n",
5051                 hdspm_get_system_sample_rate(hdspm));
5052
5053         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5054
5055         lock = 0x1;
5056         sync = 0x100;
5057
5058         for (i = 0; i < 8; i++) {
5059                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5060                                 i,
5061                                 (status1 & lock) ? 1 : 0,
5062                                 (status1 & sync) ? 1 : 0,
5063                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
5064
5065                 lock = lock<<1;
5066                 sync = sync<<1;
5067         }
5068
5069         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5070                         (status1 & 0x1000000) ? 1 : 0,
5071                         (status1 & 0x2000000) ? 1 : 0,
5072                         texts_freq[(status1 >> 16) & 0xF]);
5073
5074         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5075                         (status1 & 0x4000000) ? 1 : 0,
5076                         (status1 & 0x8000000) ? 1 : 0,
5077                         texts_freq[(status1 >> 20) & 0xF]);
5078
5079         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5080                         (status3 & 0x400) ? 1 : 0,
5081                         (status3 & 0x800) ? 1 : 0,
5082                         texts_freq[(status2 >> 12) & 0xF]);
5083
5084 }
5085
5086 #ifdef CONFIG_SND_DEBUG
5087 static void
5088 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5089                           struct snd_info_buffer *buffer)
5090 {
5091         struct hdspm *hdspm = entry->private_data;
5092
5093         int j,i;
5094
5095         for (i = 0; i < 256 /* 1024*64 */; i += j) {
5096                 snd_iprintf(buffer, "0x%08X: ", i);
5097                 for (j = 0; j < 16; j += 4)
5098                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5099                 snd_iprintf(buffer, "\n");
5100         }
5101 }
5102 #endif
5103
5104
5105 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5106                           struct snd_info_buffer *buffer)
5107 {
5108         struct hdspm *hdspm = entry->private_data;
5109         int i;
5110
5111         snd_iprintf(buffer, "# generated by hdspm\n");
5112
5113         for (i = 0; i < hdspm->max_channels_in; i++) {
5114                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5115         }
5116 }
5117
5118 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5119                           struct snd_info_buffer *buffer)
5120 {
5121         struct hdspm *hdspm = entry->private_data;
5122         int i;
5123
5124         snd_iprintf(buffer, "# generated by hdspm\n");
5125
5126         for (i = 0; i < hdspm->max_channels_out; i++) {
5127                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5128         }
5129 }
5130
5131
5132 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
5133 {
5134         struct snd_info_entry *entry;
5135
5136         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5137                 switch (hdspm->io_type) {
5138                 case AES32:
5139                         snd_info_set_text_ops(entry, hdspm,
5140                                         snd_hdspm_proc_read_aes32);
5141                         break;
5142                 case MADI:
5143                         snd_info_set_text_ops(entry, hdspm,
5144                                         snd_hdspm_proc_read_madi);
5145                         break;
5146                 case MADIface:
5147                         /* snd_info_set_text_ops(entry, hdspm,
5148                          snd_hdspm_proc_read_madiface); */
5149                         break;
5150                 case RayDAT:
5151                         snd_info_set_text_ops(entry, hdspm,
5152                                         snd_hdspm_proc_read_raydat);
5153                         break;
5154                 case AIO:
5155                         break;
5156                 }
5157         }
5158
5159         if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5160                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5161         }
5162
5163         if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5164                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5165         }
5166
5167 #ifdef CONFIG_SND_DEBUG
5168         /* debug file to read all hdspm registers */
5169         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5170                 snd_info_set_text_ops(entry, hdspm,
5171                                 snd_hdspm_proc_read_debug);
5172 #endif
5173 }
5174
5175 /*------------------------------------------------------------
5176    hdspm intitialize
5177  ------------------------------------------------------------*/
5178
5179 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5180 {
5181         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5182            hold it (e.g. during module initialization).
5183            */
5184
5185         /* set defaults:       */
5186
5187         hdspm->settings_register = 0;
5188
5189         switch (hdspm->io_type) {
5190         case MADI:
5191         case MADIface:
5192                 hdspm->control_register =
5193                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5194                 break;
5195
5196         case RayDAT:
5197         case AIO:
5198                 hdspm->settings_register = 0x1 + 0x1000;
5199                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5200                  * line_out */
5201                 hdspm->control_register =
5202                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5203                 break;
5204
5205         case AES32:
5206                 hdspm->control_register =
5207                         HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5208                         hdspm_encode_latency(7) | /* latency max=8192samples */
5209                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5210                         HDSPM_LineOut | /* Analog output in */
5211                         HDSPM_Professional;  /* Professional mode */
5212                 break;
5213         }
5214
5215         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5216
5217         if (AES32 == hdspm->io_type) {
5218                 /* No control2 register for AES32 */
5219 #ifdef SNDRV_BIG_ENDIAN
5220                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5221 #else
5222                 hdspm->control2_register = 0;
5223 #endif
5224
5225                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5226         }
5227         hdspm_compute_period_size(hdspm);
5228
5229         /* silence everything */
5230
5231         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5232
5233         if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5234                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5235         }
5236
5237         /* set a default rate so that the channel map is set up. */
5238         hdspm_set_rate(hdspm, 48000, 1);
5239
5240         return 0;
5241 }
5242
5243
5244 /*------------------------------------------------------------
5245    interrupt
5246  ------------------------------------------------------------*/
5247
5248 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5249 {
5250         struct hdspm *hdspm = (struct hdspm *) dev_id;
5251         unsigned int status;
5252         int i, audio, midi, schedule = 0;
5253         /* cycles_t now; */
5254
5255         status = hdspm_read(hdspm, HDSPM_statusRegister);
5256
5257         audio = status & HDSPM_audioIRQPending;
5258         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5259                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5260
5261         /* now = get_cycles(); */
5262         /**
5263          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5264          *          6       4096   ~256053425     ~514672358
5265          *          5       2048   ~128024983     ~257373821
5266          *          4       1024    ~64023706     ~128718089
5267          *          3        512    ~32005945      ~64385999
5268          *          2        256    ~16003039      ~32260176
5269          *          1        128     ~7998738      ~16194507
5270          *          0         64     ~3998231       ~8191558
5271          **/
5272         /*
5273            snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5274            now-hdspm->last_interrupt, status & 0xFFC0);
5275            hdspm->last_interrupt = now;
5276         */
5277
5278         if (!audio && !midi)
5279                 return IRQ_NONE;
5280
5281         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5282         hdspm->irq_count++;
5283
5284
5285         if (audio) {
5286                 if (hdspm->capture_substream)
5287                         snd_pcm_period_elapsed(hdspm->capture_substream);
5288
5289                 if (hdspm->playback_substream)
5290                         snd_pcm_period_elapsed(hdspm->playback_substream);
5291         }
5292
5293         if (midi) {
5294                 i = 0;
5295                 while (i < hdspm->midiPorts) {
5296                         if ((hdspm_read(hdspm,
5297                                 hdspm->midi[i].statusIn) & 0xff) &&
5298                                         (status & hdspm->midi[i].irq)) {
5299                                 /* we disable interrupts for this input until
5300                                  * processing is done
5301                                  */
5302                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5303                                 hdspm_write(hdspm, HDSPM_controlRegister,
5304                                                 hdspm->control_register);
5305                                 hdspm->midi[i].pending = 1;
5306                                 schedule = 1;
5307                         }
5308
5309                         i++;
5310                 }
5311
5312                 if (schedule)
5313                         tasklet_hi_schedule(&hdspm->midi_tasklet);
5314         }
5315
5316         return IRQ_HANDLED;
5317 }
5318
5319 /*------------------------------------------------------------
5320    pcm interface
5321   ------------------------------------------------------------*/
5322
5323
5324 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5325                                               *substream)
5326 {
5327         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5328         return hdspm_hw_pointer(hdspm);
5329 }
5330
5331
5332 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5333 {
5334         struct snd_pcm_runtime *runtime = substream->runtime;
5335         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5336         struct snd_pcm_substream *other;
5337
5338         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5339                 other = hdspm->capture_substream;
5340         else
5341                 other = hdspm->playback_substream;
5342
5343         if (hdspm->running)
5344                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5345         else
5346                 runtime->status->hw_ptr = 0;
5347         if (other) {
5348                 struct snd_pcm_substream *s;
5349                 struct snd_pcm_runtime *oruntime = other->runtime;
5350                 snd_pcm_group_for_each_entry(s, substream) {
5351                         if (s == other) {
5352                                 oruntime->status->hw_ptr =
5353                                         runtime->status->hw_ptr;
5354                                 break;
5355                         }
5356                 }
5357         }
5358         return 0;
5359 }
5360
5361 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5362                                struct snd_pcm_hw_params *params)
5363 {
5364         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5365         int err;
5366         int i;
5367         pid_t this_pid;
5368         pid_t other_pid;
5369
5370         spin_lock_irq(&hdspm->lock);
5371
5372         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5373                 this_pid = hdspm->playback_pid;
5374                 other_pid = hdspm->capture_pid;
5375         } else {
5376                 this_pid = hdspm->capture_pid;
5377                 other_pid = hdspm->playback_pid;
5378         }
5379
5380         if (other_pid > 0 && this_pid != other_pid) {
5381
5382                 /* The other stream is open, and not by the same
5383                    task as this one. Make sure that the parameters
5384                    that matter are the same.
5385                    */
5386
5387                 if (params_rate(params) != hdspm->system_sample_rate) {
5388                         spin_unlock_irq(&hdspm->lock);
5389                         _snd_pcm_hw_param_setempty(params,
5390                                         SNDRV_PCM_HW_PARAM_RATE);
5391                         return -EBUSY;
5392                 }
5393
5394                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5395                         spin_unlock_irq(&hdspm->lock);
5396                         _snd_pcm_hw_param_setempty(params,
5397                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5398                         return -EBUSY;
5399                 }
5400
5401         }
5402         /* We're fine. */
5403         spin_unlock_irq(&hdspm->lock);
5404
5405         /* how to make sure that the rate matches an externally-set one ?   */
5406
5407         spin_lock_irq(&hdspm->lock);
5408         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5409         if (err < 0) {
5410                 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5411                 spin_unlock_irq(&hdspm->lock);
5412                 _snd_pcm_hw_param_setempty(params,
5413                                 SNDRV_PCM_HW_PARAM_RATE);
5414                 return err;
5415         }
5416         spin_unlock_irq(&hdspm->lock);
5417
5418         err = hdspm_set_interrupt_interval(hdspm,
5419                         params_period_size(params));
5420         if (err < 0) {
5421                 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5422                 _snd_pcm_hw_param_setempty(params,
5423                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5424                 return err;
5425         }
5426
5427         /* Memory allocation, takashi's method, dont know if we should
5428          * spinlock
5429          */
5430         /* malloc all buffer even if not enabled to get sure */
5431         /* Update for MADI rev 204: we need to allocate for all channels,
5432          * otherwise it doesn't work at 96kHz */
5433
5434         err =
5435                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5436         if (err < 0) {
5437                 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5438                 return err;
5439         }
5440
5441         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5442
5443                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5444                                 params_channels(params));
5445
5446                 for (i = 0; i < params_channels(params); ++i)
5447                         snd_hdspm_enable_out(hdspm, i, 1);
5448
5449                 hdspm->playback_buffer =
5450                         (unsigned char *) substream->runtime->dma_area;
5451                 snd_printdd("Allocated sample buffer for playback at %p\n",
5452                                 hdspm->playback_buffer);
5453         } else {
5454                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5455                                 params_channels(params));
5456
5457                 for (i = 0; i < params_channels(params); ++i)
5458                         snd_hdspm_enable_in(hdspm, i, 1);
5459
5460                 hdspm->capture_buffer =
5461                         (unsigned char *) substream->runtime->dma_area;
5462                 snd_printdd("Allocated sample buffer for capture at %p\n",
5463                                 hdspm->capture_buffer);
5464         }
5465
5466         /*
5467            snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5468            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5469            "playback" : "capture",
5470            snd_pcm_sgbuf_get_addr(substream, 0));
5471            */
5472         /*
5473            snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5474            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5475            "playback" : "capture",
5476            params_rate(params), params_channels(params),
5477            params_buffer_size(params));
5478            */
5479
5480
5481         /* Switch to native float format if requested */
5482         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5483                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5484                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5485
5486                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5487         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5488                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5489                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5490
5491                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5492         }
5493         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5494
5495         return 0;
5496 }
5497
5498 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5499 {
5500         int i;
5501         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5502
5503         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5504
5505                 /* params_channels(params) should be enough,
5506                    but to get sure in case of error */
5507                 for (i = 0; i < hdspm->max_channels_out; ++i)
5508                         snd_hdspm_enable_out(hdspm, i, 0);
5509
5510                 hdspm->playback_buffer = NULL;
5511         } else {
5512                 for (i = 0; i < hdspm->max_channels_in; ++i)
5513                         snd_hdspm_enable_in(hdspm, i, 0);
5514
5515                 hdspm->capture_buffer = NULL;
5516
5517         }
5518
5519         snd_pcm_lib_free_pages(substream);
5520
5521         return 0;
5522 }
5523
5524
5525 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5526                 struct snd_pcm_channel_info *info)
5527 {
5528         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5529
5530         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5531                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5532                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5533                         return -EINVAL;
5534                 }
5535
5536                 if (hdspm->channel_map_out[info->channel] < 0) {
5537                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5538                         return -EINVAL;
5539                 }
5540
5541                 info->offset = hdspm->channel_map_out[info->channel] *
5542                         HDSPM_CHANNEL_BUFFER_BYTES;
5543         } else {
5544                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5545                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5546                         return -EINVAL;
5547                 }
5548
5549                 if (hdspm->channel_map_in[info->channel] < 0) {
5550                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5551                         return -EINVAL;
5552                 }
5553
5554                 info->offset = hdspm->channel_map_in[info->channel] *
5555                         HDSPM_CHANNEL_BUFFER_BYTES;
5556         }
5557
5558         info->first = 0;
5559         info->step = 32;
5560         return 0;
5561 }
5562
5563
5564 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5565                 unsigned int cmd, void *arg)
5566 {
5567         switch (cmd) {
5568         case SNDRV_PCM_IOCTL1_RESET:
5569                 return snd_hdspm_reset(substream);
5570
5571         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5572                 {
5573                         struct snd_pcm_channel_info *info = arg;
5574                         return snd_hdspm_channel_info(substream, info);
5575                 }
5576         default:
5577                 break;
5578         }
5579
5580         return snd_pcm_lib_ioctl(substream, cmd, arg);
5581 }
5582
5583 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5584 {
5585         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5586         struct snd_pcm_substream *other;
5587         int running;
5588
5589         spin_lock(&hdspm->lock);
5590         running = hdspm->running;
5591         switch (cmd) {
5592         case SNDRV_PCM_TRIGGER_START:
5593                 running |= 1 << substream->stream;
5594                 break;
5595         case SNDRV_PCM_TRIGGER_STOP:
5596                 running &= ~(1 << substream->stream);
5597                 break;
5598         default:
5599                 snd_BUG();
5600                 spin_unlock(&hdspm->lock);
5601                 return -EINVAL;
5602         }
5603         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5604                 other = hdspm->capture_substream;
5605         else
5606                 other = hdspm->playback_substream;
5607
5608         if (other) {
5609                 struct snd_pcm_substream *s;
5610                 snd_pcm_group_for_each_entry(s, substream) {
5611                         if (s == other) {
5612                                 snd_pcm_trigger_done(s, substream);
5613                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5614                                         running |= 1 << s->stream;
5615                                 else
5616                                         running &= ~(1 << s->stream);
5617                                 goto _ok;
5618                         }
5619                 }
5620                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5621                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5622                                         && substream->stream ==
5623                                         SNDRV_PCM_STREAM_CAPTURE)
5624                                 hdspm_silence_playback(hdspm);
5625                 } else {
5626                         if (running &&
5627                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5628                                 hdspm_silence_playback(hdspm);
5629                 }
5630         } else {
5631                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5632                         hdspm_silence_playback(hdspm);
5633         }
5634 _ok:
5635         snd_pcm_trigger_done(substream, substream);
5636         if (!hdspm->running && running)
5637                 hdspm_start_audio(hdspm);
5638         else if (hdspm->running && !running)
5639                 hdspm_stop_audio(hdspm);
5640         hdspm->running = running;
5641         spin_unlock(&hdspm->lock);
5642
5643         return 0;
5644 }
5645
5646 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5647 {
5648         return 0;
5649 }
5650
5651 static unsigned int period_sizes_old[] = {
5652         64, 128, 256, 512, 1024, 2048, 4096
5653 };
5654
5655 static unsigned int period_sizes_new[] = {
5656         32, 64, 128, 256, 512, 1024, 2048, 4096
5657 };
5658
5659 /* RayDAT and AIO always have a buffer of 16384 samples per channel */
5660 static unsigned int raydat_aio_buffer_sizes[] = {
5661         16384
5662 };
5663
5664 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5665         .info = (SNDRV_PCM_INFO_MMAP |
5666                  SNDRV_PCM_INFO_MMAP_VALID |
5667                  SNDRV_PCM_INFO_NONINTERLEAVED |
5668                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5669         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5670         .rates = (SNDRV_PCM_RATE_32000 |
5671                   SNDRV_PCM_RATE_44100 |
5672                   SNDRV_PCM_RATE_48000 |
5673                   SNDRV_PCM_RATE_64000 |
5674                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5675                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5676         .rate_min = 32000,
5677         .rate_max = 192000,
5678         .channels_min = 1,
5679         .channels_max = HDSPM_MAX_CHANNELS,
5680         .buffer_bytes_max =
5681             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5682         .period_bytes_min = (64 * 4),
5683         .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5684         .periods_min = 2,
5685         .periods_max = 512,
5686         .fifo_size = 0
5687 };
5688
5689 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5690         .info = (SNDRV_PCM_INFO_MMAP |
5691                  SNDRV_PCM_INFO_MMAP_VALID |
5692                  SNDRV_PCM_INFO_NONINTERLEAVED |
5693                  SNDRV_PCM_INFO_SYNC_START),
5694         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5695         .rates = (SNDRV_PCM_RATE_32000 |
5696                   SNDRV_PCM_RATE_44100 |
5697                   SNDRV_PCM_RATE_48000 |
5698                   SNDRV_PCM_RATE_64000 |
5699                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5700                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5701         .rate_min = 32000,
5702         .rate_max = 192000,
5703         .channels_min = 1,
5704         .channels_max = HDSPM_MAX_CHANNELS,
5705         .buffer_bytes_max =
5706             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5707         .period_bytes_min = (64 * 4),
5708         .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5709         .periods_min = 2,
5710         .periods_max = 512,
5711         .fifo_size = 0
5712 };
5713
5714 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_old = {
5715         .count = ARRAY_SIZE(period_sizes_old),
5716         .list = period_sizes_old,
5717         .mask = 0
5718 };
5719
5720 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_new = {
5721         .count = ARRAY_SIZE(period_sizes_new),
5722         .list = period_sizes_new,
5723         .mask = 0
5724 };
5725
5726 static struct snd_pcm_hw_constraint_list hw_constraints_raydat_io_buffer = {
5727         .count = ARRAY_SIZE(raydat_aio_buffer_sizes),
5728         .list = raydat_aio_buffer_sizes,
5729         .mask = 0
5730 };
5731
5732 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5733                                            struct snd_pcm_hw_rule *rule)
5734 {
5735         struct hdspm *hdspm = rule->private;
5736         struct snd_interval *c =
5737             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5738         struct snd_interval *r =
5739             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5740
5741         if (r->min > 96000 && r->max <= 192000) {
5742                 struct snd_interval t = {
5743                         .min = hdspm->qs_in_channels,
5744                         .max = hdspm->qs_in_channels,
5745                         .integer = 1,
5746                 };
5747                 return snd_interval_refine(c, &t);
5748         } else if (r->min > 48000 && r->max <= 96000) {
5749                 struct snd_interval t = {
5750                         .min = hdspm->ds_in_channels,
5751                         .max = hdspm->ds_in_channels,
5752                         .integer = 1,
5753                 };
5754                 return snd_interval_refine(c, &t);
5755         } else if (r->max < 64000) {
5756                 struct snd_interval t = {
5757                         .min = hdspm->ss_in_channels,
5758                         .max = hdspm->ss_in_channels,
5759                         .integer = 1,
5760                 };
5761                 return snd_interval_refine(c, &t);
5762         }
5763
5764         return 0;
5765 }
5766
5767 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5768                                            struct snd_pcm_hw_rule * rule)
5769 {
5770         struct hdspm *hdspm = rule->private;
5771         struct snd_interval *c =
5772             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5773         struct snd_interval *r =
5774             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5775
5776         if (r->min > 96000 && r->max <= 192000) {
5777                 struct snd_interval t = {
5778                         .min = hdspm->qs_out_channels,
5779                         .max = hdspm->qs_out_channels,
5780                         .integer = 1,
5781                 };
5782                 return snd_interval_refine(c, &t);
5783         } else if (r->min > 48000 && r->max <= 96000) {
5784                 struct snd_interval t = {
5785                         .min = hdspm->ds_out_channels,
5786                         .max = hdspm->ds_out_channels,
5787                         .integer = 1,
5788                 };
5789                 return snd_interval_refine(c, &t);
5790         } else if (r->max < 64000) {
5791                 struct snd_interval t = {
5792                         .min = hdspm->ss_out_channels,
5793                         .max = hdspm->ss_out_channels,
5794                         .integer = 1,
5795                 };
5796                 return snd_interval_refine(c, &t);
5797         } else {
5798         }
5799         return 0;
5800 }
5801
5802 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5803                                            struct snd_pcm_hw_rule * rule)
5804 {
5805         struct hdspm *hdspm = rule->private;
5806         struct snd_interval *c =
5807             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5808         struct snd_interval *r =
5809             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5810
5811         if (c->min >= hdspm->ss_in_channels) {
5812                 struct snd_interval t = {
5813                         .min = 32000,
5814                         .max = 48000,
5815                         .integer = 1,
5816                 };
5817                 return snd_interval_refine(r, &t);
5818         } else if (c->max <= hdspm->qs_in_channels) {
5819                 struct snd_interval t = {
5820                         .min = 128000,
5821                         .max = 192000,
5822                         .integer = 1,
5823                 };
5824                 return snd_interval_refine(r, &t);
5825         } else if (c->max <= hdspm->ds_in_channels) {
5826                 struct snd_interval t = {
5827                         .min = 64000,
5828                         .max = 96000,
5829                         .integer = 1,
5830                 };
5831                 return snd_interval_refine(r, &t);
5832         }
5833
5834         return 0;
5835 }
5836 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5837                                            struct snd_pcm_hw_rule *rule)
5838 {
5839         struct hdspm *hdspm = rule->private;
5840         struct snd_interval *c =
5841             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5842         struct snd_interval *r =
5843             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5844
5845         if (c->min >= hdspm->ss_out_channels) {
5846                 struct snd_interval t = {
5847                         .min = 32000,
5848                         .max = 48000,
5849                         .integer = 1,
5850                 };
5851                 return snd_interval_refine(r, &t);
5852         } else if (c->max <= hdspm->qs_out_channels) {
5853                 struct snd_interval t = {
5854                         .min = 128000,
5855                         .max = 192000,
5856                         .integer = 1,
5857                 };
5858                 return snd_interval_refine(r, &t);
5859         } else if (c->max <= hdspm->ds_out_channels) {
5860                 struct snd_interval t = {
5861                         .min = 64000,
5862                         .max = 96000,
5863                         .integer = 1,
5864                 };
5865                 return snd_interval_refine(r, &t);
5866         }
5867
5868         return 0;
5869 }
5870
5871 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5872                                       struct snd_pcm_hw_rule *rule)
5873 {
5874         unsigned int list[3];
5875         struct hdspm *hdspm = rule->private;
5876         struct snd_interval *c = hw_param_interval(params,
5877                         SNDRV_PCM_HW_PARAM_CHANNELS);
5878
5879         list[0] = hdspm->qs_in_channels;
5880         list[1] = hdspm->ds_in_channels;
5881         list[2] = hdspm->ss_in_channels;
5882         return snd_interval_list(c, 3, list, 0);
5883 }
5884
5885 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5886                                       struct snd_pcm_hw_rule *rule)
5887 {
5888         unsigned int list[3];
5889         struct hdspm *hdspm = rule->private;
5890         struct snd_interval *c = hw_param_interval(params,
5891                         SNDRV_PCM_HW_PARAM_CHANNELS);
5892
5893         list[0] = hdspm->qs_out_channels;
5894         list[1] = hdspm->ds_out_channels;
5895         list[2] = hdspm->ss_out_channels;
5896         return snd_interval_list(c, 3, list, 0);
5897 }
5898
5899
5900 static unsigned int hdspm_aes32_sample_rates[] = {
5901         32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5902 };
5903
5904 static struct snd_pcm_hw_constraint_list
5905 hdspm_hw_constraints_aes32_sample_rates = {
5906         .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5907         .list = hdspm_aes32_sample_rates,
5908         .mask = 0
5909 };
5910
5911 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5912 {
5913         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5914         struct snd_pcm_runtime *runtime = substream->runtime;
5915
5916         spin_lock_irq(&hdspm->lock);
5917
5918         snd_pcm_set_sync(substream);
5919
5920
5921         runtime->hw = snd_hdspm_playback_subinfo;
5922
5923         if (hdspm->capture_substream == NULL)
5924                 hdspm_stop_audio(hdspm);
5925
5926         hdspm->playback_pid = current->pid;
5927         hdspm->playback_substream = substream;
5928
5929         spin_unlock_irq(&hdspm->lock);
5930
5931         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5932
5933         switch (hdspm->io_type) {
5934         case AIO:
5935         case RayDAT:
5936                 snd_pcm_hw_constraint_list(runtime, 0,
5937                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5938                                 &hw_constraints_period_sizes_new);
5939                 snd_pcm_hw_constraint_list(runtime, 0,
5940                                 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5941                                 &hw_constraints_raydat_io_buffer);
5942
5943                 break;
5944
5945         default:
5946                 snd_pcm_hw_constraint_list(runtime, 0,
5947                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5948                                 &hw_constraints_period_sizes_old);
5949         }
5950
5951         if (AES32 == hdspm->io_type) {
5952                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5953                                 &hdspm_hw_constraints_aes32_sample_rates);
5954         } else {
5955                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5956                                 snd_hdspm_hw_rule_rate_out_channels, hdspm,
5957                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5958         }
5959
5960         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5961                         snd_hdspm_hw_rule_out_channels, hdspm,
5962                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5963
5964         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5965                         snd_hdspm_hw_rule_out_channels_rate, hdspm,
5966                         SNDRV_PCM_HW_PARAM_RATE, -1);
5967
5968         return 0;
5969 }
5970
5971 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
5972 {
5973         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5974
5975         spin_lock_irq(&hdspm->lock);
5976
5977         hdspm->playback_pid = -1;
5978         hdspm->playback_substream = NULL;
5979
5980         spin_unlock_irq(&hdspm->lock);
5981
5982         return 0;
5983 }
5984
5985
5986 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
5987 {
5988         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5989         struct snd_pcm_runtime *runtime = substream->runtime;
5990
5991         spin_lock_irq(&hdspm->lock);
5992         snd_pcm_set_sync(substream);
5993         runtime->hw = snd_hdspm_capture_subinfo;
5994
5995         if (hdspm->playback_substream == NULL)
5996                 hdspm_stop_audio(hdspm);
5997
5998         hdspm->capture_pid = current->pid;
5999         hdspm->capture_substream = substream;
6000
6001         spin_unlock_irq(&hdspm->lock);
6002
6003         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6004         switch (hdspm->io_type) {
6005         case AIO:
6006         case RayDAT:
6007           snd_pcm_hw_constraint_list(runtime, 0,
6008                                      SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6009                                      &hw_constraints_period_sizes_new);
6010           snd_pcm_hw_constraint_list(runtime, 0,
6011                                      SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6012                                      &hw_constraints_raydat_io_buffer);
6013           break;
6014
6015         default:
6016           snd_pcm_hw_constraint_list(runtime, 0,
6017                                      SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6018                                      &hw_constraints_period_sizes_old);
6019         }
6020
6021         if (AES32 == hdspm->io_type) {
6022                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6023                                 &hdspm_hw_constraints_aes32_sample_rates);
6024         } else {
6025                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6026                                 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6027                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6028         }
6029
6030         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6031                         snd_hdspm_hw_rule_in_channels, hdspm,
6032                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6033
6034         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6035                         snd_hdspm_hw_rule_in_channels_rate, hdspm,
6036                         SNDRV_PCM_HW_PARAM_RATE, -1);
6037
6038         return 0;
6039 }
6040
6041 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6042 {
6043         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6044
6045         spin_lock_irq(&hdspm->lock);
6046
6047         hdspm->capture_pid = -1;
6048         hdspm->capture_substream = NULL;
6049
6050         spin_unlock_irq(&hdspm->lock);
6051         return 0;
6052 }
6053
6054 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6055 {
6056         /* we have nothing to initialize but the call is required */
6057         return 0;
6058 }
6059
6060 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6061 {
6062         u32 val = readl(src);
6063         return copy_to_user(dest, &val, 4);
6064 }
6065
6066 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6067                 unsigned int cmd, unsigned long __user arg)
6068 {
6069         void __user *argp = (void __user *)arg;
6070         struct hdspm *hdspm = hw->private_data;
6071         struct hdspm_mixer_ioctl mixer;
6072         struct hdspm_config info;
6073         struct hdspm_status status;
6074         struct hdspm_version hdspm_version;
6075         struct hdspm_peak_rms *levels;
6076         struct hdspm_ltc ltc;
6077         unsigned int statusregister;
6078         long unsigned int s;
6079         int i = 0;
6080
6081         switch (cmd) {
6082
6083         case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6084                 levels = &hdspm->peak_rms;
6085                 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6086                         levels->input_peaks[i] =
6087                                 readl(hdspm->iobase +
6088                                                 HDSPM_MADI_INPUT_PEAK + i*4);
6089                         levels->playback_peaks[i] =
6090                                 readl(hdspm->iobase +
6091                                                 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6092                         levels->output_peaks[i] =
6093                                 readl(hdspm->iobase +
6094                                                 HDSPM_MADI_OUTPUT_PEAK + i*4);
6095
6096                         levels->input_rms[i] =
6097                                 ((uint64_t) readl(hdspm->iobase +
6098                                         HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6099                                 (uint64_t) readl(hdspm->iobase +
6100                                                 HDSPM_MADI_INPUT_RMS_L + i*4);
6101                         levels->playback_rms[i] =
6102                                 ((uint64_t)readl(hdspm->iobase +
6103                                         HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6104                                 (uint64_t)readl(hdspm->iobase +
6105                                         HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6106                         levels->output_rms[i] =
6107                                 ((uint64_t)readl(hdspm->iobase +
6108                                         HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6109                                 (uint64_t)readl(hdspm->iobase +
6110                                                 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6111                 }
6112
6113                 if (hdspm->system_sample_rate > 96000) {
6114                         levels->speed = qs;
6115                 } else if (hdspm->system_sample_rate > 48000) {
6116                         levels->speed = ds;
6117                 } else {
6118                         levels->speed = ss;
6119                 }
6120                 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6121
6122                 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6123                 if (0 != s) {
6124                         /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6125                          [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6126                          */
6127                         return -EFAULT;
6128                 }
6129                 break;
6130
6131         case SNDRV_HDSPM_IOCTL_GET_LTC:
6132                 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6133                 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6134                 if (i & HDSPM_TCO1_LTC_Input_valid) {
6135                         switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6136                                 HDSPM_TCO1_LTC_Format_MSB)) {
6137                         case 0:
6138                                 ltc.format = fps_24;
6139                                 break;
6140                         case HDSPM_TCO1_LTC_Format_LSB:
6141                                 ltc.format = fps_25;
6142                                 break;
6143                         case HDSPM_TCO1_LTC_Format_MSB:
6144                                 ltc.format = fps_2997;
6145                                 break;
6146                         default:
6147                                 ltc.format = 30;
6148                                 break;
6149                         }
6150                         if (i & HDSPM_TCO1_set_drop_frame_flag) {
6151                                 ltc.frame = drop_frame;
6152                         } else {
6153                                 ltc.frame = full_frame;
6154                         }
6155                 } else {
6156                         ltc.format = format_invalid;
6157                         ltc.frame = frame_invalid;
6158                 }
6159                 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6160                         ltc.input_format = ntsc;
6161                 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6162                         ltc.input_format = pal;
6163                 } else {
6164                         ltc.input_format = no_video;
6165                 }
6166
6167                 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6168                 if (0 != s) {
6169                         /*
6170                          snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6171                         return -EFAULT;
6172                 }
6173
6174                 break;
6175
6176         case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6177
6178                 memset(&info, 0, sizeof(info));
6179                 spin_lock_irq(&hdspm->lock);
6180                 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6181                 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6182
6183                 info.system_sample_rate = hdspm->system_sample_rate;
6184                 info.autosync_sample_rate =
6185                         hdspm_external_sample_rate(hdspm);
6186                 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6187                 info.clock_source = hdspm_clock_source(hdspm);
6188                 info.autosync_ref = hdspm_autosync_ref(hdspm);
6189                 info.line_out = hdspm_line_out(hdspm);
6190                 info.passthru = 0;
6191                 spin_unlock_irq(&hdspm->lock);
6192                 if (copy_to_user((void __user *) arg, &info, sizeof(info)))
6193                         return -EFAULT;
6194                 break;
6195
6196         case SNDRV_HDSPM_IOCTL_GET_STATUS:
6197                 status.card_type = hdspm->io_type;
6198
6199                 status.autosync_source = hdspm_autosync_ref(hdspm);
6200
6201                 status.card_clock = 110069313433624ULL;
6202                 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6203
6204                 switch (hdspm->io_type) {
6205                 case MADI:
6206                 case MADIface:
6207                         status.card_specific.madi.sync_wc =
6208                                 hdspm_wc_sync_check(hdspm);
6209                         status.card_specific.madi.sync_madi =
6210                                 hdspm_madi_sync_check(hdspm);
6211                         status.card_specific.madi.sync_tco =
6212                                 hdspm_tco_sync_check(hdspm);
6213                         status.card_specific.madi.sync_in =
6214                                 hdspm_sync_in_sync_check(hdspm);
6215
6216                         statusregister =
6217                                 hdspm_read(hdspm, HDSPM_statusRegister);
6218                         status.card_specific.madi.madi_input =
6219                                 (statusregister & HDSPM_AB_int) ? 1 : 0;
6220                         status.card_specific.madi.channel_format =
6221                                 (statusregister & HDSPM_TX_64ch) ? 1 : 0;
6222                         /* TODO: Mac driver sets it when f_s>48kHz */
6223                         status.card_specific.madi.frame_format = 0;
6224
6225                 default:
6226                         break;
6227                 }
6228
6229                 if (copy_to_user((void __user *) arg, &status, sizeof(status)))
6230                         return -EFAULT;
6231
6232
6233                 break;
6234
6235         case SNDRV_HDSPM_IOCTL_GET_VERSION:
6236                 hdspm_version.card_type = hdspm->io_type;
6237                 strncpy(hdspm_version.cardname, hdspm->card_name,
6238                                 sizeof(hdspm_version.cardname));
6239                 hdspm_version.serial = (hdspm_read(hdspm,
6240                                         HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6241                 hdspm_version.firmware_rev = hdspm->firmware_rev;
6242                 hdspm_version.addons = 0;
6243                 if (hdspm->tco)
6244                         hdspm_version.addons |= HDSPM_ADDON_TCO;
6245
6246                 if (copy_to_user((void __user *) arg, &hdspm_version,
6247                                         sizeof(hdspm_version)))
6248                         return -EFAULT;
6249                 break;
6250
6251         case SNDRV_HDSPM_IOCTL_GET_MIXER:
6252                 if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer)))
6253                         return -EFAULT;
6254                 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6255                                         sizeof(struct hdspm_mixer)))
6256                         return -EFAULT;
6257                 break;
6258
6259         default:
6260                 return -EINVAL;
6261         }
6262         return 0;
6263 }
6264
6265 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6266         .open = snd_hdspm_playback_open,
6267         .close = snd_hdspm_playback_release,
6268         .ioctl = snd_hdspm_ioctl,
6269         .hw_params = snd_hdspm_hw_params,
6270         .hw_free = snd_hdspm_hw_free,
6271         .prepare = snd_hdspm_prepare,
6272         .trigger = snd_hdspm_trigger,
6273         .pointer = snd_hdspm_hw_pointer,
6274         .page = snd_pcm_sgbuf_ops_page,
6275 };
6276
6277 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6278         .open = snd_hdspm_capture_open,
6279         .close = snd_hdspm_capture_release,
6280         .ioctl = snd_hdspm_ioctl,
6281         .hw_params = snd_hdspm_hw_params,
6282         .hw_free = snd_hdspm_hw_free,
6283         .prepare = snd_hdspm_prepare,
6284         .trigger = snd_hdspm_trigger,
6285         .pointer = snd_hdspm_hw_pointer,
6286         .page = snd_pcm_sgbuf_ops_page,
6287 };
6288
6289 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
6290                                             struct hdspm * hdspm)
6291 {
6292         struct snd_hwdep *hw;
6293         int err;
6294
6295         err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6296         if (err < 0)
6297                 return err;
6298
6299         hdspm->hwdep = hw;
6300         hw->private_data = hdspm;
6301         strcpy(hw->name, "HDSPM hwdep interface");
6302
6303         hw->ops.open = snd_hdspm_hwdep_dummy_op;
6304         hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6305         hw->ops.release = snd_hdspm_hwdep_dummy_op;
6306
6307         return 0;
6308 }
6309
6310
6311 /*------------------------------------------------------------
6312    memory interface
6313  ------------------------------------------------------------*/
6314 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6315 {
6316         int err;
6317         struct snd_pcm *pcm;
6318         size_t wanted;
6319
6320         pcm = hdspm->pcm;
6321
6322         wanted = HDSPM_DMA_AREA_BYTES;
6323
6324         err =
6325              snd_pcm_lib_preallocate_pages_for_all(pcm,
6326                                                    SNDRV_DMA_TYPE_DEV_SG,
6327                                                    snd_dma_pci_data(hdspm->pci),
6328                                                    wanted,
6329                                                    wanted);
6330         if (err < 0) {
6331                 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6332
6333                 return err;
6334         } else
6335                 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6336
6337         return 0;
6338 }
6339
6340
6341 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6342                             struct snd_pcm_substream *substream,
6343                              unsigned int reg, int channels)
6344 {
6345         int i;
6346
6347         /* continuous memory segment */
6348         for (i = 0; i < (channels * 16); i++)
6349                 hdspm_write(hdspm, reg + 4 * i,
6350                                 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6351 }
6352
6353
6354 /* ------------- ALSA Devices ---------------------------- */
6355 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
6356                                           struct hdspm *hdspm)
6357 {
6358         struct snd_pcm *pcm;
6359         int err;
6360
6361         err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6362         if (err < 0)
6363                 return err;
6364
6365         hdspm->pcm = pcm;
6366         pcm->private_data = hdspm;
6367         strcpy(pcm->name, hdspm->card_name);
6368
6369         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6370                         &snd_hdspm_playback_ops);
6371         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6372                         &snd_hdspm_capture_ops);
6373
6374         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6375
6376         err = snd_hdspm_preallocate_memory(hdspm);
6377         if (err < 0)
6378                 return err;
6379
6380         return 0;
6381 }
6382
6383 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6384 {
6385         int i;
6386
6387         for (i = 0; i < hdspm->midiPorts; i++)
6388                 snd_hdspm_flush_midi_input(hdspm, i);
6389 }
6390
6391 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
6392                                                    struct hdspm * hdspm)
6393 {
6394         int err, i;
6395
6396         snd_printdd("Create card...\n");
6397         err = snd_hdspm_create_pcm(card, hdspm);
6398         if (err < 0)
6399                 return err;
6400
6401         i = 0;
6402         while (i < hdspm->midiPorts) {
6403                 err = snd_hdspm_create_midi(card, hdspm, i);
6404                 if (err < 0) {
6405                         return err;
6406                 }
6407                 i++;
6408         }
6409
6410         err = snd_hdspm_create_controls(card, hdspm);
6411         if (err < 0)
6412                 return err;
6413
6414         err = snd_hdspm_create_hwdep(card, hdspm);
6415         if (err < 0)
6416                 return err;
6417
6418         snd_printdd("proc init...\n");
6419         snd_hdspm_proc_init(hdspm);
6420
6421         hdspm->system_sample_rate = -1;
6422         hdspm->last_external_sample_rate = -1;
6423         hdspm->last_internal_sample_rate = -1;
6424         hdspm->playback_pid = -1;
6425         hdspm->capture_pid = -1;
6426         hdspm->capture_substream = NULL;
6427         hdspm->playback_substream = NULL;
6428
6429         snd_printdd("Set defaults...\n");
6430         err = snd_hdspm_set_defaults(hdspm);
6431         if (err < 0)
6432                 return err;
6433
6434         snd_printdd("Update mixer controls...\n");
6435         hdspm_update_simple_mixer_controls(hdspm);
6436
6437         snd_printdd("Initializeing complete ???\n");
6438
6439         err = snd_card_register(card);
6440         if (err < 0) {
6441                 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6442                 return err;
6443         }
6444
6445         snd_printdd("... yes now\n");
6446
6447         return 0;
6448 }
6449
6450 static int __devinit snd_hdspm_create(struct snd_card *card,
6451                 struct hdspm *hdspm) {
6452
6453         struct pci_dev *pci = hdspm->pci;
6454         int err;
6455         unsigned long io_extent;
6456
6457         hdspm->irq = -1;
6458         hdspm->card = card;
6459
6460         spin_lock_init(&hdspm->lock);
6461
6462         pci_read_config_word(hdspm->pci,
6463                         PCI_CLASS_REVISION, &hdspm->firmware_rev);
6464
6465         strcpy(card->mixername, "Xilinx FPGA");
6466         strcpy(card->driver, "HDSPM");
6467
6468         switch (hdspm->firmware_rev) {
6469         case HDSPM_MADI_REV:
6470         case HDSPM_MADI_OLD_REV:
6471                 hdspm->io_type = MADI;
6472                 hdspm->card_name = "RME MADI";
6473                 hdspm->midiPorts = 3;
6474                 break;
6475         case HDSPM_RAYDAT_REV:
6476                 hdspm->io_type = RayDAT;
6477                 hdspm->card_name = "RME RayDAT";
6478                 hdspm->midiPorts = 2;
6479                 break;
6480         case HDSPM_AIO_REV:
6481                 hdspm->io_type = AIO;
6482                 hdspm->card_name = "RME AIO";
6483                 hdspm->midiPorts = 1;
6484                 break;
6485         case HDSPM_MADIFACE_REV:
6486                 hdspm->io_type = MADIface;
6487                 hdspm->card_name = "RME MADIface";
6488                 hdspm->midiPorts = 1;
6489                 break;
6490         case HDSPM_AES_REV:
6491         case HDSPM_AES32_REV:
6492         case HDSPM_AES32_OLD_REV:
6493                 hdspm->io_type = AES32;
6494                 hdspm->card_name = "RME AES32";
6495                 hdspm->midiPorts = 2;
6496                 break;
6497         default:
6498                 snd_printk(KERN_ERR "HDSPM: unknown firmware revision %x\n",
6499                                 hdspm->firmware_rev);
6500                 return -ENODEV;
6501         }
6502
6503         err = pci_enable_device(pci);
6504         if (err < 0)
6505                 return err;
6506
6507         pci_set_master(hdspm->pci);
6508
6509         err = pci_request_regions(pci, "hdspm");
6510         if (err < 0)
6511                 return err;
6512
6513         hdspm->port = pci_resource_start(pci, 0);
6514         io_extent = pci_resource_len(pci, 0);
6515
6516         snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6517                         hdspm->port, hdspm->port + io_extent - 1);
6518
6519         hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6520         if (!hdspm->iobase) {
6521                 snd_printk(KERN_ERR "HDSPM: "
6522                                 "unable to remap region 0x%lx-0x%lx\n",
6523                                 hdspm->port, hdspm->port + io_extent - 1);
6524                 return -EBUSY;
6525         }
6526         snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6527                         (unsigned long)hdspm->iobase, hdspm->port,
6528                         hdspm->port + io_extent - 1);
6529
6530         if (request_irq(pci->irq, snd_hdspm_interrupt,
6531                         IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6532                 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6533                 return -EBUSY;
6534         }
6535
6536         snd_printdd("use IRQ %d\n", pci->irq);
6537
6538         hdspm->irq = pci->irq;
6539
6540         snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6541                         sizeof(struct hdspm_mixer));
6542         hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6543         if (!hdspm->mixer) {
6544                 snd_printk(KERN_ERR "HDSPM: "
6545                                 "unable to kmalloc Mixer memory of %d Bytes\n",
6546                                 (int)sizeof(struct hdspm_mixer));
6547                 return err;
6548         }
6549
6550         hdspm->port_names_in = NULL;
6551         hdspm->port_names_out = NULL;
6552
6553         switch (hdspm->io_type) {
6554         case AES32:
6555                 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6556                 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6557                 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6558
6559                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6560                         channel_map_aes32;
6561                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6562                         channel_map_aes32;
6563                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6564                         channel_map_aes32;
6565                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6566                         texts_ports_aes32;
6567                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6568                         texts_ports_aes32;
6569                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6570                         texts_ports_aes32;
6571
6572                 hdspm->max_channels_out = hdspm->max_channels_in =
6573                         AES32_CHANNELS;
6574                 hdspm->port_names_in = hdspm->port_names_out =
6575                         texts_ports_aes32;
6576                 hdspm->channel_map_in = hdspm->channel_map_out =
6577                         channel_map_aes32;
6578
6579                 break;
6580
6581         case MADI:
6582         case MADIface:
6583                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6584                         MADI_SS_CHANNELS;
6585                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6586                         MADI_DS_CHANNELS;
6587                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6588                         MADI_QS_CHANNELS;
6589
6590                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6591                         channel_map_unity_ss;
6592                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6593                         channel_map_unity_ss;
6594                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6595                         channel_map_unity_ss;
6596
6597                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6598                         texts_ports_madi;
6599                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6600                         texts_ports_madi;
6601                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6602                         texts_ports_madi;
6603                 break;
6604
6605         case AIO:
6606                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6607                         snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6608                 }
6609
6610                 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6611                 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6612                 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6613                 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6614                 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6615                 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6616
6617                 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6618                 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6619                 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6620
6621                 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6622                 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6623                 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6624
6625                 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6626                 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6627                 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6628                 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6629                 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6630                 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6631
6632                 break;
6633
6634         case RayDAT:
6635                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6636                         RAYDAT_SS_CHANNELS;
6637                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6638                         RAYDAT_DS_CHANNELS;
6639                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6640                         RAYDAT_QS_CHANNELS;
6641
6642                 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6643                 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6644
6645                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6646                         channel_map_raydat_ss;
6647                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6648                         channel_map_raydat_ds;
6649                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6650                         channel_map_raydat_qs;
6651                 hdspm->channel_map_in = hdspm->channel_map_out =
6652                         channel_map_raydat_ss;
6653
6654                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6655                         texts_ports_raydat_ss;
6656                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6657                         texts_ports_raydat_ds;
6658                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6659                         texts_ports_raydat_qs;
6660
6661
6662                 break;
6663
6664         }
6665
6666         /* TCO detection */
6667         switch (hdspm->io_type) {
6668         case AIO:
6669         case RayDAT:
6670                 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6671                                 HDSPM_s2_tco_detect) {
6672                         hdspm->midiPorts++;
6673                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6674                                         GFP_KERNEL);
6675                         if (NULL != hdspm->tco) {
6676                                 hdspm_tco_write(hdspm);
6677                         }
6678                         snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6679                 } else {
6680                         hdspm->tco = NULL;
6681                 }
6682                 break;
6683
6684         case MADI:
6685                 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6686                         hdspm->midiPorts++;
6687                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6688                                         GFP_KERNEL);
6689                         if (NULL != hdspm->tco) {
6690                                 hdspm_tco_write(hdspm);
6691                         }
6692                         snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6693                 } else {
6694                         hdspm->tco = NULL;
6695                 }
6696                 break;
6697
6698         default:
6699                 hdspm->tco = NULL;
6700         }
6701
6702         /* texts */
6703         switch (hdspm->io_type) {
6704         case AES32:
6705                 if (hdspm->tco) {
6706                         hdspm->texts_autosync = texts_autosync_aes_tco;
6707                         hdspm->texts_autosync_items = 10;
6708                 } else {
6709                         hdspm->texts_autosync = texts_autosync_aes;
6710                         hdspm->texts_autosync_items = 9;
6711                 }
6712                 break;
6713
6714         case MADI:
6715                 if (hdspm->tco) {
6716                         hdspm->texts_autosync = texts_autosync_madi_tco;
6717                         hdspm->texts_autosync_items = 4;
6718                 } else {
6719                         hdspm->texts_autosync = texts_autosync_madi;
6720                         hdspm->texts_autosync_items = 3;
6721                 }
6722                 break;
6723
6724         case MADIface:
6725
6726                 break;
6727
6728         case RayDAT:
6729                 if (hdspm->tco) {
6730                         hdspm->texts_autosync = texts_autosync_raydat_tco;
6731                         hdspm->texts_autosync_items = 9;
6732                 } else {
6733                         hdspm->texts_autosync = texts_autosync_raydat;
6734                         hdspm->texts_autosync_items = 8;
6735                 }
6736                 break;
6737
6738         case AIO:
6739                 if (hdspm->tco) {
6740                         hdspm->texts_autosync = texts_autosync_aio_tco;
6741                         hdspm->texts_autosync_items = 6;
6742                 } else {
6743                         hdspm->texts_autosync = texts_autosync_aio;
6744                         hdspm->texts_autosync_items = 5;
6745                 }
6746                 break;
6747
6748         }
6749
6750         tasklet_init(&hdspm->midi_tasklet,
6751                         hdspm_midi_tasklet, (unsigned long) hdspm);
6752
6753         snd_printdd("create alsa devices.\n");
6754         err = snd_hdspm_create_alsa_devices(card, hdspm);
6755         if (err < 0)
6756                 return err;
6757
6758         snd_hdspm_initialize_midi_flush(hdspm);
6759
6760         return 0;
6761 }
6762
6763
6764 static int snd_hdspm_free(struct hdspm * hdspm)
6765 {
6766
6767         if (hdspm->port) {
6768
6769                 /* stop th audio, and cancel all interrupts */
6770                 hdspm->control_register &=
6771                     ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6772                       HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6773                       HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6774                 hdspm_write(hdspm, HDSPM_controlRegister,
6775                             hdspm->control_register);
6776         }
6777
6778         if (hdspm->irq >= 0)
6779                 free_irq(hdspm->irq, (void *) hdspm);
6780
6781         kfree(hdspm->mixer);
6782
6783         if (hdspm->iobase)
6784                 iounmap(hdspm->iobase);
6785
6786         if (hdspm->port)
6787                 pci_release_regions(hdspm->pci);
6788
6789         pci_disable_device(hdspm->pci);
6790         return 0;
6791 }
6792
6793
6794 static void snd_hdspm_card_free(struct snd_card *card)
6795 {
6796         struct hdspm *hdspm = card->private_data;
6797
6798         if (hdspm)
6799                 snd_hdspm_free(hdspm);
6800 }
6801
6802
6803 static int __devinit snd_hdspm_probe(struct pci_dev *pci,
6804                                      const struct pci_device_id *pci_id)
6805 {
6806         static int dev;
6807         struct hdspm *hdspm;
6808         struct snd_card *card;
6809         int err;
6810
6811         if (dev >= SNDRV_CARDS)
6812                 return -ENODEV;
6813         if (!enable[dev]) {
6814                 dev++;
6815                 return -ENOENT;
6816         }
6817
6818         err = snd_card_create(index[dev], id[dev],
6819                         THIS_MODULE, sizeof(struct hdspm), &card);
6820         if (err < 0)
6821                 return err;
6822
6823         hdspm = card->private_data;
6824         card->private_free = snd_hdspm_card_free;
6825         hdspm->dev = dev;
6826         hdspm->pci = pci;
6827
6828         snd_card_set_dev(card, &pci->dev);
6829
6830         err = snd_hdspm_create(card, hdspm);
6831         if (err < 0) {
6832                 snd_card_free(card);
6833                 return err;
6834         }
6835
6836         if (hdspm->io_type != MADIface) {
6837                 sprintf(card->shortname, "%s_%x",
6838                         hdspm->card_name,
6839                         (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
6840                 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6841                         hdspm->card_name,
6842                         (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF,
6843                         hdspm->port, hdspm->irq);
6844         } else {
6845                 sprintf(card->shortname, "%s", hdspm->card_name);
6846                 sprintf(card->longname, "%s at 0x%lx, irq %d",
6847                                 hdspm->card_name, hdspm->port, hdspm->irq);
6848         }
6849
6850         err = snd_card_register(card);
6851         if (err < 0) {
6852                 snd_card_free(card);
6853                 return err;
6854         }
6855
6856         pci_set_drvdata(pci, card);
6857
6858         dev++;
6859         return 0;
6860 }
6861
6862 static void __devexit snd_hdspm_remove(struct pci_dev *pci)
6863 {
6864         snd_card_free(pci_get_drvdata(pci));
6865         pci_set_drvdata(pci, NULL);
6866 }
6867
6868 static struct pci_driver driver = {
6869         .name = KBUILD_MODNAME,
6870         .id_table = snd_hdspm_ids,
6871         .probe = snd_hdspm_probe,
6872         .remove = __devexit_p(snd_hdspm_remove),
6873 };
6874
6875
6876 static int __init alsa_card_hdspm_init(void)
6877 {
6878         return pci_register_driver(&driver);
6879 }
6880
6881 static void __exit alsa_card_hdspm_exit(void)
6882 {
6883         pci_unregister_driver(&driver);
6884 }
6885
6886 module_init(alsa_card_hdspm_init)
6887 module_exit(alsa_card_hdspm_exit)