sound/pci/rme9652/hdspm.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
   3  *
   4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
   5  *      code based on hdsp.c   Paul Davis
   6  *                             Marcus Andersson
   7  *                             Thomas Charbonnel
   8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
   9  *                                               <remy.bruno@trinnov.com>
  10  *
  11  *      Modified 2009-04-13 for proper metering by Florian Faber
  12  *                                               <faber@faberman.de>
  13  *
  14  *      Modified 2009-04-14 for native float support by Florian Faber
  15  *                                               <faber@faberman.de>
  16  *
  17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
  18  *                                               <faber@faberman.de>
  19  *
  20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
  21  *
  22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
  23  *
  24  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
  25  *
  26  *   This program is free software; you can redistribute it and/or modify
  27  *   it under the terms of the GNU General Public License as published by
  28  *   the Free Software Foundation; either version 2 of the License, or
  29  *   (at your option) any later version.
  30  *
  31  *   This program is distributed in the hope that it will be useful,
  32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  34  *   GNU General Public License for more details.
  35  *
  36  *   You should have received a copy of the GNU General Public License
  37  *   along with this program; if not, write to the Free Software
  38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  39  *
  40  */
  41 #include <linux/init.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/module.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/math64.h>
  48 #include <asm/io.h>
  49
  50 #include <sound/core.h>
  51 #include <sound/control.h>
  52 #include <sound/pcm.h>
  53 #include <sound/pcm_params.h>
  54 #include <sound/info.h>
  55 #include <sound/asoundef.h>
  56 #include <sound/rawmidi.h>
  57 #include <sound/hwdep.h>
  58 #include <sound/initval.h>
  59
  60 #include <sound/hdspm.h>
  61
  62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
  63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
  64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  65
  66 module_param_array(index, int, NULL, 0444);
  67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
  68
  69 module_param_array(id, charp, NULL, 0444);
  70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
  71
  72 module_param_array(enable, bool, NULL, 0444);
  73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
  74
  75
  76 MODULE_AUTHOR
  77 (
  78         "Winfried Ritsch <ritsch_AT_iem.at>, "
  79         "Paul Davis <paul@linuxaudiosystems.com>, "
  80         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
  81         "Remy Bruno <remy.bruno@trinnov.com>, "
  82         "Florian Faber <faberman@linuxproaudio.org>, "
  83         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
  84 );
  85 MODULE_DESCRIPTION("RME HDSPM");
  86 MODULE_LICENSE("GPL");
  87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
  88
  89 /* --- Write registers. ---
  90   These are defined as byte-offsets from the iobase value.  */
  91
  92 #define HDSPM_WR_SETTINGS             0
  93 #define HDSPM_outputBufferAddress    32
  94 #define HDSPM_inputBufferAddress     36
  95 #define HDSPM_controlRegister        64
  96 #define HDSPM_interruptConfirmation  96
  97 #define HDSPM_control2Reg            256  /* not in specs ???????? */
  98 #define HDSPM_freqReg                256  /* for AES32 */
  99 #define HDSPM_midiDataOut0           352  /* just believe in old code */
 100 #define HDSPM_midiDataOut1           356
 101 #define HDSPM_eeprom_wr              384  /* for AES32 */
 102
 103 /* DMA enable for 64 channels, only Bit 0 is relevant */
 104 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
 105 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
 106
 107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
 108    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
 109 #define HDSPM_pageAddressBufferOut       8192
 110 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
 111
 112 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
 113
 114 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
 115
 116 /* --- Read registers. ---
 117    These are defined as byte-offsets from the iobase value */
 118 #define HDSPM_statusRegister    0
 119 /*#define HDSPM_statusRegister2  96 */
 120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
 121  * offset 192, for AES32 *and* MADI
 122  * => need to check that offset 192 is working on MADI */
 123 #define HDSPM_statusRegister2  192
 124 #define HDSPM_timecodeRegister 128
 125
 126 /* AIO, RayDAT */
 127 #define HDSPM_RD_STATUS_0 0
 128 #define HDSPM_RD_STATUS_1 64
 129 #define HDSPM_RD_STATUS_2 128
 130 #define HDSPM_RD_STATUS_3 192
 131
 132 #define HDSPM_RD_TCO           256
 133 #define HDSPM_RD_PLL_FREQ      512
 134 #define HDSPM_WR_TCO           128
 135
 136 #define HDSPM_TCO1_TCO_lock                     0x00000001
 137 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
 138 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
 139 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
 140 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
 141 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
 142 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
 143
 144 #define HDSPM_TCO1_set_TC                       0x00000100
 145 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
 146 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
 147 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
 148
 149 #define HDSPM_TCO2_TC_run                       0x00010000
 150 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
 151 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
 152 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
 153 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
 154 #define HDSPM_TCO2_set_jam_sync                 0x00200000
 155 #define HDSPM_TCO2_set_flywheel                 0x00400000
 156
 157 #define HDSPM_TCO2_set_01_4                     0x01000000
 158 #define HDSPM_TCO2_set_pull_down                0x02000000
 159 #define HDSPM_TCO2_set_pull_up                  0x04000000
 160 #define HDSPM_TCO2_set_freq                     0x08000000
 161 #define HDSPM_TCO2_set_term_75R                 0x10000000
 162 #define HDSPM_TCO2_set_input_LSB                0x20000000
 163 #define HDSPM_TCO2_set_input_MSB                0x40000000
 164 #define HDSPM_TCO2_set_freq_from_app            0x80000000
 165
 166
 167 #define HDSPM_midiDataOut0    352
 168 #define HDSPM_midiDataOut1    356
 169 #define HDSPM_midiDataOut2    368
 170
 171 #define HDSPM_midiDataIn0     360
 172 #define HDSPM_midiDataIn1     364
 173 #define HDSPM_midiDataIn2     372
 174 #define HDSPM_midiDataIn3     376
 175
 176 /* status is data bytes in MIDI-FIFO (0-128) */
 177 #define HDSPM_midiStatusOut0  384
 178 #define HDSPM_midiStatusOut1  388
 179 #define HDSPM_midiStatusOut2  400
 180
 181 #define HDSPM_midiStatusIn0   392
 182 #define HDSPM_midiStatusIn1   396
 183 #define HDSPM_midiStatusIn2   404
 184 #define HDSPM_midiStatusIn3   408
 185
 186
 187 /* the meters are regular i/o-mapped registers, but offset
 188    considerably from the rest. the peak registers are reset
 189    when read; the least-significant 4 bits are full-scale counters;
 190    the actual peak value is in the most-significant 24 bits.
 191 */
 192
 193 #define HDSPM_MADI_INPUT_PEAK           4096
 194 #define HDSPM_MADI_PLAYBACK_PEAK        4352
 195 #define HDSPM_MADI_OUTPUT_PEAK          4608
 196
 197 #define HDSPM_MADI_INPUT_RMS_L          6144
 198 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
 199 #define HDSPM_MADI_OUTPUT_RMS_L         6656
 200
 201 #define HDSPM_MADI_INPUT_RMS_H          7168
 202 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
 203 #define HDSPM_MADI_OUTPUT_RMS_H         7680
 204
 205 /* --- Control Register bits --------- */
 206 #define HDSPM_Start                (1<<0) /* start engine */
 207
 208 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
 209 #define HDSPM_Latency1             (1<<2) /* where n is defined */
 210 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
 211
 212 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
 213 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
 214                                           register [RayDAT, AIO] */
 215
 216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
 217
 218 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
 219 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
 220 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
 221 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
 222
 223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
 224 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
 225                                      56channelMODE=0 */ /* MADI ONLY*/
 226 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
 227
 228 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
 229                                      0=off, 1=on  */ /* MADI ONLY */
 230 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
 231
 232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
 233                                     * -- MADI ONLY
 234                                     */
 235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
 236
 237 #define HDSPM_SyncRef2     (1<<13)
 238 #define HDSPM_SyncRef3     (1<<25)
 239
 240 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
 241 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
 242                                       AES additional bits in
 243                                       lower 5 Audiodatabits ??? */
 244 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
 245 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
 246
 247 #define HDSPM_Midi0InterruptEnable 0x0400000
 248 #define HDSPM_Midi1InterruptEnable 0x0800000
 249 #define HDSPM_Midi2InterruptEnable 0x0200000
 250 #define HDSPM_Midi3InterruptEnable 0x4000000
 251
 252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
 253 #define HDSPe_FLOAT_FORMAT         0x2000000
 254
 255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
 256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
 257 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
 258
 259 #define HDSPM_wclk_sel (1<<30)
 260
 261 /* additional control register bits for AIO*/
 262 #define HDSPM_c0_Wck48                          0x20 /* also RayDAT */
 263 #define HDSPM_c0_Input0                         0x1000
 264 #define HDSPM_c0_Input1                         0x2000
 265 #define HDSPM_c0_Spdif_Opt                      0x4000
 266 #define HDSPM_c0_Pro                            0x8000
 267 #define HDSPM_c0_clr_tms                        0x10000
 268 #define HDSPM_c0_AEB1                           0x20000
 269 #define HDSPM_c0_AEB2                           0x40000
 270 #define HDSPM_c0_LineOut                        0x80000
 271 #define HDSPM_c0_AD_GAIN0                       0x100000
 272 #define HDSPM_c0_AD_GAIN1                       0x200000
 273 #define HDSPM_c0_DA_GAIN0                       0x400000
 274 #define HDSPM_c0_DA_GAIN1                       0x800000
 275 #define HDSPM_c0_PH_GAIN0                       0x1000000
 276 #define HDSPM_c0_PH_GAIN1                       0x2000000
 277 #define HDSPM_c0_Sym6db                         0x4000000
 278
 279
 280 /* --- bit helper defines */
 281 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
 282 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
 283                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
 284 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
 285 #define HDSPM_InputOptical   0
 286 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
 287 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
 288                               HDSPM_SyncRef2|HDSPM_SyncRef3)
 289
 290 #define HDSPM_c0_SyncRef0      0x2
 291 #define HDSPM_c0_SyncRef1      0x4
 292 #define HDSPM_c0_SyncRef2      0x8
 293 #define HDSPM_c0_SyncRef3      0x10
 294 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
 295                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
 296
 297 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
 298 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
 299 #define HDSPM_SYNC_FROM_TCO     2
 300 #define HDSPM_SYNC_FROM_SYNC_IN 3
 301
 302 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
 303 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
 304 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
 305 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
 306 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
 307 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
 308                                 HDSPM_Frequency0)
 309 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
 310 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
 311 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
 312                                  HDSPM_Frequency0)
 313
 314
 315 /* Synccheck Status */
 316 #define HDSPM_SYNC_CHECK_NO_LOCK 0
 317 #define HDSPM_SYNC_CHECK_LOCK    1
 318 #define HDSPM_SYNC_CHECK_SYNC    2
 319
 320 /* AutoSync References - used by "autosync_ref" control switch */
 321 #define HDSPM_AUTOSYNC_FROM_WORD      0
 322 #define HDSPM_AUTOSYNC_FROM_MADI      1
 323 #define HDSPM_AUTOSYNC_FROM_TCO       2
 324 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
 325 #define HDSPM_AUTOSYNC_FROM_NONE      4
 326
 327 /* Possible sources of MADI input */
 328 #define HDSPM_OPTICAL 0         /* optical   */
 329 #define HDSPM_COAXIAL 1         /* BNC */
 330
 331 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
 332 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
 333
 334 #define hdspm_encode_in(x) (((x)&0x3)<<14)
 335 #define hdspm_decode_in(x) (((x)>>14)&0x3)
 336
 337 /* --- control2 register bits --- */
 338 #define HDSPM_TMS             (1<<0)
 339 #define HDSPM_TCK             (1<<1)
 340 #define HDSPM_TDI             (1<<2)
 341 #define HDSPM_JTAG            (1<<3)
 342 #define HDSPM_PWDN            (1<<4)
 343 #define HDSPM_PROGRAM         (1<<5)
 344 #define HDSPM_CONFIG_MODE_0   (1<<6)
 345 #define HDSPM_CONFIG_MODE_1   (1<<7)
 346 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
 347 #define HDSPM_BIGENDIAN_MODE  (1<<9)
 348 #define HDSPM_RD_MULTIPLE     (1<<10)
 349
 350 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
 351      that do not conflict with specific bits for AES32 seem to be valid also
 352      for the AES32
 353  */
 354 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
 355 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
 356 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
 357                                          * (like inp0)
 358                                          */
 359
 360 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
 361 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
 362
 363 #define HDSPM_tcoLock    0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
 364 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status */
 365
 366 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
 367 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
 368
 369 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 370                         /* since 64byte accurate, last 6 bits are not used */
 371
 372
 373
 374 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
 375
 376 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
 377 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
 378 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
 379 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
 380
 381 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
 382                                          * Interrupt
 383                                          */
 384 #define HDSPM_tco_detect         0x08000000
 385 #define HDSPM_tco_lock           0x20000000
 386
 387 #define HDSPM_s2_tco_detect      0x00000040
 388 #define HDSPM_s2_AEBO_D          0x00000080
 389 #define HDSPM_s2_AEBI_D          0x00000100
 390
 391
 392 #define HDSPM_midi0IRQPending    0x40000000
 393 #define HDSPM_midi1IRQPending    0x80000000
 394 #define HDSPM_midi2IRQPending    0x20000000
 395 #define HDSPM_midi2IRQPendingAES 0x00000020
 396 #define HDSPM_midi3IRQPending    0x00200000
 397
 398 /* --- status bit helpers */
 399 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
 400                              HDSPM_madiFreq2|HDSPM_madiFreq3)
 401 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
 402 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
 403 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
 404 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
 405 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
 406 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
 407 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
 408 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
 409 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
 410
 411 /* Status2 Register bits */ /* MADI ONLY */
 412
 413 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
 414 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
 415 #define HDSPM_version2 (1<<2)
 416
 417 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
 418 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
 419
 420 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
 421 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
 422 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, 111=128 */
 423 #define HDSPM_wc_freq3 0x800    /* 1000=176.4, 1001=192 */
 424
 425 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
 426 #define HDSPM_SyncRef1 0x20000
 427
 428 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
 429 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
 430 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
 431
 432 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
 433
 434 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
 435                             HDSPM_wc_freq3)
 436 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
 437 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
 438 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
 439 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
 440 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
 441 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
 442 #define HDSPM_wcFreq128   (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
 443 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
 444 #define HDSPM_wcFreq192   (HDSPM_wc_freq0|HDSPM_wc_freq3)
 445
 446 #define HDSPM_status1_F_0 0x0400000
 447 #define HDSPM_status1_F_1 0x0800000
 448 #define HDSPM_status1_F_2 0x1000000
 449 #define HDSPM_status1_F_3 0x2000000
 450 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
 451
 452
 453 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 454                                     HDSPM_SelSyncRef2)
 455 #define HDSPM_SelSyncRef_WORD      0
 456 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
 457 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
 458 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
 459 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 460                                     HDSPM_SelSyncRef2)
 461
 462 /*
 463    For AES32, bits for status, status2 and timecode are different
 464 */
 465 /* status */
 466 #define HDSPM_AES32_wcLock      0x0200000
 467 #define HDSPM_AES32_wcSync      0x0100000
 468 #define HDSPM_AES32_wcFreq_bit  22
 469 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
 470   HDSPM_bit2freq */
 471 #define HDSPM_AES32_syncref_bit  16
 472 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
 473
 474 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
 475 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
 476 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
 477 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
 478 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
 479 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
 480 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
 481 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
 482 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
 483 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
 484
 485 /*  status2 */
 486 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
 487 #define HDSPM_LockAES   0x80
 488 #define HDSPM_LockAES1  0x80
 489 #define HDSPM_LockAES2  0x40
 490 #define HDSPM_LockAES3  0x20
 491 #define HDSPM_LockAES4  0x10
 492 #define HDSPM_LockAES5  0x8
 493 #define HDSPM_LockAES6  0x4
 494 #define HDSPM_LockAES7  0x2
 495 #define HDSPM_LockAES8  0x1
 496 /*
 497    Timecode
 498    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
 499    AES i+1
 500  bits 3210
 501       0001  32kHz
 502       0010  44.1kHz
 503       0011  48kHz
 504       0100  64kHz
 505       0101  88.2kHz
 506       0110  96kHz
 507       0111  128kHz
 508       1000  176.4kHz
 509       1001  192kHz
 510   NB: Timecode register doesn't seem to work on AES32 card revision 230
 511 */
 512
 513 /* Mixer Values */
 514 #define UNITY_GAIN          32768       /* = 65536/2 */
 515 #define MINUS_INFINITY_GAIN 0
 516
 517 /* Number of channels for different Speed Modes */
 518 #define MADI_SS_CHANNELS       64
 519 #define MADI_DS_CHANNELS       32
 520 #define MADI_QS_CHANNELS       16
 521
 522 #define RAYDAT_SS_CHANNELS     36
 523 #define RAYDAT_DS_CHANNELS     20
 524 #define RAYDAT_QS_CHANNELS     12
 525
 526 #define AIO_IN_SS_CHANNELS        14
 527 #define AIO_IN_DS_CHANNELS        10
 528 #define AIO_IN_QS_CHANNELS        8
 529 #define AIO_OUT_SS_CHANNELS        16
 530 #define AIO_OUT_DS_CHANNELS        12
 531 #define AIO_OUT_QS_CHANNELS        10
 532
 533 #define AES32_CHANNELS          16
 534
 535 /* the size of a substream (1 mono data stream) */
 536 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
 537 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
 538
 539 /* the size of the area we need to allocate for DMA transfers. the
 540    size is the same regardless of the number of channels, and
 541    also the latency to use.
 542    for one direction !!!
 543 */
 544 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
 545 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
 546
 547 #define HDSPM_RAYDAT_REV        211
 548 #define HDSPM_AIO_REV           212
 549 #define HDSPM_MADIFACE_REV      213
 550
 551 /* speed factor modes */
 552 #define HDSPM_SPEED_SINGLE 0
 553 #define HDSPM_SPEED_DOUBLE 1
 554 #define HDSPM_SPEED_QUAD   2
 555
 556 /* names for speed modes */
 557 static char *hdspm_speed_names[] = { "single", "double", "quad" };
 558
 559 static char *texts_autosync_aes_tco[] = { "Word Clock",
 560                                           "AES1", "AES2", "AES3", "AES4",
 561                                           "AES5", "AES6", "AES7", "AES8",
 562                                           "TCO" };
 563 static char *texts_autosync_aes[] = { "Word Clock",
 564                                       "AES1", "AES2", "AES3", "AES4",
 565                                       "AES5", "AES6", "AES7", "AES8" };
 566 static char *texts_autosync_madi_tco[] = { "Word Clock",
 567                                            "MADI", "TCO", "Sync In" };
 568 static char *texts_autosync_madi[] = { "Word Clock",
 569                                        "MADI", "Sync In" };
 570
 571 static char *texts_autosync_raydat_tco[] = {
 572         "Word Clock",
 573         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 574         "AES", "SPDIF", "TCO", "Sync In"
 575 };
 576 static char *texts_autosync_raydat[] = {
 577         "Word Clock",
 578         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 579         "AES", "SPDIF", "Sync In"
 580 };
 581 static char *texts_autosync_aio_tco[] = {
 582         "Word Clock",
 583         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
 584 };
 585 static char *texts_autosync_aio[] = { "Word Clock",
 586                                       "ADAT", "AES", "SPDIF", "Sync In" };
 587
 588 static char *texts_freq[] = {
 589         "No Lock",
 590         "32 kHz",
 591         "44.1 kHz",
 592         "48 kHz",
 593         "64 kHz",
 594         "88.2 kHz",
 595         "96 kHz",
 596         "128 kHz",
 597         "176.4 kHz",
 598         "192 kHz"
 599 };
 600
 601 static char *texts_ports_madi[] = {
 602         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
 603         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
 604         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
 605         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
 606         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
 607         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
 608         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
 609         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
 610         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
 611         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
 612         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
 613 };
 614
 615
 616 static char *texts_ports_raydat_ss[] = {
 617         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
 618         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 619         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
 620         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
 621         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
 622         "ADAT4.7", "ADAT4.8",
 623         "AES.L", "AES.R",
 624         "SPDIF.L", "SPDIF.R"
 625 };
 626
 627 static char *texts_ports_raydat_ds[] = {
 628         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
 629         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 630         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
 631         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
 632         "AES.L", "AES.R",
 633         "SPDIF.L", "SPDIF.R"
 634 };
 635
 636 static char *texts_ports_raydat_qs[] = {
 637         "ADAT1.1", "ADAT1.2",
 638         "ADAT2.1", "ADAT2.2",
 639         "ADAT3.1", "ADAT3.2",
 640         "ADAT4.1", "ADAT4.2",
 641         "AES.L", "AES.R",
 642         "SPDIF.L", "SPDIF.R"
 643 };
 644
 645
 646 static char *texts_ports_aio_in_ss[] = {
 647         "Analogue.L", "Analogue.R",
 648         "AES.L", "AES.R",
 649         "SPDIF.L", "SPDIF.R",
 650         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 651         "ADAT.7", "ADAT.8"
 652 };
 653
 654 static char *texts_ports_aio_out_ss[] = {
 655         "Analogue.L", "Analogue.R",
 656         "AES.L", "AES.R",
 657         "SPDIF.L", "SPDIF.R",
 658         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 659         "ADAT.7", "ADAT.8",
 660         "Phone.L", "Phone.R"
 661 };
 662
 663 static char *texts_ports_aio_in_ds[] = {
 664         "Analogue.L", "Analogue.R",
 665         "AES.L", "AES.R",
 666         "SPDIF.L", "SPDIF.R",
 667         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
 668 };
 669
 670 static char *texts_ports_aio_out_ds[] = {
 671         "Analogue.L", "Analogue.R",
 672         "AES.L", "AES.R",
 673         "SPDIF.L", "SPDIF.R",
 674         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 675         "Phone.L", "Phone.R"
 676 };
 677
 678 static char *texts_ports_aio_in_qs[] = {
 679         "Analogue.L", "Analogue.R",
 680         "AES.L", "AES.R",
 681         "SPDIF.L", "SPDIF.R",
 682         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
 683 };
 684
 685 static char *texts_ports_aio_out_qs[] = {
 686         "Analogue.L", "Analogue.R",
 687         "AES.L", "AES.R",
 688         "SPDIF.L", "SPDIF.R",
 689         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 690         "Phone.L", "Phone.R"
 691 };
 692
 693 static char *texts_ports_aes32[] = {
 694         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
 695         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
 696         "AES.15", "AES.16"
 697 };
 698
 699 /* These tables map the ALSA channels 1..N to the channels that we
 700    need to use in order to find the relevant channel buffer. RME
 701    refers to this kind of mapping as between "the ADAT channel and
 702    the DMA channel." We index it using the logical audio channel,
 703    and the value is the DMA channel (i.e. channel buffer number)
 704    where the data for that channel can be read/written from/to.
 705 */
 706
 707 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
 708         0, 1, 2, 3, 4, 5, 6, 7,
 709         8, 9, 10, 11, 12, 13, 14, 15,
 710         16, 17, 18, 19, 20, 21, 22, 23,
 711         24, 25, 26, 27, 28, 29, 30, 31,
 712         32, 33, 34, 35, 36, 37, 38, 39,
 713         40, 41, 42, 43, 44, 45, 46, 47,
 714         48, 49, 50, 51, 52, 53, 54, 55,
 715         56, 57, 58, 59, 60, 61, 62, 63
 716 };
 717
 718 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
 719         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
 720         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
 721         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
 722         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
 723         0, 1,                   /* AES */
 724         2, 3,                   /* SPDIF */
 725         -1, -1, -1, -1,
 726         -1, -1, -1, -1, -1, -1, -1, -1,
 727         -1, -1, -1, -1, -1, -1, -1, -1,
 728         -1, -1, -1, -1, -1, -1, -1, -1,
 729 };
 730
 731 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
 732         4, 5, 6, 7,             /* ADAT 1 */
 733         8, 9, 10, 11,           /* ADAT 2 */
 734         12, 13, 14, 15,         /* ADAT 3 */
 735         16, 17, 18, 19,         /* ADAT 4 */
 736         0, 1,                   /* AES */
 737         2, 3,                   /* SPDIF */
 738         -1, -1, -1, -1,
 739         -1, -1, -1, -1, -1, -1, -1, -1,
 740         -1, -1, -1, -1, -1, -1, -1, -1,
 741         -1, -1, -1, -1, -1, -1, -1, -1,
 742         -1, -1, -1, -1, -1, -1, -1, -1,
 743         -1, -1, -1, -1, -1, -1, -1, -1,
 744 };
 745
 746 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
 747         4, 5,                   /* ADAT 1 */
 748         6, 7,                   /* ADAT 2 */
 749         8, 9,                   /* ADAT 3 */
 750         10, 11,                 /* ADAT 4 */
 751         0, 1,                   /* AES */
 752         2, 3,                   /* SPDIF */
 753         -1, -1, -1, -1,
 754         -1, -1, -1, -1, -1, -1, -1, -1,
 755         -1, -1, -1, -1, -1, -1, -1, -1,
 756         -1, -1, -1, -1, -1, -1, -1, -1,
 757         -1, -1, -1, -1, -1, -1, -1, -1,
 758         -1, -1, -1, -1, -1, -1, -1, -1,
 759         -1, -1, -1, -1, -1, -1, -1, -1,
 760 };
 761
 762 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
 763         0, 1,                   /* line in */
 764         8, 9,                   /* aes in, */
 765         10, 11,                 /* spdif in */
 766         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
 767         -1, -1,
 768         -1, -1, -1, -1, -1, -1, -1, -1,
 769         -1, -1, -1, -1, -1, -1, -1, -1,
 770         -1, -1, -1, -1, -1, -1, -1, -1,
 771         -1, -1, -1, -1, -1, -1, -1, -1,
 772         -1, -1, -1, -1, -1, -1, -1, -1,
 773         -1, -1, -1, -1, -1, -1, -1, -1,
 774 };
 775
 776 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
 777         0, 1,                   /* line out */
 778         8, 9,                   /* aes out */
 779         10, 11,                 /* spdif out */
 780         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
 781         6, 7,                   /* phone out */
 782         -1, -1, -1, -1, -1, -1, -1, -1,
 783         -1, -1, -1, -1, -1, -1, -1, -1,
 784         -1, -1, -1, -1, -1, -1, -1, -1,
 785         -1, -1, -1, -1, -1, -1, -1, -1,
 786         -1, -1, -1, -1, -1, -1, -1, -1,
 787         -1, -1, -1, -1, -1, -1, -1, -1,
 788 };
 789
 790 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
 791         0, 1,                   /* line in */
 792         8, 9,                   /* aes in */
 793         10, 11,                 /* spdif in */
 794         12, 14, 16, 18,         /* adat in */
 795         -1, -1, -1, -1, -1, -1,
 796         -1, -1, -1, -1, -1, -1, -1, -1,
 797         -1, -1, -1, -1, -1, -1, -1, -1,
 798         -1, -1, -1, -1, -1, -1, -1, -1,
 799         -1, -1, -1, -1, -1, -1, -1, -1,
 800         -1, -1, -1, -1, -1, -1, -1, -1,
 801         -1, -1, -1, -1, -1, -1, -1, -1
 802 };
 803
 804 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
 805         0, 1,                   /* line out */
 806         8, 9,                   /* aes out */
 807         10, 11,                 /* spdif out */
 808         12, 14, 16, 18,         /* adat out */
 809         6, 7,                   /* phone out */
 810         -1, -1, -1, -1,
 811         -1, -1, -1, -1, -1, -1, -1, -1,
 812         -1, -1, -1, -1, -1, -1, -1, -1,
 813         -1, -1, -1, -1, -1, -1, -1, -1,
 814         -1, -1, -1, -1, -1, -1, -1, -1,
 815         -1, -1, -1, -1, -1, -1, -1, -1,
 816         -1, -1, -1, -1, -1, -1, -1, -1
 817 };
 818
 819 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
 820         0, 1,                   /* line in */
 821         8, 9,                   /* aes in */
 822         10, 11,                 /* spdif in */
 823         12, 16,                 /* adat in */
 824         -1, -1, -1, -1, -1, -1, -1, -1,
 825         -1, -1, -1, -1, -1, -1, -1, -1,
 826         -1, -1, -1, -1, -1, -1, -1, -1,
 827         -1, -1, -1, -1, -1, -1, -1, -1,
 828         -1, -1, -1, -1, -1, -1, -1, -1,
 829         -1, -1, -1, -1, -1, -1, -1, -1,
 830         -1, -1, -1, -1, -1, -1, -1, -1
 831 };
 832
 833 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
 834         0, 1,                   /* line out */
 835         8, 9,                   /* aes out */
 836         10, 11,                 /* spdif out */
 837         12, 16,                 /* adat out */
 838         6, 7,                   /* phone out */
 839         -1, -1, -1, -1, -1, -1,
 840         -1, -1, -1, -1, -1, -1, -1, -1,
 841         -1, -1, -1, -1, -1, -1, -1, -1,
 842         -1, -1, -1, -1, -1, -1, -1, -1,
 843         -1, -1, -1, -1, -1, -1, -1, -1,
 844         -1, -1, -1, -1, -1, -1, -1, -1,
 845         -1, -1, -1, -1, -1, -1, -1, -1
 846 };
 847
 848 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
 849         0, 1, 2, 3, 4, 5, 6, 7,
 850         8, 9, 10, 11, 12, 13, 14, 15,
 851         -1, -1, -1, -1, -1, -1, -1, -1,
 852         -1, -1, -1, -1, -1, -1, -1, -1,
 853         -1, -1, -1, -1, -1, -1, -1, -1,
 854         -1, -1, -1, -1, -1, -1, -1, -1,
 855         -1, -1, -1, -1, -1, -1, -1, -1,
 856         -1, -1, -1, -1, -1, -1, -1, -1
 857 };
 858
 859 struct hdspm_midi {
 860         struct hdspm *hdspm;
 861         int id;
 862         struct snd_rawmidi *rmidi;
 863         struct snd_rawmidi_substream *input;
 864         struct snd_rawmidi_substream *output;
 865         char istimer;           /* timer in use */
 866         struct timer_list timer;
 867         spinlock_t lock;
 868         int pending;
 869         int dataIn;
 870         int statusIn;
 871         int dataOut;
 872         int statusOut;
 873         int ie;
 874         int irq;
 875 };
 876
 877 struct hdspm_tco {
 878         int input;
 879         int framerate;
 880         int wordclock;
 881         int samplerate;
 882         int pull;
 883         int term; /* 0 = off, 1 = on */
 884 };
 885
 886 struct hdspm {
 887         spinlock_t lock;
 888         /* only one playback and/or capture stream */
 889         struct snd_pcm_substream *capture_substream;
 890         struct snd_pcm_substream *playback_substream;
 891
 892         char *card_name;             /* for procinfo */
 893         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
 894
 895         uint8_t io_type;
 896
 897         int monitor_outs;       /* set up monitoring outs init flag */
 898
 899         u32 control_register;   /* cached value */
 900         u32 control2_register;  /* cached value */
 901         u32 settings_register;
 902
 903         struct hdspm_midi midi[4];
 904         struct tasklet_struct midi_tasklet;
 905
 906         size_t period_bytes;
 907         unsigned char ss_in_channels;
 908         unsigned char ds_in_channels;
 909         unsigned char qs_in_channels;
 910         unsigned char ss_out_channels;
 911         unsigned char ds_out_channels;
 912         unsigned char qs_out_channels;
 913
 914         unsigned char max_channels_in;
 915         unsigned char max_channels_out;
 916
 917         signed char *channel_map_in;
 918         signed char *channel_map_out;
 919
 920         signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
 921         signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
 922
 923         char **port_names_in;
 924         char **port_names_out;
 925
 926         char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
 927         char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
 928
 929         unsigned char *playback_buffer; /* suitably aligned address */
 930         unsigned char *capture_buffer;  /* suitably aligned address */
 931
 932         pid_t capture_pid;      /* process id which uses capture */
 933         pid_t playback_pid;     /* process id which uses capture */
 934         int running;            /* running status */
 935
 936         int last_external_sample_rate;  /* samplerate mystic ... */
 937         int last_internal_sample_rate;
 938         int system_sample_rate;
 939
 940         int dev;                /* Hardware vars... */
 941         int irq;
 942         unsigned long port;
 943         void __iomem *iobase;
 944
 945         int irq_count;          /* for debug */
 946         int midiPorts;
 947
 948         struct snd_card *card;  /* one card */
 949         struct snd_pcm *pcm;            /* has one pcm */
 950         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
 951         struct pci_dev *pci;    /* and an pci info */
 952
 953         /* Mixer vars */
 954         /* fast alsa mixer */
 955         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
 956         /* but input to much, so not used */
 957         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
 958         /* full mixer accessible over mixer ioctl or hwdep-device */
 959         struct hdspm_mixer *mixer;
 960
 961         struct hdspm_tco *tco;  /* NULL if no TCO detected */
 962
 963         char **texts_autosync;
 964         int texts_autosync_items;
 965
 966         cycles_t last_interrupt;
 967
 968         unsigned int serial;
 969
 970         struct hdspm_peak_rms peak_rms;
 971 };
 972
 973
 974 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
 975         {
 976          .vendor = PCI_VENDOR_ID_XILINX,
 977          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
 978          .subvendor = PCI_ANY_ID,
 979          .subdevice = PCI_ANY_ID,
 980          .class = 0,
 981          .class_mask = 0,
 982          .driver_data = 0},
 983         {0,}
 984 };
 985
 986 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
 987
 988 /* prototypes */
 989 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
 990                                          struct hdspm *hdspm);
 991 static int snd_hdspm_create_pcm(struct snd_card *card,
 992                                 struct hdspm *hdspm);
 993
 994 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
 995 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
 996 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
 997 static int hdspm_autosync_ref(struct hdspm *hdspm);
 998 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
 999 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
1000 static int hdspm_system_clock_mode(struct hdspm *hdspm);
1001 static void hdspm_set_sgbuf(struct hdspm *hdspm,
1002                             struct snd_pcm_substream *substream,
1003                              unsigned int reg, int channels);
1004
1005 static inline int HDSPM_bit2freq(int n)
1006 {
1007         static const int bit2freq_tab[] = {
1008                 0, 32000, 44100, 48000, 64000, 88200,
1009                 96000, 128000, 176400, 192000 };
1010         if (n < 1 || n > 9)
1011                 return 0;
1012         return bit2freq_tab[n];
1013 }
1014
1015 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1016 {
1017         return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1018 }
1019
1020
1021 /* Write/read to/from HDSPM with Adresses in Bytes
1022    not words but only 32Bit writes are allowed */
1023
1024 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
1025                                unsigned int val)
1026 {
1027         writel(val, hdspm->iobase + reg);
1028 }
1029
1030 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1031 {
1032         return readl(hdspm->iobase + reg);
1033 }
1034
1035 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1036    mixer is write only on hardware so we have to cache him for read
1037    each fader is a u32, but uses only the first 16 bit */
1038
1039 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1040                                      unsigned int in)
1041 {
1042         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1043                 return 0;
1044
1045         return hdspm->mixer->ch[chan].in[in];
1046 }
1047
1048 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1049                                      unsigned int pb)
1050 {
1051         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1052                 return 0;
1053         return hdspm->mixer->ch[chan].pb[pb];
1054 }
1055
1056 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1057                                       unsigned int in, unsigned short data)
1058 {
1059         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1060                 return -1;
1061
1062         hdspm_write(hdspm,
1063                     HDSPM_MADI_mixerBase +
1064                     ((in + 128 * chan) * sizeof(u32)),
1065                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1066         return 0;
1067 }
1068
1069 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1070                                       unsigned int pb, unsigned short data)
1071 {
1072         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1073                 return -1;
1074
1075         hdspm_write(hdspm,
1076                     HDSPM_MADI_mixerBase +
1077                     ((64 + pb + 128 * chan) * sizeof(u32)),
1078                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1079         return 0;
1080 }
1081
1082
1083 /* enable DMA for specific channels, now available for DSP-MADI */
1084 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1085 {
1086         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1087 }
1088
1089 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1090 {
1091         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1092 }
1093
1094 /* check if same process is writing and reading */
1095 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1096 {
1097         unsigned long flags;
1098         int ret = 1;
1099
1100         spin_lock_irqsave(&hdspm->lock, flags);
1101         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1102             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1103                 ret = 0;
1104         }
1105         spin_unlock_irqrestore(&hdspm->lock, flags);
1106         return ret;
1107 }
1108
1109 /* round arbitary sample rates to commonly known rates */
1110 static int hdspm_round_frequency(int rate)
1111 {
1112         if (rate < 38050)
1113                 return 32000;
1114         if (rate < 46008)
1115                 return 44100;
1116         else
1117                 return 48000;
1118 }
1119
1120 /* QS and DS rates normally can not be detected
1121  * automatically by the card. Only exception is MADI
1122  * in 96k frame mode.
1123  *
1124  * So if we read SS values (32 .. 48k), check for
1125  * user-provided DS/QS bits in the control register
1126  * and multiply the base frequency accordingly.
1127  */
1128 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1129 {
1130         if (rate <= 48000) {
1131                 if (hdspm->control_register & HDSPM_QuadSpeed)
1132                         return rate * 4;
1133                 else if (hdspm->control_register &
1134                                 HDSPM_DoubleSpeed)
1135                         return rate * 2;
1136         };
1137         return rate;
1138 }
1139
1140 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1141 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1142
1143 /* check for external sample rate */
1144 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1145 {
1146         unsigned int status, status2, timecode;
1147         int syncref, rate = 0, rate_bits;
1148
1149         switch (hdspm->io_type) {
1150         case AES32:
1151                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1152                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1153                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1154
1155                 syncref = hdspm_autosync_ref(hdspm);
1156
1157                 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1158                                 status & HDSPM_AES32_wcLock)
1159                         return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1160
1161                 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1162                                 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1163                                 status2 & (HDSPM_LockAES >>
1164                                 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1165                         return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1166                 return 0;
1167                 break;
1168
1169         case MADIface:
1170                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1171
1172                 if (!(status & HDSPM_madiLock)) {
1173                         rate = 0;  /* no lock */
1174                 } else {
1175                         switch (status & (HDSPM_status1_freqMask)) {
1176                         case HDSPM_status1_F_0*1:
1177                                 rate = 32000; break;
1178                         case HDSPM_status1_F_0*2:
1179                                 rate = 44100; break;
1180                         case HDSPM_status1_F_0*3:
1181                                 rate = 48000; break;
1182                         case HDSPM_status1_F_0*4:
1183                                 rate = 64000; break;
1184                         case HDSPM_status1_F_0*5:
1185                                 rate = 88200; break;
1186                         case HDSPM_status1_F_0*6:
1187                                 rate = 96000; break;
1188                         case HDSPM_status1_F_0*7:
1189                                 rate = 128000; break;
1190                         case HDSPM_status1_F_0*8:
1191                                 rate = 176400; break;
1192                         case HDSPM_status1_F_0*9:
1193                                 rate = 192000; break;
1194                         default:
1195                                 rate = 0; break;
1196                         }
1197                 }
1198
1199                 break;
1200
1201         case MADI:
1202         case AIO:
1203         case RayDAT:
1204                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1205                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1206                 rate = 0;
1207
1208                 /* if wordclock has synced freq and wordclock is valid */
1209                 if ((status2 & HDSPM_wcLock) != 0 &&
1210                                 (status2 & HDSPM_SelSyncRef0) == 0) {
1211
1212                         rate_bits = status2 & HDSPM_wcFreqMask;
1213
1214
1215                         switch (rate_bits) {
1216                         case HDSPM_wcFreq32:
1217                                 rate = 32000;
1218                                 break;
1219                         case HDSPM_wcFreq44_1:
1220                                 rate = 44100;
1221                                 break;
1222                         case HDSPM_wcFreq48:
1223                                 rate = 48000;
1224                                 break;
1225                         case HDSPM_wcFreq64:
1226                                 rate = 64000;
1227                                 break;
1228                         case HDSPM_wcFreq88_2:
1229                                 rate = 88200;
1230                                 break;
1231                         case HDSPM_wcFreq96:
1232                                 rate = 96000;
1233                                 break;
1234                         case HDSPM_wcFreq128:
1235                                 rate = 128000;
1236                                 break;
1237                         case HDSPM_wcFreq176_4:
1238                                 rate = 176400;
1239                                 break;
1240                         case HDSPM_wcFreq192:
1241                                 rate = 192000;
1242                                 break;
1243                         default:
1244                                 rate = 0;
1245                                 break;
1246                         }
1247                 }
1248
1249                 /* if rate detected and Syncref is Word than have it,
1250                  * word has priority to MADI
1251                  */
1252                 if (rate != 0 &&
1253                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1254                         return hdspm_rate_multiplier(hdspm, rate);
1255
1256                 /* maybe a madi input (which is taken if sel sync is madi) */
1257                 if (status & HDSPM_madiLock) {
1258                         rate_bits = status & HDSPM_madiFreqMask;
1259
1260                         switch (rate_bits) {
1261                         case HDSPM_madiFreq32:
1262                                 rate = 32000;
1263                                 break;
1264                         case HDSPM_madiFreq44_1:
1265                                 rate = 44100;
1266                                 break;
1267                         case HDSPM_madiFreq48:
1268                                 rate = 48000;
1269                                 break;
1270                         case HDSPM_madiFreq64:
1271                                 rate = 64000;
1272                                 break;
1273                         case HDSPM_madiFreq88_2:
1274                                 rate = 88200;
1275                                 break;
1276                         case HDSPM_madiFreq96:
1277                                 rate = 96000;
1278                                 break;
1279                         case HDSPM_madiFreq128:
1280                                 rate = 128000;
1281                                 break;
1282                         case HDSPM_madiFreq176_4:
1283                                 rate = 176400;
1284                                 break;
1285                         case HDSPM_madiFreq192:
1286                                 rate = 192000;
1287                                 break;
1288                         default:
1289                                 rate = 0;
1290                                 break;
1291                         }
1292
1293                 } /* endif HDSPM_madiLock */
1294
1295                 /* check sample rate from TCO or SYNC_IN */
1296                 {
1297                         bool is_valid_input = 0;
1298                         bool has_sync = 0;
1299
1300                         syncref = hdspm_autosync_ref(hdspm);
1301                         if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1302                                 is_valid_input = 1;
1303                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1304                                         hdspm_tco_sync_check(hdspm));
1305                         } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1306                                 is_valid_input = 1;
1307                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1308                                         hdspm_sync_in_sync_check(hdspm));
1309                         }
1310
1311                         if (is_valid_input && has_sync) {
1312                                 rate = hdspm_round_frequency(
1313                                         hdspm_get_pll_freq(hdspm));
1314                         }
1315                 }
1316
1317                 rate = hdspm_rate_multiplier(hdspm, rate);
1318
1319                 break;
1320         }
1321
1322         return rate;
1323 }
1324
1325 /* return latency in samples per period */
1326 static int hdspm_get_latency(struct hdspm *hdspm)
1327 {
1328         int n;
1329
1330         n = hdspm_decode_latency(hdspm->control_register);
1331
1332         /* Special case for new RME cards with 32 samples period size.
1333          * The three latency bits in the control register
1334          * (HDSP_LatencyMask) encode latency values of 64 samples as
1335          * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1336          * denotes 8192 samples, but on new cards like RayDAT or AIO,
1337          * it corresponds to 32 samples.
1338          */
1339         if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1340                 n = -1;
1341
1342         return 1 << (n + 6);
1343 }
1344
1345 /* Latency function */
1346 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1347 {
1348         hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1349 }
1350
1351
1352 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1353 {
1354         int position;
1355
1356         position = hdspm_read(hdspm, HDSPM_statusRegister);
1357
1358         switch (hdspm->io_type) {
1359         case RayDAT:
1360         case AIO:
1361                 position &= HDSPM_BufferPositionMask;
1362                 position /= 4; /* Bytes per sample */
1363                 break;
1364         default:
1365                 position = (position & HDSPM_BufferID) ?
1366                         (hdspm->period_bytes / 4) : 0;
1367         }
1368
1369         return position;
1370 }
1371
1372
1373 static inline void hdspm_start_audio(struct hdspm * s)
1374 {
1375         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1376         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1377 }
1378
1379 static inline void hdspm_stop_audio(struct hdspm * s)
1380 {
1381         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1382         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1383 }
1384
1385 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1386 static void hdspm_silence_playback(struct hdspm *hdspm)
1387 {
1388         int i;
1389         int n = hdspm->period_bytes;
1390         void *buf = hdspm->playback_buffer;
1391
1392         if (buf == NULL)
1393                 return;
1394
1395         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1396                 memset(buf, 0, n);
1397                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1398         }
1399 }
1400
1401 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1402 {
1403         int n;
1404
1405         spin_lock_irq(&s->lock);
1406
1407         if (32 == frames) {
1408                 /* Special case for new RME cards like RayDAT/AIO which
1409                  * support period sizes of 32 samples. Since latency is
1410                  * encoded in the three bits of HDSP_LatencyMask, we can only
1411                  * have values from 0 .. 7. While 0 still means 64 samples and
1412                  * 6 represents 4096 samples on all cards, 7 represents 8192
1413                  * on older cards and 32 samples on new cards.
1414                  *
1415                  * In other words, period size in samples is calculated by
1416                  * 2^(n+6) with n ranging from 0 .. 7.
1417                  */
1418                 n = 7;
1419         } else {
1420                 frames >>= 7;
1421                 n = 0;
1422                 while (frames) {
1423                         n++;
1424                         frames >>= 1;
1425                 }
1426         }
1427
1428         s->control_register &= ~HDSPM_LatencyMask;
1429         s->control_register |= hdspm_encode_latency(n);
1430
1431         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1432
1433         hdspm_compute_period_size(s);
1434
1435         spin_unlock_irq(&s->lock);
1436
1437         return 0;
1438 }
1439
1440 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1441 {
1442         u64 freq_const;
1443
1444         if (period == 0)
1445                 return 0;
1446
1447         switch (hdspm->io_type) {
1448         case MADI:
1449         case AES32:
1450                 freq_const = 110069313433624ULL;
1451                 break;
1452         case RayDAT:
1453         case AIO:
1454                 freq_const = 104857600000000ULL;
1455                 break;
1456         case MADIface:
1457                 freq_const = 131072000000000ULL;
1458                 break;
1459         default:
1460                 snd_BUG();
1461                 return 0;
1462         }
1463
1464         return div_u64(freq_const, period);
1465 }
1466
1467
1468 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1469 {
1470         u64 n;
1471
1472         if (rate >= 112000)
1473                 rate /= 4;
1474         else if (rate >= 56000)
1475                 rate /= 2;
1476
1477         switch (hdspm->io_type) {
1478         case MADIface:
1479                 n = 131072000000000ULL;  /* 125 MHz */
1480                 break;
1481         case MADI:
1482         case AES32:
1483                 n = 110069313433624ULL;  /* 105 MHz */
1484                 break;
1485         case RayDAT:
1486         case AIO:
1487                 n = 104857600000000ULL;  /* 100 MHz */
1488                 break;
1489         default:
1490                 snd_BUG();
1491                 return;
1492         }
1493
1494         n = div_u64(n, rate);
1495         /* n should be less than 2^32 for being written to FREQ register */
1496         snd_BUG_ON(n >> 32);
1497         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1498 }
1499
1500 /* dummy set rate lets see what happens */
1501 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1502 {
1503         int current_rate;
1504         int rate_bits;
1505         int not_set = 0;
1506         int current_speed, target_speed;
1507
1508         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1509            it (e.g. during module initialization).
1510          */
1511
1512         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1513
1514                 /* SLAVE --- */
1515                 if (called_internally) {
1516
1517                         /* request from ctl or card initialization
1518                            just make a warning an remember setting
1519                            for future master mode switching */
1520
1521                         snd_printk(KERN_WARNING "HDSPM: "
1522                                    "Warning: device is not running "
1523                                    "as a clock master.\n");
1524                         not_set = 1;
1525                 } else {
1526
1527                         /* hw_param request while in AutoSync mode */
1528                         int external_freq =
1529                             hdspm_external_sample_rate(hdspm);
1530
1531                         if (hdspm_autosync_ref(hdspm) ==
1532                             HDSPM_AUTOSYNC_FROM_NONE) {
1533
1534                                 snd_printk(KERN_WARNING "HDSPM: "
1535                                            "Detected no Externel Sync \n");
1536                                 not_set = 1;
1537
1538                         } else if (rate != external_freq) {
1539
1540                                 snd_printk(KERN_WARNING "HDSPM: "
1541                                            "Warning: No AutoSync source for "
1542                                            "requested rate\n");
1543                                 not_set = 1;
1544                         }
1545                 }
1546         }
1547
1548         current_rate = hdspm->system_sample_rate;
1549
1550         /* Changing between Singe, Double and Quad speed is not
1551            allowed if any substreams are open. This is because such a change
1552            causes a shift in the location of the DMA buffers and a reduction
1553            in the number of available buffers.
1554
1555            Note that a similar but essentially insoluble problem exists for
1556            externally-driven rate changes. All we can do is to flag rate
1557            changes in the read/write routines.
1558          */
1559
1560         if (current_rate <= 48000)
1561                 current_speed = HDSPM_SPEED_SINGLE;
1562         else if (current_rate <= 96000)
1563                 current_speed = HDSPM_SPEED_DOUBLE;
1564         else
1565                 current_speed = HDSPM_SPEED_QUAD;
1566
1567         if (rate <= 48000)
1568                 target_speed = HDSPM_SPEED_SINGLE;
1569         else if (rate <= 96000)
1570                 target_speed = HDSPM_SPEED_DOUBLE;
1571         else
1572                 target_speed = HDSPM_SPEED_QUAD;
1573
1574         switch (rate) {
1575         case 32000:
1576                 rate_bits = HDSPM_Frequency32KHz;
1577                 break;
1578         case 44100:
1579                 rate_bits = HDSPM_Frequency44_1KHz;
1580                 break;
1581         case 48000:
1582                 rate_bits = HDSPM_Frequency48KHz;
1583                 break;
1584         case 64000:
1585                 rate_bits = HDSPM_Frequency64KHz;
1586                 break;
1587         case 88200:
1588                 rate_bits = HDSPM_Frequency88_2KHz;
1589                 break;
1590         case 96000:
1591                 rate_bits = HDSPM_Frequency96KHz;
1592                 break;
1593         case 128000:
1594                 rate_bits = HDSPM_Frequency128KHz;
1595                 break;
1596         case 176400:
1597                 rate_bits = HDSPM_Frequency176_4KHz;
1598                 break;
1599         case 192000:
1600                 rate_bits = HDSPM_Frequency192KHz;
1601                 break;
1602         default:
1603                 return -EINVAL;
1604         }
1605
1606         if (current_speed != target_speed
1607             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1608                 snd_printk
1609                     (KERN_ERR "HDSPM: "
1610                      "cannot change from %s speed to %s speed mode "
1611                      "(capture PID = %d, playback PID = %d)\n",
1612                      hdspm_speed_names[current_speed],
1613                      hdspm_speed_names[target_speed],
1614                      hdspm->capture_pid, hdspm->playback_pid);
1615                 return -EBUSY;
1616         }
1617
1618         hdspm->control_register &= ~HDSPM_FrequencyMask;
1619         hdspm->control_register |= rate_bits;
1620         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1621
1622         /* For AES32, need to set DDS value in FREQ register
1623            For MADI, also apparently */
1624         hdspm_set_dds_value(hdspm, rate);
1625
1626         if (AES32 == hdspm->io_type && rate != current_rate)
1627                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1628
1629         hdspm->system_sample_rate = rate;
1630
1631         if (rate <= 48000) {
1632                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1633                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1634                 hdspm->max_channels_in = hdspm->ss_in_channels;
1635                 hdspm->max_channels_out = hdspm->ss_out_channels;
1636                 hdspm->port_names_in = hdspm->port_names_in_ss;
1637                 hdspm->port_names_out = hdspm->port_names_out_ss;
1638         } else if (rate <= 96000) {
1639                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1640                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1641                 hdspm->max_channels_in = hdspm->ds_in_channels;
1642                 hdspm->max_channels_out = hdspm->ds_out_channels;
1643                 hdspm->port_names_in = hdspm->port_names_in_ds;
1644                 hdspm->port_names_out = hdspm->port_names_out_ds;
1645         } else {
1646                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1647                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1648                 hdspm->max_channels_in = hdspm->qs_in_channels;
1649                 hdspm->max_channels_out = hdspm->qs_out_channels;
1650                 hdspm->port_names_in = hdspm->port_names_in_qs;
1651                 hdspm->port_names_out = hdspm->port_names_out_qs;
1652         }
1653
1654         if (not_set != 0)
1655                 return -1;
1656
1657         return 0;
1658 }
1659
1660 /* mainly for init to 0 on load */
1661 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1662 {
1663         int i, j;
1664         unsigned int gain;
1665
1666         if (sgain > UNITY_GAIN)
1667                 gain = UNITY_GAIN;
1668         else if (sgain < 0)
1669                 gain = 0;
1670         else
1671                 gain = sgain;
1672
1673         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1674                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1675                         hdspm_write_in_gain(hdspm, i, j, gain);
1676                         hdspm_write_pb_gain(hdspm, i, j, gain);
1677                 }
1678 }
1679
1680 /*----------------------------------------------------------------------------
1681    MIDI
1682   ----------------------------------------------------------------------------*/
1683
1684 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1685                                                       int id)
1686 {
1687         /* the hardware already does the relevant bit-mask with 0xff */
1688         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1689 }
1690
1691 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1692                                               int val)
1693 {
1694         /* the hardware already does the relevant bit-mask with 0xff */
1695         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1696 }
1697
1698 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1699 {
1700         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1701 }
1702
1703 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1704 {
1705         int fifo_bytes_used;
1706
1707         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1708
1709         if (fifo_bytes_used < 128)
1710                 return  128 - fifo_bytes_used;
1711         else
1712                 return 0;
1713 }
1714
1715 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1716 {
1717         while (snd_hdspm_midi_input_available (hdspm, id))
1718                 snd_hdspm_midi_read_byte (hdspm, id);
1719 }
1720
1721 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1722 {
1723         unsigned long flags;
1724         int n_pending;
1725         int to_write;
1726         int i;
1727         unsigned char buf[128];
1728
1729         /* Output is not interrupt driven */
1730
1731         spin_lock_irqsave (&hmidi->lock, flags);
1732         if (hmidi->output &&
1733             !snd_rawmidi_transmit_empty (hmidi->output)) {
1734                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1735                                                             hmidi->id);
1736                 if (n_pending > 0) {
1737                         if (n_pending > (int)sizeof (buf))
1738                                 n_pending = sizeof (buf);
1739
1740                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1741                                                          n_pending);
1742                         if (to_write > 0) {
1743                                 for (i = 0; i < to_write; ++i)
1744                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1745                                                                    hmidi->id,
1746                                                                    buf[i]);
1747                         }
1748                 }
1749         }
1750         spin_unlock_irqrestore (&hmidi->lock, flags);
1751         return 0;
1752 }
1753
1754 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1755 {
1756         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1757                                  * input FIFO size
1758                                  */
1759         unsigned long flags;
1760         int n_pending;
1761         int i;
1762
1763         spin_lock_irqsave (&hmidi->lock, flags);
1764         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1765         if (n_pending > 0) {
1766                 if (hmidi->input) {
1767                         if (n_pending > (int)sizeof (buf))
1768                                 n_pending = sizeof (buf);
1769                         for (i = 0; i < n_pending; ++i)
1770                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1771                                                                    hmidi->id);
1772                         if (n_pending)
1773                                 snd_rawmidi_receive (hmidi->input, buf,
1774                                                      n_pending);
1775                 } else {
1776                         /* flush the MIDI input FIFO */
1777                         while (n_pending--)
1778                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1779                                                           hmidi->id);
1780                 }
1781         }
1782         hmidi->pending = 0;
1783         spin_unlock_irqrestore(&hmidi->lock, flags);
1784
1785         spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1786         hmidi->hdspm->control_register |= hmidi->ie;
1787         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1788                     hmidi->hdspm->control_register);
1789         spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1790
1791         return snd_hdspm_midi_output_write (hmidi);
1792 }
1793
1794 static void
1795 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1796 {
1797         struct hdspm *hdspm;
1798         struct hdspm_midi *hmidi;
1799         unsigned long flags;
1800
1801         hmidi = substream->rmidi->private_data;
1802         hdspm = hmidi->hdspm;
1803
1804         spin_lock_irqsave (&hdspm->lock, flags);
1805         if (up) {
1806                 if (!(hdspm->control_register & hmidi->ie)) {
1807                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1808                         hdspm->control_register |= hmidi->ie;
1809                 }
1810         } else {
1811                 hdspm->control_register &= ~hmidi->ie;
1812         }
1813
1814         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1815         spin_unlock_irqrestore (&hdspm->lock, flags);
1816 }
1817
1818 static void snd_hdspm_midi_output_timer(unsigned long data)
1819 {
1820         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1821         unsigned long flags;
1822
1823         snd_hdspm_midi_output_write(hmidi);
1824         spin_lock_irqsave (&hmidi->lock, flags);
1825
1826         /* this does not bump hmidi->istimer, because the
1827            kernel automatically removed the timer when it
1828            expired, and we are now adding it back, thus
1829            leaving istimer wherever it was set before.
1830         */
1831
1832         if (hmidi->istimer) {
1833                 hmidi->timer.expires = 1 + jiffies;
1834                 add_timer(&hmidi->timer);
1835         }
1836
1837         spin_unlock_irqrestore (&hmidi->lock, flags);
1838 }
1839
1840 static void
1841 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1842 {
1843         struct hdspm_midi *hmidi;
1844         unsigned long flags;
1845
1846         hmidi = substream->rmidi->private_data;
1847         spin_lock_irqsave (&hmidi->lock, flags);
1848         if (up) {
1849                 if (!hmidi->istimer) {
1850                         init_timer(&hmidi->timer);
1851                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1852                         hmidi->timer.data = (unsigned long) hmidi;
1853                         hmidi->timer.expires = 1 + jiffies;
1854                         add_timer(&hmidi->timer);
1855                         hmidi->istimer++;
1856                 }
1857         } else {
1858                 if (hmidi->istimer && --hmidi->istimer <= 0)
1859                         del_timer (&hmidi->timer);
1860         }
1861         spin_unlock_irqrestore (&hmidi->lock, flags);
1862         if (up)
1863                 snd_hdspm_midi_output_write(hmidi);
1864 }
1865
1866 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1867 {
1868         struct hdspm_midi *hmidi;
1869
1870         hmidi = substream->rmidi->private_data;
1871         spin_lock_irq (&hmidi->lock);
1872         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1873         hmidi->input = substream;
1874         spin_unlock_irq (&hmidi->lock);
1875
1876         return 0;
1877 }
1878
1879 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1880 {
1881         struct hdspm_midi *hmidi;
1882
1883         hmidi = substream->rmidi->private_data;
1884         spin_lock_irq (&hmidi->lock);
1885         hmidi->output = substream;
1886         spin_unlock_irq (&hmidi->lock);
1887
1888         return 0;
1889 }
1890
1891 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1892 {
1893         struct hdspm_midi *hmidi;
1894
1895         snd_hdspm_midi_input_trigger (substream, 0);
1896
1897         hmidi = substream->rmidi->private_data;
1898         spin_lock_irq (&hmidi->lock);
1899         hmidi->input = NULL;
1900         spin_unlock_irq (&hmidi->lock);
1901
1902         return 0;
1903 }
1904
1905 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1906 {
1907         struct hdspm_midi *hmidi;
1908
1909         snd_hdspm_midi_output_trigger (substream, 0);
1910
1911         hmidi = substream->rmidi->private_data;
1912         spin_lock_irq (&hmidi->lock);
1913         hmidi->output = NULL;
1914         spin_unlock_irq (&hmidi->lock);
1915
1916         return 0;
1917 }
1918
1919 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1920 {
1921         .open =         snd_hdspm_midi_output_open,
1922         .close =        snd_hdspm_midi_output_close,
1923         .trigger =      snd_hdspm_midi_output_trigger,
1924 };
1925
1926 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1927 {
1928         .open =         snd_hdspm_midi_input_open,
1929         .close =        snd_hdspm_midi_input_close,
1930         .trigger =      snd_hdspm_midi_input_trigger,
1931 };
1932
1933 static int snd_hdspm_create_midi(struct snd_card *card,
1934                                  struct hdspm *hdspm, int id)
1935 {
1936         int err;
1937         char buf[32];
1938
1939         hdspm->midi[id].id = id;
1940         hdspm->midi[id].hdspm = hdspm;
1941         spin_lock_init (&hdspm->midi[id].lock);
1942
1943         if (0 == id) {
1944                 if (MADIface == hdspm->io_type) {
1945                         /* MIDI-over-MADI on HDSPe MADIface */
1946                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1947                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1948                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1949                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1950                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1951                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1952                 } else {
1953                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1954                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1955                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1956                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1957                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1958                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1959                 }
1960         } else if (1 == id) {
1961                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1962                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1963                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1964                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1965                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1966                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1967         } else if ((2 == id) && (MADI == hdspm->io_type)) {
1968                 /* MIDI-over-MADI on HDSPe MADI */
1969                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1970                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1971                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1972                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1973                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1974                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1975         } else if (2 == id) {
1976                 /* TCO MTC, read only */
1977                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1978                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1979                 hdspm->midi[2].dataOut = -1;
1980                 hdspm->midi[2].statusOut = -1;
1981                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1982                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1983         } else if (3 == id) {
1984                 /* TCO MTC on HDSPe MADI */
1985                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1986                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1987                 hdspm->midi[3].dataOut = -1;
1988                 hdspm->midi[3].statusOut = -1;
1989                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1990                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1991         }
1992
1993         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1994                                         (MADIface == hdspm->io_type)))) {
1995                 if ((id == 0) && (MADIface == hdspm->io_type)) {
1996                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1997                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1998                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1999                 } else {
2000                         sprintf(buf, "%s MIDI %d", card->shortname, id+1);
2001                 }
2002                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2003                                 &hdspm->midi[id].rmidi);
2004                 if (err < 0)
2005                         return err;
2006
2007                 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
2008                                 card->id, id+1);
2009                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2010
2011                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2012                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
2013                                 &snd_hdspm_midi_output);
2014                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2015                                 SNDRV_RAWMIDI_STREAM_INPUT,
2016                                 &snd_hdspm_midi_input);
2017
2018                 hdspm->midi[id].rmidi->info_flags |=
2019                         SNDRV_RAWMIDI_INFO_OUTPUT |
2020                         SNDRV_RAWMIDI_INFO_INPUT |
2021                         SNDRV_RAWMIDI_INFO_DUPLEX;
2022         } else {
2023                 /* TCO MTC, read only */
2024                 sprintf(buf, "%s MTC %d", card->shortname, id+1);
2025                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2026                                 &hdspm->midi[id].rmidi);
2027                 if (err < 0)
2028                         return err;
2029
2030                 sprintf(hdspm->midi[id].rmidi->name,
2031                                 "%s MTC %d", card->id, id+1);
2032                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2033
2034                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2035                                 SNDRV_RAWMIDI_STREAM_INPUT,
2036                                 &snd_hdspm_midi_input);
2037
2038                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2039         }
2040
2041         return 0;
2042 }
2043
2044
2045 static void hdspm_midi_tasklet(unsigned long arg)
2046 {
2047         struct hdspm *hdspm = (struct hdspm *)arg;
2048         int i = 0;
2049
2050         while (i < hdspm->midiPorts) {
2051                 if (hdspm->midi[i].pending)
2052                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
2053
2054                 i++;
2055         }
2056 }
2057
2058
2059 /*-----------------------------------------------------------------------------
2060   Status Interface
2061   ----------------------------------------------------------------------------*/
2062
2063 /* get the system sample rate which is set */
2064
2065
2066 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2067 {
2068         unsigned int period, rate;
2069
2070         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2071         rate = hdspm_calc_dds_value(hdspm, period);
2072
2073         return rate;
2074 }
2075
2076 /**
2077  * Calculate the real sample rate from the
2078  * current DDS value.
2079  **/
2080 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2081 {
2082         unsigned int rate;
2083
2084         rate = hdspm_get_pll_freq(hdspm);
2085
2086         if (rate > 207000) {
2087                 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2088                 if (0 == hdspm_system_clock_mode(hdspm)) {
2089                         /* master mode, return internal sample rate */
2090                         rate = hdspm->system_sample_rate;
2091                 } else {
2092                         /* slave mode, return external sample rate */
2093                         rate = hdspm_external_sample_rate(hdspm);
2094                 }
2095         }
2096
2097         return rate;
2098 }
2099
2100
2101 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2102 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2103         .name = xname, \
2104         .index = xindex, \
2105         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2106                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2107         .info = snd_hdspm_info_system_sample_rate, \
2108         .put = snd_hdspm_put_system_sample_rate, \
2109         .get = snd_hdspm_get_system_sample_rate \
2110 }
2111
2112 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2113                                              struct snd_ctl_elem_info *uinfo)
2114 {
2115         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2116         uinfo->count = 1;
2117         uinfo->value.integer.min = 27000;
2118         uinfo->value.integer.max = 207000;
2119         uinfo->value.integer.step = 1;
2120         return 0;
2121 }
2122
2123
2124 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2125                                             struct snd_ctl_elem_value *
2126                                             ucontrol)
2127 {
2128         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2129
2130         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2131         return 0;
2132 }
2133
2134 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2135                                             struct snd_ctl_elem_value *
2136                                             ucontrol)
2137 {
2138         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2139
2140         hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]);
2141         return 0;
2142 }
2143
2144
2145 /**
2146  * Returns the WordClock sample rate class for the given card.
2147  **/
2148 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2149 {
2150         int status;
2151
2152         switch (hdspm->io_type) {
2153         case RayDAT:
2154         case AIO:
2155                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2156                 return (status >> 16) & 0xF;
2157                 break;
2158         default:
2159                 break;
2160         }
2161
2162
2163         return 0;
2164 }
2165
2166
2167 /**
2168  * Returns the TCO sample rate class for the given card.
2169  **/
2170 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2171 {
2172         int status;
2173
2174         if (hdspm->tco) {
2175                 switch (hdspm->io_type) {
2176                 case RayDAT:
2177                 case AIO:
2178                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2179                         return (status >> 20) & 0xF;
2180                         break;
2181                 default:
2182                         break;
2183                 }
2184         }
2185
2186         return 0;
2187 }
2188
2189
2190 /**
2191  * Returns the SYNC_IN sample rate class for the given card.
2192  **/
2193 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2194 {
2195         int status;
2196
2197         if (hdspm->tco) {
2198                 switch (hdspm->io_type) {
2199                 case RayDAT:
2200                 case AIO:
2201                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2202                         return (status >> 12) & 0xF;
2203                         break;
2204                 default:
2205                         break;
2206                 }
2207         }
2208
2209         return 0;
2210 }
2211
2212
2213 /**
2214  * Returns the sample rate class for input source <idx> for
2215  * 'new style' cards like the AIO and RayDAT.
2216  **/
2217 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2218 {
2219         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2220
2221         return (status >> (idx*4)) & 0xF;
2222 }
2223
2224 static void snd_hdspm_set_infotext(struct snd_ctl_elem_info *uinfo,
2225                 char **texts, const int count)
2226 {
2227         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2228         uinfo->count = 1;
2229         uinfo->value.enumerated.items = count;
2230         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2231                 uinfo->value.enumerated.item =
2232                         uinfo->value.enumerated.items - 1;
2233         strcpy(uinfo->value.enumerated.name,
2234                         texts[uinfo->value.enumerated.item]);
2235 }
2236
2237 #define ENUMERATED_CTL_INFO(info, texts) \
2238         snd_hdspm_set_infotext(info, texts, ARRAY_SIZE(texts))
2239
2240
2241
2242 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2243 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2244         .name = xname, \
2245         .private_value = xindex, \
2246         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2247         .info = snd_hdspm_info_autosync_sample_rate, \
2248         .get = snd_hdspm_get_autosync_sample_rate \
2249 }
2250
2251
2252 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2253                                                struct snd_ctl_elem_info *uinfo)
2254 {
2255         ENUMERATED_CTL_INFO(uinfo, texts_freq);
2256         return 0;
2257 }
2258
2259
2260 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2261                                               struct snd_ctl_elem_value *
2262                                               ucontrol)
2263 {
2264         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2265
2266         switch (hdspm->io_type) {
2267         case RayDAT:
2268                 switch (kcontrol->private_value) {
2269                 case 0:
2270                         ucontrol->value.enumerated.item[0] =
2271                                 hdspm_get_wc_sample_rate(hdspm);
2272                         break;
2273                 case 7:
2274                         ucontrol->value.enumerated.item[0] =
2275                                 hdspm_get_tco_sample_rate(hdspm);
2276                         break;
2277                 case 8:
2278                         ucontrol->value.enumerated.item[0] =
2279                                 hdspm_get_sync_in_sample_rate(hdspm);
2280                         break;
2281                 default:
2282                         ucontrol->value.enumerated.item[0] =
2283                                 hdspm_get_s1_sample_rate(hdspm,
2284                                                 kcontrol->private_value-1);
2285                 }
2286                 break;
2287
2288         case AIO:
2289                 switch (kcontrol->private_value) {
2290                 case 0: /* WC */
2291                         ucontrol->value.enumerated.item[0] =
2292                                 hdspm_get_wc_sample_rate(hdspm);
2293                         break;
2294                 case 4: /* TCO */
2295                         ucontrol->value.enumerated.item[0] =
2296                                 hdspm_get_tco_sample_rate(hdspm);
2297                         break;
2298                 case 5: /* SYNC_IN */
2299                         ucontrol->value.enumerated.item[0] =
2300                                 hdspm_get_sync_in_sample_rate(hdspm);
2301                         break;
2302                 default:
2303                         ucontrol->value.enumerated.item[0] =
2304                                 hdspm_get_s1_sample_rate(hdspm,
2305                                                 ucontrol->id.index-1);
2306                 }
2307                 break;
2308
2309         case AES32:
2310
2311                 switch (kcontrol->private_value) {
2312                 case 0: /* WC */
2313                         ucontrol->value.enumerated.item[0] =
2314                                 hdspm_get_wc_sample_rate(hdspm);
2315                         break;
2316                 case 9: /* TCO */
2317                         ucontrol->value.enumerated.item[0] =
2318                                 hdspm_get_tco_sample_rate(hdspm);
2319                         break;
2320                 case 10: /* SYNC_IN */
2321                         ucontrol->value.enumerated.item[0] =
2322                                 hdspm_get_sync_in_sample_rate(hdspm);
2323                         break;
2324                 default: /* AES1 to AES8 */
2325                         ucontrol->value.enumerated.item[0] =
2326                                 hdspm_get_s1_sample_rate(hdspm,
2327                                                 kcontrol->private_value-1);
2328                         break;
2329                 }
2330                 break;
2331
2332         case MADI:
2333         case MADIface:
2334                 {
2335                         int rate = hdspm_external_sample_rate(hdspm);
2336                         int i, selected_rate = 0;
2337                         for (i = 1; i < 10; i++)
2338                                 if (HDSPM_bit2freq(i) == rate) {
2339                                         selected_rate = i;
2340                                         break;
2341                                 }
2342                         ucontrol->value.enumerated.item[0] = selected_rate;
2343                 }
2344                 break;
2345
2346         default:
2347                 break;
2348         }
2349
2350         return 0;
2351 }
2352
2353
2354 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2355 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2356         .name = xname, \
2357         .index = xindex, \
2358         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2359                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2360         .info = snd_hdspm_info_system_clock_mode, \
2361         .get = snd_hdspm_get_system_clock_mode, \
2362         .put = snd_hdspm_put_system_clock_mode, \
2363 }
2364
2365
2366 /**
2367  * Returns the system clock mode for the given card.
2368  * @returns 0 - master, 1 - slave
2369  **/
2370 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2371 {
2372         switch (hdspm->io_type) {
2373         case AIO:
2374         case RayDAT:
2375                 if (hdspm->settings_register & HDSPM_c0Master)
2376                         return 0;
2377                 break;
2378
2379         default:
2380                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2381                         return 0;
2382         }
2383
2384         return 1;
2385 }
2386
2387
2388 /**
2389  * Sets the system clock mode.
2390  * @param mode 0 - master, 1 - slave
2391  **/
2392 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2393 {
2394         hdspm_set_toggle_setting(hdspm,
2395                         (hdspm_is_raydat_or_aio(hdspm)) ?
2396                         HDSPM_c0Master : HDSPM_ClockModeMaster,
2397                         (0 == mode));
2398 }
2399
2400
2401 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2402                                             struct snd_ctl_elem_info *uinfo)
2403 {
2404         static char *texts[] = { "Master", "AutoSync" };
2405         ENUMERATED_CTL_INFO(uinfo, texts);
2406         return 0;
2407 }
2408
2409 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2410                                            struct snd_ctl_elem_value *ucontrol)
2411 {
2412         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2413
2414         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2415         return 0;
2416 }
2417
2418 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2419                                            struct snd_ctl_elem_value *ucontrol)
2420 {
2421         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2422         int val;
2423
2424         if (!snd_hdspm_use_is_exclusive(hdspm))
2425                 return -EBUSY;
2426
2427         val = ucontrol->value.enumerated.item[0];
2428         if (val < 0)
2429                 val = 0;
2430         else if (val > 1)
2431                 val = 1;
2432
2433         hdspm_set_system_clock_mode(hdspm, val);
2434
2435         return 0;
2436 }
2437
2438
2439 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2440 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2441         .name = xname, \
2442         .index = xindex, \
2443         .info = snd_hdspm_info_clock_source, \
2444         .get = snd_hdspm_get_clock_source, \
2445         .put = snd_hdspm_put_clock_source \
2446 }
2447
2448
2449 static int hdspm_clock_source(struct hdspm * hdspm)
2450 {
2451         switch (hdspm->system_sample_rate) {
2452         case 32000: return 0;
2453         case 44100: return 1;
2454         case 48000: return 2;
2455         case 64000: return 3;
2456         case 88200: return 4;
2457         case 96000: return 5;
2458         case 128000: return 6;
2459         case 176400: return 7;
2460         case 192000: return 8;
2461         }
2462
2463         return -1;
2464 }
2465
2466 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2467 {
2468         int rate;
2469         switch (mode) {
2470         case 0:
2471                 rate = 32000; break;
2472         case 1:
2473                 rate = 44100; break;
2474         case 2:
2475                 rate = 48000; break;
2476         case 3:
2477                 rate = 64000; break;
2478         case 4:
2479                 rate = 88200; break;
2480         case 5:
2481                 rate = 96000; break;
2482         case 6:
2483                 rate = 128000; break;
2484         case 7:
2485                 rate = 176400; break;
2486         case 8:
2487                 rate = 192000; break;
2488         default:
2489                 rate = 48000;
2490         }
2491         hdspm_set_rate(hdspm, rate, 1);
2492         return 0;
2493 }
2494
2495 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2496                                        struct snd_ctl_elem_info *uinfo)
2497 {
2498         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2499         uinfo->count = 1;
2500         uinfo->value.enumerated.items = 9;
2501
2502         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2503                 uinfo->value.enumerated.item =
2504                     uinfo->value.enumerated.items - 1;
2505
2506         strcpy(uinfo->value.enumerated.name,
2507                texts_freq[uinfo->value.enumerated.item+1]);
2508
2509         return 0;
2510 }
2511
2512 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2513                                       struct snd_ctl_elem_value *ucontrol)
2514 {
2515         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2516
2517         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2518         return 0;
2519 }
2520
2521 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2522                                       struct snd_ctl_elem_value *ucontrol)
2523 {
2524         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2525         int change;
2526         int val;
2527
2528         if (!snd_hdspm_use_is_exclusive(hdspm))
2529                 return -EBUSY;
2530         val = ucontrol->value.enumerated.item[0];
2531         if (val < 0)
2532                 val = 0;
2533         if (val > 9)
2534                 val = 9;
2535         spin_lock_irq(&hdspm->lock);
2536         if (val != hdspm_clock_source(hdspm))
2537                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2538         else
2539                 change = 0;
2540         spin_unlock_irq(&hdspm->lock);
2541         return change;
2542 }
2543
2544
2545 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2546 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2547         .name = xname, \
2548         .index = xindex, \
2549         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2550                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2551         .info = snd_hdspm_info_pref_sync_ref, \
2552         .get = snd_hdspm_get_pref_sync_ref, \
2553         .put = snd_hdspm_put_pref_sync_ref \
2554 }
2555
2556
2557 /**
2558  * Returns the current preferred sync reference setting.
2559  * The semantics of the return value are depending on the
2560  * card, please see the comments for clarification.
2561  **/
2562 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2563 {
2564         switch (hdspm->io_type) {
2565         case AES32:
2566                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2567                 case 0: return 0;  /* WC */
2568                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2569                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2570                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2571                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2572                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2573                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2574                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2575                                                     return 7; /* AES 7 */
2576                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2577                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2578                 }
2579                 break;
2580
2581         case MADI:
2582         case MADIface:
2583                 if (hdspm->tco) {
2584                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2585                         case 0: return 0;  /* WC */
2586                         case HDSPM_SyncRef0: return 1;  /* MADI */
2587                         case HDSPM_SyncRef1: return 2;  /* TCO */
2588                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2589                                              return 3;  /* SYNC_IN */
2590                         }
2591                 } else {
2592                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2593                         case 0: return 0;  /* WC */
2594                         case HDSPM_SyncRef0: return 1;  /* MADI */
2595                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2596                                              return 2;  /* SYNC_IN */
2597                         }
2598                 }
2599                 break;
2600
2601         case RayDAT:
2602                 if (hdspm->tco) {
2603                         switch ((hdspm->settings_register &
2604                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2605                         case 0: return 0;  /* WC */
2606                         case 3: return 1;  /* ADAT 1 */
2607                         case 4: return 2;  /* ADAT 2 */
2608                         case 5: return 3;  /* ADAT 3 */
2609                         case 6: return 4;  /* ADAT 4 */
2610                         case 1: return 5;  /* AES */
2611                         case 2: return 6;  /* SPDIF */
2612                         case 9: return 7;  /* TCO */
2613                         case 10: return 8; /* SYNC_IN */
2614                         }
2615                 } else {
2616                         switch ((hdspm->settings_register &
2617                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2618                         case 0: return 0;  /* WC */
2619                         case 3: return 1;  /* ADAT 1 */
2620                         case 4: return 2;  /* ADAT 2 */
2621                         case 5: return 3;  /* ADAT 3 */
2622                         case 6: return 4;  /* ADAT 4 */
2623                         case 1: return 5;  /* AES */
2624                         case 2: return 6;  /* SPDIF */
2625                         case 10: return 7; /* SYNC_IN */
2626                         }
2627                 }
2628
2629                 break;
2630
2631         case AIO:
2632                 if (hdspm->tco) {
2633                         switch ((hdspm->settings_register &
2634                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2635                         case 0: return 0;  /* WC */
2636                         case 3: return 1;  /* ADAT */
2637                         case 1: return 2;  /* AES */
2638                         case 2: return 3;  /* SPDIF */
2639                         case 9: return 4;  /* TCO */
2640                         case 10: return 5; /* SYNC_IN */
2641                         }
2642                 } else {
2643                         switch ((hdspm->settings_register &
2644                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2645                         case 0: return 0;  /* WC */
2646                         case 3: return 1;  /* ADAT */
2647                         case 1: return 2;  /* AES */
2648                         case 2: return 3;  /* SPDIF */
2649                         case 10: return 4; /* SYNC_IN */
2650                         }
2651                 }
2652
2653                 break;
2654         }
2655
2656         return -1;
2657 }
2658
2659
2660 /**
2661  * Set the preferred sync reference to <pref>. The semantics
2662  * of <pref> are depending on the card type, see the comments
2663  * for clarification.
2664  **/
2665 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2666 {
2667         int p = 0;
2668
2669         switch (hdspm->io_type) {
2670         case AES32:
2671                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2672                 switch (pref) {
2673                 case 0: /* WC  */
2674                         break;
2675                 case 1: /* AES 1 */
2676                         hdspm->control_register |= HDSPM_SyncRef0;
2677                         break;
2678                 case 2: /* AES 2 */
2679                         hdspm->control_register |= HDSPM_SyncRef1;
2680                         break;
2681                 case 3: /* AES 3 */
2682                         hdspm->control_register |=
2683                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2684                         break;
2685                 case 4: /* AES 4 */
2686                         hdspm->control_register |= HDSPM_SyncRef2;
2687                         break;
2688                 case 5: /* AES 5 */
2689                         hdspm->control_register |=
2690                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2691                         break;
2692                 case 6: /* AES 6 */
2693                         hdspm->control_register |=
2694                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2695                         break;
2696                 case 7: /* AES 7 */
2697                         hdspm->control_register |=
2698                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2699                         break;
2700                 case 8: /* AES 8 */
2701                         hdspm->control_register |= HDSPM_SyncRef3;
2702                         break;
2703                 case 9: /* TCO */
2704                         hdspm->control_register |=
2705                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2706                         break;
2707                 default:
2708                         return -1;
2709                 }
2710
2711                 break;
2712
2713         case MADI:
2714         case MADIface:
2715                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2716                 if (hdspm->tco) {
2717                         switch (pref) {
2718                         case 0: /* WC */
2719                                 break;
2720                         case 1: /* MADI */
2721                                 hdspm->control_register |= HDSPM_SyncRef0;
2722                                 break;
2723                         case 2: /* TCO */
2724                                 hdspm->control_register |= HDSPM_SyncRef1;
2725                                 break;
2726                         case 3: /* SYNC_IN */
2727                                 hdspm->control_register |=
2728                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2729                                 break;
2730                         default:
2731                                 return -1;
2732                         }
2733                 } else {
2734                         switch (pref) {
2735                         case 0: /* WC */
2736                                 break;
2737                         case 1: /* MADI */
2738                                 hdspm->control_register |= HDSPM_SyncRef0;
2739                                 break;
2740                         case 2: /* SYNC_IN */
2741                                 hdspm->control_register |=
2742                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2743                                 break;
2744                         default:
2745                                 return -1;
2746                         }
2747                 }
2748
2749                 break;
2750
2751         case RayDAT:
2752                 if (hdspm->tco) {
2753                         switch (pref) {
2754                         case 0: p = 0; break;  /* WC */
2755                         case 1: p = 3; break;  /* ADAT 1 */
2756                         case 2: p = 4; break;  /* ADAT 2 */
2757                         case 3: p = 5; break;  /* ADAT 3 */
2758                         case 4: p = 6; break;  /* ADAT 4 */
2759                         case 5: p = 1; break;  /* AES */
2760                         case 6: p = 2; break;  /* SPDIF */
2761                         case 7: p = 9; break;  /* TCO */
2762                         case 8: p = 10; break; /* SYNC_IN */
2763                         default: return -1;
2764                         }
2765                 } else {
2766                         switch (pref) {
2767                         case 0: p = 0; break;  /* WC */
2768                         case 1: p = 3; break;  /* ADAT 1 */
2769                         case 2: p = 4; break;  /* ADAT 2 */
2770                         case 3: p = 5; break;  /* ADAT 3 */
2771                         case 4: p = 6; break;  /* ADAT 4 */
2772                         case 5: p = 1; break;  /* AES */
2773                         case 6: p = 2; break;  /* SPDIF */
2774                         case 7: p = 10; break; /* SYNC_IN */
2775                         default: return -1;
2776                         }
2777                 }
2778                 break;
2779
2780         case AIO:
2781                 if (hdspm->tco) {
2782                         switch (pref) {
2783                         case 0: p = 0; break;  /* WC */
2784                         case 1: p = 3; break;  /* ADAT */
2785                         case 2: p = 1; break;  /* AES */
2786                         case 3: p = 2; break;  /* SPDIF */
2787                         case 4: p = 9; break;  /* TCO */
2788                         case 5: p = 10; break; /* SYNC_IN */
2789                         default: return -1;
2790                         }
2791                 } else {
2792                         switch (pref) {
2793                         case 0: p = 0; break;  /* WC */
2794                         case 1: p = 3; break;  /* ADAT */
2795                         case 2: p = 1; break;  /* AES */
2796                         case 3: p = 2; break;  /* SPDIF */
2797                         case 4: p = 10; break; /* SYNC_IN */
2798                         default: return -1;
2799                         }
2800                 }
2801                 break;
2802         }
2803
2804         switch (hdspm->io_type) {
2805         case RayDAT:
2806         case AIO:
2807                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2808                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2809                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2810                 break;
2811
2812         case MADI:
2813         case MADIface:
2814         case AES32:
2815                 hdspm_write(hdspm, HDSPM_controlRegister,
2816                                 hdspm->control_register);
2817         }
2818
2819         return 0;
2820 }
2821
2822
2823 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2824                                         struct snd_ctl_elem_info *uinfo)
2825 {
2826         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2827
2828         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2829         uinfo->count = 1;
2830         uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2831
2832         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2833                 uinfo->value.enumerated.item =
2834                         uinfo->value.enumerated.items - 1;
2835
2836         strcpy(uinfo->value.enumerated.name,
2837                         hdspm->texts_autosync[uinfo->value.enumerated.item]);
2838
2839         return 0;
2840 }
2841
2842 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2843                                        struct snd_ctl_elem_value *ucontrol)
2844 {
2845         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2846         int psf = hdspm_pref_sync_ref(hdspm);
2847
2848         if (psf >= 0) {
2849                 ucontrol->value.enumerated.item[0] = psf;
2850                 return 0;
2851         }
2852
2853         return -1;
2854 }
2855
2856 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2857                                        struct snd_ctl_elem_value *ucontrol)
2858 {
2859         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2860         int val, change = 0;
2861
2862         if (!snd_hdspm_use_is_exclusive(hdspm))
2863                 return -EBUSY;
2864
2865         val = ucontrol->value.enumerated.item[0];
2866
2867         if (val < 0)
2868                 val = 0;
2869         else if (val >= hdspm->texts_autosync_items)
2870                 val = hdspm->texts_autosync_items-1;
2871
2872         spin_lock_irq(&hdspm->lock);
2873         if (val != hdspm_pref_sync_ref(hdspm))
2874                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2875
2876         spin_unlock_irq(&hdspm->lock);
2877         return change;
2878 }
2879
2880
2881 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2882 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2883         .name = xname, \
2884         .index = xindex, \
2885         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2886         .info = snd_hdspm_info_autosync_ref, \
2887         .get = snd_hdspm_get_autosync_ref, \
2888 }
2889
2890 static int hdspm_autosync_ref(struct hdspm *hdspm)
2891 {
2892         if (AES32 == hdspm->io_type) {
2893                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2894                 unsigned int syncref =
2895                         (status >> HDSPM_AES32_syncref_bit) & 0xF;
2896                 if (syncref == 0)
2897                         return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2898                 if (syncref <= 8)
2899                         return syncref;
2900                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2901         } else if (MADI == hdspm->io_type) {
2902                 /* This looks at the autosync selected sync reference */
2903                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2904
2905                 switch (status2 & HDSPM_SelSyncRefMask) {
2906                 case HDSPM_SelSyncRef_WORD:
2907                         return HDSPM_AUTOSYNC_FROM_WORD;
2908                 case HDSPM_SelSyncRef_MADI:
2909                         return HDSPM_AUTOSYNC_FROM_MADI;
2910                 case HDSPM_SelSyncRef_TCO:
2911                         return HDSPM_AUTOSYNC_FROM_TCO;
2912                 case HDSPM_SelSyncRef_SyncIn:
2913                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2914                 case HDSPM_SelSyncRef_NVALID:
2915                         return HDSPM_AUTOSYNC_FROM_NONE;
2916                 default:
2917                         return 0;
2918                 }
2919
2920         }
2921         return 0;
2922 }
2923
2924
2925 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2926                                        struct snd_ctl_elem_info *uinfo)
2927 {
2928         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2929
2930         if (AES32 == hdspm->io_type) {
2931                 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2932                         "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2933
2934                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2935                 uinfo->count = 1;
2936                 uinfo->value.enumerated.items = 10;
2937                 if (uinfo->value.enumerated.item >=
2938                     uinfo->value.enumerated.items)
2939                         uinfo->value.enumerated.item =
2940                                 uinfo->value.enumerated.items - 1;
2941                 strcpy(uinfo->value.enumerated.name,
2942                                 texts[uinfo->value.enumerated.item]);
2943         } else if (MADI == hdspm->io_type) {
2944                 static char *texts[] = {"Word Clock", "MADI", "TCO",
2945                         "Sync In", "None" };
2946
2947                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2948                 uinfo->count = 1;
2949                 uinfo->value.enumerated.items = 5;
2950                 if (uinfo->value.enumerated.item >=
2951                                 uinfo->value.enumerated.items)
2952                         uinfo->value.enumerated.item =
2953                                 uinfo->value.enumerated.items - 1;
2954                 strcpy(uinfo->value.enumerated.name,
2955                                 texts[uinfo->value.enumerated.item]);
2956         }
2957         return 0;
2958 }
2959
2960 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2961                                       struct snd_ctl_elem_value *ucontrol)
2962 {
2963         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2964
2965         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2966         return 0;
2967 }
2968
2969
2970
2971 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
2972 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2973         .name = xname, \
2974         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
2975                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2976         .info = snd_hdspm_info_tco_video_input_format, \
2977         .get = snd_hdspm_get_tco_video_input_format, \
2978 }
2979
2980 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
2981                                        struct snd_ctl_elem_info *uinfo)
2982 {
2983         static char *texts[] = {"No video", "NTSC", "PAL"};
2984         ENUMERATED_CTL_INFO(uinfo, texts);
2985         return 0;
2986 }
2987
2988 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
2989                                       struct snd_ctl_elem_value *ucontrol)
2990 {
2991         u32 status;
2992         int ret = 0;
2993
2994         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2995         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
2996         switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
2997                         HDSPM_TCO1_Video_Input_Format_PAL)) {
2998         case HDSPM_TCO1_Video_Input_Format_NTSC:
2999                 /* ntsc */
3000                 ret = 1;
3001                 break;
3002         case HDSPM_TCO1_Video_Input_Format_PAL:
3003                 /* pal */
3004                 ret = 2;
3005                 break;
3006         default:
3007                 /* no video */
3008                 ret = 0;
3009                 break;
3010         }
3011         ucontrol->value.enumerated.item[0] = ret;
3012         return 0;
3013 }
3014
3015
3016
3017 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
3018 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3019         .name = xname, \
3020         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3021                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3022         .info = snd_hdspm_info_tco_ltc_frames, \
3023         .get = snd_hdspm_get_tco_ltc_frames, \
3024 }
3025
3026 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3027                                        struct snd_ctl_elem_info *uinfo)
3028 {
3029         static char *texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3030                                 "30 fps"};
3031         ENUMERATED_CTL_INFO(uinfo, texts);
3032         return 0;
3033 }
3034
3035 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3036 {
3037         u32 status;
3038         int ret = 0;
3039
3040         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3041         if (status & HDSPM_TCO1_LTC_Input_valid) {
3042                 switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3043                                         HDSPM_TCO1_LTC_Format_MSB)) {
3044                 case 0:
3045                         /* 24 fps */
3046                         ret = 1;
3047                         break;
3048                 case HDSPM_TCO1_LTC_Format_LSB:
3049                         /* 25 fps */
3050                         ret = 2;
3051                         break;
3052                 case HDSPM_TCO1_LTC_Format_MSB:
3053                         /* 25 fps */
3054                         ret = 3;
3055                         break;
3056                 default:
3057                         /* 30 fps */
3058                         ret = 4;
3059                         break;
3060                 }
3061         }
3062
3063         return ret;
3064 }
3065
3066 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3067                                       struct snd_ctl_elem_value *ucontrol)
3068 {
3069         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3070
3071         ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3072         return 0;
3073 }
3074
3075 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3076 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3077         .name = xname, \
3078         .private_value = xindex, \
3079         .info = snd_hdspm_info_toggle_setting, \
3080         .get = snd_hdspm_get_toggle_setting, \
3081         .put = snd_hdspm_put_toggle_setting \
3082 }
3083
3084 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3085 {
3086         u32 reg;
3087
3088         if (hdspm_is_raydat_or_aio(hdspm))
3089                 reg = hdspm->settings_register;
3090         else
3091                 reg = hdspm->control_register;
3092
3093         return (reg & regmask) ? 1 : 0;
3094 }
3095
3096 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3097 {
3098         u32 *reg;
3099         u32 target_reg;
3100
3101         if (hdspm_is_raydat_or_aio(hdspm)) {
3102                 reg = &(hdspm->settings_register);
3103                 target_reg = HDSPM_WR_SETTINGS;
3104         } else {
3105                 reg = &(hdspm->control_register);
3106                 target_reg = HDSPM_controlRegister;
3107         }
3108
3109         if (out)
3110                 *reg |= regmask;
3111         else
3112                 *reg &= ~regmask;
3113
3114         hdspm_write(hdspm, target_reg, *reg);
3115
3116         return 0;
3117 }
3118
3119 #define snd_hdspm_info_toggle_setting           snd_ctl_boolean_mono_info
3120
3121 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3122                                struct snd_ctl_elem_value *ucontrol)
3123 {
3124         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3125         u32 regmask = kcontrol->private_value;
3126
3127         spin_lock_irq(&hdspm->lock);
3128         ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3129         spin_unlock_irq(&hdspm->lock);
3130         return 0;
3131 }
3132
3133 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3134                                struct snd_ctl_elem_value *ucontrol)
3135 {
3136         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3137         u32 regmask = kcontrol->private_value;
3138         int change;
3139         unsigned int val;
3140
3141         if (!snd_hdspm_use_is_exclusive(hdspm))
3142                 return -EBUSY;
3143         val = ucontrol->value.integer.value[0] & 1;
3144         spin_lock_irq(&hdspm->lock);
3145         change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3146         hdspm_set_toggle_setting(hdspm, regmask, val);
3147         spin_unlock_irq(&hdspm->lock);
3148         return change;
3149 }
3150
3151 #define HDSPM_INPUT_SELECT(xname, xindex) \
3152 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3153         .name = xname, \
3154         .index = xindex, \
3155         .info = snd_hdspm_info_input_select, \
3156         .get = snd_hdspm_get_input_select, \
3157         .put = snd_hdspm_put_input_select \
3158 }
3159
3160 static int hdspm_input_select(struct hdspm * hdspm)
3161 {
3162         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3163 }
3164
3165 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3166 {
3167         if (out)
3168                 hdspm->control_register |= HDSPM_InputSelect0;
3169         else
3170                 hdspm->control_register &= ~HDSPM_InputSelect0;
3171         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3172
3173         return 0;
3174 }
3175
3176 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3177                                        struct snd_ctl_elem_info *uinfo)
3178 {
3179         static char *texts[] = { "optical", "coaxial" };
3180         ENUMERATED_CTL_INFO(uinfo, texts);
3181         return 0;
3182 }
3183
3184 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3185                                       struct snd_ctl_elem_value *ucontrol)
3186 {
3187         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3188
3189         spin_lock_irq(&hdspm->lock);
3190         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3191         spin_unlock_irq(&hdspm->lock);
3192         return 0;
3193 }
3194
3195 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3196                                       struct snd_ctl_elem_value *ucontrol)
3197 {
3198         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3199         int change;
3200         unsigned int val;
3201
3202         if (!snd_hdspm_use_is_exclusive(hdspm))
3203                 return -EBUSY;
3204         val = ucontrol->value.integer.value[0] & 1;
3205         spin_lock_irq(&hdspm->lock);
3206         change = (int) val != hdspm_input_select(hdspm);
3207         hdspm_set_input_select(hdspm, val);
3208         spin_unlock_irq(&hdspm->lock);
3209         return change;
3210 }
3211
3212
3213 #define HDSPM_DS_WIRE(xname, xindex) \
3214 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3215         .name = xname, \
3216         .index = xindex, \
3217         .info = snd_hdspm_info_ds_wire, \
3218         .get = snd_hdspm_get_ds_wire, \
3219         .put = snd_hdspm_put_ds_wire \
3220 }
3221
3222 static int hdspm_ds_wire(struct hdspm * hdspm)
3223 {
3224         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3225 }
3226
3227 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3228 {
3229         if (ds)
3230                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3231         else
3232                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3233         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3234
3235         return 0;
3236 }
3237
3238 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3239                                   struct snd_ctl_elem_info *uinfo)
3240 {
3241         static char *texts[] = { "Single", "Double" };
3242         ENUMERATED_CTL_INFO(uinfo, texts);
3243         return 0;
3244 }
3245
3246 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3247                                  struct snd_ctl_elem_value *ucontrol)
3248 {
3249         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3250
3251         spin_lock_irq(&hdspm->lock);
3252         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3253         spin_unlock_irq(&hdspm->lock);
3254         return 0;
3255 }
3256
3257 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3258                                  struct snd_ctl_elem_value *ucontrol)
3259 {
3260         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3261         int change;
3262         unsigned int val;
3263
3264         if (!snd_hdspm_use_is_exclusive(hdspm))
3265                 return -EBUSY;
3266         val = ucontrol->value.integer.value[0] & 1;
3267         spin_lock_irq(&hdspm->lock);
3268         change = (int) val != hdspm_ds_wire(hdspm);
3269         hdspm_set_ds_wire(hdspm, val);
3270         spin_unlock_irq(&hdspm->lock);
3271         return change;
3272 }
3273
3274
3275 #define HDSPM_QS_WIRE(xname, xindex) \
3276 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3277         .name = xname, \
3278         .index = xindex, \
3279         .info = snd_hdspm_info_qs_wire, \
3280         .get = snd_hdspm_get_qs_wire, \
3281         .put = snd_hdspm_put_qs_wire \
3282 }
3283
3284 static int hdspm_qs_wire(struct hdspm * hdspm)
3285 {
3286         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3287                 return 1;
3288         if (hdspm->control_register & HDSPM_QS_QuadWire)
3289                 return 2;
3290         return 0;
3291 }
3292
3293 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3294 {
3295         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3296         switch (mode) {
3297         case 0:
3298                 break;
3299         case 1:
3300                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3301                 break;
3302         case 2:
3303                 hdspm->control_register |= HDSPM_QS_QuadWire;
3304                 break;
3305         }
3306         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3307
3308         return 0;
3309 }
3310
3311 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3312                                        struct snd_ctl_elem_info *uinfo)
3313 {
3314         static char *texts[] = { "Single", "Double", "Quad" };
3315         ENUMERATED_CTL_INFO(uinfo, texts);
3316         return 0;
3317 }
3318
3319 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3320                                       struct snd_ctl_elem_value *ucontrol)
3321 {
3322         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3323
3324         spin_lock_irq(&hdspm->lock);
3325         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3326         spin_unlock_irq(&hdspm->lock);
3327         return 0;
3328 }
3329
3330 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3331                                       struct snd_ctl_elem_value *ucontrol)
3332 {
3333         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3334         int change;
3335         int val;
3336
3337         if (!snd_hdspm_use_is_exclusive(hdspm))
3338                 return -EBUSY;
3339         val = ucontrol->value.integer.value[0];
3340         if (val < 0)
3341                 val = 0;
3342         if (val > 2)
3343                 val = 2;
3344         spin_lock_irq(&hdspm->lock);
3345         change = val != hdspm_qs_wire(hdspm);
3346         hdspm_set_qs_wire(hdspm, val);
3347         spin_unlock_irq(&hdspm->lock);
3348         return change;
3349 }
3350
3351 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \
3352 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3353         .name = xname, \
3354         .private_value = xindex, \
3355         .info = snd_hdspm_info_tristate, \
3356         .get = snd_hdspm_get_tristate, \
3357         .put = snd_hdspm_put_tristate \
3358 }
3359
3360 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3361 {
3362         u32 reg = hdspm->settings_register & (regmask * 3);
3363         return reg / regmask;
3364 }
3365
3366 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3367 {
3368         hdspm->settings_register &= ~(regmask * 3);
3369         hdspm->settings_register |= (regmask * mode);
3370         hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3371
3372         return 0;
3373 }
3374
3375 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol,
3376                                        struct snd_ctl_elem_info *uinfo)
3377 {
3378         u32 regmask = kcontrol->private_value;
3379
3380         static char *texts_spdif[] = { "Optical", "Coaxial", "Internal" };
3381         static char *texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
3382
3383         switch (regmask) {
3384         case HDSPM_c0_Input0:
3385                 ENUMERATED_CTL_INFO(uinfo, texts_spdif);
3386                 break;
3387         default:
3388                 ENUMERATED_CTL_INFO(uinfo, texts_levels);
3389                 break;
3390         }
3391         return 0;
3392 }
3393
3394 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol,
3395                                       struct snd_ctl_elem_value *ucontrol)
3396 {
3397         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3398         u32 regmask = kcontrol->private_value;
3399
3400         spin_lock_irq(&hdspm->lock);
3401         ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3402         spin_unlock_irq(&hdspm->lock);
3403         return 0;
3404 }
3405
3406 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol,
3407                                       struct snd_ctl_elem_value *ucontrol)
3408 {
3409         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3410         u32 regmask = kcontrol->private_value;
3411         int change;
3412         int val;
3413
3414         if (!snd_hdspm_use_is_exclusive(hdspm))
3415                 return -EBUSY;
3416         val = ucontrol->value.integer.value[0];
3417         if (val < 0)
3418                 val = 0;
3419         if (val > 2)
3420                 val = 2;
3421
3422         spin_lock_irq(&hdspm->lock);
3423         change = val != hdspm_tristate(hdspm, regmask);
3424         hdspm_set_tristate(hdspm, val, regmask);
3425         spin_unlock_irq(&hdspm->lock);
3426         return change;
3427 }
3428
3429 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3430 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3431         .name = xname, \
3432         .index = xindex, \
3433         .info = snd_hdspm_info_madi_speedmode, \
3434         .get = snd_hdspm_get_madi_speedmode, \
3435         .put = snd_hdspm_put_madi_speedmode \
3436 }
3437
3438 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3439 {
3440         if (hdspm->control_register & HDSPM_QuadSpeed)
3441                 return 2;
3442         if (hdspm->control_register & HDSPM_DoubleSpeed)
3443                 return 1;
3444         return 0;
3445 }
3446
3447 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3448 {
3449         hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3450         switch (mode) {
3451         case 0:
3452                 break;
3453         case 1:
3454                 hdspm->control_register |= HDSPM_DoubleSpeed;
3455                 break;
3456         case 2:
3457                 hdspm->control_register |= HDSPM_QuadSpeed;
3458                 break;
3459         }
3460         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3461
3462         return 0;
3463 }
3464
3465 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3466                                        struct snd_ctl_elem_info *uinfo)
3467 {
3468         static char *texts[] = { "Single", "Double", "Quad" };
3469         ENUMERATED_CTL_INFO(uinfo, texts);
3470         return 0;
3471 }
3472
3473 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3474                                       struct snd_ctl_elem_value *ucontrol)
3475 {
3476         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3477
3478         spin_lock_irq(&hdspm->lock);
3479         ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3480         spin_unlock_irq(&hdspm->lock);
3481         return 0;
3482 }
3483
3484 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3485                                       struct snd_ctl_elem_value *ucontrol)
3486 {
3487         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3488         int change;
3489         int val;
3490
3491         if (!snd_hdspm_use_is_exclusive(hdspm))
3492                 return -EBUSY;
3493         val = ucontrol->value.integer.value[0];
3494         if (val < 0)
3495                 val = 0;
3496         if (val > 2)
3497                 val = 2;
3498         spin_lock_irq(&hdspm->lock);
3499         change = val != hdspm_madi_speedmode(hdspm);
3500         hdspm_set_madi_speedmode(hdspm, val);
3501         spin_unlock_irq(&hdspm->lock);
3502         return change;
3503 }
3504
3505 #define HDSPM_MIXER(xname, xindex) \
3506 {       .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3507         .name = xname, \
3508         .index = xindex, \
3509         .device = 0, \
3510         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3511                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3512         .info = snd_hdspm_info_mixer, \
3513         .get = snd_hdspm_get_mixer, \
3514         .put = snd_hdspm_put_mixer \
3515 }
3516
3517 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3518                                 struct snd_ctl_elem_info *uinfo)
3519 {
3520         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3521         uinfo->count = 3;
3522         uinfo->value.integer.min = 0;
3523         uinfo->value.integer.max = 65535;
3524         uinfo->value.integer.step = 1;
3525         return 0;
3526 }
3527
3528 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3529                                struct snd_ctl_elem_value *ucontrol)
3530 {
3531         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3532         int source;
3533         int destination;
3534
3535         source = ucontrol->value.integer.value[0];
3536         if (source < 0)
3537                 source = 0;
3538         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3539                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3540
3541         destination = ucontrol->value.integer.value[1];
3542         if (destination < 0)
3543                 destination = 0;
3544         else if (destination >= HDSPM_MAX_CHANNELS)
3545                 destination = HDSPM_MAX_CHANNELS - 1;
3546
3547         spin_lock_irq(&hdspm->lock);
3548         if (source >= HDSPM_MAX_CHANNELS)
3549                 ucontrol->value.integer.value[2] =
3550                     hdspm_read_pb_gain(hdspm, destination,
3551                                        source - HDSPM_MAX_CHANNELS);
3552         else
3553                 ucontrol->value.integer.value[2] =
3554                     hdspm_read_in_gain(hdspm, destination, source);
3555
3556         spin_unlock_irq(&hdspm->lock);
3557
3558         return 0;
3559 }
3560
3561 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3562                                struct snd_ctl_elem_value *ucontrol)
3563 {
3564         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3565         int change;
3566         int source;
3567         int destination;
3568         int gain;
3569
3570         if (!snd_hdspm_use_is_exclusive(hdspm))
3571                 return -EBUSY;
3572
3573         source = ucontrol->value.integer.value[0];
3574         destination = ucontrol->value.integer.value[1];
3575
3576         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3577                 return -1;
3578         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3579                 return -1;
3580
3581         gain = ucontrol->value.integer.value[2];
3582
3583         spin_lock_irq(&hdspm->lock);
3584
3585         if (source >= HDSPM_MAX_CHANNELS)
3586                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3587                                                     source -
3588                                                     HDSPM_MAX_CHANNELS);
3589         else
3590                 change = gain != hdspm_read_in_gain(hdspm, destination,
3591                                                     source);
3592
3593         if (change) {
3594                 if (source >= HDSPM_MAX_CHANNELS)
3595                         hdspm_write_pb_gain(hdspm, destination,
3596                                             source - HDSPM_MAX_CHANNELS,
3597                                             gain);
3598                 else
3599                         hdspm_write_in_gain(hdspm, destination, source,
3600                                             gain);
3601         }
3602         spin_unlock_irq(&hdspm->lock);
3603
3604         return change;
3605 }
3606
3607 /* The simple mixer control(s) provide gain control for the
3608    basic 1:1 mappings of playback streams to output
3609    streams.
3610 */
3611
3612 #define HDSPM_PLAYBACK_MIXER \
3613 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3614         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3615                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3616         .info = snd_hdspm_info_playback_mixer, \
3617         .get = snd_hdspm_get_playback_mixer, \
3618         .put = snd_hdspm_put_playback_mixer \
3619 }
3620
3621 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3622                                          struct snd_ctl_elem_info *uinfo)
3623 {
3624         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3625         uinfo->count = 1;
3626         uinfo->value.integer.min = 0;
3627         uinfo->value.integer.max = 64;
3628         uinfo->value.integer.step = 1;
3629         return 0;
3630 }
3631
3632 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3633                                         struct snd_ctl_elem_value *ucontrol)
3634 {
3635         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3636         int channel;
3637
3638         channel = ucontrol->id.index - 1;
3639
3640         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3641                 return -EINVAL;
3642
3643         spin_lock_irq(&hdspm->lock);
3644         ucontrol->value.integer.value[0] =
3645           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3646         spin_unlock_irq(&hdspm->lock);
3647
3648         return 0;
3649 }
3650
3651 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3652                                         struct snd_ctl_elem_value *ucontrol)
3653 {
3654         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3655         int change;
3656         int channel;
3657         int gain;
3658
3659         if (!snd_hdspm_use_is_exclusive(hdspm))
3660                 return -EBUSY;
3661
3662         channel = ucontrol->id.index - 1;
3663
3664         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3665                 return -EINVAL;
3666
3667         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3668
3669         spin_lock_irq(&hdspm->lock);
3670         change =
3671             gain != hdspm_read_pb_gain(hdspm, channel,
3672                                        channel);
3673         if (change)
3674                 hdspm_write_pb_gain(hdspm, channel, channel,
3675                                     gain);
3676         spin_unlock_irq(&hdspm->lock);
3677         return change;
3678 }
3679
3680 #define HDSPM_SYNC_CHECK(xname, xindex) \
3681 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3682         .name = xname, \
3683         .private_value = xindex, \
3684         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3685         .info = snd_hdspm_info_sync_check, \
3686         .get = snd_hdspm_get_sync_check \
3687 }
3688
3689 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3690 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3691         .name = xname, \
3692         .private_value = xindex, \
3693         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3694         .info = snd_hdspm_tco_info_lock_check, \
3695         .get = snd_hdspm_get_sync_check \
3696 }
3697
3698
3699
3700 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3701                                      struct snd_ctl_elem_info *uinfo)
3702 {
3703         static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3704         ENUMERATED_CTL_INFO(uinfo, texts);
3705         return 0;
3706 }
3707
3708 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3709                                      struct snd_ctl_elem_info *uinfo)
3710 {
3711         static char *texts[] = { "No Lock", "Lock" };
3712         ENUMERATED_CTL_INFO(uinfo, texts);
3713         return 0;
3714 }
3715
3716 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3717 {
3718         int status, status2;
3719
3720         switch (hdspm->io_type) {
3721         case AES32:
3722                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3723                 if (status & HDSPM_AES32_wcLock) {
3724                         if (status & HDSPM_AES32_wcSync)
3725                                 return 2;
3726                         else
3727                                 return 1;
3728                 }
3729                 return 0;
3730                 break;
3731
3732         case MADI:
3733                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3734                 if (status2 & HDSPM_wcLock) {
3735                         if (status2 & HDSPM_wcSync)
3736                                 return 2;
3737                         else
3738                                 return 1;
3739                 }
3740                 return 0;
3741                 break;
3742
3743         case RayDAT:
3744         case AIO:
3745                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3746
3747                 if (status & 0x2000000)
3748                         return 2;
3749                 else if (status & 0x1000000)
3750                         return 1;
3751                 return 0;
3752
3753                 break;
3754
3755         case MADIface:
3756                 break;
3757         }
3758
3759
3760         return 3;
3761 }
3762
3763
3764 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3765 {
3766         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3767         if (status & HDSPM_madiLock) {
3768                 if (status & HDSPM_madiSync)
3769                         return 2;
3770                 else
3771                         return 1;
3772         }
3773         return 0;
3774 }
3775
3776
3777 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3778 {
3779         int status, lock, sync;
3780
3781         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3782
3783         lock = (status & (0x1<<idx)) ? 1 : 0;
3784         sync = (status & (0x100<<idx)) ? 1 : 0;
3785
3786         if (lock && sync)
3787                 return 2;
3788         else if (lock)
3789                 return 1;
3790         return 0;
3791 }
3792
3793
3794 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3795 {
3796         int status, lock = 0, sync = 0;
3797
3798         switch (hdspm->io_type) {
3799         case RayDAT:
3800         case AIO:
3801                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3802                 lock = (status & 0x400) ? 1 : 0;
3803                 sync = (status & 0x800) ? 1 : 0;
3804                 break;
3805
3806         case MADI:
3807                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3808                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3809                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3810                 break;
3811
3812         case AES32:
3813                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3814                 lock = (status & 0x100000) ? 1 : 0;
3815                 sync = (status & 0x200000) ? 1 : 0;
3816                 break;
3817
3818         case MADIface:
3819                 break;
3820         }
3821
3822         if (lock && sync)
3823                 return 2;
3824         else if (lock)
3825                 return 1;
3826
3827         return 0;
3828 }
3829
3830 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3831 {
3832         int status2, lock, sync;
3833         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3834
3835         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3836         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3837
3838         if (sync)
3839                 return 2;
3840         else if (lock)
3841                 return 1;
3842         return 0;
3843 }
3844
3845 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3846 {
3847         u32 status;
3848         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3849
3850         return (status & mask) ? 1 : 0;
3851 }
3852
3853
3854 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3855 {
3856         int status;
3857
3858         if (hdspm->tco) {
3859                 switch (hdspm->io_type) {
3860                 case MADI:
3861                 case AES32:
3862                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3863                         if (status & HDSPM_tcoLock) {
3864                                 if (status & HDSPM_tcoSync)
3865                                         return 2;
3866                                 else
3867                                         return 1;
3868                         }
3869                         return 0;
3870
3871                         break;
3872
3873                 case RayDAT:
3874                 case AIO:
3875                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3876
3877                         if (status & 0x8000000)
3878                                 return 2; /* Sync */
3879                         if (status & 0x4000000)
3880                                 return 1; /* Lock */
3881                         return 0; /* No signal */
3882                         break;
3883
3884                 default:
3885                         break;
3886                 }
3887         }
3888
3889         return 3; /* N/A */
3890 }
3891
3892
3893 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3894                                     struct snd_ctl_elem_value *ucontrol)
3895 {
3896         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3897         int val = -1;
3898
3899         switch (hdspm->io_type) {
3900         case RayDAT:
3901                 switch (kcontrol->private_value) {
3902                 case 0: /* WC */
3903                         val = hdspm_wc_sync_check(hdspm); break;
3904                 case 7: /* TCO */
3905                         val = hdspm_tco_sync_check(hdspm); break;
3906                 case 8: /* SYNC IN */
3907                         val = hdspm_sync_in_sync_check(hdspm); break;
3908                 default:
3909                         val = hdspm_s1_sync_check(hdspm,
3910                                         kcontrol->private_value-1);
3911                 }
3912                 break;
3913
3914         case AIO:
3915                 switch (kcontrol->private_value) {
3916                 case 0: /* WC */
3917                         val = hdspm_wc_sync_check(hdspm); break;
3918                 case 4: /* TCO */
3919                         val = hdspm_tco_sync_check(hdspm); break;
3920                 case 5: /* SYNC IN */
3921                         val = hdspm_sync_in_sync_check(hdspm); break;
3922                 default:
3923                         val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3924                 }
3925                 break;
3926
3927         case MADI:
3928                 switch (kcontrol->private_value) {
3929                 case 0: /* WC */
3930                         val = hdspm_wc_sync_check(hdspm); break;
3931                 case 1: /* MADI */
3932                         val = hdspm_madi_sync_check(hdspm); break;
3933                 case 2: /* TCO */
3934                         val = hdspm_tco_sync_check(hdspm); break;
3935                 case 3: /* SYNC_IN */
3936                         val = hdspm_sync_in_sync_check(hdspm); break;
3937                 }
3938                 break;
3939
3940         case MADIface:
3941                 val = hdspm_madi_sync_check(hdspm); /* MADI */
3942                 break;
3943
3944         case AES32:
3945                 switch (kcontrol->private_value) {
3946                 case 0: /* WC */
3947                         val = hdspm_wc_sync_check(hdspm); break;
3948                 case 9: /* TCO */
3949                         val = hdspm_tco_sync_check(hdspm); break;
3950                 case 10 /* SYNC IN */:
3951                         val = hdspm_sync_in_sync_check(hdspm); break;
3952                 default: /* AES1 to AES8 */
3953                          val = hdspm_aes_sync_check(hdspm,
3954                                          kcontrol->private_value-1);
3955                 }
3956                 break;
3957
3958         }
3959
3960         if (hdspm->tco) {
3961                 switch (kcontrol->private_value) {
3962                 case 11:
3963                         /* Check TCO for lock state of its current input */
3964                         val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
3965                         break;
3966                 case 12:
3967                         /* Check TCO for valid time code on LTC input. */
3968                         val = hdspm_tco_input_check(hdspm,
3969                                 HDSPM_TCO1_LTC_Input_valid);
3970                         break;
3971                 default:
3972                         break;
3973                 }
3974         }
3975
3976         if (-1 == val)
3977                 val = 3;
3978
3979         ucontrol->value.enumerated.item[0] = val;
3980         return 0;
3981 }
3982
3983
3984
3985 /**
3986  * TCO controls
3987  **/
3988 static void hdspm_tco_write(struct hdspm *hdspm)
3989 {
3990         unsigned int tc[4] = { 0, 0, 0, 0};
3991
3992         switch (hdspm->tco->input) {
3993         case 0:
3994                 tc[2] |= HDSPM_TCO2_set_input_MSB;
3995                 break;
3996         case 1:
3997                 tc[2] |= HDSPM_TCO2_set_input_LSB;
3998                 break;
3999         default:
4000                 break;
4001         }
4002
4003         switch (hdspm->tco->framerate) {
4004         case 1:
4005                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4006                 break;
4007         case 2:
4008                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4009                 break;
4010         case 3:
4011                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4012                         HDSPM_TCO1_set_drop_frame_flag;
4013                 break;
4014         case 4:
4015                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4016                         HDSPM_TCO1_LTC_Format_MSB;
4017                 break;
4018         case 5:
4019                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4020                         HDSPM_TCO1_LTC_Format_MSB +
4021                         HDSPM_TCO1_set_drop_frame_flag;
4022                 break;
4023         default:
4024                 break;
4025         }
4026
4027         switch (hdspm->tco->wordclock) {
4028         case 1:
4029                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4030                 break;
4031         case 2:
4032                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4033                 break;
4034         default:
4035                 break;
4036         }
4037
4038         switch (hdspm->tco->samplerate) {
4039         case 1:
4040                 tc[2] |= HDSPM_TCO2_set_freq;
4041                 break;
4042         case 2:
4043                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4044                 break;
4045         default:
4046                 break;
4047         }
4048
4049         switch (hdspm->tco->pull) {
4050         case 1:
4051                 tc[2] |= HDSPM_TCO2_set_pull_up;
4052                 break;
4053         case 2:
4054                 tc[2] |= HDSPM_TCO2_set_pull_down;
4055                 break;
4056         case 3:
4057                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4058                 break;
4059         case 4:
4060                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4061                 break;
4062         default:
4063                 break;
4064         }
4065
4066         if (1 == hdspm->tco->term) {
4067                 tc[2] |= HDSPM_TCO2_set_term_75R;
4068         }
4069
4070         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4071         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4072         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4073         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4074 }
4075
4076
4077 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4078 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4079         .name = xname, \
4080         .index = xindex, \
4081         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4082                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4083         .info = snd_hdspm_info_tco_sample_rate, \
4084         .get = snd_hdspm_get_tco_sample_rate, \
4085         .put = snd_hdspm_put_tco_sample_rate \
4086 }
4087
4088 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4089                                           struct snd_ctl_elem_info *uinfo)
4090 {
4091         static char *texts[] = { "44.1 kHz", "48 kHz" };
4092         ENUMERATED_CTL_INFO(uinfo, texts);
4093         return 0;
4094 }
4095
4096 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4097                                       struct snd_ctl_elem_value *ucontrol)
4098 {
4099         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4100
4101         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4102
4103         return 0;
4104 }
4105
4106 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4107                                          struct snd_ctl_elem_value *ucontrol)
4108 {
4109         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4110
4111         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4112                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4113
4114                 hdspm_tco_write(hdspm);
4115
4116                 return 1;
4117         }
4118
4119         return 0;
4120 }
4121
4122
4123 #define HDSPM_TCO_PULL(xname, xindex) \
4124 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4125         .name = xname, \
4126         .index = xindex, \
4127         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4128                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4129         .info = snd_hdspm_info_tco_pull, \
4130         .get = snd_hdspm_get_tco_pull, \
4131         .put = snd_hdspm_put_tco_pull \
4132 }
4133
4134 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4135                                    struct snd_ctl_elem_info *uinfo)
4136 {
4137         static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4138         ENUMERATED_CTL_INFO(uinfo, texts);
4139         return 0;
4140 }
4141
4142 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4143                                   struct snd_ctl_elem_value *ucontrol)
4144 {
4145         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4146
4147         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4148
4149         return 0;
4150 }
4151
4152 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4153                                   struct snd_ctl_elem_value *ucontrol)
4154 {
4155         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4156
4157         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4158                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4159
4160                 hdspm_tco_write(hdspm);
4161
4162                 return 1;
4163         }
4164
4165         return 0;
4166 }
4167
4168 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4169 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4170         .name = xname, \
4171         .index = xindex, \
4172         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4173                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4174         .info = snd_hdspm_info_tco_wck_conversion, \
4175         .get = snd_hdspm_get_tco_wck_conversion, \
4176         .put = snd_hdspm_put_tco_wck_conversion \
4177 }
4178
4179 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4180                                              struct snd_ctl_elem_info *uinfo)
4181 {
4182         static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4183         ENUMERATED_CTL_INFO(uinfo, texts);
4184         return 0;
4185 }
4186
4187 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4188                                             struct snd_ctl_elem_value *ucontrol)
4189 {
4190         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4191
4192         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4193
4194         return 0;
4195 }
4196
4197 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4198                                             struct snd_ctl_elem_value *ucontrol)
4199 {
4200         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4201
4202         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4203                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4204
4205                 hdspm_tco_write(hdspm);
4206
4207                 return 1;
4208         }
4209
4210         return 0;
4211 }
4212
4213
4214 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4215 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4216         .name = xname, \
4217         .index = xindex, \
4218         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4219                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4220         .info = snd_hdspm_info_tco_frame_rate, \
4221         .get = snd_hdspm_get_tco_frame_rate, \
4222         .put = snd_hdspm_put_tco_frame_rate \
4223 }
4224
4225 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4226                                           struct snd_ctl_elem_info *uinfo)
4227 {
4228         static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4229                 "29.97 dfps", "30 fps", "30 dfps" };
4230         ENUMERATED_CTL_INFO(uinfo, texts);
4231         return 0;
4232 }
4233
4234 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4235                                         struct snd_ctl_elem_value *ucontrol)
4236 {
4237         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4238
4239         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4240
4241         return 0;
4242 }
4243
4244 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4245                                         struct snd_ctl_elem_value *ucontrol)
4246 {
4247         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4248
4249         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4250                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4251
4252                 hdspm_tco_write(hdspm);
4253
4254                 return 1;
4255         }
4256
4257         return 0;
4258 }
4259
4260
4261 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4262 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4263         .name = xname, \
4264         .index = xindex, \
4265         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4266                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4267         .info = snd_hdspm_info_tco_sync_source, \
4268         .get = snd_hdspm_get_tco_sync_source, \
4269         .put = snd_hdspm_put_tco_sync_source \
4270 }
4271
4272 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4273                                           struct snd_ctl_elem_info *uinfo)
4274 {
4275         static char *texts[] = { "LTC", "Video", "WCK" };
4276         ENUMERATED_CTL_INFO(uinfo, texts);
4277         return 0;
4278 }
4279
4280 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4281                                          struct snd_ctl_elem_value *ucontrol)
4282 {
4283         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4284
4285         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4286
4287         return 0;
4288 }
4289
4290 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4291                                          struct snd_ctl_elem_value *ucontrol)
4292 {
4293         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4294
4295         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4296                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4297
4298                 hdspm_tco_write(hdspm);
4299
4300                 return 1;
4301         }
4302
4303         return 0;
4304 }
4305
4306
4307 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4308 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4309         .name = xname, \
4310         .index = xindex, \
4311         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4312                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4313         .info = snd_hdspm_info_tco_word_term, \
4314         .get = snd_hdspm_get_tco_word_term, \
4315         .put = snd_hdspm_put_tco_word_term \
4316 }
4317
4318 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4319                                         struct snd_ctl_elem_info *uinfo)
4320 {
4321         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4322         uinfo->count = 1;
4323         uinfo->value.integer.min = 0;
4324         uinfo->value.integer.max = 1;
4325
4326         return 0;
4327 }
4328
4329
4330 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4331                                        struct snd_ctl_elem_value *ucontrol)
4332 {
4333         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4334
4335         ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4336
4337         return 0;
4338 }
4339
4340
4341 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4342                                        struct snd_ctl_elem_value *ucontrol)
4343 {
4344         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4345
4346         if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4347                 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4348
4349                 hdspm_tco_write(hdspm);
4350
4351                 return 1;
4352         }
4353
4354         return 0;
4355 }
4356
4357
4358
4359
4360 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4361         HDSPM_MIXER("Mixer", 0),
4362         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4363         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4364         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4365         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4366         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4367         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4368         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4369         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4370         HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4371         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4372         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4373         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4374         HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4375         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4376         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4377         HDSPM_INPUT_SELECT("Input Select", 0),
4378         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4379 };
4380
4381
4382 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4383         HDSPM_MIXER("Mixer", 0),
4384         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4385         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4386         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4387         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4388         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4389         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4390         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4391         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4392         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4393 };
4394
4395 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4396         HDSPM_MIXER("Mixer", 0),
4397         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4398         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4399         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4400         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4401         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4402         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4403         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4404         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4405         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4406         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4407         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4408         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4409         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4410         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4411         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4412         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4413         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4414         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
4415         HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt),
4416         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4417         HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1),
4418         HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db),
4419         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
4420
4421                 /*
4422                    HDSPM_INPUT_SELECT("Input Select", 0),
4423                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4424                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4425                    HDSPM_SPDIF_IN("SPDIF In", 0);
4426                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4427                    HDSPM_INPUT_LEVEL("Input Level", 0);
4428                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4429                    HDSPM_PHONES("Phones", 0);
4430                    */
4431 };
4432
4433 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4434         HDSPM_MIXER("Mixer", 0),
4435         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4436         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4437         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4438         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4439         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4440         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4441         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4442         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4443         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4444         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4445         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4446         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4447         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4448         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4449         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4450         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4451         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4452         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4453         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4454         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4455         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4456         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4457         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4458         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
4459 };
4460
4461 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4462         HDSPM_MIXER("Mixer", 0),
4463         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4464         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4465         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4466         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4467         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4468         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4469         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4470         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4471         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4472         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4473         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4474         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4475         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4476         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4477         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4478         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4479         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4480         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4481         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4482         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4483         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4484         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4485         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4486         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4487         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4488         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4489         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4490         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4491         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4492         HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4493         HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4494         HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4495         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4496         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4497         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4498 };
4499
4500
4501
4502 /* Control elements for the optional TCO module */
4503 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4504         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4505         HDSPM_TCO_PULL("TCO Pull", 0),
4506         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4507         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4508         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4509         HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4510         HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4511         HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4512         HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4513         HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4514 };
4515
4516
4517 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4518
4519
4520 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4521 {
4522         int i;
4523
4524         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4525                 if (hdspm->system_sample_rate > 48000) {
4526                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4527                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4528                                 SNDRV_CTL_ELEM_ACCESS_READ |
4529                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4530                 } else {
4531                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4532                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4533                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4534                 }
4535                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4536                                 SNDRV_CTL_EVENT_MASK_INFO,
4537                                 &hdspm->playback_mixer_ctls[i]->id);
4538         }
4539
4540         return 0;
4541 }
4542
4543
4544 static int snd_hdspm_create_controls(struct snd_card *card,
4545                                         struct hdspm *hdspm)
4546 {
4547         unsigned int idx, limit;
4548         int err;
4549         struct snd_kcontrol *kctl;
4550         struct snd_kcontrol_new *list = NULL;
4551
4552         switch (hdspm->io_type) {
4553         case MADI:
4554                 list = snd_hdspm_controls_madi;
4555                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4556                 break;
4557         case MADIface:
4558                 list = snd_hdspm_controls_madiface;
4559                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4560                 break;
4561         case AIO:
4562                 list = snd_hdspm_controls_aio;
4563                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4564                 break;
4565         case RayDAT:
4566                 list = snd_hdspm_controls_raydat;
4567                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4568                 break;
4569         case AES32:
4570                 list = snd_hdspm_controls_aes32;
4571                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4572                 break;
4573         }
4574
4575         if (NULL != list) {
4576                 for (idx = 0; idx < limit; idx++) {
4577                         err = snd_ctl_add(card,
4578                                         snd_ctl_new1(&list[idx], hdspm));
4579                         if (err < 0)
4580                                 return err;
4581                 }
4582         }
4583
4584
4585         /* create simple 1:1 playback mixer controls */
4586         snd_hdspm_playback_mixer.name = "Chn";
4587         if (hdspm->system_sample_rate >= 128000) {
4588                 limit = hdspm->qs_out_channels;
4589         } else if (hdspm->system_sample_rate >= 64000) {
4590                 limit = hdspm->ds_out_channels;
4591         } else {
4592                 limit = hdspm->ss_out_channels;
4593         }
4594         for (idx = 0; idx < limit; ++idx) {
4595                 snd_hdspm_playback_mixer.index = idx + 1;
4596                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4597                 err = snd_ctl_add(card, kctl);
4598                 if (err < 0)
4599                         return err;
4600                 hdspm->playback_mixer_ctls[idx] = kctl;
4601         }
4602
4603
4604         if (hdspm->tco) {
4605                 /* add tco control elements */
4606                 list = snd_hdspm_controls_tco;
4607                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4608                 for (idx = 0; idx < limit; idx++) {
4609                         err = snd_ctl_add(card,
4610                                         snd_ctl_new1(&list[idx], hdspm));
4611                         if (err < 0)
4612                                 return err;
4613                 }
4614         }
4615
4616         return 0;
4617 }
4618
4619 /*------------------------------------------------------------
4620    /proc interface
4621  ------------------------------------------------------------*/
4622
4623 static void
4624 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4625                          struct snd_info_buffer *buffer)
4626 {
4627         struct hdspm *hdspm = entry->private_data;
4628         unsigned int status, status2, control, freq;
4629
4630         char *pref_sync_ref;
4631         char *autosync_ref;
4632         char *system_clock_mode;
4633         char *insel;
4634         int x, x2;
4635
4636         /* TCO stuff */
4637         int a, ltc, frames, seconds, minutes, hours;
4638         unsigned int period;
4639         u64 freq_const = 0;
4640         u32 rate;
4641
4642         status = hdspm_read(hdspm, HDSPM_statusRegister);
4643         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4644         control = hdspm->control_register;
4645         freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4646
4647         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4648                         hdspm->card_name, hdspm->card->number + 1,
4649                         hdspm->firmware_rev,
4650                         (status2 & HDSPM_version0) |
4651                         (status2 & HDSPM_version1) | (status2 &
4652                                 HDSPM_version2));
4653
4654         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4655                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4656                         hdspm->serial);
4657
4658         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4659                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4660
4661         snd_iprintf(buffer, "--- System ---\n");
4662
4663         snd_iprintf(buffer,
4664                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4665                 status & HDSPM_audioIRQPending,
4666                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4667                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4668                 hdspm->irq_count);
4669         snd_iprintf(buffer,
4670                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4671                 "estimated= %ld (bytes)\n",
4672                 ((status & HDSPM_BufferID) ? 1 : 0),
4673                 (status & HDSPM_BufferPositionMask),
4674                 (status & HDSPM_BufferPositionMask) %
4675                 (2 * (int)hdspm->period_bytes),
4676                 ((status & HDSPM_BufferPositionMask) - 64) %
4677                 (2 * (int)hdspm->period_bytes),
4678                 (long) hdspm_hw_pointer(hdspm) * 4);
4679
4680         snd_iprintf(buffer,
4681                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4682                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4683                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4684                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4685                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4686         snd_iprintf(buffer,
4687                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4688                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4689                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4690         snd_iprintf(buffer,
4691                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4692                 "status2=0x%x\n",
4693                 hdspm->control_register, hdspm->control2_register,
4694                 status, status2);
4695         if (status & HDSPM_tco_detect) {
4696                 snd_iprintf(buffer, "TCO module detected.\n");
4697                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4698                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4699                         snd_iprintf(buffer, "  LTC valid, ");
4700                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4701                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4702                         case 0:
4703                                 snd_iprintf(buffer, "24 fps, ");
4704                                 break;
4705                         case HDSPM_TCO1_LTC_Format_LSB:
4706                                 snd_iprintf(buffer, "25 fps, ");
4707                                 break;
4708                         case HDSPM_TCO1_LTC_Format_MSB:
4709                                 snd_iprintf(buffer, "29.97 fps, ");
4710                                 break;
4711                         default:
4712                                 snd_iprintf(buffer, "30 fps, ");
4713                                 break;
4714                         }
4715                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4716                                 snd_iprintf(buffer, "drop frame\n");
4717                         } else {
4718                                 snd_iprintf(buffer, "full frame\n");
4719                         }
4720                 } else {
4721                         snd_iprintf(buffer, "  no LTC\n");
4722                 }
4723                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4724                         snd_iprintf(buffer, "  Video: NTSC\n");
4725                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4726                         snd_iprintf(buffer, "  Video: PAL\n");
4727                 } else {
4728                         snd_iprintf(buffer, "  No video\n");
4729                 }
4730                 if (a & HDSPM_TCO1_TCO_lock) {
4731                         snd_iprintf(buffer, "  Sync: lock\n");
4732                 } else {
4733                         snd_iprintf(buffer, "  Sync: no lock\n");
4734                 }
4735
4736                 switch (hdspm->io_type) {
4737                 case MADI:
4738                 case AES32:
4739                         freq_const = 110069313433624ULL;
4740                         break;
4741                 case RayDAT:
4742                 case AIO:
4743                         freq_const = 104857600000000ULL;
4744                         break;
4745                 case MADIface:
4746                         break; /* no TCO possible */
4747                 }
4748
4749                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4750                 snd_iprintf(buffer, "    period: %u\n", period);
4751
4752
4753                 /* rate = freq_const/period; */
4754                 rate = div_u64(freq_const, period);
4755
4756                 if (control & HDSPM_QuadSpeed) {
4757                         rate *= 4;
4758                 } else if (control & HDSPM_DoubleSpeed) {
4759                         rate *= 2;
4760                 }
4761
4762                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4763                                 (unsigned int) rate);
4764
4765                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4766                 frames = ltc & 0xF;
4767                 ltc >>= 4;
4768                 frames += (ltc & 0x3) * 10;
4769                 ltc >>= 4;
4770                 seconds = ltc & 0xF;
4771                 ltc >>= 4;
4772                 seconds += (ltc & 0x7) * 10;
4773                 ltc >>= 4;
4774                 minutes = ltc & 0xF;
4775                 ltc >>= 4;
4776                 minutes += (ltc & 0x7) * 10;
4777                 ltc >>= 4;
4778                 hours = ltc & 0xF;
4779                 ltc >>= 4;
4780                 hours += (ltc & 0x3) * 10;
4781                 snd_iprintf(buffer,
4782                         "  LTC In: %02d:%02d:%02d:%02d\n",
4783                         hours, minutes, seconds, frames);
4784
4785         } else {
4786                 snd_iprintf(buffer, "No TCO module detected.\n");
4787         }
4788
4789         snd_iprintf(buffer, "--- Settings ---\n");
4790
4791         x = hdspm_get_latency(hdspm);
4792
4793         snd_iprintf(buffer,
4794                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4795                 x, (unsigned long) hdspm->period_bytes);
4796
4797         snd_iprintf(buffer, "Line out: %s\n",
4798                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4799
4800         switch (hdspm->control_register & HDSPM_InputMask) {
4801         case HDSPM_InputOptical:
4802                 insel = "Optical";
4803                 break;
4804         case HDSPM_InputCoaxial:
4805                 insel = "Coaxial";
4806                 break;
4807         default:
4808                 insel = "Unknown";
4809         }
4810
4811         snd_iprintf(buffer,
4812                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4813                 "Auto Input %s\n",
4814                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4815                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4816                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4817
4818
4819         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4820                 system_clock_mode = "AutoSync";
4821         else
4822                 system_clock_mode = "Master";
4823         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4824
4825         switch (hdspm_pref_sync_ref(hdspm)) {
4826         case HDSPM_SYNC_FROM_WORD:
4827                 pref_sync_ref = "Word Clock";
4828                 break;
4829         case HDSPM_SYNC_FROM_MADI:
4830                 pref_sync_ref = "MADI Sync";
4831                 break;
4832         case HDSPM_SYNC_FROM_TCO:
4833                 pref_sync_ref = "TCO";
4834                 break;
4835         case HDSPM_SYNC_FROM_SYNC_IN:
4836                 pref_sync_ref = "Sync In";
4837                 break;
4838         default:
4839                 pref_sync_ref = "XXXX Clock";
4840                 break;
4841         }
4842         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4843                         pref_sync_ref);
4844
4845         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4846                         hdspm->system_sample_rate);
4847
4848
4849         snd_iprintf(buffer, "--- Status:\n");
4850
4851         x = status & HDSPM_madiSync;
4852         x2 = status2 & HDSPM_wcSync;
4853
4854         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4855                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4856                         "NoLock",
4857                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4858                         "NoLock");
4859
4860         switch (hdspm_autosync_ref(hdspm)) {
4861         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4862                 autosync_ref = "Sync In";
4863                 break;
4864         case HDSPM_AUTOSYNC_FROM_TCO:
4865                 autosync_ref = "TCO";
4866                 break;
4867         case HDSPM_AUTOSYNC_FROM_WORD:
4868                 autosync_ref = "Word Clock";
4869                 break;
4870         case HDSPM_AUTOSYNC_FROM_MADI:
4871                 autosync_ref = "MADI Sync";
4872                 break;
4873         case HDSPM_AUTOSYNC_FROM_NONE:
4874                 autosync_ref = "Input not valid";
4875                 break;
4876         default:
4877                 autosync_ref = "---";
4878                 break;
4879         }
4880         snd_iprintf(buffer,
4881                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4882                 autosync_ref, hdspm_external_sample_rate(hdspm),
4883                 (status & HDSPM_madiFreqMask) >> 22,
4884                 (status2 & HDSPM_wcFreqMask) >> 5);
4885
4886         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4887                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4888                 (status & HDSPM_RX_64ch) ? "64 channels" :
4889                 "56 channels");
4890
4891         snd_iprintf(buffer, "\n");
4892 }
4893
4894 static void
4895 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4896                           struct snd_info_buffer *buffer)
4897 {
4898         struct hdspm *hdspm = entry->private_data;
4899         unsigned int status;
4900         unsigned int status2;
4901         unsigned int timecode;
4902         unsigned int wcLock, wcSync;
4903         int pref_syncref;
4904         char *autosync_ref;
4905         int x;
4906
4907         status = hdspm_read(hdspm, HDSPM_statusRegister);
4908         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4909         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4910
4911         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4912                     hdspm->card_name, hdspm->card->number + 1,
4913                     hdspm->firmware_rev);
4914
4915         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4916                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4917
4918         snd_iprintf(buffer, "--- System ---\n");
4919
4920         snd_iprintf(buffer,
4921                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4922                     status & HDSPM_audioIRQPending,
4923                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
4924                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
4925                     hdspm->irq_count);
4926         snd_iprintf(buffer,
4927                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
4928                     "estimated= %ld (bytes)\n",
4929                     ((status & HDSPM_BufferID) ? 1 : 0),
4930                     (status & HDSPM_BufferPositionMask),
4931                     (status & HDSPM_BufferPositionMask) %
4932                     (2 * (int)hdspm->period_bytes),
4933                     ((status & HDSPM_BufferPositionMask) - 64) %
4934                     (2 * (int)hdspm->period_bytes),
4935                     (long) hdspm_hw_pointer(hdspm) * 4);
4936
4937         snd_iprintf(buffer,
4938                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4939                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4940                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4941                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4942                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4943         snd_iprintf(buffer,
4944                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4945                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4946                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4947         snd_iprintf(buffer,
4948                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4949                     "status2=0x%x\n",
4950                     hdspm->control_register, hdspm->control2_register,
4951                     status, status2);
4952
4953         snd_iprintf(buffer, "--- Settings ---\n");
4954
4955         x = hdspm_get_latency(hdspm);
4956
4957         snd_iprintf(buffer,
4958                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4959                     x, (unsigned long) hdspm->period_bytes);
4960
4961         snd_iprintf(buffer, "Line out: %s\n",
4962                     (hdspm->
4963                      control_register & HDSPM_LineOut) ? "on " : "off");
4964
4965         snd_iprintf(buffer,
4966                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
4967                     (hdspm->
4968                      control_register & HDSPM_clr_tms) ? "on" : "off",
4969                     (hdspm->
4970                      control_register & HDSPM_Emphasis) ? "on" : "off",
4971                     (hdspm->
4972                      control_register & HDSPM_Dolby) ? "on" : "off");
4973
4974
4975         pref_syncref = hdspm_pref_sync_ref(hdspm);
4976         if (pref_syncref == 0)
4977                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
4978         else
4979                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
4980                                 pref_syncref);
4981
4982         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4983                     hdspm->system_sample_rate);
4984
4985         snd_iprintf(buffer, "Double speed: %s\n",
4986                         hdspm->control_register & HDSPM_DS_DoubleWire?
4987                         "Double wire" : "Single wire");
4988         snd_iprintf(buffer, "Quad speed: %s\n",
4989                         hdspm->control_register & HDSPM_QS_DoubleWire?
4990                         "Double wire" :
4991                         hdspm->control_register & HDSPM_QS_QuadWire?
4992                         "Quad wire" : "Single wire");
4993
4994         snd_iprintf(buffer, "--- Status:\n");
4995
4996         wcLock = status & HDSPM_AES32_wcLock;
4997         wcSync = wcLock && (status & HDSPM_AES32_wcSync);
4998
4999         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
5000                     (wcLock) ? (wcSync ? "Sync   " : "Lock   ") : "No Lock",
5001                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5002
5003         for (x = 0; x < 8; x++) {
5004                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
5005                             x+1,
5006                             (status2 & (HDSPM_LockAES >> x)) ?
5007                             "Sync   " : "No Lock",
5008                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5009         }
5010
5011         switch (hdspm_autosync_ref(hdspm)) {
5012         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5013                 autosync_ref = "None"; break;
5014         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5015                 autosync_ref = "Word Clock"; break;
5016         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5017                 autosync_ref = "AES1"; break;
5018         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5019                 autosync_ref = "AES2"; break;
5020         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5021                 autosync_ref = "AES3"; break;
5022         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5023                 autosync_ref = "AES4"; break;
5024         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5025                 autosync_ref = "AES5"; break;
5026         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5027                 autosync_ref = "AES6"; break;
5028         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5029                 autosync_ref = "AES7"; break;
5030         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5031                 autosync_ref = "AES8"; break;
5032         default:
5033                 autosync_ref = "---"; break;
5034         }
5035         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5036
5037         snd_iprintf(buffer, "\n");
5038 }
5039
5040 static void
5041 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5042                          struct snd_info_buffer *buffer)
5043 {
5044         struct hdspm *hdspm = entry->private_data;
5045         unsigned int status1, status2, status3, control, i;
5046         unsigned int lock, sync;
5047
5048         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5049         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5050         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5051
5052         control = hdspm->control_register;
5053
5054         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5055         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5056         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5057
5058
5059         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5060
5061         snd_iprintf(buffer, "Clock mode      : %s\n",
5062                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5063         snd_iprintf(buffer, "System frequency: %d Hz\n",
5064                 hdspm_get_system_sample_rate(hdspm));
5065
5066         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5067
5068         lock = 0x1;
5069         sync = 0x100;
5070
5071         for (i = 0; i < 8; i++) {
5072                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5073                                 i,
5074                                 (status1 & lock) ? 1 : 0,
5075                                 (status1 & sync) ? 1 : 0,
5076                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
5077
5078                 lock = lock<<1;
5079                 sync = sync<<1;
5080         }
5081
5082         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5083                         (status1 & 0x1000000) ? 1 : 0,
5084                         (status1 & 0x2000000) ? 1 : 0,
5085                         texts_freq[(status1 >> 16) & 0xF]);
5086
5087         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5088                         (status1 & 0x4000000) ? 1 : 0,
5089                         (status1 & 0x8000000) ? 1 : 0,
5090                         texts_freq[(status1 >> 20) & 0xF]);
5091
5092         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5093                         (status3 & 0x400) ? 1 : 0,
5094                         (status3 & 0x800) ? 1 : 0,
5095                         texts_freq[(status2 >> 12) & 0xF]);
5096
5097 }
5098
5099 #ifdef CONFIG_SND_DEBUG
5100 static void
5101 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5102                           struct snd_info_buffer *buffer)
5103 {
5104         struct hdspm *hdspm = entry->private_data;
5105
5106         int j,i;
5107
5108         for (i = 0; i < 256 /* 1024*64 */; i += j) {
5109                 snd_iprintf(buffer, "0x%08X: ", i);
5110                 for (j = 0; j < 16; j += 4)
5111                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5112                 snd_iprintf(buffer, "\n");
5113         }
5114 }
5115 #endif
5116
5117
5118 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5119                           struct snd_info_buffer *buffer)
5120 {
5121         struct hdspm *hdspm = entry->private_data;
5122         int i;
5123
5124         snd_iprintf(buffer, "# generated by hdspm\n");
5125
5126         for (i = 0; i < hdspm->max_channels_in; i++) {
5127                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5128         }
5129 }
5130
5131 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5132                           struct snd_info_buffer *buffer)
5133 {
5134         struct hdspm *hdspm = entry->private_data;
5135         int i;
5136
5137         snd_iprintf(buffer, "# generated by hdspm\n");
5138
5139         for (i = 0; i < hdspm->max_channels_out; i++) {
5140                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5141         }
5142 }
5143
5144
5145 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5146 {
5147         struct snd_info_entry *entry;
5148
5149         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5150                 switch (hdspm->io_type) {
5151                 case AES32:
5152                         snd_info_set_text_ops(entry, hdspm,
5153                                         snd_hdspm_proc_read_aes32);
5154                         break;
5155                 case MADI:
5156                         snd_info_set_text_ops(entry, hdspm,
5157                                         snd_hdspm_proc_read_madi);
5158                         break;
5159                 case MADIface:
5160                         /* snd_info_set_text_ops(entry, hdspm,
5161                          snd_hdspm_proc_read_madiface); */
5162                         break;
5163                 case RayDAT:
5164                         snd_info_set_text_ops(entry, hdspm,
5165                                         snd_hdspm_proc_read_raydat);
5166                         break;
5167                 case AIO:
5168                         break;
5169                 }
5170         }
5171
5172         if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5173                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5174         }
5175
5176         if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5177                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5178         }
5179
5180 #ifdef CONFIG_SND_DEBUG
5181         /* debug file to read all hdspm registers */
5182         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5183                 snd_info_set_text_ops(entry, hdspm,
5184                                 snd_hdspm_proc_read_debug);
5185 #endif
5186 }
5187
5188 /*------------------------------------------------------------
5189    hdspm intitialize
5190  ------------------------------------------------------------*/
5191
5192 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5193 {
5194         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5195            hold it (e.g. during module initialization).
5196            */
5197
5198         /* set defaults:       */
5199
5200         hdspm->settings_register = 0;
5201
5202         switch (hdspm->io_type) {
5203         case MADI:
5204         case MADIface:
5205                 hdspm->control_register =
5206                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5207                 break;
5208
5209         case RayDAT:
5210         case AIO:
5211                 hdspm->settings_register = 0x1 + 0x1000;
5212                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5213                  * line_out */
5214                 hdspm->control_register =
5215                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5216                 break;
5217
5218         case AES32:
5219                 hdspm->control_register =
5220                         HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5221                         hdspm_encode_latency(7) | /* latency max=8192samples */
5222                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5223                         HDSPM_LineOut | /* Analog output in */
5224                         HDSPM_Professional;  /* Professional mode */
5225                 break;
5226         }
5227
5228         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5229
5230         if (AES32 == hdspm->io_type) {
5231                 /* No control2 register for AES32 */
5232 #ifdef SNDRV_BIG_ENDIAN
5233                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5234 #else
5235                 hdspm->control2_register = 0;
5236 #endif
5237
5238                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5239         }
5240         hdspm_compute_period_size(hdspm);
5241
5242         /* silence everything */
5243
5244         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5245
5246         if (hdspm_is_raydat_or_aio(hdspm))
5247                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5248
5249         /* set a default rate so that the channel map is set up. */
5250         hdspm_set_rate(hdspm, 48000, 1);
5251
5252         return 0;
5253 }
5254
5255
5256 /*------------------------------------------------------------
5257    interrupt
5258  ------------------------------------------------------------*/
5259
5260 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5261 {
5262         struct hdspm *hdspm = (struct hdspm *) dev_id;
5263         unsigned int status;
5264         int i, audio, midi, schedule = 0;
5265         /* cycles_t now; */
5266
5267         status = hdspm_read(hdspm, HDSPM_statusRegister);
5268
5269         audio = status & HDSPM_audioIRQPending;
5270         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5271                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5272
5273         /* now = get_cycles(); */
5274         /**
5275          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5276          *          6       4096   ~256053425     ~514672358
5277          *          5       2048   ~128024983     ~257373821
5278          *          4       1024    ~64023706     ~128718089
5279          *          3        512    ~32005945      ~64385999
5280          *          2        256    ~16003039      ~32260176
5281          *          1        128     ~7998738      ~16194507
5282          *          0         64     ~3998231       ~8191558
5283          **/
5284         /*
5285            snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5286            now-hdspm->last_interrupt, status & 0xFFC0);
5287            hdspm->last_interrupt = now;
5288         */
5289
5290         if (!audio && !midi)
5291                 return IRQ_NONE;
5292
5293         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5294         hdspm->irq_count++;
5295
5296
5297         if (audio) {
5298                 if (hdspm->capture_substream)
5299                         snd_pcm_period_elapsed(hdspm->capture_substream);
5300
5301                 if (hdspm->playback_substream)
5302                         snd_pcm_period_elapsed(hdspm->playback_substream);
5303         }
5304
5305         if (midi) {
5306                 i = 0;
5307                 while (i < hdspm->midiPorts) {
5308                         if ((hdspm_read(hdspm,
5309                                 hdspm->midi[i].statusIn) & 0xff) &&
5310                                         (status & hdspm->midi[i].irq)) {
5311                                 /* we disable interrupts for this input until
5312                                  * processing is done
5313                                  */
5314                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5315                                 hdspm_write(hdspm, HDSPM_controlRegister,
5316                                                 hdspm->control_register);
5317                                 hdspm->midi[i].pending = 1;
5318                                 schedule = 1;
5319                         }
5320
5321                         i++;
5322                 }
5323
5324                 if (schedule)
5325                         tasklet_hi_schedule(&hdspm->midi_tasklet);
5326         }
5327
5328         return IRQ_HANDLED;
5329 }
5330
5331 /*------------------------------------------------------------
5332    pcm interface
5333   ------------------------------------------------------------*/
5334
5335
5336 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5337                                               *substream)
5338 {
5339         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5340         return hdspm_hw_pointer(hdspm);
5341 }
5342
5343
5344 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5345 {
5346         struct snd_pcm_runtime *runtime = substream->runtime;
5347         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5348         struct snd_pcm_substream *other;
5349
5350         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5351                 other = hdspm->capture_substream;
5352         else
5353                 other = hdspm->playback_substream;
5354
5355         if (hdspm->running)
5356                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5357         else
5358                 runtime->status->hw_ptr = 0;
5359         if (other) {
5360                 struct snd_pcm_substream *s;
5361                 struct snd_pcm_runtime *oruntime = other->runtime;
5362                 snd_pcm_group_for_each_entry(s, substream) {
5363                         if (s == other) {
5364                                 oruntime->status->hw_ptr =
5365                                         runtime->status->hw_ptr;
5366                                 break;
5367                         }
5368                 }
5369         }
5370         return 0;
5371 }
5372
5373 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5374                                struct snd_pcm_hw_params *params)
5375 {
5376         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5377         int err;
5378         int i;
5379         pid_t this_pid;
5380         pid_t other_pid;
5381
5382         spin_lock_irq(&hdspm->lock);
5383
5384         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5385                 this_pid = hdspm->playback_pid;
5386                 other_pid = hdspm->capture_pid;
5387         } else {
5388                 this_pid = hdspm->capture_pid;
5389                 other_pid = hdspm->playback_pid;
5390         }
5391
5392         if (other_pid > 0 && this_pid != other_pid) {
5393
5394                 /* The other stream is open, and not by the same
5395                    task as this one. Make sure that the parameters
5396                    that matter are the same.
5397                    */
5398
5399                 if (params_rate(params) != hdspm->system_sample_rate) {
5400                         spin_unlock_irq(&hdspm->lock);
5401                         _snd_pcm_hw_param_setempty(params,
5402                                         SNDRV_PCM_HW_PARAM_RATE);
5403                         return -EBUSY;
5404                 }
5405
5406                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5407                         spin_unlock_irq(&hdspm->lock);
5408                         _snd_pcm_hw_param_setempty(params,
5409                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5410                         return -EBUSY;
5411                 }
5412
5413         }
5414         /* We're fine. */
5415         spin_unlock_irq(&hdspm->lock);
5416
5417         /* how to make sure that the rate matches an externally-set one ?   */
5418
5419         spin_lock_irq(&hdspm->lock);
5420         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5421         if (err < 0) {
5422                 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5423                 spin_unlock_irq(&hdspm->lock);
5424                 _snd_pcm_hw_param_setempty(params,
5425                                 SNDRV_PCM_HW_PARAM_RATE);
5426                 return err;
5427         }
5428         spin_unlock_irq(&hdspm->lock);
5429
5430         err = hdspm_set_interrupt_interval(hdspm,
5431                         params_period_size(params));
5432         if (err < 0) {
5433                 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5434                 _snd_pcm_hw_param_setempty(params,
5435                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5436                 return err;
5437         }
5438
5439         /* Memory allocation, takashi's method, dont know if we should
5440          * spinlock
5441          */
5442         /* malloc all buffer even if not enabled to get sure */
5443         /* Update for MADI rev 204: we need to allocate for all channels,
5444          * otherwise it doesn't work at 96kHz */
5445
5446         err =
5447                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5448         if (err < 0) {
5449                 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5450                 return err;
5451         }
5452
5453         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5454
5455                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5456                                 params_channels(params));
5457
5458                 for (i = 0; i < params_channels(params); ++i)
5459                         snd_hdspm_enable_out(hdspm, i, 1);
5460
5461                 hdspm->playback_buffer =
5462                         (unsigned char *) substream->runtime->dma_area;
5463                 snd_printdd("Allocated sample buffer for playback at %p\n",
5464                                 hdspm->playback_buffer);
5465         } else {
5466                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5467                                 params_channels(params));
5468
5469                 for (i = 0; i < params_channels(params); ++i)
5470                         snd_hdspm_enable_in(hdspm, i, 1);
5471
5472                 hdspm->capture_buffer =
5473                         (unsigned char *) substream->runtime->dma_area;
5474                 snd_printdd("Allocated sample buffer for capture at %p\n",
5475                                 hdspm->capture_buffer);
5476         }
5477
5478         /*
5479            snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5480            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5481            "playback" : "capture",
5482            snd_pcm_sgbuf_get_addr(substream, 0));
5483            */
5484         /*
5485            snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5486            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5487            "playback" : "capture",
5488            params_rate(params), params_channels(params),
5489            params_buffer_size(params));
5490            */
5491
5492
5493         /* Switch to native float format if requested */
5494         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5495                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5496                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5497
5498                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5499         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5500                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5501                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5502
5503                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5504         }
5505         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5506
5507         return 0;
5508 }
5509
5510 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5511 {
5512         int i;
5513         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5514
5515         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5516
5517                 /* params_channels(params) should be enough,
5518                    but to get sure in case of error */
5519                 for (i = 0; i < hdspm->max_channels_out; ++i)
5520                         snd_hdspm_enable_out(hdspm, i, 0);
5521
5522                 hdspm->playback_buffer = NULL;
5523         } else {
5524                 for (i = 0; i < hdspm->max_channels_in; ++i)
5525                         snd_hdspm_enable_in(hdspm, i, 0);
5526
5527                 hdspm->capture_buffer = NULL;
5528
5529         }
5530
5531         snd_pcm_lib_free_pages(substream);
5532
5533         return 0;
5534 }
5535
5536
5537 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5538                 struct snd_pcm_channel_info *info)
5539 {
5540         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5541
5542         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5543                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5544                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5545                         return -EINVAL;
5546                 }
5547
5548                 if (hdspm->channel_map_out[info->channel] < 0) {
5549                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5550                         return -EINVAL;
5551                 }
5552
5553                 info->offset = hdspm->channel_map_out[info->channel] *
5554                         HDSPM_CHANNEL_BUFFER_BYTES;
5555         } else {
5556                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5557                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5558                         return -EINVAL;
5559                 }
5560
5561                 if (hdspm->channel_map_in[info->channel] < 0) {
5562                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5563                         return -EINVAL;
5564                 }
5565
5566                 info->offset = hdspm->channel_map_in[info->channel] *
5567                         HDSPM_CHANNEL_BUFFER_BYTES;
5568         }
5569
5570         info->first = 0;
5571         info->step = 32;
5572         return 0;
5573 }
5574
5575
5576 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5577                 unsigned int cmd, void *arg)
5578 {
5579         switch (cmd) {
5580         case SNDRV_PCM_IOCTL1_RESET:
5581                 return snd_hdspm_reset(substream);
5582
5583         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5584                 {
5585                         struct snd_pcm_channel_info *info = arg;
5586                         return snd_hdspm_channel_info(substream, info);
5587                 }
5588         default:
5589                 break;
5590         }
5591
5592         return snd_pcm_lib_ioctl(substream, cmd, arg);
5593 }
5594
5595 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5596 {
5597         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5598         struct snd_pcm_substream *other;
5599         int running;
5600
5601         spin_lock(&hdspm->lock);
5602         running = hdspm->running;
5603         switch (cmd) {
5604         case SNDRV_PCM_TRIGGER_START:
5605                 running |= 1 << substream->stream;
5606                 break;
5607         case SNDRV_PCM_TRIGGER_STOP:
5608                 running &= ~(1 << substream->stream);
5609                 break;
5610         default:
5611                 snd_BUG();
5612                 spin_unlock(&hdspm->lock);
5613                 return -EINVAL;
5614         }
5615         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5616                 other = hdspm->capture_substream;
5617         else
5618                 other = hdspm->playback_substream;
5619
5620         if (other) {
5621                 struct snd_pcm_substream *s;
5622                 snd_pcm_group_for_each_entry(s, substream) {
5623                         if (s == other) {
5624                                 snd_pcm_trigger_done(s, substream);
5625                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5626                                         running |= 1 << s->stream;
5627                                 else
5628                                         running &= ~(1 << s->stream);
5629                                 goto _ok;
5630                         }
5631                 }
5632                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5633                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5634                                         && substream->stream ==
5635                                         SNDRV_PCM_STREAM_CAPTURE)
5636                                 hdspm_silence_playback(hdspm);
5637                 } else {
5638                         if (running &&
5639                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5640                                 hdspm_silence_playback(hdspm);
5641                 }
5642         } else {
5643                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5644                         hdspm_silence_playback(hdspm);
5645         }
5646 _ok:
5647         snd_pcm_trigger_done(substream, substream);
5648         if (!hdspm->running && running)
5649                 hdspm_start_audio(hdspm);
5650         else if (hdspm->running && !running)
5651                 hdspm_stop_audio(hdspm);
5652         hdspm->running = running;
5653         spin_unlock(&hdspm->lock);
5654
5655         return 0;
5656 }
5657
5658 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5659 {
5660         return 0;
5661 }
5662
5663 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5664         .info = (SNDRV_PCM_INFO_MMAP |
5665                  SNDRV_PCM_INFO_MMAP_VALID |
5666                  SNDRV_PCM_INFO_NONINTERLEAVED |
5667                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5668         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5669         .rates = (SNDRV_PCM_RATE_32000 |
5670                   SNDRV_PCM_RATE_44100 |
5671                   SNDRV_PCM_RATE_48000 |
5672                   SNDRV_PCM_RATE_64000 |
5673                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5674                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5675         .rate_min = 32000,
5676         .rate_max = 192000,
5677         .channels_min = 1,
5678         .channels_max = HDSPM_MAX_CHANNELS,
5679         .buffer_bytes_max =
5680             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5681         .period_bytes_min = (32 * 4),
5682         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5683         .periods_min = 2,
5684         .periods_max = 512,
5685         .fifo_size = 0
5686 };
5687
5688 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5689         .info = (SNDRV_PCM_INFO_MMAP |
5690                  SNDRV_PCM_INFO_MMAP_VALID |
5691                  SNDRV_PCM_INFO_NONINTERLEAVED |
5692                  SNDRV_PCM_INFO_SYNC_START),
5693         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5694         .rates = (SNDRV_PCM_RATE_32000 |
5695                   SNDRV_PCM_RATE_44100 |
5696                   SNDRV_PCM_RATE_48000 |
5697                   SNDRV_PCM_RATE_64000 |
5698                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5699                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5700         .rate_min = 32000,
5701         .rate_max = 192000,
5702         .channels_min = 1,
5703         .channels_max = HDSPM_MAX_CHANNELS,
5704         .buffer_bytes_max =
5705             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5706         .period_bytes_min = (32 * 4),
5707         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5708         .periods_min = 2,
5709         .periods_max = 512,
5710         .fifo_size = 0
5711 };
5712
5713 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5714                                            struct snd_pcm_hw_rule *rule)
5715 {
5716         struct hdspm *hdspm = rule->private;
5717         struct snd_interval *c =
5718             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5719         struct snd_interval *r =
5720             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5721
5722         if (r->min > 96000 && r->max <= 192000) {
5723                 struct snd_interval t = {
5724                         .min = hdspm->qs_in_channels,
5725                         .max = hdspm->qs_in_channels,
5726                         .integer = 1,
5727                 };
5728                 return snd_interval_refine(c, &t);
5729         } else if (r->min > 48000 && r->max <= 96000) {
5730                 struct snd_interval t = {
5731                         .min = hdspm->ds_in_channels,
5732                         .max = hdspm->ds_in_channels,
5733                         .integer = 1,
5734                 };
5735                 return snd_interval_refine(c, &t);
5736         } else if (r->max < 64000) {
5737                 struct snd_interval t = {
5738                         .min = hdspm->ss_in_channels,
5739                         .max = hdspm->ss_in_channels,
5740                         .integer = 1,
5741                 };
5742                 return snd_interval_refine(c, &t);
5743         }
5744
5745         return 0;
5746 }
5747
5748 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5749                                            struct snd_pcm_hw_rule * rule)
5750 {
5751         struct hdspm *hdspm = rule->private;
5752         struct snd_interval *c =
5753             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5754         struct snd_interval *r =
5755             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5756
5757         if (r->min > 96000 && r->max <= 192000) {
5758                 struct snd_interval t = {
5759                         .min = hdspm->qs_out_channels,
5760                         .max = hdspm->qs_out_channels,
5761                         .integer = 1,
5762                 };
5763                 return snd_interval_refine(c, &t);
5764         } else if (r->min > 48000 && r->max <= 96000) {
5765                 struct snd_interval t = {
5766                         .min = hdspm->ds_out_channels,
5767                         .max = hdspm->ds_out_channels,
5768                         .integer = 1,
5769                 };
5770                 return snd_interval_refine(c, &t);
5771         } else if (r->max < 64000) {
5772                 struct snd_interval t = {
5773                         .min = hdspm->ss_out_channels,
5774                         .max = hdspm->ss_out_channels,
5775                         .integer = 1,
5776                 };
5777                 return snd_interval_refine(c, &t);
5778         } else {
5779         }
5780         return 0;
5781 }
5782
5783 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5784                                            struct snd_pcm_hw_rule * rule)
5785 {
5786         struct hdspm *hdspm = rule->private;
5787         struct snd_interval *c =
5788             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5789         struct snd_interval *r =
5790             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5791
5792         if (c->min >= hdspm->ss_in_channels) {
5793                 struct snd_interval t = {
5794                         .min = 32000,
5795                         .max = 48000,
5796                         .integer = 1,
5797                 };
5798                 return snd_interval_refine(r, &t);
5799         } else if (c->max <= hdspm->qs_in_channels) {
5800                 struct snd_interval t = {
5801                         .min = 128000,
5802                         .max = 192000,
5803                         .integer = 1,
5804                 };
5805                 return snd_interval_refine(r, &t);
5806         } else if (c->max <= hdspm->ds_in_channels) {
5807                 struct snd_interval t = {
5808                         .min = 64000,
5809                         .max = 96000,
5810                         .integer = 1,
5811                 };
5812                 return snd_interval_refine(r, &t);
5813         }
5814
5815         return 0;
5816 }
5817 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5818                                            struct snd_pcm_hw_rule *rule)
5819 {
5820         struct hdspm *hdspm = rule->private;
5821         struct snd_interval *c =
5822             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5823         struct snd_interval *r =
5824             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5825
5826         if (c->min >= hdspm->ss_out_channels) {
5827                 struct snd_interval t = {
5828                         .min = 32000,
5829                         .max = 48000,
5830                         .integer = 1,
5831                 };
5832                 return snd_interval_refine(r, &t);
5833         } else if (c->max <= hdspm->qs_out_channels) {
5834                 struct snd_interval t = {
5835                         .min = 128000,
5836                         .max = 192000,
5837                         .integer = 1,
5838                 };
5839                 return snd_interval_refine(r, &t);
5840         } else if (c->max <= hdspm->ds_out_channels) {
5841                 struct snd_interval t = {
5842                         .min = 64000,
5843                         .max = 96000,
5844                         .integer = 1,
5845                 };
5846                 return snd_interval_refine(r, &t);
5847         }
5848
5849         return 0;
5850 }
5851
5852 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5853                                       struct snd_pcm_hw_rule *rule)
5854 {
5855         unsigned int list[3];
5856         struct hdspm *hdspm = rule->private;
5857         struct snd_interval *c = hw_param_interval(params,
5858                         SNDRV_PCM_HW_PARAM_CHANNELS);
5859
5860         list[0] = hdspm->qs_in_channels;
5861         list[1] = hdspm->ds_in_channels;
5862         list[2] = hdspm->ss_in_channels;
5863         return snd_interval_list(c, 3, list, 0);
5864 }
5865
5866 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5867                                       struct snd_pcm_hw_rule *rule)
5868 {
5869         unsigned int list[3];
5870         struct hdspm *hdspm = rule->private;
5871         struct snd_interval *c = hw_param_interval(params,
5872                         SNDRV_PCM_HW_PARAM_CHANNELS);
5873
5874         list[0] = hdspm->qs_out_channels;
5875         list[1] = hdspm->ds_out_channels;
5876         list[2] = hdspm->ss_out_channels;
5877         return snd_interval_list(c, 3, list, 0);
5878 }
5879
5880
5881 static unsigned int hdspm_aes32_sample_rates[] = {
5882         32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5883 };
5884
5885 static struct snd_pcm_hw_constraint_list
5886 hdspm_hw_constraints_aes32_sample_rates = {
5887         .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5888         .list = hdspm_aes32_sample_rates,
5889         .mask = 0
5890 };
5891
5892 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5893 {
5894         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5895         struct snd_pcm_runtime *runtime = substream->runtime;
5896
5897         spin_lock_irq(&hdspm->lock);
5898
5899         snd_pcm_set_sync(substream);
5900
5901
5902         runtime->hw = snd_hdspm_playback_subinfo;
5903
5904         if (hdspm->capture_substream == NULL)
5905                 hdspm_stop_audio(hdspm);
5906
5907         hdspm->playback_pid = current->pid;
5908         hdspm->playback_substream = substream;
5909
5910         spin_unlock_irq(&hdspm->lock);
5911
5912         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5913         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5914
5915         switch (hdspm->io_type) {
5916         case AIO:
5917         case RayDAT:
5918                 snd_pcm_hw_constraint_minmax(runtime,
5919                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5920                                              32, 4096);
5921                 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
5922                 snd_pcm_hw_constraint_minmax(runtime,
5923                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5924                                              16384, 16384);
5925                 break;
5926
5927         default:
5928                 snd_pcm_hw_constraint_minmax(runtime,
5929                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5930                                              64, 8192);
5931                 break;
5932         }
5933
5934         if (AES32 == hdspm->io_type) {
5935                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
5936                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5937                                 &hdspm_hw_constraints_aes32_sample_rates);
5938         } else {
5939                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5940                                 snd_hdspm_hw_rule_rate_out_channels, hdspm,
5941                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5942         }
5943
5944         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5945                         snd_hdspm_hw_rule_out_channels, hdspm,
5946                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5947
5948         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5949                         snd_hdspm_hw_rule_out_channels_rate, hdspm,
5950                         SNDRV_PCM_HW_PARAM_RATE, -1);
5951
5952         return 0;
5953 }
5954
5955 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
5956 {
5957         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5958
5959         spin_lock_irq(&hdspm->lock);
5960
5961         hdspm->playback_pid = -1;
5962         hdspm->playback_substream = NULL;
5963
5964         spin_unlock_irq(&hdspm->lock);
5965
5966         return 0;
5967 }
5968
5969
5970 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
5971 {
5972         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5973         struct snd_pcm_runtime *runtime = substream->runtime;
5974
5975         spin_lock_irq(&hdspm->lock);
5976         snd_pcm_set_sync(substream);
5977         runtime->hw = snd_hdspm_capture_subinfo;
5978
5979         if (hdspm->playback_substream == NULL)
5980                 hdspm_stop_audio(hdspm);
5981
5982         hdspm->capture_pid = current->pid;
5983         hdspm->capture_substream = substream;
5984
5985         spin_unlock_irq(&hdspm->lock);
5986
5987         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5988         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5989
5990         switch (hdspm->io_type) {
5991         case AIO:
5992         case RayDAT:
5993                 snd_pcm_hw_constraint_minmax(runtime,
5994                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5995                                              32, 4096);
5996                 snd_pcm_hw_constraint_minmax(runtime,
5997                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5998                                              16384, 16384);
5999                 break;
6000
6001         default:
6002                 snd_pcm_hw_constraint_minmax(runtime,
6003                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6004                                              64, 8192);
6005                 break;
6006         }
6007
6008         if (AES32 == hdspm->io_type) {
6009                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6010                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6011                                 &hdspm_hw_constraints_aes32_sample_rates);
6012         } else {
6013                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6014                                 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6015                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6016         }
6017
6018         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6019                         snd_hdspm_hw_rule_in_channels, hdspm,
6020                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6021
6022         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6023                         snd_hdspm_hw_rule_in_channels_rate, hdspm,
6024                         SNDRV_PCM_HW_PARAM_RATE, -1);
6025
6026         return 0;
6027 }
6028
6029 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6030 {
6031         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6032
6033         spin_lock_irq(&hdspm->lock);
6034
6035         hdspm->capture_pid = -1;
6036         hdspm->capture_substream = NULL;
6037
6038         spin_unlock_irq(&hdspm->lock);
6039         return 0;
6040 }
6041
6042 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6043 {
6044         /* we have nothing to initialize but the call is required */
6045         return 0;
6046 }
6047
6048 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6049 {
6050         u32 val = readl(src);
6051         return copy_to_user(dest, &val, 4);
6052 }
6053
6054 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6055                 unsigned int cmd, unsigned long arg)
6056 {
6057         void __user *argp = (void __user *)arg;
6058         struct hdspm *hdspm = hw->private_data;
6059         struct hdspm_mixer_ioctl mixer;
6060         struct hdspm_config info;
6061         struct hdspm_status status;
6062         struct hdspm_version hdspm_version;
6063         struct hdspm_peak_rms *levels;
6064         struct hdspm_ltc ltc;
6065         unsigned int statusregister;
6066         long unsigned int s;
6067         int i = 0;
6068
6069         switch (cmd) {
6070
6071         case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6072                 levels = &hdspm->peak_rms;
6073                 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6074                         levels->input_peaks[i] =
6075                                 readl(hdspm->iobase +
6076                                                 HDSPM_MADI_INPUT_PEAK + i*4);
6077                         levels->playback_peaks[i] =
6078                                 readl(hdspm->iobase +
6079                                                 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6080                         levels->output_peaks[i] =
6081                                 readl(hdspm->iobase +
6082                                                 HDSPM_MADI_OUTPUT_PEAK + i*4);
6083
6084                         levels->input_rms[i] =
6085                                 ((uint64_t) readl(hdspm->iobase +
6086                                         HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6087                                 (uint64_t) readl(hdspm->iobase +
6088                                                 HDSPM_MADI_INPUT_RMS_L + i*4);
6089                         levels->playback_rms[i] =
6090                                 ((uint64_t)readl(hdspm->iobase +
6091                                         HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6092                                 (uint64_t)readl(hdspm->iobase +
6093                                         HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6094                         levels->output_rms[i] =
6095                                 ((uint64_t)readl(hdspm->iobase +
6096                                         HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6097                                 (uint64_t)readl(hdspm->iobase +
6098                                                 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6099                 }
6100
6101                 if (hdspm->system_sample_rate > 96000) {
6102                         levels->speed = qs;
6103                 } else if (hdspm->system_sample_rate > 48000) {
6104                         levels->speed = ds;
6105                 } else {
6106                         levels->speed = ss;
6107                 }
6108                 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6109
6110                 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6111                 if (0 != s) {
6112                         /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6113                          [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6114                          */
6115                         return -EFAULT;
6116                 }
6117                 break;
6118
6119         case SNDRV_HDSPM_IOCTL_GET_LTC:
6120                 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6121                 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6122                 if (i & HDSPM_TCO1_LTC_Input_valid) {
6123                         switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6124                                 HDSPM_TCO1_LTC_Format_MSB)) {
6125                         case 0:
6126                                 ltc.format = fps_24;
6127                                 break;
6128                         case HDSPM_TCO1_LTC_Format_LSB:
6129                                 ltc.format = fps_25;
6130                                 break;
6131                         case HDSPM_TCO1_LTC_Format_MSB:
6132                                 ltc.format = fps_2997;
6133                                 break;
6134                         default:
6135                                 ltc.format = 30;
6136                                 break;
6137                         }
6138                         if (i & HDSPM_TCO1_set_drop_frame_flag) {
6139                                 ltc.frame = drop_frame;
6140                         } else {
6141                                 ltc.frame = full_frame;
6142                         }
6143                 } else {
6144                         ltc.format = format_invalid;
6145                         ltc.frame = frame_invalid;
6146                 }
6147                 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6148                         ltc.input_format = ntsc;
6149                 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6150                         ltc.input_format = pal;
6151                 } else {
6152                         ltc.input_format = no_video;
6153                 }
6154
6155                 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6156                 if (0 != s) {
6157                         /*
6158                          snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6159                         return -EFAULT;
6160                 }
6161
6162                 break;
6163
6164         case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6165
6166                 memset(&info, 0, sizeof(info));
6167                 spin_lock_irq(&hdspm->lock);
6168                 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6169                 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6170
6171                 info.system_sample_rate = hdspm->system_sample_rate;
6172                 info.autosync_sample_rate =
6173                         hdspm_external_sample_rate(hdspm);
6174                 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6175                 info.clock_source = hdspm_clock_source(hdspm);
6176                 info.autosync_ref = hdspm_autosync_ref(hdspm);
6177                 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut);
6178                 info.passthru = 0;
6179                 spin_unlock_irq(&hdspm->lock);
6180                 if (copy_to_user(argp, &info, sizeof(info)))
6181                         return -EFAULT;
6182                 break;
6183
6184         case SNDRV_HDSPM_IOCTL_GET_STATUS:
6185                 memset(&status, 0, sizeof(status));
6186
6187                 status.card_type = hdspm->io_type;
6188
6189                 status.autosync_source = hdspm_autosync_ref(hdspm);
6190
6191                 status.card_clock = 110069313433624ULL;
6192                 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6193
6194                 switch (hdspm->io_type) {
6195                 case MADI:
6196                 case MADIface:
6197                         status.card_specific.madi.sync_wc =
6198                                 hdspm_wc_sync_check(hdspm);
6199                         status.card_specific.madi.sync_madi =
6200                                 hdspm_madi_sync_check(hdspm);
6201                         status.card_specific.madi.sync_tco =
6202                                 hdspm_tco_sync_check(hdspm);
6203                         status.card_specific.madi.sync_in =
6204                                 hdspm_sync_in_sync_check(hdspm);
6205
6206                         statusregister =
6207                                 hdspm_read(hdspm, HDSPM_statusRegister);
6208                         status.card_specific.madi.madi_input =
6209                                 (statusregister & HDSPM_AB_int) ? 1 : 0;
6210                         status.card_specific.madi.channel_format =
6211                                 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6212                         /* TODO: Mac driver sets it when f_s>48kHz */
6213                         status.card_specific.madi.frame_format = 0;
6214
6215                 default:
6216                         break;
6217                 }
6218
6219                 if (copy_to_user(argp, &status, sizeof(status)))
6220                         return -EFAULT;
6221
6222
6223                 break;
6224
6225         case SNDRV_HDSPM_IOCTL_GET_VERSION:
6226                 memset(&hdspm_version, 0, sizeof(hdspm_version));
6227
6228                 hdspm_version.card_type = hdspm->io_type;
6229                 strncpy(hdspm_version.cardname, hdspm->card_name,
6230                                 sizeof(hdspm_version.cardname));
6231                 hdspm_version.serial = hdspm->serial;
6232                 hdspm_version.firmware_rev = hdspm->firmware_rev;
6233                 hdspm_version.addons = 0;
6234                 if (hdspm->tco)
6235                         hdspm_version.addons |= HDSPM_ADDON_TCO;
6236
6237                 if (copy_to_user(argp, &hdspm_version,
6238                                         sizeof(hdspm_version)))
6239                         return -EFAULT;
6240                 break;
6241
6242         case SNDRV_HDSPM_IOCTL_GET_MIXER:
6243                 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6244                         return -EFAULT;
6245                 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6246                                         sizeof(struct hdspm_mixer)))
6247                         return -EFAULT;
6248                 break;
6249
6250         default:
6251                 return -EINVAL;
6252         }
6253         return 0;
6254 }
6255
6256 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6257         .open = snd_hdspm_playback_open,
6258         .close = snd_hdspm_playback_release,
6259         .ioctl = snd_hdspm_ioctl,
6260         .hw_params = snd_hdspm_hw_params,
6261         .hw_free = snd_hdspm_hw_free,
6262         .prepare = snd_hdspm_prepare,
6263         .trigger = snd_hdspm_trigger,
6264         .pointer = snd_hdspm_hw_pointer,
6265         .page = snd_pcm_sgbuf_ops_page,
6266 };
6267
6268 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6269         .open = snd_hdspm_capture_open,
6270         .close = snd_hdspm_capture_release,
6271         .ioctl = snd_hdspm_ioctl,
6272         .hw_params = snd_hdspm_hw_params,
6273         .hw_free = snd_hdspm_hw_free,
6274         .prepare = snd_hdspm_prepare,
6275         .trigger = snd_hdspm_trigger,
6276         .pointer = snd_hdspm_hw_pointer,
6277         .page = snd_pcm_sgbuf_ops_page,
6278 };
6279
6280 static int snd_hdspm_create_hwdep(struct snd_card *card,
6281                                   struct hdspm *hdspm)
6282 {
6283         struct snd_hwdep *hw;
6284         int err;
6285
6286         err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6287         if (err < 0)
6288                 return err;
6289
6290         hdspm->hwdep = hw;
6291         hw->private_data = hdspm;
6292         strcpy(hw->name, "HDSPM hwdep interface");
6293
6294         hw->ops.open = snd_hdspm_hwdep_dummy_op;
6295         hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6296         hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6297         hw->ops.release = snd_hdspm_hwdep_dummy_op;
6298
6299         return 0;
6300 }
6301
6302
6303 /*------------------------------------------------------------
6304    memory interface
6305  ------------------------------------------------------------*/
6306 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6307 {
6308         int err;
6309         struct snd_pcm *pcm;
6310         size_t wanted;
6311
6312         pcm = hdspm->pcm;
6313
6314         wanted = HDSPM_DMA_AREA_BYTES;
6315
6316         err =
6317              snd_pcm_lib_preallocate_pages_for_all(pcm,
6318                                                    SNDRV_DMA_TYPE_DEV_SG,
6319                                                    snd_dma_pci_data(hdspm->pci),
6320                                                    wanted,
6321                                                    wanted);
6322         if (err < 0) {
6323                 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6324
6325                 return err;
6326         } else
6327                 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6328
6329         return 0;
6330 }
6331
6332
6333 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6334                             struct snd_pcm_substream *substream,
6335                              unsigned int reg, int channels)
6336 {
6337         int i;
6338
6339         /* continuous memory segment */
6340         for (i = 0; i < (channels * 16); i++)
6341                 hdspm_write(hdspm, reg + 4 * i,
6342                                 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6343 }
6344
6345
6346 /* ------------- ALSA Devices ---------------------------- */
6347 static int snd_hdspm_create_pcm(struct snd_card *card,
6348                                 struct hdspm *hdspm)
6349 {
6350         struct snd_pcm *pcm;
6351         int err;
6352
6353         err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6354         if (err < 0)
6355                 return err;
6356
6357         hdspm->pcm = pcm;
6358         pcm->private_data = hdspm;
6359         strcpy(pcm->name, hdspm->card_name);
6360
6361         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6362                         &snd_hdspm_playback_ops);
6363         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6364                         &snd_hdspm_capture_ops);
6365
6366         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6367
6368         err = snd_hdspm_preallocate_memory(hdspm);
6369         if (err < 0)
6370                 return err;
6371
6372         return 0;
6373 }
6374
6375 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6376 {
6377         int i;
6378
6379         for (i = 0; i < hdspm->midiPorts; i++)
6380                 snd_hdspm_flush_midi_input(hdspm, i);
6381 }
6382
6383 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
6384                                          struct hdspm *hdspm)
6385 {
6386         int err, i;
6387
6388         snd_printdd("Create card...\n");
6389         err = snd_hdspm_create_pcm(card, hdspm);
6390         if (err < 0)
6391                 return err;
6392
6393         i = 0;
6394         while (i < hdspm->midiPorts) {
6395                 err = snd_hdspm_create_midi(card, hdspm, i);
6396                 if (err < 0) {
6397                         return err;
6398                 }
6399                 i++;
6400         }
6401
6402         err = snd_hdspm_create_controls(card, hdspm);
6403         if (err < 0)
6404                 return err;
6405
6406         err = snd_hdspm_create_hwdep(card, hdspm);
6407         if (err < 0)
6408                 return err;
6409
6410         snd_printdd("proc init...\n");
6411         snd_hdspm_proc_init(hdspm);
6412
6413         hdspm->system_sample_rate = -1;
6414         hdspm->last_external_sample_rate = -1;
6415         hdspm->last_internal_sample_rate = -1;
6416         hdspm->playback_pid = -1;
6417         hdspm->capture_pid = -1;
6418         hdspm->capture_substream = NULL;
6419         hdspm->playback_substream = NULL;
6420
6421         snd_printdd("Set defaults...\n");
6422         err = snd_hdspm_set_defaults(hdspm);
6423         if (err < 0)
6424                 return err;
6425
6426         snd_printdd("Update mixer controls...\n");
6427         hdspm_update_simple_mixer_controls(hdspm);
6428
6429         snd_printdd("Initializeing complete ???\n");
6430
6431         err = snd_card_register(card);
6432         if (err < 0) {
6433                 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6434                 return err;
6435         }
6436
6437         snd_printdd("... yes now\n");
6438
6439         return 0;
6440 }
6441
6442 static int snd_hdspm_create(struct snd_card *card,
6443                             struct hdspm *hdspm)
6444 {
6445
6446         struct pci_dev *pci = hdspm->pci;
6447         int err;
6448         unsigned long io_extent;
6449
6450         hdspm->irq = -1;
6451         hdspm->card = card;
6452
6453         spin_lock_init(&hdspm->lock);
6454
6455         pci_read_config_word(hdspm->pci,
6456                         PCI_CLASS_REVISION, &hdspm->firmware_rev);
6457
6458         strcpy(card->mixername, "Xilinx FPGA");
6459         strcpy(card->driver, "HDSPM");
6460
6461         switch (hdspm->firmware_rev) {
6462         case HDSPM_RAYDAT_REV:
6463                 hdspm->io_type = RayDAT;
6464                 hdspm->card_name = "RME RayDAT";
6465                 hdspm->midiPorts = 2;
6466                 break;
6467         case HDSPM_AIO_REV:
6468                 hdspm->io_type = AIO;
6469                 hdspm->card_name = "RME AIO";
6470                 hdspm->midiPorts = 1;
6471                 break;
6472         case HDSPM_MADIFACE_REV:
6473                 hdspm->io_type = MADIface;
6474                 hdspm->card_name = "RME MADIface";
6475                 hdspm->midiPorts = 1;
6476                 break;
6477         default:
6478                 if ((hdspm->firmware_rev == 0xf0) ||
6479                         ((hdspm->firmware_rev >= 0xe6) &&
6480                                         (hdspm->firmware_rev <= 0xea))) {
6481                         hdspm->io_type = AES32;
6482                         hdspm->card_name = "RME AES32";
6483                         hdspm->midiPorts = 2;
6484                 } else if ((hdspm->firmware_rev == 0xd2) ||
6485                         ((hdspm->firmware_rev >= 0xc8)  &&
6486                                 (hdspm->firmware_rev <= 0xcf))) {
6487                         hdspm->io_type = MADI;
6488                         hdspm->card_name = "RME MADI";
6489                         hdspm->midiPorts = 3;
6490                 } else {
6491                         snd_printk(KERN_ERR
6492                                 "HDSPM: unknown firmware revision %x\n",
6493                                 hdspm->firmware_rev);
6494                         return -ENODEV;
6495                 }
6496         }
6497
6498         err = pci_enable_device(pci);
6499         if (err < 0)
6500                 return err;
6501
6502         pci_set_master(hdspm->pci);
6503
6504         err = pci_request_regions(pci, "hdspm");
6505         if (err < 0)
6506                 return err;
6507
6508         hdspm->port = pci_resource_start(pci, 0);
6509         io_extent = pci_resource_len(pci, 0);
6510
6511         snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6512                         hdspm->port, hdspm->port + io_extent - 1);
6513
6514         hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6515         if (!hdspm->iobase) {
6516                 snd_printk(KERN_ERR "HDSPM: "
6517                                 "unable to remap region 0x%lx-0x%lx\n",
6518                                 hdspm->port, hdspm->port + io_extent - 1);
6519                 return -EBUSY;
6520         }
6521         snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6522                         (unsigned long)hdspm->iobase, hdspm->port,
6523                         hdspm->port + io_extent - 1);
6524
6525         if (request_irq(pci->irq, snd_hdspm_interrupt,
6526                         IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6527                 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6528                 return -EBUSY;
6529         }
6530
6531         snd_printdd("use IRQ %d\n", pci->irq);
6532
6533         hdspm->irq = pci->irq;
6534
6535         snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6536                         sizeof(struct hdspm_mixer));
6537         hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6538         if (!hdspm->mixer) {
6539                 snd_printk(KERN_ERR "HDSPM: "
6540                                 "unable to kmalloc Mixer memory of %d Bytes\n",
6541                                 (int)sizeof(struct hdspm_mixer));
6542                 return -ENOMEM;
6543         }
6544
6545         hdspm->port_names_in = NULL;
6546         hdspm->port_names_out = NULL;
6547
6548         switch (hdspm->io_type) {
6549         case AES32:
6550                 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6551                 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6552                 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6553
6554                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6555                         channel_map_aes32;
6556                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6557                         channel_map_aes32;
6558                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6559                         channel_map_aes32;
6560                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6561                         texts_ports_aes32;
6562                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6563                         texts_ports_aes32;
6564                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6565                         texts_ports_aes32;
6566
6567                 hdspm->max_channels_out = hdspm->max_channels_in =
6568                         AES32_CHANNELS;
6569                 hdspm->port_names_in = hdspm->port_names_out =
6570                         texts_ports_aes32;
6571                 hdspm->channel_map_in = hdspm->channel_map_out =
6572                         channel_map_aes32;
6573
6574                 break;
6575
6576         case MADI:
6577         case MADIface:
6578                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6579                         MADI_SS_CHANNELS;
6580                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6581                         MADI_DS_CHANNELS;
6582                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6583                         MADI_QS_CHANNELS;
6584
6585                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6586                         channel_map_unity_ss;
6587                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6588                         channel_map_unity_ss;
6589                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6590                         channel_map_unity_ss;
6591
6592                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6593                         texts_ports_madi;
6594                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6595                         texts_ports_madi;
6596                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6597                         texts_ports_madi;
6598                 break;
6599
6600         case AIO:
6601                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6602                         snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6603                 }
6604
6605                 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6606                 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6607                 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6608                 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6609                 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6610                 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6611
6612                 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6613                 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6614                 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6615
6616                 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6617                 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6618                 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6619
6620                 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6621                 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6622                 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6623                 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6624                 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6625                 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6626
6627                 break;
6628
6629         case RayDAT:
6630                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6631                         RAYDAT_SS_CHANNELS;
6632                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6633                         RAYDAT_DS_CHANNELS;
6634                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6635                         RAYDAT_QS_CHANNELS;
6636
6637                 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6638                 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6639
6640                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6641                         channel_map_raydat_ss;
6642                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6643                         channel_map_raydat_ds;
6644                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6645                         channel_map_raydat_qs;
6646                 hdspm->channel_map_in = hdspm->channel_map_out =
6647                         channel_map_raydat_ss;
6648
6649                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6650                         texts_ports_raydat_ss;
6651                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6652                         texts_ports_raydat_ds;
6653                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6654                         texts_ports_raydat_qs;
6655
6656
6657                 break;
6658
6659         }
6660
6661         /* TCO detection */
6662         switch (hdspm->io_type) {
6663         case AIO:
6664         case RayDAT:
6665                 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6666                                 HDSPM_s2_tco_detect) {
6667                         hdspm->midiPorts++;
6668                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6669                                         GFP_KERNEL);
6670                         if (NULL != hdspm->tco) {
6671                                 hdspm_tco_write(hdspm);
6672                         }
6673                         snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6674                 } else {
6675                         hdspm->tco = NULL;
6676                 }
6677                 break;
6678
6679         case MADI:
6680                 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6681                         hdspm->midiPorts++;
6682                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6683                                         GFP_KERNEL);
6684                         if (NULL != hdspm->tco) {
6685                                 hdspm_tco_write(hdspm);
6686                         }
6687                         snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6688                 } else {
6689                         hdspm->tco = NULL;
6690                 }
6691                 break;
6692
6693         default:
6694                 hdspm->tco = NULL;
6695         }
6696
6697         /* texts */
6698         switch (hdspm->io_type) {
6699         case AES32:
6700                 if (hdspm->tco) {
6701                         hdspm->texts_autosync = texts_autosync_aes_tco;
6702                         hdspm->texts_autosync_items = 10;
6703                 } else {
6704                         hdspm->texts_autosync = texts_autosync_aes;
6705                         hdspm->texts_autosync_items = 9;
6706                 }
6707                 break;
6708
6709         case MADI:
6710                 if (hdspm->tco) {
6711                         hdspm->texts_autosync = texts_autosync_madi_tco;
6712                         hdspm->texts_autosync_items = 4;
6713                 } else {
6714                         hdspm->texts_autosync = texts_autosync_madi;
6715                         hdspm->texts_autosync_items = 3;
6716                 }
6717                 break;
6718
6719         case MADIface:
6720
6721                 break;
6722
6723         case RayDAT:
6724                 if (hdspm->tco) {
6725                         hdspm->texts_autosync = texts_autosync_raydat_tco;
6726                         hdspm->texts_autosync_items = 9;
6727                 } else {
6728                         hdspm->texts_autosync = texts_autosync_raydat;
6729                         hdspm->texts_autosync_items = 8;
6730                 }
6731                 break;
6732
6733         case AIO:
6734                 if (hdspm->tco) {
6735                         hdspm->texts_autosync = texts_autosync_aio_tco;
6736                         hdspm->texts_autosync_items = 6;
6737                 } else {
6738                         hdspm->texts_autosync = texts_autosync_aio;
6739                         hdspm->texts_autosync_items = 5;
6740                 }
6741                 break;
6742
6743         }
6744
6745         tasklet_init(&hdspm->midi_tasklet,
6746                         hdspm_midi_tasklet, (unsigned long) hdspm);
6747
6748
6749         if (hdspm->io_type != MADIface) {
6750                 hdspm->serial = (hdspm_read(hdspm,
6751                                 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6752                 /* id contains either a user-provided value or the default
6753                  * NULL. If it's the default, we're safe to
6754                  * fill card->id with the serial number.
6755                  *
6756                  * If the serial number is 0xFFFFFF, then we're dealing with
6757                  * an old PCI revision that comes without a sane number. In
6758                  * this case, we don't set card->id to avoid collisions
6759                  * when running with multiple cards.
6760                  */
6761                 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6762                         sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6763                         snd_card_set_id(card, card->id);
6764                 }
6765         }
6766
6767         snd_printdd("create alsa devices.\n");
6768         err = snd_hdspm_create_alsa_devices(card, hdspm);
6769         if (err < 0)
6770                 return err;
6771
6772         snd_hdspm_initialize_midi_flush(hdspm);
6773
6774         return 0;
6775 }
6776
6777
6778 static int snd_hdspm_free(struct hdspm * hdspm)
6779 {
6780
6781         if (hdspm->port) {
6782
6783                 /* stop th audio, and cancel all interrupts */
6784                 hdspm->control_register &=
6785                     ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6786                       HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6787                       HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6788                 hdspm_write(hdspm, HDSPM_controlRegister,
6789                             hdspm->control_register);
6790         }
6791
6792         if (hdspm->irq >= 0)
6793                 free_irq(hdspm->irq, (void *) hdspm);
6794
6795         kfree(hdspm->mixer);
6796
6797         if (hdspm->iobase)
6798                 iounmap(hdspm->iobase);
6799
6800         if (hdspm->port)
6801                 pci_release_regions(hdspm->pci);
6802
6803         pci_disable_device(hdspm->pci);
6804         return 0;
6805 }
6806
6807
6808 static void snd_hdspm_card_free(struct snd_card *card)
6809 {
6810         struct hdspm *hdspm = card->private_data;
6811
6812         if (hdspm)
6813                 snd_hdspm_free(hdspm);
6814 }
6815
6816
6817 static int snd_hdspm_probe(struct pci_dev *pci,
6818                            const struct pci_device_id *pci_id)
6819 {
6820         static int dev;
6821         struct hdspm *hdspm;
6822         struct snd_card *card;
6823         int err;
6824
6825         if (dev >= SNDRV_CARDS)
6826                 return -ENODEV;
6827         if (!enable[dev]) {
6828                 dev++;
6829                 return -ENOENT;
6830         }
6831
6832         err = snd_card_create(index[dev], id[dev],
6833                         THIS_MODULE, sizeof(struct hdspm), &card);
6834         if (err < 0)
6835                 return err;
6836
6837         hdspm = card->private_data;
6838         card->private_free = snd_hdspm_card_free;
6839         hdspm->dev = dev;
6840         hdspm->pci = pci;
6841
6842         snd_card_set_dev(card, &pci->dev);
6843
6844         err = snd_hdspm_create(card, hdspm);
6845         if (err < 0) {
6846                 snd_card_free(card);
6847                 return err;
6848         }
6849
6850         if (hdspm->io_type != MADIface) {
6851                 sprintf(card->shortname, "%s_%x",
6852                         hdspm->card_name,
6853                         hdspm->serial);
6854                 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6855                         hdspm->card_name,
6856                         hdspm->serial,
6857                         hdspm->port, hdspm->irq);
6858         } else {
6859                 sprintf(card->shortname, "%s", hdspm->card_name);
6860                 sprintf(card->longname, "%s at 0x%lx, irq %d",
6861                                 hdspm->card_name, hdspm->port, hdspm->irq);
6862         }
6863
6864         err = snd_card_register(card);
6865         if (err < 0) {
6866                 snd_card_free(card);
6867                 return err;
6868         }
6869
6870         pci_set_drvdata(pci, card);
6871
6872         dev++;
6873         return 0;
6874 }
6875
6876 static void snd_hdspm_remove(struct pci_dev *pci)
6877 {
6878         snd_card_free(pci_get_drvdata(pci));
6879 }
6880
6881 static struct pci_driver hdspm_driver = {
6882         .name = KBUILD_MODNAME,
6883         .id_table = snd_hdspm_ids,
6884         .probe = snd_hdspm_probe,
6885         .remove = snd_hdspm_remove,
6886 };
6887
6888 module_pci_driver(hdspm_driver);