2 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2008 Atmel
7 * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
10 * Based on at91-ssc.c by
11 * Frank Mandarino <fmandarino@endrelia.com>
12 * Based on pxa2xx Platform drivers by
13 * Liam Girdwood <lrg@slimlogic.co.uk>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include <linux/init.h>
31 #include <linux/module.h>
32 #include <linux/interrupt.h>
33 #include <linux/device.h>
34 #include <linux/delay.h>
35 #include <linux/clk.h>
36 #include <linux/atmel_pdc.h>
38 #include <linux/atmel-ssc.h>
39 #include <sound/core.h>
40 #include <sound/pcm.h>
41 #include <sound/pcm_params.h>
42 #include <sound/initval.h>
43 #include <sound/soc.h>
45 #include "atmel-pcm.h"
46 #include "atmel_ssc_dai.h"
49 #define NUM_SSC_DEVICES 3
52 * SSC PDC registers required by the PCM DMA engine.
54 static struct atmel_pdc_regs pdc_tx_reg = {
57 .xnpr = ATMEL_PDC_TNPR,
58 .xncr = ATMEL_PDC_TNCR,
61 static struct atmel_pdc_regs pdc_rx_reg = {
64 .xnpr = ATMEL_PDC_RNPR,
65 .xncr = ATMEL_PDC_RNCR,
69 * SSC & PDC status bits for transmit and receive.
71 static struct atmel_ssc_mask ssc_tx_mask = {
72 .ssc_enable = SSC_BIT(CR_TXEN),
73 .ssc_disable = SSC_BIT(CR_TXDIS),
74 .ssc_endx = SSC_BIT(SR_ENDTX),
75 .ssc_endbuf = SSC_BIT(SR_TXBUFE),
76 .pdc_enable = ATMEL_PDC_TXTEN,
77 .pdc_disable = ATMEL_PDC_TXTDIS,
80 static struct atmel_ssc_mask ssc_rx_mask = {
81 .ssc_enable = SSC_BIT(CR_RXEN),
82 .ssc_disable = SSC_BIT(CR_RXDIS),
83 .ssc_endx = SSC_BIT(SR_ENDRX),
84 .ssc_endbuf = SSC_BIT(SR_RXBUFF),
85 .pdc_enable = ATMEL_PDC_RXTEN,
86 .pdc_disable = ATMEL_PDC_RXTDIS,
93 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
95 .name = "SSC0 PCM out",
100 .name = "SSC0 PCM in",
102 .mask = &ssc_rx_mask,
105 .name = "SSC1 PCM out",
107 .mask = &ssc_tx_mask,
110 .name = "SSC1 PCM in",
112 .mask = &ssc_rx_mask,
115 .name = "SSC2 PCM out",
117 .mask = &ssc_tx_mask,
120 .name = "SSC2 PCM in",
122 .mask = &ssc_rx_mask,
127 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
130 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
131 .dir_mask = SSC_DIR_MASK_UNUSED,
136 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
137 .dir_mask = SSC_DIR_MASK_UNUSED,
142 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
143 .dir_mask = SSC_DIR_MASK_UNUSED,
150 * SSC interrupt handler. Passes PDC interrupts to the DMA
151 * interrupt handler in the PCM driver.
153 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
155 struct atmel_ssc_info *ssc_p = dev_id;
156 struct atmel_pcm_dma_params *dma_params;
158 u32 ssc_substream_mask;
161 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
162 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
165 * Loop through the substreams attached to this SSC. If
166 * a DMA-related interrupt occurred on that substream, call
167 * the DMA interrupt handler function, if one has been
168 * registered in the dma_params structure by the PCM driver.
170 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
171 dma_params = ssc_p->dma_params[i];
173 if ((dma_params != NULL) &&
174 (dma_params->dma_intr_handler != NULL)) {
175 ssc_substream_mask = (dma_params->mask->ssc_endx |
176 dma_params->mask->ssc_endbuf);
177 if (ssc_sr & ssc_substream_mask) {
178 dma_params->dma_intr_handler(ssc_sr,
189 /*-------------------------------------------------------------------------*\
191 \*-------------------------------------------------------------------------*/
193 * Startup. Only that one substream allowed in each direction.
195 static int atmel_ssc_startup(struct snd_pcm_substream *substream,
196 struct snd_soc_dai *dai)
198 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
199 struct atmel_pcm_dma_params *dma_params;
202 pr_debug("atmel_ssc_startup: SSC_SR=0x%u\n",
203 ssc_readl(ssc_p->ssc->regs, SR));
205 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
207 dir_mask = SSC_DIR_MASK_PLAYBACK;
210 dir_mask = SSC_DIR_MASK_CAPTURE;
213 dma_params = &ssc_dma_params[dai->id][dir];
214 dma_params->ssc = ssc_p->ssc;
215 dma_params->substream = substream;
217 ssc_p->dma_params[dir] = dma_params;
219 snd_soc_dai_set_dma_data(dai, substream, dma_params);
221 spin_lock_irq(&ssc_p->lock);
222 if (ssc_p->dir_mask & dir_mask) {
223 spin_unlock_irq(&ssc_p->lock);
226 ssc_p->dir_mask |= dir_mask;
227 spin_unlock_irq(&ssc_p->lock);
233 * Shutdown. Clear DMA parameters and shutdown the SSC if there
234 * are no other substreams open.
236 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
237 struct snd_soc_dai *dai)
239 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
240 struct atmel_pcm_dma_params *dma_params;
243 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
248 dma_params = ssc_p->dma_params[dir];
250 if (dma_params != NULL) {
251 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
252 pr_debug("atmel_ssc_shutdown: %s disabled SSC_SR=0x%08x\n",
253 (dir ? "receive" : "transmit"),
254 ssc_readl(ssc_p->ssc->regs, SR));
256 dma_params->ssc = NULL;
257 dma_params->substream = NULL;
258 ssc_p->dma_params[dir] = NULL;
263 spin_lock_irq(&ssc_p->lock);
264 ssc_p->dir_mask &= ~dir_mask;
265 if (!ssc_p->dir_mask) {
266 if (ssc_p->initialized) {
267 /* Shutdown the SSC clock. */
268 pr_debug("atmel_ssc_dau: Stopping clock\n");
269 clk_disable(ssc_p->ssc->clk);
271 free_irq(ssc_p->ssc->irq, ssc_p);
272 ssc_p->initialized = 0;
276 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
277 /* Clear the SSC dividers */
278 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
280 spin_unlock_irq(&ssc_p->lock);
285 * Record the DAI format for use in hw_params().
287 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
290 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
297 * Record SSC clock dividers for use in hw_params().
299 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
302 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
305 case ATMEL_SSC_CMR_DIV:
307 * The same master clock divider is used for both
308 * transmit and receive, so if a value has already
309 * been set, it must match this value.
311 if (ssc_p->cmr_div == 0)
312 ssc_p->cmr_div = div;
314 if (div != ssc_p->cmr_div)
318 case ATMEL_SSC_TCMR_PERIOD:
319 ssc_p->tcmr_period = div;
322 case ATMEL_SSC_RCMR_PERIOD:
323 ssc_p->rcmr_period = div;
336 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
337 struct snd_pcm_hw_params *params,
338 struct snd_soc_dai *dai)
341 struct atmel_ssc_info *ssc_p = &ssc_info[id];
342 struct atmel_pcm_dma_params *dma_params;
343 int dir, channels, bits;
344 u32 tfmr, rfmr, tcmr, rcmr;
349 * Currently, there is only one set of dma params for
350 * each direction. If more are added, this code will
351 * have to be changed to select the proper set.
353 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
358 dma_params = ssc_p->dma_params[dir];
360 channels = params_channels(params);
363 * Determine sample size in bits and the PDC increment.
365 switch (params_format(params)) {
366 case SNDRV_PCM_FORMAT_S8:
368 dma_params->pdc_xfer_size = 1;
370 case SNDRV_PCM_FORMAT_S16_LE:
372 dma_params->pdc_xfer_size = 2;
374 case SNDRV_PCM_FORMAT_S24_LE:
376 dma_params->pdc_xfer_size = 4;
378 case SNDRV_PCM_FORMAT_S32_LE:
380 dma_params->pdc_xfer_size = 4;
383 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
388 * The SSC only supports up to 16-bit samples in I2S format, due
389 * to the size of the Frame Mode Register FSLEN field.
391 if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S
394 "atmel_ssc_dai: sample size %d "
395 "is too large for I2S\n", bits);
400 * Compute SSC register settings.
402 switch (ssc_p->daifmt
403 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
405 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
407 * I2S format, SSC provides BCLK and LRC clocks.
409 * The SSC transmit and receive clocks are generated
410 * from the MCK divider, and the BCLK signal
411 * is output on the SSC TK line.
413 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
414 | SSC_BF(RCMR_STTDLY, START_DELAY)
415 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
416 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
417 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
418 | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
420 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
421 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
422 | SSC_BF(RFMR_FSLEN, (bits - 1))
423 | SSC_BF(RFMR_DATNB, (channels - 1))
425 | SSC_BF(RFMR_LOOP, 0)
426 | SSC_BF(RFMR_DATLEN, (bits - 1));
428 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
429 | SSC_BF(TCMR_STTDLY, START_DELAY)
430 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
431 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
432 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
433 | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
435 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
436 | SSC_BF(TFMR_FSDEN, 0)
437 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
438 | SSC_BF(TFMR_FSLEN, (bits - 1))
439 | SSC_BF(TFMR_DATNB, (channels - 1))
441 | SSC_BF(TFMR_DATDEF, 0)
442 | SSC_BF(TFMR_DATLEN, (bits - 1));
445 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
447 * I2S format, CODEC supplies BCLK and LRC clocks.
449 * The SSC transmit clock is obtained from the BCLK signal on
450 * on the TK line, and the SSC receive clock is
451 * generated from the transmit clock.
453 * For single channel data, one sample is transferred
454 * on the falling edge of the LRC clock.
455 * For two channel data, one sample is
456 * transferred on both edges of the LRC clock.
458 start_event = ((channels == 1)
459 ? SSC_START_FALLING_RF
460 : SSC_START_EDGE_RF);
462 rcmr = SSC_BF(RCMR_PERIOD, 0)
463 | SSC_BF(RCMR_STTDLY, START_DELAY)
464 | SSC_BF(RCMR_START, start_event)
465 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
466 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
467 | SSC_BF(RCMR_CKS, SSC_CKS_CLOCK);
469 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
470 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
471 | SSC_BF(RFMR_FSLEN, 0)
472 | SSC_BF(RFMR_DATNB, 0)
474 | SSC_BF(RFMR_LOOP, 0)
475 | SSC_BF(RFMR_DATLEN, (bits - 1));
477 tcmr = SSC_BF(TCMR_PERIOD, 0)
478 | SSC_BF(TCMR_STTDLY, START_DELAY)
479 | SSC_BF(TCMR_START, start_event)
480 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
481 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
482 | SSC_BF(TCMR_CKS, SSC_CKS_PIN);
484 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
485 | SSC_BF(TFMR_FSDEN, 0)
486 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
487 | SSC_BF(TFMR_FSLEN, 0)
488 | SSC_BF(TFMR_DATNB, 0)
490 | SSC_BF(TFMR_DATDEF, 0)
491 | SSC_BF(TFMR_DATLEN, (bits - 1));
494 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
496 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
498 * The SSC transmit and receive clocks are generated from the
499 * MCK divider, and the BCLK signal is output
500 * on the SSC TK line.
502 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
503 | SSC_BF(RCMR_STTDLY, 1)
504 | SSC_BF(RCMR_START, SSC_START_RISING_RF)
505 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
506 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
507 | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
509 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
510 | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
511 | SSC_BF(RFMR_FSLEN, 0)
512 | SSC_BF(RFMR_DATNB, (channels - 1))
514 | SSC_BF(RFMR_LOOP, 0)
515 | SSC_BF(RFMR_DATLEN, (bits - 1));
517 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
518 | SSC_BF(TCMR_STTDLY, 1)
519 | SSC_BF(TCMR_START, SSC_START_RISING_RF)
520 | SSC_BF(TCMR_CKI, SSC_CKI_RISING)
521 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
522 | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
524 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
525 | SSC_BF(TFMR_FSDEN, 0)
526 | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
527 | SSC_BF(TFMR_FSLEN, 0)
528 | SSC_BF(TFMR_DATNB, (channels - 1))
530 | SSC_BF(TFMR_DATDEF, 0)
531 | SSC_BF(TFMR_DATLEN, (bits - 1));
534 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
536 * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks.
538 * The SSC transmit clock is obtained from the BCLK signal on
539 * on the TK line, and the SSC receive clock is
540 * generated from the transmit clock.
542 * Data is transferred on first BCLK after LRC pulse rising
543 * edge.If stereo, the right channel data is contiguous with
544 * the left channel data.
546 rcmr = SSC_BF(RCMR_PERIOD, 0)
547 | SSC_BF(RCMR_STTDLY, START_DELAY)
548 | SSC_BF(RCMR_START, SSC_START_RISING_RF)
549 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
550 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
551 | SSC_BF(RCMR_CKS, SSC_CKS_PIN);
553 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
554 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
555 | SSC_BF(RFMR_FSLEN, 0)
556 | SSC_BF(RFMR_DATNB, (channels - 1))
558 | SSC_BF(RFMR_LOOP, 0)
559 | SSC_BF(RFMR_DATLEN, (bits - 1));
561 tcmr = SSC_BF(TCMR_PERIOD, 0)
562 | SSC_BF(TCMR_STTDLY, START_DELAY)
563 | SSC_BF(TCMR_START, SSC_START_RISING_RF)
564 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
565 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
566 | SSC_BF(TCMR_CKS, SSC_CKS_PIN);
568 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
569 | SSC_BF(TFMR_FSDEN, 0)
570 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
571 | SSC_BF(TFMR_FSLEN, 0)
572 | SSC_BF(TFMR_DATNB, (channels - 1))
574 | SSC_BF(TFMR_DATDEF, 0)
575 | SSC_BF(TFMR_DATLEN, (bits - 1));
579 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
583 pr_debug("atmel_ssc_hw_params: "
584 "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
585 rcmr, rfmr, tcmr, tfmr);
587 if (!ssc_p->initialized) {
589 /* Enable PMC peripheral clock for this SSC */
590 pr_debug("atmel_ssc_dai: Starting clock\n");
591 clk_enable(ssc_p->ssc->clk);
593 /* Reset the SSC and its PDC registers */
594 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
596 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
597 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
598 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
599 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
601 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
602 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
603 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
604 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
606 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
610 "atmel_ssc_dai: request_irq failure\n");
611 pr_debug("Atmel_ssc_dai: Stoping clock\n");
612 clk_disable(ssc_p->ssc->clk);
616 ssc_p->initialized = 1;
619 /* set SSC clock mode register */
620 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
622 /* set receive clock mode and format */
623 ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
624 ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
626 /* set transmit clock mode and format */
627 ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
628 ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
630 pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
635 static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
636 struct snd_soc_dai *dai)
638 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
639 struct atmel_pcm_dma_params *dma_params;
642 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
647 dma_params = ssc_p->dma_params[dir];
649 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
651 pr_debug("%s enabled SSC_SR=0x%08x\n",
652 dir ? "receive" : "transmit",
653 ssc_readl(ssc_p->ssc->regs, SR));
659 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
661 struct atmel_ssc_info *ssc_p;
663 if (!cpu_dai->active)
666 ssc_p = &ssc_info[cpu_dai->id];
668 /* Save the status register before disabling transmit and receive */
669 ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
670 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
672 /* Save the current interrupt mask, then disable unmasked interrupts */
673 ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
674 ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
676 ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
677 ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
678 ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
679 ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
680 ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
687 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
689 struct atmel_ssc_info *ssc_p;
692 if (!cpu_dai->active)
695 ssc_p = &ssc_info[cpu_dai->id];
697 /* restore SSC register settings */
698 ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
699 ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
700 ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
701 ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
702 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
704 /* re-enable interrupts */
705 ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
707 /* Re-enable receive and transmit as appropriate */
710 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
712 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
713 ssc_writel(ssc_p->ssc->regs, CR, cr);
717 #else /* CONFIG_PM */
718 # define atmel_ssc_suspend NULL
719 # define atmel_ssc_resume NULL
720 #endif /* CONFIG_PM */
722 #define ATMEL_SSC_RATES (SNDRV_PCM_RATE_8000_96000)
724 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
725 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
727 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = {
728 .startup = atmel_ssc_startup,
729 .shutdown = atmel_ssc_shutdown,
730 .prepare = atmel_ssc_prepare,
731 .hw_params = atmel_ssc_hw_params,
732 .set_fmt = atmel_ssc_set_dai_fmt,
733 .set_clkdiv = atmel_ssc_set_dai_clkdiv,
736 static struct snd_soc_dai_driver atmel_ssc_dai = {
737 .suspend = atmel_ssc_suspend,
738 .resume = atmel_ssc_resume,
742 .rates = ATMEL_SSC_RATES,
743 .formats = ATMEL_SSC_FORMATS,},
747 .rates = ATMEL_SSC_RATES,
748 .formats = ATMEL_SSC_FORMATS,},
749 .ops = &atmel_ssc_dai_ops,
752 static const struct snd_soc_component_driver atmel_ssc_component = {
756 static int asoc_ssc_init(struct device *dev)
758 struct platform_device *pdev = to_platform_device(dev);
759 struct ssc_device *ssc = platform_get_drvdata(pdev);
762 ret = snd_soc_register_component(dev, &atmel_ssc_component,
765 dev_err(dev, "Could not register DAI: %d\n", ret);
769 if (ssc->pdata->use_dma)
770 ret = atmel_pcm_dma_platform_register(dev);
772 ret = atmel_pcm_pdc_platform_register(dev);
775 dev_err(dev, "Could not register PCM: %d\n", ret);
776 goto err_unregister_dai;
782 snd_soc_unregister_component(dev);
787 static void asoc_ssc_exit(struct device *dev)
789 struct platform_device *pdev = to_platform_device(dev);
790 struct ssc_device *ssc = platform_get_drvdata(pdev);
792 if (ssc->pdata->use_dma)
793 atmel_pcm_dma_platform_unregister(dev);
795 atmel_pcm_pdc_platform_unregister(dev);
797 snd_soc_unregister_component(dev);
801 * atmel_ssc_set_audio - Allocate the specified SSC for audio use.
803 int atmel_ssc_set_audio(int ssc_id)
805 struct ssc_device *ssc;
808 /* If we can grab the SSC briefly to parent the DAI device off it */
809 ssc = ssc_request(ssc_id);
811 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n",
815 ssc_info[ssc_id].ssc = ssc;
818 ret = asoc_ssc_init(&ssc->pdev->dev);
822 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio);
824 void atmel_ssc_put_audio(int ssc_id)
826 struct ssc_device *ssc = ssc_info[ssc_id].ssc;
828 asoc_ssc_exit(&ssc->pdev->dev);
831 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);
833 /* Module information */
834 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
835 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
836 MODULE_LICENSE("GPL");