2 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2008 Atmel
7 * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
10 * Based on at91-ssc.c by
11 * Frank Mandarino <fmandarino@endrelia.com>
12 * Based on pxa2xx Platform drivers by
13 * Liam Girdwood <lrg@slimlogic.co.uk>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include <linux/init.h>
31 #include <linux/module.h>
32 #include <linux/interrupt.h>
33 #include <linux/device.h>
34 #include <linux/delay.h>
35 #include <linux/clk.h>
36 #include <linux/atmel_pdc.h>
38 #include <linux/atmel-ssc.h>
39 #include <sound/core.h>
40 #include <sound/pcm.h>
41 #include <sound/pcm_params.h>
42 #include <sound/initval.h>
43 #include <sound/soc.h>
45 #include "atmel-pcm.h"
46 #include "atmel_ssc_dai.h"
49 #define NUM_SSC_DEVICES 3
52 * SSC PDC registers required by the PCM DMA engine.
54 static struct atmel_pdc_regs pdc_tx_reg = {
57 .xnpr = ATMEL_PDC_TNPR,
58 .xncr = ATMEL_PDC_TNCR,
61 static struct atmel_pdc_regs pdc_rx_reg = {
64 .xnpr = ATMEL_PDC_RNPR,
65 .xncr = ATMEL_PDC_RNCR,
69 * SSC & PDC status bits for transmit and receive.
71 static struct atmel_ssc_mask ssc_tx_mask = {
72 .ssc_enable = SSC_BIT(CR_TXEN),
73 .ssc_disable = SSC_BIT(CR_TXDIS),
74 .ssc_endx = SSC_BIT(SR_ENDTX),
75 .ssc_endbuf = SSC_BIT(SR_TXBUFE),
76 .ssc_error = SSC_BIT(SR_OVRUN),
77 .pdc_enable = ATMEL_PDC_TXTEN,
78 .pdc_disable = ATMEL_PDC_TXTDIS,
81 static struct atmel_ssc_mask ssc_rx_mask = {
82 .ssc_enable = SSC_BIT(CR_RXEN),
83 .ssc_disable = SSC_BIT(CR_RXDIS),
84 .ssc_endx = SSC_BIT(SR_ENDRX),
85 .ssc_endbuf = SSC_BIT(SR_RXBUFF),
86 .ssc_error = SSC_BIT(SR_OVRUN),
87 .pdc_enable = ATMEL_PDC_RXTEN,
88 .pdc_disable = ATMEL_PDC_RXTDIS,
95 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
97 .name = "SSC0 PCM out",
102 .name = "SSC0 PCM in",
104 .mask = &ssc_rx_mask,
107 .name = "SSC1 PCM out",
109 .mask = &ssc_tx_mask,
112 .name = "SSC1 PCM in",
114 .mask = &ssc_rx_mask,
117 .name = "SSC2 PCM out",
119 .mask = &ssc_tx_mask,
122 .name = "SSC2 PCM in",
124 .mask = &ssc_rx_mask,
129 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
132 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
133 .dir_mask = SSC_DIR_MASK_UNUSED,
138 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
139 .dir_mask = SSC_DIR_MASK_UNUSED,
144 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
145 .dir_mask = SSC_DIR_MASK_UNUSED,
152 * SSC interrupt handler. Passes PDC interrupts to the DMA
153 * interrupt handler in the PCM driver.
155 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
157 struct atmel_ssc_info *ssc_p = dev_id;
158 struct atmel_pcm_dma_params *dma_params;
160 u32 ssc_substream_mask;
163 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
164 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
167 * Loop through the substreams attached to this SSC. If
168 * a DMA-related interrupt occurred on that substream, call
169 * the DMA interrupt handler function, if one has been
170 * registered in the dma_params structure by the PCM driver.
172 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
173 dma_params = ssc_p->dma_params[i];
175 if ((dma_params != NULL) &&
176 (dma_params->dma_intr_handler != NULL)) {
177 ssc_substream_mask = (dma_params->mask->ssc_endx |
178 dma_params->mask->ssc_endbuf);
179 if (ssc_sr & ssc_substream_mask) {
180 dma_params->dma_intr_handler(ssc_sr,
191 /*-------------------------------------------------------------------------*\
193 \*-------------------------------------------------------------------------*/
195 * Startup. Only that one substream allowed in each direction.
197 static int atmel_ssc_startup(struct snd_pcm_substream *substream,
198 struct snd_soc_dai *dai)
200 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
201 struct atmel_pcm_dma_params *dma_params;
204 pr_debug("atmel_ssc_startup: SSC_SR=0x%u\n",
205 ssc_readl(ssc_p->ssc->regs, SR));
207 /* Enable PMC peripheral clock for this SSC */
208 pr_debug("atmel_ssc_dai: Starting clock\n");
209 clk_enable(ssc_p->ssc->clk);
211 /* Reset the SSC to keep it at a clean status */
212 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
214 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
216 dir_mask = SSC_DIR_MASK_PLAYBACK;
219 dir_mask = SSC_DIR_MASK_CAPTURE;
222 dma_params = &ssc_dma_params[dai->id][dir];
223 dma_params->ssc = ssc_p->ssc;
224 dma_params->substream = substream;
226 ssc_p->dma_params[dir] = dma_params;
228 snd_soc_dai_set_dma_data(dai, substream, dma_params);
230 spin_lock_irq(&ssc_p->lock);
231 if (ssc_p->dir_mask & dir_mask) {
232 spin_unlock_irq(&ssc_p->lock);
235 ssc_p->dir_mask |= dir_mask;
236 spin_unlock_irq(&ssc_p->lock);
242 * Shutdown. Clear DMA parameters and shutdown the SSC if there
243 * are no other substreams open.
245 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
246 struct snd_soc_dai *dai)
248 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
249 struct atmel_pcm_dma_params *dma_params;
252 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
257 dma_params = ssc_p->dma_params[dir];
259 if (dma_params != NULL) {
260 dma_params->ssc = NULL;
261 dma_params->substream = NULL;
262 ssc_p->dma_params[dir] = NULL;
267 spin_lock_irq(&ssc_p->lock);
268 ssc_p->dir_mask &= ~dir_mask;
269 if (!ssc_p->dir_mask) {
270 if (ssc_p->initialized) {
271 free_irq(ssc_p->ssc->irq, ssc_p);
272 ssc_p->initialized = 0;
276 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
277 /* Clear the SSC dividers */
278 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
280 spin_unlock_irq(&ssc_p->lock);
282 /* Shutdown the SSC clock. */
283 pr_debug("atmel_ssc_dai: Stopping clock\n");
284 clk_disable(ssc_p->ssc->clk);
289 * Record the DAI format for use in hw_params().
291 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
294 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
301 * Record SSC clock dividers for use in hw_params().
303 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
306 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
309 case ATMEL_SSC_CMR_DIV:
311 * The same master clock divider is used for both
312 * transmit and receive, so if a value has already
313 * been set, it must match this value.
315 if (ssc_p->dir_mask !=
316 (SSC_DIR_MASK_PLAYBACK | SSC_DIR_MASK_CAPTURE))
317 ssc_p->cmr_div = div;
318 else if (ssc_p->cmr_div == 0)
319 ssc_p->cmr_div = div;
321 if (div != ssc_p->cmr_div)
325 case ATMEL_SSC_TCMR_PERIOD:
326 ssc_p->tcmr_period = div;
329 case ATMEL_SSC_RCMR_PERIOD:
330 ssc_p->rcmr_period = div;
343 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
344 struct snd_pcm_hw_params *params,
345 struct snd_soc_dai *dai)
348 struct atmel_ssc_info *ssc_p = &ssc_info[id];
349 struct ssc_device *ssc = ssc_p->ssc;
350 struct atmel_pcm_dma_params *dma_params;
351 int dir, channels, bits;
352 u32 tfmr, rfmr, tcmr, rcmr;
354 int fslen, fslen_ext;
357 * Currently, there is only one set of dma params for
358 * each direction. If more are added, this code will
359 * have to be changed to select the proper set.
361 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
366 dma_params = ssc_p->dma_params[dir];
368 channels = params_channels(params);
371 * Determine sample size in bits and the PDC increment.
373 switch (params_format(params)) {
374 case SNDRV_PCM_FORMAT_S8:
376 dma_params->pdc_xfer_size = 1;
378 case SNDRV_PCM_FORMAT_S16_LE:
380 dma_params->pdc_xfer_size = 2;
382 case SNDRV_PCM_FORMAT_S24_LE:
384 dma_params->pdc_xfer_size = 4;
386 case SNDRV_PCM_FORMAT_S32_LE:
388 dma_params->pdc_xfer_size = 4;
391 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
396 * Compute SSC register settings.
398 switch (ssc_p->daifmt
399 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
401 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
403 * I2S format, SSC provides BCLK and LRC clocks.
405 * The SSC transmit and receive clocks are generated
406 * from the MCK divider, and the BCLK signal
407 * is output on the SSC TK line.
410 if (bits > 16 && !ssc->pdata->has_fslen_ext) {
412 "sample size %d is too large for SSC device\n",
417 fslen_ext = (bits - 1) / 16;
418 fslen = (bits - 1) % 16;
420 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
421 | SSC_BF(RCMR_STTDLY, START_DELAY)
422 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
423 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
424 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
425 | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
427 rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
428 | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
429 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
430 | SSC_BF(RFMR_FSLEN, fslen)
431 | SSC_BF(RFMR_DATNB, (channels - 1))
433 | SSC_BF(RFMR_LOOP, 0)
434 | SSC_BF(RFMR_DATLEN, (bits - 1));
436 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
437 | SSC_BF(TCMR_STTDLY, START_DELAY)
438 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
439 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
440 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
441 | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
443 tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
444 | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
445 | SSC_BF(TFMR_FSDEN, 0)
446 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
447 | SSC_BF(TFMR_FSLEN, fslen)
448 | SSC_BF(TFMR_DATNB, (channels - 1))
450 | SSC_BF(TFMR_DATDEF, 0)
451 | SSC_BF(TFMR_DATLEN, (bits - 1));
454 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
455 /* I2S format, CODEC supplies BCLK and LRC clocks. */
456 rcmr = SSC_BF(RCMR_PERIOD, 0)
457 | SSC_BF(RCMR_STTDLY, START_DELAY)
458 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
459 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
460 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
461 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
462 SSC_CKS_PIN : SSC_CKS_CLOCK);
464 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
465 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
466 | SSC_BF(RFMR_FSLEN, 0)
467 | SSC_BF(RFMR_DATNB, (channels - 1))
469 | SSC_BF(RFMR_LOOP, 0)
470 | SSC_BF(RFMR_DATLEN, (bits - 1));
472 tcmr = SSC_BF(TCMR_PERIOD, 0)
473 | SSC_BF(TCMR_STTDLY, START_DELAY)
474 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
475 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
476 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
477 | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
478 SSC_CKS_CLOCK : SSC_CKS_PIN);
480 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
481 | SSC_BF(TFMR_FSDEN, 0)
482 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
483 | SSC_BF(TFMR_FSLEN, 0)
484 | SSC_BF(TFMR_DATNB, (channels - 1))
486 | SSC_BF(TFMR_DATDEF, 0)
487 | SSC_BF(TFMR_DATLEN, (bits - 1));
490 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFS:
491 /* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */
492 if (bits > 16 && !ssc->pdata->has_fslen_ext) {
494 "sample size %d is too large for SSC device\n",
499 fslen_ext = (bits - 1) / 16;
500 fslen = (bits - 1) % 16;
502 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
503 | SSC_BF(RCMR_STTDLY, START_DELAY)
504 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
505 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
506 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
507 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
508 SSC_CKS_PIN : SSC_CKS_CLOCK);
510 rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
511 | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
512 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
513 | SSC_BF(RFMR_FSLEN, fslen)
514 | SSC_BF(RFMR_DATNB, (channels - 1))
516 | SSC_BF(RFMR_LOOP, 0)
517 | SSC_BF(RFMR_DATLEN, (bits - 1));
519 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
520 | SSC_BF(TCMR_STTDLY, START_DELAY)
521 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
522 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
523 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
524 | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
525 SSC_CKS_CLOCK : SSC_CKS_PIN);
527 tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
528 | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_NEGATIVE)
529 | SSC_BF(TFMR_FSDEN, 0)
530 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
531 | SSC_BF(TFMR_FSLEN, fslen)
532 | SSC_BF(TFMR_DATNB, (channels - 1))
534 | SSC_BF(TFMR_DATDEF, 0)
535 | SSC_BF(TFMR_DATLEN, (bits - 1));
538 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
540 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
542 * The SSC transmit and receive clocks are generated from the
543 * MCK divider, and the BCLK signal is output
544 * on the SSC TK line.
546 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
547 | SSC_BF(RCMR_STTDLY, 1)
548 | SSC_BF(RCMR_START, SSC_START_RISING_RF)
549 | SSC_BF(RCMR_CKI, SSC_CKI_FALLING)
550 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
551 | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
553 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
554 | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
555 | SSC_BF(RFMR_FSLEN, 0)
556 | SSC_BF(RFMR_DATNB, (channels - 1))
558 | SSC_BF(RFMR_LOOP, 0)
559 | SSC_BF(RFMR_DATLEN, (bits - 1));
561 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
562 | SSC_BF(TCMR_STTDLY, 1)
563 | SSC_BF(TCMR_START, SSC_START_RISING_RF)
564 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
565 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
566 | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
568 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
569 | SSC_BF(TFMR_FSDEN, 0)
570 | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
571 | SSC_BF(TFMR_FSLEN, 0)
572 | SSC_BF(TFMR_DATNB, (channels - 1))
574 | SSC_BF(TFMR_DATDEF, 0)
575 | SSC_BF(TFMR_DATLEN, (bits - 1));
578 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
580 * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks.
582 * Data is transferred on first BCLK after LRC pulse rising
583 * edge.If stereo, the right channel data is contiguous with
584 * the left channel data.
586 rcmr = SSC_BF(RCMR_PERIOD, 0)
587 | SSC_BF(RCMR_STTDLY, START_DELAY)
588 | SSC_BF(RCMR_START, SSC_START_RISING_RF)
589 | SSC_BF(RCMR_CKI, SSC_CKI_FALLING)
590 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
591 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
592 SSC_CKS_PIN : SSC_CKS_CLOCK);
594 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
595 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
596 | SSC_BF(RFMR_FSLEN, 0)
597 | SSC_BF(RFMR_DATNB, (channels - 1))
599 | SSC_BF(RFMR_LOOP, 0)
600 | SSC_BF(RFMR_DATLEN, (bits - 1));
602 tcmr = SSC_BF(TCMR_PERIOD, 0)
603 | SSC_BF(TCMR_STTDLY, START_DELAY)
604 | SSC_BF(TCMR_START, SSC_START_RISING_RF)
605 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
606 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
607 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
608 SSC_CKS_CLOCK : SSC_CKS_PIN);
610 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
611 | SSC_BF(TFMR_FSDEN, 0)
612 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
613 | SSC_BF(TFMR_FSLEN, 0)
614 | SSC_BF(TFMR_DATNB, (channels - 1))
616 | SSC_BF(TFMR_DATDEF, 0)
617 | SSC_BF(TFMR_DATLEN, (bits - 1));
621 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
625 pr_debug("atmel_ssc_hw_params: "
626 "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
627 rcmr, rfmr, tcmr, tfmr);
629 if (!ssc_p->initialized) {
630 if (!ssc_p->ssc->pdata->use_dma) {
631 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
632 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
633 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
634 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
636 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
637 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
638 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
639 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
642 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
646 "atmel_ssc_dai: request_irq failure\n");
647 pr_debug("Atmel_ssc_dai: Stoping clock\n");
648 clk_disable(ssc_p->ssc->clk);
652 ssc_p->initialized = 1;
655 /* set SSC clock mode register */
656 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
658 /* set receive clock mode and format */
659 ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
660 ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
662 /* set transmit clock mode and format */
663 ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
664 ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
666 pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
671 static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
672 struct snd_soc_dai *dai)
674 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
675 struct atmel_pcm_dma_params *dma_params;
678 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
683 dma_params = ssc_p->dma_params[dir];
685 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
686 ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error);
688 pr_debug("%s enabled SSC_SR=0x%08x\n",
689 dir ? "receive" : "transmit",
690 ssc_readl(ssc_p->ssc->regs, SR));
694 static int atmel_ssc_trigger(struct snd_pcm_substream *substream,
695 int cmd, struct snd_soc_dai *dai)
697 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
698 struct atmel_pcm_dma_params *dma_params;
701 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
706 dma_params = ssc_p->dma_params[dir];
709 case SNDRV_PCM_TRIGGER_START:
710 case SNDRV_PCM_TRIGGER_RESUME:
711 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
712 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
715 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
723 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
725 struct atmel_ssc_info *ssc_p;
727 if (!cpu_dai->active)
730 ssc_p = &ssc_info[cpu_dai->id];
732 /* Save the status register before disabling transmit and receive */
733 ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
734 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
736 /* Save the current interrupt mask, then disable unmasked interrupts */
737 ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
738 ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
740 ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
741 ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
742 ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
743 ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
744 ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
751 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
753 struct atmel_ssc_info *ssc_p;
756 if (!cpu_dai->active)
759 ssc_p = &ssc_info[cpu_dai->id];
761 /* restore SSC register settings */
762 ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
763 ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
764 ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
765 ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
766 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
768 /* re-enable interrupts */
769 ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
771 /* Re-enable receive and transmit as appropriate */
774 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
776 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
777 ssc_writel(ssc_p->ssc->regs, CR, cr);
781 #else /* CONFIG_PM */
782 # define atmel_ssc_suspend NULL
783 # define atmel_ssc_resume NULL
784 #endif /* CONFIG_PM */
786 #define ATMEL_SSC_RATES (SNDRV_PCM_RATE_8000_96000)
788 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
789 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
791 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = {
792 .startup = atmel_ssc_startup,
793 .shutdown = atmel_ssc_shutdown,
794 .prepare = atmel_ssc_prepare,
795 .trigger = atmel_ssc_trigger,
796 .hw_params = atmel_ssc_hw_params,
797 .set_fmt = atmel_ssc_set_dai_fmt,
798 .set_clkdiv = atmel_ssc_set_dai_clkdiv,
801 static struct snd_soc_dai_driver atmel_ssc_dai = {
802 .suspend = atmel_ssc_suspend,
803 .resume = atmel_ssc_resume,
807 .rates = ATMEL_SSC_RATES,
808 .formats = ATMEL_SSC_FORMATS,},
812 .rates = ATMEL_SSC_RATES,
813 .formats = ATMEL_SSC_FORMATS,},
814 .ops = &atmel_ssc_dai_ops,
817 static const struct snd_soc_component_driver atmel_ssc_component = {
821 static int asoc_ssc_init(struct device *dev)
823 struct platform_device *pdev = to_platform_device(dev);
824 struct ssc_device *ssc = platform_get_drvdata(pdev);
827 ret = snd_soc_register_component(dev, &atmel_ssc_component,
830 dev_err(dev, "Could not register DAI: %d\n", ret);
834 if (ssc->pdata->use_dma)
835 ret = atmel_pcm_dma_platform_register(dev);
837 ret = atmel_pcm_pdc_platform_register(dev);
840 dev_err(dev, "Could not register PCM: %d\n", ret);
841 goto err_unregister_dai;
847 snd_soc_unregister_component(dev);
852 static void asoc_ssc_exit(struct device *dev)
854 struct platform_device *pdev = to_platform_device(dev);
855 struct ssc_device *ssc = platform_get_drvdata(pdev);
857 if (ssc->pdata->use_dma)
858 atmel_pcm_dma_platform_unregister(dev);
860 atmel_pcm_pdc_platform_unregister(dev);
862 snd_soc_unregister_component(dev);
866 * atmel_ssc_set_audio - Allocate the specified SSC for audio use.
868 int atmel_ssc_set_audio(int ssc_id)
870 struct ssc_device *ssc;
873 /* If we can grab the SSC briefly to parent the DAI device off it */
874 ssc = ssc_request(ssc_id);
876 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n",
880 ssc_info[ssc_id].ssc = ssc;
883 ret = asoc_ssc_init(&ssc->pdev->dev);
887 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio);
889 void atmel_ssc_put_audio(int ssc_id)
891 struct ssc_device *ssc = ssc_info[ssc_id].ssc;
893 asoc_ssc_exit(&ssc->pdev->dev);
896 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);
898 /* Module information */
899 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
900 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
901 MODULE_LICENSE("GPL");