2 * Common code for ADAU1X61 and ADAU1X81 codecs
4 * Copyright 2011-2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 * Licensed under the GPL-2 or later.
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <sound/core.h>
15 #include <sound/pcm.h>
16 #include <sound/pcm_params.h>
17 #include <sound/soc.h>
18 #include <sound/tlv.h>
19 #include <linux/gcd.h>
20 #include <linux/i2c.h>
21 #include <linux/spi/spi.h>
22 #include <linux/regmap.h>
27 static const char * const adau17x1_capture_mixer_boost_text[] = {
28 "Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3",
31 static SOC_ENUM_SINGLE_DECL(adau17x1_capture_boost_enum,
32 ADAU17X1_REC_POWER_MGMT, 5, adau17x1_capture_mixer_boost_text);
34 static const char * const adau17x1_mic_bias_mode_text[] = {
35 "Normal operation", "High performance",
38 static SOC_ENUM_SINGLE_DECL(adau17x1_mic_bias_mode_enum,
39 ADAU17X1_MICBIAS, 3, adau17x1_mic_bias_mode_text);
41 static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0);
43 static const struct snd_kcontrol_new adau17x1_controls[] = {
44 SOC_DOUBLE_R_TLV("Digital Capture Volume",
45 ADAU17X1_LEFT_INPUT_DIGITAL_VOL,
46 ADAU17X1_RIGHT_INPUT_DIGITAL_VOL,
47 0, 0xff, 1, adau17x1_digital_tlv),
48 SOC_DOUBLE_R_TLV("Digital Playback Volume", ADAU17X1_DAC_CONTROL1,
49 ADAU17X1_DAC_CONTROL2, 0, 0xff, 1, adau17x1_digital_tlv),
51 SOC_SINGLE("ADC High Pass Filter Switch", ADAU17X1_ADC_CONTROL,
53 SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0,
56 SOC_ENUM("Capture Boost", adau17x1_capture_boost_enum),
58 SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum),
61 static int adau17x1_pll_event(struct snd_soc_dapm_widget *w,
62 struct snd_kcontrol *kcontrol, int event)
64 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
65 struct adau *adau = snd_soc_codec_get_drvdata(codec);
68 if (SND_SOC_DAPM_EVENT_ON(event)) {
69 adau->pll_regs[5] = 1;
71 adau->pll_regs[5] = 0;
72 /* Bypass the PLL when disabled, otherwise registers will become
74 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
75 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0);
78 /* The PLL register is 6 bytes long and can only be written at once. */
79 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
80 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
82 if (SND_SOC_DAPM_EVENT_ON(event)) {
84 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
85 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL,
86 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL);
92 static const char * const adau17x1_mono_stereo_text[] = {
94 "Mono Left Channel (L+R)",
95 "Mono Right Channel (L+R)",
99 static SOC_ENUM_SINGLE_DECL(adau17x1_dac_mode_enum,
100 ADAU17X1_DAC_CONTROL0, 6, adau17x1_mono_stereo_text);
102 static const struct snd_kcontrol_new adau17x1_dac_mode_mux =
103 SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum);
105 static const struct snd_soc_dapm_widget adau17x1_dapm_widgets[] = {
106 SND_SOC_DAPM_SUPPLY_S("PLL", 3, SND_SOC_NOPM, 0, 0, adau17x1_pll_event,
107 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
109 SND_SOC_DAPM_SUPPLY("AIFCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
111 SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU17X1_MICBIAS, 0, 0, NULL, 0),
113 SND_SOC_DAPM_SUPPLY("Left Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
115 SND_SOC_DAPM_SUPPLY("Right Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
118 SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0,
119 &adau17x1_dac_mode_mux),
120 SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0,
121 &adau17x1_dac_mode_mux),
123 SND_SOC_DAPM_ADC("Left Decimator", NULL, ADAU17X1_ADC_CONTROL, 0, 0),
124 SND_SOC_DAPM_ADC("Right Decimator", NULL, ADAU17X1_ADC_CONTROL, 1, 0),
125 SND_SOC_DAPM_DAC("Left DAC", NULL, ADAU17X1_DAC_CONTROL0, 0, 0),
126 SND_SOC_DAPM_DAC("Right DAC", NULL, ADAU17X1_DAC_CONTROL0, 1, 0),
129 static const struct snd_soc_dapm_route adau17x1_dapm_routes[] = {
130 { "Left Decimator", NULL, "SYSCLK" },
131 { "Right Decimator", NULL, "SYSCLK" },
132 { "Left DAC", NULL, "SYSCLK" },
133 { "Right DAC", NULL, "SYSCLK" },
134 { "Capture", NULL, "SYSCLK" },
135 { "Playback", NULL, "SYSCLK" },
137 { "Left DAC", NULL, "Left DAC Mode Mux" },
138 { "Right DAC", NULL, "Right DAC Mode Mux" },
140 { "Capture", NULL, "AIFCLK" },
141 { "Playback", NULL, "AIFCLK" },
144 static const struct snd_soc_dapm_route adau17x1_dapm_pll_route = {
145 "SYSCLK", NULL, "PLL",
149 * The MUX register for the Capture and Playback MUXs selects either DSP as
150 * source/destination or one of the TDM slots. The TDM slot is selected via
151 * snd_soc_dai_set_tdm_slot(), so we only expose whether to go to the DSP or
152 * directly to the DAI interface with this control.
154 static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol,
155 struct snd_ctl_elem_value *ucontrol)
157 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
158 struct adau *adau = snd_soc_codec_get_drvdata(codec);
159 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
160 struct snd_soc_dapm_update update;
161 unsigned int stream = e->shift_l;
162 unsigned int val, change;
165 if (ucontrol->value.enumerated.item[0] >= e->items)
168 switch (ucontrol->value.enumerated.item[0]) {
171 adau->dsp_bypass[stream] = false;
174 val = (adau->tdm_slot[stream] * 2) + 1;
175 adau->dsp_bypass[stream] = true;
179 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
180 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
182 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
184 change = snd_soc_test_bits(codec, reg, 0xff, val);
186 update.kcontrol = kcontrol;
191 snd_soc_dapm_mux_update_power(&codec->dapm, kcontrol,
192 ucontrol->value.enumerated.item[0], e, &update);
198 static int adau17x1_dsp_mux_enum_get(struct snd_kcontrol *kcontrol,
199 struct snd_ctl_elem_value *ucontrol)
201 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
202 struct adau *adau = snd_soc_codec_get_drvdata(codec);
203 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
204 unsigned int stream = e->shift_l;
205 unsigned int reg, val;
208 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
209 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
211 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
213 ret = regmap_read(adau->regmap, reg, &val);
219 ucontrol->value.enumerated.item[0] = val;
224 #define DECLARE_ADAU17X1_DSP_MUX_CTRL(_name, _label, _stream, _text) \
225 const struct snd_kcontrol_new _name = \
226 SOC_DAPM_ENUM_EXT(_label, (const struct soc_enum)\
227 SOC_ENUM_SINGLE(SND_SOC_NOPM, _stream, \
228 ARRAY_SIZE(_text), _text), \
229 adau17x1_dsp_mux_enum_get, adau17x1_dsp_mux_enum_put)
231 static const char * const adau17x1_dac_mux_text[] = {
236 static const char * const adau17x1_capture_mux_text[] = {
241 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_dac_mux, "DAC Playback Mux",
242 SNDRV_PCM_STREAM_PLAYBACK, adau17x1_dac_mux_text);
244 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_capture_mux, "Capture Mux",
245 SNDRV_PCM_STREAM_CAPTURE, adau17x1_capture_mux_text);
247 static const struct snd_soc_dapm_widget adau17x1_dsp_dapm_widgets[] = {
248 SND_SOC_DAPM_PGA("DSP", ADAU17X1_DSP_RUN, 0, 0, NULL, 0),
249 SND_SOC_DAPM_SIGGEN("DSP Siggen"),
251 SND_SOC_DAPM_MUX("DAC Playback Mux", SND_SOC_NOPM, 0, 0,
253 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
254 &adau17x1_capture_mux),
257 static const struct snd_soc_dapm_route adau17x1_dsp_dapm_routes[] = {
258 { "DAC Playback Mux", "DSP", "DSP" },
259 { "DAC Playback Mux", "AIFIN", "Playback" },
261 { "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" },
262 { "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
263 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" },
264 { "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" },
265 { "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
266 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" },
268 { "Capture Mux", "DSP", "DSP" },
269 { "Capture Mux", "Decimator", "Left Decimator" },
270 { "Capture Mux", "Decimator", "Right Decimator" },
272 { "Capture", NULL, "Capture Mux" },
274 { "DSP", NULL, "DSP Siggen" },
276 { "DSP", NULL, "Left Decimator" },
277 { "DSP", NULL, "Right Decimator" },
280 static const struct snd_soc_dapm_route adau17x1_no_dsp_dapm_routes[] = {
281 { "Left DAC Mode Mux", "Stereo", "Playback" },
282 { "Left DAC Mode Mux", "Mono (L+R)", "Playback" },
283 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" },
284 { "Right DAC Mode Mux", "Stereo", "Playback" },
285 { "Right DAC Mode Mux", "Mono (L+R)", "Playback" },
286 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" },
287 { "Capture", NULL, "Left Decimator" },
288 { "Capture", NULL, "Right Decimator" },
291 bool adau17x1_has_dsp(struct adau *adau)
293 switch (adau->type) {
302 EXPORT_SYMBOL_GPL(adau17x1_has_dsp);
304 static int adau17x1_hw_params(struct snd_pcm_substream *substream,
305 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
307 struct snd_soc_codec *codec = dai->codec;
308 struct adau *adau = snd_soc_codec_get_drvdata(codec);
309 unsigned int val, div, dsp_div;
313 if (adau->clk_src == ADAU17X1_CLK_SRC_PLL)
314 freq = adau->pll_freq;
318 if (freq % params_rate(params) != 0)
321 switch (freq / params_rate(params)) {
326 case 6144: /* fs / 6 */
330 case 4096: /* fs / 4 */
334 case 3072: /* fs / 3 */
338 case 2048: /* fs / 2 */
342 case 1536: /* fs / 1.5 */
346 case 512: /* fs / 0.5 */
354 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
355 ADAU17X1_CONVERTER0_CONVSR_MASK, div);
356 if (adau17x1_has_dsp(adau)) {
357 regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div);
358 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dsp_div);
361 if (adau->sigmadsp) {
362 ret = adau17x1_setup_firmware(adau, params_rate(params));
367 if (adau->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
370 switch (params_width(params)) {
372 val = ADAU17X1_SERIAL_PORT1_DELAY16;
375 val = ADAU17X1_SERIAL_PORT1_DELAY8;
378 val = ADAU17X1_SERIAL_PORT1_DELAY0;
384 return regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
385 ADAU17X1_SERIAL_PORT1_DELAY_MASK, val);
388 static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id,
389 int source, unsigned int freq_in, unsigned int freq_out)
391 struct snd_soc_codec *codec = dai->codec;
392 struct adau *adau = snd_soc_codec_get_drvdata(codec);
393 unsigned int r, n, m, i, j;
397 if (freq_in < 8000000 || freq_in > 27000000)
406 if (freq_out % freq_in != 0) {
407 div = DIV_ROUND_UP(freq_in, 13500000);
409 r = freq_out / freq_in;
410 i = freq_out % freq_in;
416 r = freq_out / freq_in;
421 if (n > 0xffff || m > 0xffff || div > 3 || r > 8 || r < 2)
425 adau->pll_regs[0] = m >> 8;
426 adau->pll_regs[1] = m & 0xff;
427 adau->pll_regs[2] = n >> 8;
428 adau->pll_regs[3] = n & 0xff;
429 adau->pll_regs[4] = (r << 3) | (div << 1);
431 adau->pll_regs[4] |= 1; /* Fractional mode */
433 /* The PLL register is 6 bytes long and can only be written at once. */
434 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
435 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
439 adau->pll_freq = freq_out;
444 static int adau17x1_set_dai_sysclk(struct snd_soc_dai *dai,
445 int clk_id, unsigned int freq, int dir)
447 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
448 struct snd_soc_dapm_context *dapm = &dai->codec->dapm;
451 case ADAU17X1_CLK_SRC_MCLK:
452 case ADAU17X1_CLK_SRC_PLL:
460 if (adau->clk_src != clk_id) {
461 if (clk_id == ADAU17X1_CLK_SRC_PLL) {
462 snd_soc_dapm_add_routes(dapm,
463 &adau17x1_dapm_pll_route, 1);
465 snd_soc_dapm_del_routes(dapm,
466 &adau17x1_dapm_pll_route, 1);
470 adau->clk_src = clk_id;
475 static int adau17x1_set_dai_fmt(struct snd_soc_dai *dai,
478 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
479 unsigned int ctrl0, ctrl1;
482 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
483 case SND_SOC_DAIFMT_CBM_CFM:
484 ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER;
487 case SND_SOC_DAIFMT_CBS_CFS:
489 adau->master = false;
495 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
496 case SND_SOC_DAIFMT_I2S:
498 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
500 case SND_SOC_DAIFMT_LEFT_J:
501 case SND_SOC_DAIFMT_RIGHT_J:
503 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
505 case SND_SOC_DAIFMT_DSP_A:
507 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
508 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
510 case SND_SOC_DAIFMT_DSP_B:
512 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
513 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
519 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
520 case SND_SOC_DAIFMT_NB_NF:
522 case SND_SOC_DAIFMT_IB_NF:
523 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
525 case SND_SOC_DAIFMT_NB_IF:
526 lrclk_pol = !lrclk_pol;
528 case SND_SOC_DAIFMT_IB_IF:
529 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
530 lrclk_pol = !lrclk_pol;
537 ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL;
539 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0);
540 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT1, ctrl1);
542 adau->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
547 static int adau17x1_set_dai_tdm_slot(struct snd_soc_dai *dai,
548 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
550 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
551 unsigned int ser_ctrl0, ser_ctrl1;
552 unsigned int conv_ctrl0, conv_ctrl1;
564 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_STEREO;
567 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM4;
570 if (adau->type == ADAU1361)
573 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM8;
579 switch (slot_width * slots) {
581 if (adau->type == ADAU1761)
584 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK32;
587 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK64;
590 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK48;
593 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK128;
596 if (adau->type == ADAU1361)
599 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK256;
607 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(1);
608 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 0;
611 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(2);
612 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 1;
615 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(3);
616 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 2;
619 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(4);
620 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 3;
628 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(1);
629 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 0;
632 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(2);
633 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 1;
636 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(3);
637 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 2;
640 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(4);
641 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 3;
647 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
648 ADAU17X1_CONVERTER0_DAC_PAIR_MASK, conv_ctrl0);
649 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER1,
650 ADAU17X1_CONVERTER1_ADC_PAIR_MASK, conv_ctrl1);
651 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0,
652 ADAU17X1_SERIAL_PORT0_TDM_MASK, ser_ctrl0);
653 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
654 ADAU17X1_SERIAL_PORT1_BCLK_MASK, ser_ctrl1);
656 if (!adau17x1_has_dsp(adau))
659 if (adau->dsp_bypass[SNDRV_PCM_STREAM_PLAYBACK]) {
660 regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE,
661 (adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] * 2) + 1);
664 if (adau->dsp_bypass[SNDRV_PCM_STREAM_CAPTURE]) {
665 regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE,
666 (adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] * 2) + 1);
672 static int adau17x1_startup(struct snd_pcm_substream *substream,
673 struct snd_soc_dai *dai)
675 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
678 return sigmadsp_restrict_params(adau->sigmadsp, substream);
683 const struct snd_soc_dai_ops adau17x1_dai_ops = {
684 .hw_params = adau17x1_hw_params,
685 .set_sysclk = adau17x1_set_dai_sysclk,
686 .set_fmt = adau17x1_set_dai_fmt,
687 .set_pll = adau17x1_set_dai_pll,
688 .set_tdm_slot = adau17x1_set_dai_tdm_slot,
689 .startup = adau17x1_startup,
691 EXPORT_SYMBOL_GPL(adau17x1_dai_ops);
693 int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec,
694 enum adau17x1_micbias_voltage micbias)
696 struct adau *adau = snd_soc_codec_get_drvdata(codec);
699 case ADAU17X1_MICBIAS_0_90_AVDD:
700 case ADAU17X1_MICBIAS_0_65_AVDD:
706 return regmap_write(adau->regmap, ADAU17X1_MICBIAS, micbias << 2);
708 EXPORT_SYMBOL_GPL(adau17x1_set_micbias_voltage);
710 bool adau17x1_precious_register(struct device *dev, unsigned int reg)
712 /* SigmaDSP parameter memory */
718 EXPORT_SYMBOL_GPL(adau17x1_precious_register);
720 bool adau17x1_readable_register(struct device *dev, unsigned int reg)
722 /* SigmaDSP parameter memory */
727 case ADAU17X1_CLOCK_CONTROL:
728 case ADAU17X1_PLL_CONTROL:
729 case ADAU17X1_REC_POWER_MGMT:
730 case ADAU17X1_MICBIAS:
731 case ADAU17X1_SERIAL_PORT0:
732 case ADAU17X1_SERIAL_PORT1:
733 case ADAU17X1_CONVERTER0:
734 case ADAU17X1_CONVERTER1:
735 case ADAU17X1_LEFT_INPUT_DIGITAL_VOL:
736 case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL:
737 case ADAU17X1_ADC_CONTROL:
738 case ADAU17X1_PLAY_POWER_MGMT:
739 case ADAU17X1_DAC_CONTROL0:
740 case ADAU17X1_DAC_CONTROL1:
741 case ADAU17X1_DAC_CONTROL2:
742 case ADAU17X1_SERIAL_PORT_PAD:
743 case ADAU17X1_CONTROL_PORT_PAD0:
744 case ADAU17X1_CONTROL_PORT_PAD1:
745 case ADAU17X1_DSP_SAMPLING_RATE:
746 case ADAU17X1_SERIAL_INPUT_ROUTE:
747 case ADAU17X1_SERIAL_OUTPUT_ROUTE:
748 case ADAU17X1_DSP_ENABLE:
749 case ADAU17X1_DSP_RUN:
750 case ADAU17X1_SERIAL_SAMPLING_RATE:
757 EXPORT_SYMBOL_GPL(adau17x1_readable_register);
759 bool adau17x1_volatile_register(struct device *dev, unsigned int reg)
761 /* SigmaDSP parameter and program memory */
766 /* The PLL register is 6 bytes long */
767 case ADAU17X1_PLL_CONTROL:
768 case ADAU17X1_PLL_CONTROL + 1:
769 case ADAU17X1_PLL_CONTROL + 2:
770 case ADAU17X1_PLL_CONTROL + 3:
771 case ADAU17X1_PLL_CONTROL + 4:
772 case ADAU17X1_PLL_CONTROL + 5:
780 EXPORT_SYMBOL_GPL(adau17x1_volatile_register);
782 int adau17x1_setup_firmware(struct adau *adau, unsigned int rate)
787 ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr);
791 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1);
792 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf);
794 ret = sigmadsp_setup(adau->sigmadsp, rate);
796 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0);
799 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr);
803 EXPORT_SYMBOL_GPL(adau17x1_setup_firmware);
805 int adau17x1_add_widgets(struct snd_soc_codec *codec)
807 struct adau *adau = snd_soc_codec_get_drvdata(codec);
810 ret = snd_soc_add_codec_controls(codec, adau17x1_controls,
811 ARRAY_SIZE(adau17x1_controls));
814 ret = snd_soc_dapm_new_controls(&codec->dapm, adau17x1_dapm_widgets,
815 ARRAY_SIZE(adau17x1_dapm_widgets));
819 if (adau17x1_has_dsp(adau)) {
820 ret = snd_soc_dapm_new_controls(&codec->dapm,
821 adau17x1_dsp_dapm_widgets,
822 ARRAY_SIZE(adau17x1_dsp_dapm_widgets));
829 ret = sigmadsp_attach(adau->sigmadsp, &codec->component);
831 dev_err(codec->dev, "Failed to attach firmware: %d\n",
839 EXPORT_SYMBOL_GPL(adau17x1_add_widgets);
841 int adau17x1_add_routes(struct snd_soc_codec *codec)
843 struct adau *adau = snd_soc_codec_get_drvdata(codec);
846 ret = snd_soc_dapm_add_routes(&codec->dapm, adau17x1_dapm_routes,
847 ARRAY_SIZE(adau17x1_dapm_routes));
851 if (adau17x1_has_dsp(adau)) {
852 ret = snd_soc_dapm_add_routes(&codec->dapm,
853 adau17x1_dsp_dapm_routes,
854 ARRAY_SIZE(adau17x1_dsp_dapm_routes));
856 ret = snd_soc_dapm_add_routes(&codec->dapm,
857 adau17x1_no_dsp_dapm_routes,
858 ARRAY_SIZE(adau17x1_no_dsp_dapm_routes));
862 EXPORT_SYMBOL_GPL(adau17x1_add_routes);
864 int adau17x1_resume(struct snd_soc_codec *codec)
866 struct adau *adau = snd_soc_codec_get_drvdata(codec);
868 if (adau->switch_mode)
869 adau->switch_mode(codec->dev);
871 regcache_sync(adau->regmap);
875 EXPORT_SYMBOL_GPL(adau17x1_resume);
877 int adau17x1_probe(struct device *dev, struct regmap *regmap,
878 enum adau17x1_type type, void (*switch_mode)(struct device *dev),
879 const char *firmware_name)
884 return PTR_ERR(regmap);
886 adau = devm_kzalloc(dev, sizeof(*adau), GFP_KERNEL);
890 adau->regmap = regmap;
891 adau->switch_mode = switch_mode;
894 dev_set_drvdata(dev, adau);
897 adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap, NULL,
899 if (IS_ERR(adau->sigmadsp)) {
900 dev_warn(dev, "Could not find firmware file: %ld\n",
901 PTR_ERR(adau->sigmadsp));
902 adau->sigmadsp = NULL;
911 EXPORT_SYMBOL_GPL(adau17x1_probe);
913 MODULE_DESCRIPTION("ASoC ADAU1X61/ADAU1X81 common code");
914 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
915 MODULE_LICENSE("GPL");