2 * ADAU1977/ADAU1978/ADAU1979 driver
4 * Copyright 2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 * Licensed under the GPL-2.
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/i2c.h>
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/platform_data/adau1977.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/slab.h>
21 #include <sound/core.h>
22 #include <sound/initval.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/tlv.h>
30 #define ADAU1977_REG_POWER 0x00
31 #define ADAU1977_REG_PLL 0x01
32 #define ADAU1977_REG_BOOST 0x02
33 #define ADAU1977_REG_MICBIAS 0x03
34 #define ADAU1977_REG_BLOCK_POWER_SAI 0x04
35 #define ADAU1977_REG_SAI_CTRL0 0x05
36 #define ADAU1977_REG_SAI_CTRL1 0x06
37 #define ADAU1977_REG_CMAP12 0x07
38 #define ADAU1977_REG_CMAP34 0x08
39 #define ADAU1977_REG_SAI_OVERTEMP 0x09
40 #define ADAU1977_REG_POST_ADC_GAIN(x) (0x0a + (x))
41 #define ADAU1977_REG_MISC_CONTROL 0x0e
42 #define ADAU1977_REG_DIAG_CONTROL 0x10
43 #define ADAU1977_REG_STATUS(x) (0x11 + (x))
44 #define ADAU1977_REG_DIAG_IRQ1 0x15
45 #define ADAU1977_REG_DIAG_IRQ2 0x16
46 #define ADAU1977_REG_ADJUST1 0x17
47 #define ADAU1977_REG_ADJUST2 0x18
48 #define ADAU1977_REG_ADC_CLIP 0x19
49 #define ADAU1977_REG_DC_HPF_CAL 0x1a
51 #define ADAU1977_POWER_RESET BIT(7)
52 #define ADAU1977_POWER_PWUP BIT(0)
54 #define ADAU1977_PLL_CLK_S BIT(4)
55 #define ADAU1977_PLL_MCS_MASK 0x7
57 #define ADAU1977_MICBIAS_MB_VOLTS_MASK 0xf0
58 #define ADAU1977_MICBIAS_MB_VOLTS_OFFSET 4
60 #define ADAU1977_BLOCK_POWER_SAI_LR_POL BIT(7)
61 #define ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE BIT(6)
62 #define ADAU1977_BLOCK_POWER_SAI_LDO_EN BIT(5)
64 #define ADAU1977_SAI_CTRL0_FMT_MASK (0x3 << 6)
65 #define ADAU1977_SAI_CTRL0_FMT_I2S (0x0 << 6)
66 #define ADAU1977_SAI_CTRL0_FMT_LJ (0x1 << 6)
67 #define ADAU1977_SAI_CTRL0_FMT_RJ_24BIT (0x2 << 6)
68 #define ADAU1977_SAI_CTRL0_FMT_RJ_16BIT (0x3 << 6)
70 #define ADAU1977_SAI_CTRL0_SAI_MASK (0x7 << 3)
71 #define ADAU1977_SAI_CTRL0_SAI_I2S (0x0 << 3)
72 #define ADAU1977_SAI_CTRL0_SAI_TDM_2 (0x1 << 3)
73 #define ADAU1977_SAI_CTRL0_SAI_TDM_4 (0x2 << 3)
74 #define ADAU1977_SAI_CTRL0_SAI_TDM_8 (0x3 << 3)
75 #define ADAU1977_SAI_CTRL0_SAI_TDM_16 (0x4 << 3)
77 #define ADAU1977_SAI_CTRL0_FS_MASK (0x7)
78 #define ADAU1977_SAI_CTRL0_FS_8000_12000 (0x0)
79 #define ADAU1977_SAI_CTRL0_FS_16000_24000 (0x1)
80 #define ADAU1977_SAI_CTRL0_FS_32000_48000 (0x2)
81 #define ADAU1977_SAI_CTRL0_FS_64000_96000 (0x3)
82 #define ADAU1977_SAI_CTRL0_FS_128000_192000 (0x4)
84 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK (0x3 << 5)
85 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_32 (0x0 << 5)
86 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_24 (0x1 << 5)
87 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_16 (0x2 << 5)
88 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK (0x1 << 4)
89 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT (0x1 << 4)
90 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT (0x0 << 4)
91 #define ADAU1977_SAI_CTRL1_LRCLK_PULSE BIT(3)
92 #define ADAU1977_SAI_CTRL1_MSB BIT(2)
93 #define ADAU1977_SAI_CTRL1_BCLKRATE_16 (0x1 << 1)
94 #define ADAU1977_SAI_CTRL1_BCLKRATE_32 (0x0 << 1)
95 #define ADAU1977_SAI_CTRL1_BCLKRATE_MASK (0x1 << 1)
96 #define ADAU1977_SAI_CTRL1_MASTER BIT(0)
98 #define ADAU1977_SAI_OVERTEMP_DRV_C(x) BIT(4 + (x))
99 #define ADAU1977_SAI_OVERTEMP_DRV_HIZ BIT(3)
101 #define ADAU1977_MISC_CONTROL_SUM_MODE_MASK (0x3 << 6)
102 #define ADAU1977_MISC_CONTROL_SUM_MODE_1CH (0x2 << 6)
103 #define ADAU1977_MISC_CONTROL_SUM_MODE_2CH (0x1 << 6)
104 #define ADAU1977_MISC_CONTROL_SUM_MODE_4CH (0x0 << 6)
105 #define ADAU1977_MISC_CONTROL_MMUTE BIT(4)
106 #define ADAU1977_MISC_CONTROL_DC_CAL BIT(0)
108 #define ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET 4
109 #define ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET 0
112 struct regmap *regmap;
115 enum adau1977_sysclk_src sysclk_src;
116 struct gpio_desc *reset_gpio;
117 enum adau1977_type type;
119 struct regulator *avdd_reg;
120 struct regulator *dvdd_reg;
122 struct snd_pcm_hw_constraint_list constraints;
125 void (*switch_mode)(struct device *dev);
127 unsigned int max_master_fs;
128 unsigned int slot_width;
133 static const struct reg_default adau1977_reg_defaults[] = {
157 static const DECLARE_TLV_DB_MINMAX_MUTE(adau1977_adc_gain, -3562, 6000);
159 static const struct snd_soc_dapm_widget adau1977_micbias_dapm_widgets[] = {
160 SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU1977_REG_MICBIAS,
164 static const struct snd_soc_dapm_widget adau1977_dapm_widgets[] = {
165 SND_SOC_DAPM_SUPPLY("Vref", ADAU1977_REG_BLOCK_POWER_SAI,
168 SND_SOC_DAPM_ADC("ADC1", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 0, 0),
169 SND_SOC_DAPM_ADC("ADC2", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 1, 0),
170 SND_SOC_DAPM_ADC("ADC3", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 2, 0),
171 SND_SOC_DAPM_ADC("ADC4", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 3, 0),
173 SND_SOC_DAPM_INPUT("AIN1"),
174 SND_SOC_DAPM_INPUT("AIN2"),
175 SND_SOC_DAPM_INPUT("AIN3"),
176 SND_SOC_DAPM_INPUT("AIN4"),
178 SND_SOC_DAPM_OUTPUT("VREF"),
181 static const struct snd_soc_dapm_route adau1977_dapm_routes[] = {
182 { "ADC1", NULL, "AIN1" },
183 { "ADC2", NULL, "AIN2" },
184 { "ADC3", NULL, "AIN3" },
185 { "ADC4", NULL, "AIN4" },
187 { "ADC1", NULL, "Vref" },
188 { "ADC2", NULL, "Vref" },
189 { "ADC3", NULL, "Vref" },
190 { "ADC4", NULL, "Vref" },
192 { "VREF", NULL, "Vref" },
195 #define ADAU1977_VOLUME(x) \
196 SOC_SINGLE_TLV("ADC" #x " Capture Volume", \
197 ADAU1977_REG_POST_ADC_GAIN((x) - 1), \
198 0, 255, 1, adau1977_adc_gain)
200 #define ADAU1977_HPF_SWITCH(x) \
201 SOC_SINGLE("ADC" #x " Highpass-Filter Capture Switch", \
202 ADAU1977_REG_DC_HPF_CAL, (x) - 1, 1, 0)
204 #define ADAU1977_DC_SUB_SWITCH(x) \
205 SOC_SINGLE("ADC" #x " DC Substraction Capture Switch", \
206 ADAU1977_REG_DC_HPF_CAL, (x) + 3, 1, 0)
208 static const struct snd_kcontrol_new adau1977_snd_controls[] = {
214 ADAU1977_HPF_SWITCH(1),
215 ADAU1977_HPF_SWITCH(2),
216 ADAU1977_HPF_SWITCH(3),
217 ADAU1977_HPF_SWITCH(4),
219 ADAU1977_DC_SUB_SWITCH(1),
220 ADAU1977_DC_SUB_SWITCH(2),
221 ADAU1977_DC_SUB_SWITCH(3),
222 ADAU1977_DC_SUB_SWITCH(4),
225 static int adau1977_reset(struct adau1977 *adau1977)
230 * The reset bit is obviously volatile, but we need to be able to cache
231 * the other bits in the register, so we can't just mark the whole
232 * register as volatile. Since this is the only place where we'll ever
233 * touch the reset bit just bypass the cache for this operation.
235 regcache_cache_bypass(adau1977->regmap, true);
236 ret = regmap_write(adau1977->regmap, ADAU1977_REG_POWER,
237 ADAU1977_POWER_RESET);
238 regcache_cache_bypass(adau1977->regmap, false);
246 * Returns the appropriate setting for ths FS field in the CTRL0 register
247 * depending on the rate.
249 static int adau1977_lookup_fs(unsigned int rate)
251 if (rate >= 8000 && rate <= 12000)
252 return ADAU1977_SAI_CTRL0_FS_8000_12000;
253 else if (rate >= 16000 && rate <= 24000)
254 return ADAU1977_SAI_CTRL0_FS_16000_24000;
255 else if (rate >= 32000 && rate <= 48000)
256 return ADAU1977_SAI_CTRL0_FS_32000_48000;
257 else if (rate >= 64000 && rate <= 96000)
258 return ADAU1977_SAI_CTRL0_FS_64000_96000;
259 else if (rate >= 128000 && rate <= 192000)
260 return ADAU1977_SAI_CTRL0_FS_128000_192000;
265 static int adau1977_lookup_mcs(struct adau1977 *adau1977, unsigned int rate,
271 * rate = sysclk / (512 * mcs_lut[mcs]) * 2**fs
272 * => mcs_lut[mcs] = sysclk / (512 * rate) * 2**fs
273 * => mcs_lut[mcs] = sysclk / ((512 / 2**fs) * rate)
278 if (adau1977->sysclk % rate != 0)
281 mcs = adau1977->sysclk / rate;
283 /* The factors configured by MCS are 1, 2, 3, 4, 6 */
284 if (mcs < 1 || mcs > 6 || mcs == 5)
294 static int adau1977_hw_params(struct snd_pcm_substream *substream,
295 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
297 struct snd_soc_codec *codec = dai->codec;
298 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(codec);
299 unsigned int rate = params_rate(params);
300 unsigned int slot_width;
301 unsigned int ctrl0, ctrl0_mask;
306 fs = adau1977_lookup_fs(rate);
310 if (adau1977->sysclk_src == ADAU1977_SYSCLK_SRC_MCLK) {
311 mcs = adau1977_lookup_mcs(adau1977, rate, fs);
318 ctrl0_mask = ADAU1977_SAI_CTRL0_FS_MASK;
321 if (adau1977->right_j) {
322 switch (params_width(params)) {
324 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_16BIT;
327 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
332 ctrl0_mask |= ADAU1977_SAI_CTRL0_FMT_MASK;
335 if (adau1977->master) {
336 switch (params_width(params)) {
338 ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT;
343 ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT;
350 /* In TDM mode there is a fixed slot width */
351 if (adau1977->slot_width)
352 slot_width = adau1977->slot_width;
354 if (slot_width == 16)
355 ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_16;
357 ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_32;
359 ret = regmap_update_bits(adau1977->regmap,
360 ADAU1977_REG_SAI_CTRL1,
361 ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK |
362 ADAU1977_SAI_CTRL1_BCLKRATE_MASK,
368 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
373 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
374 ADAU1977_PLL_MCS_MASK, mcs);
377 static int adau1977_power_disable(struct adau1977 *adau1977)
381 if (!adau1977->enabled)
384 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
385 ADAU1977_POWER_PWUP, 0);
389 regcache_mark_dirty(adau1977->regmap);
391 if (adau1977->reset_gpio)
392 gpiod_set_value_cansleep(adau1977->reset_gpio, 0);
394 regcache_cache_only(adau1977->regmap, true);
396 regulator_disable(adau1977->avdd_reg);
397 if (adau1977->dvdd_reg)
398 regulator_disable(adau1977->dvdd_reg);
400 adau1977->enabled = false;
405 static int adau1977_power_enable(struct adau1977 *adau1977)
410 if (adau1977->enabled)
413 ret = regulator_enable(adau1977->avdd_reg);
417 if (adau1977->dvdd_reg) {
418 ret = regulator_enable(adau1977->dvdd_reg);
420 goto err_disable_avdd;
423 if (adau1977->reset_gpio)
424 gpiod_set_value_cansleep(adau1977->reset_gpio, 1);
426 regcache_cache_only(adau1977->regmap, false);
428 if (adau1977->switch_mode)
429 adau1977->switch_mode(adau1977->dev);
431 ret = adau1977_reset(adau1977);
433 goto err_disable_dvdd;
435 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
436 ADAU1977_POWER_PWUP, ADAU1977_POWER_PWUP);
438 goto err_disable_dvdd;
440 ret = regcache_sync(adau1977->regmap);
442 goto err_disable_dvdd;
445 * The PLL register is not affected by the software reset. It is
446 * possible that the value of the register was changed to the
447 * default value while we were in cache only mode. In this case
448 * regcache_sync will skip over it and we have to manually sync
451 ret = regmap_read(adau1977->regmap, ADAU1977_REG_PLL, &val);
453 goto err_disable_dvdd;
456 regcache_cache_bypass(adau1977->regmap, true);
457 ret = regmap_write(adau1977->regmap, ADAU1977_REG_PLL,
460 goto err_disable_dvdd;
461 regcache_cache_bypass(adau1977->regmap, false);
464 adau1977->enabled = true;
469 if (adau1977->dvdd_reg)
470 regulator_disable(adau1977->dvdd_reg);
472 regulator_disable(adau1977->avdd_reg);
476 static int adau1977_set_bias_level(struct snd_soc_codec *codec,
477 enum snd_soc_bias_level level)
479 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(codec);
483 case SND_SOC_BIAS_ON:
485 case SND_SOC_BIAS_PREPARE:
487 case SND_SOC_BIAS_STANDBY:
488 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
489 ret = adau1977_power_enable(adau1977);
491 case SND_SOC_BIAS_OFF:
492 ret = adau1977_power_disable(adau1977);
499 codec->dapm.bias_level = level;
504 static int adau1977_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
505 unsigned int rx_mask, int slots, int width)
507 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
508 unsigned int ctrl0, ctrl1, drv;
509 unsigned int slot[4];
514 /* 0 = No fixed slot width */
515 adau1977->slot_width = 0;
516 adau1977->max_master_fs = 192000;
517 return regmap_update_bits(adau1977->regmap,
518 ADAU1977_REG_SAI_CTRL0, ADAU1977_SAI_CTRL0_SAI_MASK,
519 ADAU1977_SAI_CTRL0_SAI_I2S);
522 if (rx_mask == 0 || tx_mask != 0)
526 for (i = 0; i < 4; i++) {
527 slot[i] = __ffs(rx_mask);
528 drv |= ADAU1977_SAI_OVERTEMP_DRV_C(i);
529 rx_mask &= ~(1 << slot[i]);
530 if (slot[i] >= slots)
541 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_16;
544 /* We can only generate 16 bit or 32 bit wide slots */
545 if (adau1977->master)
547 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_24;
550 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_32;
558 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_2;
561 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_4;
564 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_8;
567 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_16;
573 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
574 ADAU1977_SAI_OVERTEMP_DRV_C(0) |
575 ADAU1977_SAI_OVERTEMP_DRV_C(1) |
576 ADAU1977_SAI_OVERTEMP_DRV_C(2) |
577 ADAU1977_SAI_OVERTEMP_DRV_C(3), drv);
581 ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP12,
582 (slot[1] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
583 (slot[0] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
587 ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP34,
588 (slot[3] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
589 (slot[2] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
593 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
594 ADAU1977_SAI_CTRL0_SAI_MASK, ctrl0);
598 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
599 ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK, ctrl1);
603 adau1977->slot_width = width;
605 /* In master mode the maximum bitclock is 24.576 MHz */
606 adau1977->max_master_fs = min(192000, 24576000 / width / slots);
611 static int adau1977_mute(struct snd_soc_dai *dai, int mute, int stream)
613 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
617 val = ADAU1977_MISC_CONTROL_MMUTE;
621 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MISC_CONTROL,
622 ADAU1977_MISC_CONTROL_MMUTE, val);
625 static int adau1977_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
627 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
628 unsigned int ctrl0 = 0, ctrl1 = 0, block_power = 0;
632 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
633 case SND_SOC_DAIFMT_CBS_CFS:
634 adau1977->master = false;
636 case SND_SOC_DAIFMT_CBM_CFM:
637 ctrl1 |= ADAU1977_SAI_CTRL1_MASTER;
638 adau1977->master = true;
644 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
645 case SND_SOC_DAIFMT_NB_NF:
646 invert_lrclk = false;
648 case SND_SOC_DAIFMT_IB_NF:
649 block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
650 invert_lrclk = false;
652 case SND_SOC_DAIFMT_NB_IF:
655 case SND_SOC_DAIFMT_IB_IF:
656 block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
663 adau1977->right_j = false;
664 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
665 case SND_SOC_DAIFMT_I2S:
666 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
668 case SND_SOC_DAIFMT_LEFT_J:
669 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
670 invert_lrclk = !invert_lrclk;
672 case SND_SOC_DAIFMT_RIGHT_J:
673 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
674 adau1977->right_j = true;
675 invert_lrclk = !invert_lrclk;
677 case SND_SOC_DAIFMT_DSP_A:
678 ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
679 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
680 invert_lrclk = false;
682 case SND_SOC_DAIFMT_DSP_B:
683 ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
684 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
685 invert_lrclk = false;
692 block_power |= ADAU1977_BLOCK_POWER_SAI_LR_POL;
694 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
695 ADAU1977_BLOCK_POWER_SAI_LR_POL |
696 ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE, block_power);
700 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
701 ADAU1977_SAI_CTRL0_FMT_MASK,
706 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
707 ADAU1977_SAI_CTRL1_MASTER | ADAU1977_SAI_CTRL1_LRCLK_PULSE,
711 static int adau1977_startup(struct snd_pcm_substream *substream,
712 struct snd_soc_dai *dai)
714 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
717 if (adau1977->slot_width == 16)
718 formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE;
719 else if (adau1977->right_j || adau1977->slot_width == 24)
720 formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
721 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE;
723 snd_pcm_hw_constraint_list(substream->runtime, 0,
724 SNDRV_PCM_HW_PARAM_RATE, &adau1977->constraints);
726 if (adau1977->master)
727 snd_pcm_hw_constraint_minmax(substream->runtime,
728 SNDRV_PCM_HW_PARAM_RATE, 8000, adau1977->max_master_fs);
731 snd_pcm_hw_constraint_mask64(substream->runtime,
732 SNDRV_PCM_HW_PARAM_FORMAT, formats);
737 static int adau1977_set_tristate(struct snd_soc_dai *dai, int tristate)
739 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
743 val = ADAU1977_SAI_OVERTEMP_DRV_HIZ;
747 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
748 ADAU1977_SAI_OVERTEMP_DRV_HIZ, val);
751 static const struct snd_soc_dai_ops adau1977_dai_ops = {
752 .startup = adau1977_startup,
753 .hw_params = adau1977_hw_params,
754 .mute_stream = adau1977_mute,
755 .set_fmt = adau1977_set_dai_fmt,
756 .set_tdm_slot = adau1977_set_tdm_slot,
757 .set_tristate = adau1977_set_tristate,
760 static struct snd_soc_dai_driver adau1977_dai = {
761 .name = "adau1977-hifi",
763 .stream_name = "Capture",
766 .rates = SNDRV_PCM_RATE_KNOT,
767 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
768 SNDRV_PCM_FMTBIT_S32_LE,
771 .ops = &adau1977_dai_ops,
774 static const unsigned int adau1977_rates[] = {
775 8000, 16000, 32000, 64000, 128000,
776 11025, 22050, 44100, 88200, 172400,
777 12000, 24000, 48000, 96000, 192000,
780 #define ADAU1977_RATE_CONSTRAINT_MASK_32000 0x001f
781 #define ADAU1977_RATE_CONSTRAINT_MASK_44100 0x03e0
782 #define ADAU1977_RATE_CONSTRAINT_MASK_48000 0x7c00
783 /* All rates >= 32000 */
784 #define ADAU1977_RATE_CONSTRAINT_MASK_LRCLK 0x739c
786 static bool adau1977_check_sysclk(unsigned int mclk, unsigned int base_freq)
790 if (mclk % (base_freq * 128) != 0)
793 mcs = mclk / (128 * base_freq);
794 if (mcs < 1 || mcs > 6 || mcs == 5)
800 static int adau1977_set_sysclk(struct snd_soc_codec *codec,
801 int clk_id, int source, unsigned int freq, int dir)
803 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(codec);
804 unsigned int mask = 0;
805 unsigned int clk_src;
808 if (dir != SND_SOC_CLOCK_IN)
811 if (clk_id != ADAU1977_SYSCLK)
815 case ADAU1977_SYSCLK_SRC_MCLK:
818 case ADAU1977_SYSCLK_SRC_LRCLK:
819 clk_src = ADAU1977_PLL_CLK_S;
825 if (freq != 0 && source == ADAU1977_SYSCLK_SRC_MCLK) {
826 if (freq < 4000000 || freq > 36864000)
829 if (adau1977_check_sysclk(freq, 32000))
830 mask |= ADAU1977_RATE_CONSTRAINT_MASK_32000;
831 if (adau1977_check_sysclk(freq, 44100))
832 mask |= ADAU1977_RATE_CONSTRAINT_MASK_44100;
833 if (adau1977_check_sysclk(freq, 48000))
834 mask |= ADAU1977_RATE_CONSTRAINT_MASK_48000;
838 } else if (source == ADAU1977_SYSCLK_SRC_LRCLK) {
839 mask = ADAU1977_RATE_CONSTRAINT_MASK_LRCLK;
842 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
843 ADAU1977_PLL_CLK_S, clk_src);
847 adau1977->constraints.mask = mask;
848 adau1977->sysclk_src = source;
849 adau1977->sysclk = freq;
854 static int adau1977_codec_probe(struct snd_soc_codec *codec)
856 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(codec);
859 switch (adau1977->type) {
861 ret = snd_soc_dapm_new_controls(&codec->dapm,
862 adau1977_micbias_dapm_widgets,
863 ARRAY_SIZE(adau1977_micbias_dapm_widgets));
874 static struct snd_soc_codec_driver adau1977_codec_driver = {
875 .probe = adau1977_codec_probe,
876 .set_bias_level = adau1977_set_bias_level,
877 .set_sysclk = adau1977_set_sysclk,
878 .idle_bias_off = true,
880 .controls = adau1977_snd_controls,
881 .num_controls = ARRAY_SIZE(adau1977_snd_controls),
882 .dapm_widgets = adau1977_dapm_widgets,
883 .num_dapm_widgets = ARRAY_SIZE(adau1977_dapm_widgets),
884 .dapm_routes = adau1977_dapm_routes,
885 .num_dapm_routes = ARRAY_SIZE(adau1977_dapm_routes),
888 static int adau1977_setup_micbias(struct adau1977 *adau1977)
890 struct adau1977_platform_data *pdata = adau1977->dev->platform_data;
891 unsigned int micbias;
894 micbias = pdata->micbias;
895 if (micbias > ADAU1977_MICBIAS_9V0)
899 micbias = ADAU1977_MICBIAS_8V5;
902 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MICBIAS,
903 ADAU1977_MICBIAS_MB_VOLTS_MASK,
904 micbias << ADAU1977_MICBIAS_MB_VOLTS_OFFSET);
907 int adau1977_probe(struct device *dev, struct regmap *regmap,
908 enum adau1977_type type, void (*switch_mode)(struct device *dev))
910 unsigned int power_off_mask;
911 struct adau1977 *adau1977;
915 return PTR_ERR(regmap);
917 adau1977 = devm_kzalloc(dev, sizeof(*adau1977), GFP_KERNEL);
918 if (adau1977 == NULL)
922 adau1977->type = type;
923 adau1977->regmap = regmap;
924 adau1977->switch_mode = switch_mode;
925 adau1977->max_master_fs = 192000;
927 adau1977->constraints.list = adau1977_rates;
928 adau1977->constraints.count = ARRAY_SIZE(adau1977_rates);
930 adau1977->avdd_reg = devm_regulator_get(dev, "AVDD");
931 if (IS_ERR(adau1977->avdd_reg))
932 return PTR_ERR(adau1977->avdd_reg);
934 adau1977->dvdd_reg = devm_regulator_get_optional(dev, "DVDD");
935 if (IS_ERR(adau1977->dvdd_reg)) {
936 if (PTR_ERR(adau1977->dvdd_reg) != -ENODEV)
937 return PTR_ERR(adau1977->dvdd_reg);
938 adau1977->dvdd_reg = NULL;
941 adau1977->reset_gpio = devm_gpiod_get_optional(dev, "reset",
943 if (IS_ERR(adau1977->reset_gpio))
944 return PTR_ERR(adau1977->reset_gpio);
946 dev_set_drvdata(dev, adau1977);
948 if (adau1977->reset_gpio)
951 ret = adau1977_power_enable(adau1977);
955 if (type == ADAU1977) {
956 ret = adau1977_setup_micbias(adau1977);
961 if (adau1977->dvdd_reg)
964 power_off_mask = (unsigned int)~ADAU1977_BLOCK_POWER_SAI_LDO_EN;
966 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
967 power_off_mask, 0x00);
971 ret = adau1977_power_disable(adau1977);
975 return snd_soc_register_codec(dev, &adau1977_codec_driver,
979 adau1977_power_disable(adau1977);
983 EXPORT_SYMBOL_GPL(adau1977_probe);
985 static bool adau1977_register_volatile(struct device *dev, unsigned int reg)
988 case ADAU1977_REG_STATUS(0):
989 case ADAU1977_REG_STATUS(1):
990 case ADAU1977_REG_STATUS(2):
991 case ADAU1977_REG_STATUS(3):
992 case ADAU1977_REG_ADC_CLIP:
999 const struct regmap_config adau1977_regmap_config = {
1000 .max_register = ADAU1977_REG_DC_HPF_CAL,
1001 .volatile_reg = adau1977_register_volatile,
1003 .cache_type = REGCACHE_RBTREE,
1004 .reg_defaults = adau1977_reg_defaults,
1005 .num_reg_defaults = ARRAY_SIZE(adau1977_reg_defaults),
1007 EXPORT_SYMBOL_GPL(adau1977_regmap_config);
1009 MODULE_DESCRIPTION("ASoC ADAU1977/ADAU1978/ADAU1979 driver");
1010 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1011 MODULE_LICENSE("GPL");