2 * arizona.c - Wolfson Arizona class device shared support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/gcd.h>
14 #include <linux/module.h>
15 #include <linux/pm_runtime.h>
16 #include <sound/pcm.h>
17 #include <sound/pcm_params.h>
18 #include <sound/tlv.h>
20 #include <linux/mfd/arizona/core.h>
21 #include <linux/mfd/arizona/registers.h>
25 #define ARIZONA_AIF_BCLK_CTRL 0x00
26 #define ARIZONA_AIF_TX_PIN_CTRL 0x01
27 #define ARIZONA_AIF_RX_PIN_CTRL 0x02
28 #define ARIZONA_AIF_RATE_CTRL 0x03
29 #define ARIZONA_AIF_FORMAT 0x04
30 #define ARIZONA_AIF_TX_BCLK_RATE 0x05
31 #define ARIZONA_AIF_RX_BCLK_RATE 0x06
32 #define ARIZONA_AIF_FRAME_CTRL_1 0x07
33 #define ARIZONA_AIF_FRAME_CTRL_2 0x08
34 #define ARIZONA_AIF_FRAME_CTRL_3 0x09
35 #define ARIZONA_AIF_FRAME_CTRL_4 0x0A
36 #define ARIZONA_AIF_FRAME_CTRL_5 0x0B
37 #define ARIZONA_AIF_FRAME_CTRL_6 0x0C
38 #define ARIZONA_AIF_FRAME_CTRL_7 0x0D
39 #define ARIZONA_AIF_FRAME_CTRL_8 0x0E
40 #define ARIZONA_AIF_FRAME_CTRL_9 0x0F
41 #define ARIZONA_AIF_FRAME_CTRL_10 0x10
42 #define ARIZONA_AIF_FRAME_CTRL_11 0x11
43 #define ARIZONA_AIF_FRAME_CTRL_12 0x12
44 #define ARIZONA_AIF_FRAME_CTRL_13 0x13
45 #define ARIZONA_AIF_FRAME_CTRL_14 0x14
46 #define ARIZONA_AIF_FRAME_CTRL_15 0x15
47 #define ARIZONA_AIF_FRAME_CTRL_16 0x16
48 #define ARIZONA_AIF_FRAME_CTRL_17 0x17
49 #define ARIZONA_AIF_FRAME_CTRL_18 0x18
50 #define ARIZONA_AIF_TX_ENABLES 0x19
51 #define ARIZONA_AIF_RX_ENABLES 0x1A
52 #define ARIZONA_AIF_FORCE_WRITE 0x1B
54 #define arizona_fll_err(_fll, fmt, ...) \
55 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
56 #define arizona_fll_warn(_fll, fmt, ...) \
57 dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
58 #define arizona_fll_dbg(_fll, fmt, ...) \
59 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
61 #define arizona_aif_err(_dai, fmt, ...) \
62 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
63 #define arizona_aif_warn(_dai, fmt, ...) \
64 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
65 #define arizona_aif_dbg(_dai, fmt, ...) \
66 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
68 const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = {
145 EXPORT_SYMBOL_GPL(arizona_mixer_texts);
147 int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = {
153 0x0c, /* Noise mixer */
154 0x0d, /* Comfort noise */
224 EXPORT_SYMBOL_GPL(arizona_mixer_values);
226 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0);
227 EXPORT_SYMBOL_GPL(arizona_mixer_tlv);
229 static const char *arizona_vol_ramp_text[] = {
230 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
231 "15ms/6dB", "30ms/6dB",
234 const struct soc_enum arizona_in_vd_ramp =
235 SOC_ENUM_SINGLE(ARIZONA_INPUT_VOLUME_RAMP,
236 ARIZONA_IN_VD_RAMP_SHIFT, 7, arizona_vol_ramp_text);
237 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp);
239 const struct soc_enum arizona_in_vi_ramp =
240 SOC_ENUM_SINGLE(ARIZONA_INPUT_VOLUME_RAMP,
241 ARIZONA_IN_VI_RAMP_SHIFT, 7, arizona_vol_ramp_text);
242 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp);
244 const struct soc_enum arizona_out_vd_ramp =
245 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_VOLUME_RAMP,
246 ARIZONA_OUT_VD_RAMP_SHIFT, 7, arizona_vol_ramp_text);
247 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp);
249 const struct soc_enum arizona_out_vi_ramp =
250 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_VOLUME_RAMP,
251 ARIZONA_OUT_VI_RAMP_SHIFT, 7, arizona_vol_ramp_text);
252 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp);
254 static const char *arizona_lhpf_mode_text[] = {
255 "Low-pass", "High-pass"
258 const struct soc_enum arizona_lhpf1_mode =
259 SOC_ENUM_SINGLE(ARIZONA_HPLPF1_1, ARIZONA_LHPF1_MODE_SHIFT, 2,
260 arizona_lhpf_mode_text);
261 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode);
263 const struct soc_enum arizona_lhpf2_mode =
264 SOC_ENUM_SINGLE(ARIZONA_HPLPF2_1, ARIZONA_LHPF2_MODE_SHIFT, 2,
265 arizona_lhpf_mode_text);
266 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode);
268 const struct soc_enum arizona_lhpf3_mode =
269 SOC_ENUM_SINGLE(ARIZONA_HPLPF3_1, ARIZONA_LHPF3_MODE_SHIFT, 2,
270 arizona_lhpf_mode_text);
271 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode);
273 const struct soc_enum arizona_lhpf4_mode =
274 SOC_ENUM_SINGLE(ARIZONA_HPLPF4_1, ARIZONA_LHPF4_MODE_SHIFT, 2,
275 arizona_lhpf_mode_text);
276 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode);
278 int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
283 EXPORT_SYMBOL_GPL(arizona_in_ev);
285 int arizona_out_ev(struct snd_soc_dapm_widget *w,
286 struct snd_kcontrol *kcontrol,
291 EXPORT_SYMBOL_GPL(arizona_out_ev);
293 static unsigned int arizona_sysclk_48k_rates[] = {
303 static unsigned int arizona_sysclk_44k1_rates[] = {
313 static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk,
316 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
319 int ref, div, refclk;
322 case ARIZONA_CLK_OPCLK:
323 reg = ARIZONA_OUTPUT_SYSTEM_CLOCK;
324 refclk = priv->sysclk;
326 case ARIZONA_CLK_ASYNC_OPCLK:
327 reg = ARIZONA_OUTPUT_ASYNC_CLOCK;
328 refclk = priv->asyncclk;
335 rates = arizona_sysclk_44k1_rates;
337 rates = arizona_sysclk_48k_rates;
339 for (ref = 0; ref < ARRAY_SIZE(arizona_sysclk_48k_rates) &&
340 rates[ref] <= refclk; ref++) {
342 while (rates[ref] / div >= freq && div < 32) {
343 if (rates[ref] / div == freq) {
344 dev_dbg(codec->dev, "Configured %dHz OPCLK\n",
346 snd_soc_update_bits(codec, reg,
347 ARIZONA_OPCLK_DIV_MASK |
348 ARIZONA_OPCLK_SEL_MASK,
350 ARIZONA_OPCLK_DIV_SHIFT) |
358 dev_err(codec->dev, "Unable to generate %dHz OPCLK\n", freq);
362 int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
363 int source, unsigned int freq, int dir)
365 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
366 struct arizona *arizona = priv->arizona;
369 unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK;
370 unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT;
374 case ARIZONA_CLK_SYSCLK:
376 reg = ARIZONA_SYSTEM_CLOCK_1;
378 mask |= ARIZONA_SYSCLK_FRAC;
380 case ARIZONA_CLK_ASYNCCLK:
382 reg = ARIZONA_ASYNC_CLOCK_1;
383 clk = &priv->asyncclk;
385 case ARIZONA_CLK_OPCLK:
386 case ARIZONA_CLK_ASYNC_OPCLK:
387 return arizona_set_opclk(codec, clk_id, freq);
398 val |= 1 << ARIZONA_SYSCLK_FREQ_SHIFT;
402 val |= 2 << ARIZONA_SYSCLK_FREQ_SHIFT;
406 val |= 3 << ARIZONA_SYSCLK_FREQ_SHIFT;
410 val |= 4 << ARIZONA_SYSCLK_FREQ_SHIFT;
414 val |= 5 << ARIZONA_SYSCLK_FREQ_SHIFT;
418 val |= 6 << ARIZONA_SYSCLK_FREQ_SHIFT;
427 val |= ARIZONA_SYSCLK_FRAC;
429 dev_dbg(arizona->dev, "%s set to %uHz", name, freq);
431 return regmap_update_bits(arizona->regmap, reg, mask, val);
433 EXPORT_SYMBOL_GPL(arizona_set_sysclk);
435 static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
437 struct snd_soc_codec *codec = dai->codec;
438 int lrclk, bclk, mode, base;
440 base = dai->driver->base;
445 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
446 case SND_SOC_DAIFMT_DSP_A:
449 case SND_SOC_DAIFMT_I2S:
453 arizona_aif_err(dai, "Unsupported DAI format %d\n",
454 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
458 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
459 case SND_SOC_DAIFMT_CBS_CFS:
461 case SND_SOC_DAIFMT_CBS_CFM:
462 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
464 case SND_SOC_DAIFMT_CBM_CFS:
465 bclk |= ARIZONA_AIF1_BCLK_MSTR;
467 case SND_SOC_DAIFMT_CBM_CFM:
468 bclk |= ARIZONA_AIF1_BCLK_MSTR;
469 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
472 arizona_aif_err(dai, "Unsupported master mode %d\n",
473 fmt & SND_SOC_DAIFMT_MASTER_MASK);
477 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
478 case SND_SOC_DAIFMT_NB_NF:
480 case SND_SOC_DAIFMT_IB_IF:
481 bclk |= ARIZONA_AIF1_BCLK_INV;
482 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
484 case SND_SOC_DAIFMT_IB_NF:
485 bclk |= ARIZONA_AIF1_BCLK_INV;
487 case SND_SOC_DAIFMT_NB_IF:
488 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
494 snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL,
495 ARIZONA_AIF1_BCLK_INV | ARIZONA_AIF1_BCLK_MSTR,
497 snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_PIN_CTRL,
498 ARIZONA_AIF1TX_LRCLK_INV |
499 ARIZONA_AIF1TX_LRCLK_MSTR, lrclk);
500 snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_PIN_CTRL,
501 ARIZONA_AIF1RX_LRCLK_INV |
502 ARIZONA_AIF1RX_LRCLK_MSTR, lrclk);
503 snd_soc_update_bits(codec, base + ARIZONA_AIF_FORMAT,
504 ARIZONA_AIF1_FMT_MASK, mode);
509 static const int arizona_48k_bclk_rates[] = {
531 static const unsigned int arizona_48k_rates[] = {
549 static const struct snd_pcm_hw_constraint_list arizona_48k_constraint = {
550 .count = ARRAY_SIZE(arizona_48k_rates),
551 .list = arizona_48k_rates,
554 static const int arizona_44k1_bclk_rates[] = {
576 static const unsigned int arizona_44k1_rates[] = {
586 static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint = {
587 .count = ARRAY_SIZE(arizona_44k1_rates),
588 .list = arizona_44k1_rates,
591 static int arizona_sr_vals[] = {
618 static int arizona_startup(struct snd_pcm_substream *substream,
619 struct snd_soc_dai *dai)
621 struct snd_soc_codec *codec = dai->codec;
622 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
623 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
624 const struct snd_pcm_hw_constraint_list *constraint;
625 unsigned int base_rate;
627 switch (dai_priv->clk) {
628 case ARIZONA_CLK_SYSCLK:
629 base_rate = priv->sysclk;
631 case ARIZONA_CLK_ASYNCCLK:
632 base_rate = priv->asyncclk;
638 if (base_rate % 8000)
639 constraint = &arizona_44k1_constraint;
641 constraint = &arizona_48k_constraint;
643 return snd_pcm_hw_constraint_list(substream->runtime, 0,
644 SNDRV_PCM_HW_PARAM_RATE,
648 static int arizona_hw_params(struct snd_pcm_substream *substream,
649 struct snd_pcm_hw_params *params,
650 struct snd_soc_dai *dai)
652 struct snd_soc_codec *codec = dai->codec;
653 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
654 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
655 int base = dai->driver->base;
658 int bclk, lrclk, wl, frame, sr_val;
660 if (params_rate(params) % 8000)
661 rates = &arizona_44k1_bclk_rates[0];
663 rates = &arizona_48k_bclk_rates[0];
665 for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) {
666 if (rates[i] >= snd_soc_params_to_bclk(params) &&
667 rates[i] % params_rate(params) == 0) {
672 if (i == ARRAY_SIZE(arizona_44k1_bclk_rates)) {
673 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
674 params_rate(params));
678 for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
679 if (arizona_sr_vals[i] == params_rate(params))
681 if (i == ARRAY_SIZE(arizona_sr_vals)) {
682 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
683 params_rate(params));
688 lrclk = snd_soc_params_to_bclk(params) / params_rate(params);
690 arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
691 rates[bclk], rates[bclk] / lrclk);
693 wl = snd_pcm_format_width(params_format(params));
694 frame = wl << ARIZONA_AIF1TX_WL_SHIFT | wl;
697 * We will need to be more flexible than this in future,
698 * currently we use a single sample rate for SYSCLK.
700 switch (dai_priv->clk) {
701 case ARIZONA_CLK_SYSCLK:
702 snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1,
703 ARIZONA_SAMPLE_RATE_1_MASK, sr_val);
704 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
705 ARIZONA_AIF1_RATE_MASK, 0);
707 case ARIZONA_CLK_ASYNCCLK:
708 snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
709 ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val);
710 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
711 ARIZONA_AIF1_RATE_MASK,
712 8 << ARIZONA_AIF1_RATE_SHIFT);
715 arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
719 snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL,
720 ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
721 snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_BCLK_RATE,
722 ARIZONA_AIF1TX_BCPF_MASK, lrclk);
723 snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_BCLK_RATE,
724 ARIZONA_AIF1RX_BCPF_MASK, lrclk);
725 snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_1,
726 ARIZONA_AIF1TX_WL_MASK |
727 ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
728 snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_2,
729 ARIZONA_AIF1RX_WL_MASK |
730 ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
735 static const char *arizona_dai_clk_str(int clk_id)
738 case ARIZONA_CLK_SYSCLK:
740 case ARIZONA_CLK_ASYNCCLK:
743 return "Unknown clock";
747 static int arizona_dai_set_sysclk(struct snd_soc_dai *dai,
748 int clk_id, unsigned int freq, int dir)
750 struct snd_soc_codec *codec = dai->codec;
751 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
752 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
753 struct snd_soc_dapm_route routes[2];
756 case ARIZONA_CLK_SYSCLK:
757 case ARIZONA_CLK_ASYNCCLK:
763 if (clk_id == dai_priv->clk)
767 dev_err(codec->dev, "Can't change clock on active DAI %d\n",
772 dev_dbg(codec->dev, "Setting AIF%d to %s\n", dai->id + 1,
773 arizona_dai_clk_str(clk_id));
775 memset(&routes, 0, sizeof(routes));
776 routes[0].sink = dai->driver->capture.stream_name;
777 routes[1].sink = dai->driver->playback.stream_name;
779 routes[0].source = arizona_dai_clk_str(dai_priv->clk);
780 routes[1].source = arizona_dai_clk_str(dai_priv->clk);
781 snd_soc_dapm_del_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
783 routes[0].source = arizona_dai_clk_str(clk_id);
784 routes[1].source = arizona_dai_clk_str(clk_id);
785 snd_soc_dapm_add_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
787 dai_priv->clk = clk_id;
789 return snd_soc_dapm_sync(&codec->dapm);
792 const struct snd_soc_dai_ops arizona_dai_ops = {
793 .startup = arizona_startup,
794 .set_fmt = arizona_set_fmt,
795 .hw_params = arizona_hw_params,
796 .set_sysclk = arizona_dai_set_sysclk,
798 EXPORT_SYMBOL_GPL(arizona_dai_ops);
800 int arizona_init_dai(struct arizona_priv *priv, int id)
802 struct arizona_dai_priv *dai_priv = &priv->dai[id];
804 dai_priv->clk = ARIZONA_CLK_SYSCLK;
808 EXPORT_SYMBOL_GPL(arizona_init_dai);
810 static irqreturn_t arizona_fll_lock(int irq, void *data)
812 struct arizona_fll *fll = data;
814 arizona_fll_dbg(fll, "Lock status changed\n");
816 complete(&fll->lock);
821 static irqreturn_t arizona_fll_clock_ok(int irq, void *data)
823 struct arizona_fll *fll = data;
825 arizona_fll_dbg(fll, "clock OK\n");
839 { 64000, 128000, 3, 8 },
840 { 128000, 256000, 2, 4 },
841 { 256000, 1000000, 1, 2 },
842 { 1000000, 13500000, 0, 1 },
845 struct arizona_fll_cfg {
854 static int arizona_calc_fll(struct arizona_fll *fll,
855 struct arizona_fll_cfg *cfg,
859 unsigned int target, div, gcd_fll;
862 arizona_fll_dbg(fll, "Fref=%u Fout=%u\n", Fref, Fout);
864 /* Fref must be <=13.5MHz */
867 while ((Fref / div) > 13500000) {
873 "Can't scale %dMHz in to <=13.5MHz\n",
879 /* Apply the division for our remaining calculations */
882 /* Fvco should be over the targt; don't check the upper bound */
884 while (Fout * div < 90000000 * fll->vco_mult) {
887 arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n",
892 target = Fout * div / fll->vco_mult;
895 arizona_fll_dbg(fll, "Fvco=%dHz\n", target);
897 /* Find an appropraite FLL_FRATIO and factor it out of the target */
898 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
899 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
900 cfg->fratio = fll_fratios[i].fratio;
901 ratio = fll_fratios[i].ratio;
905 if (i == ARRAY_SIZE(fll_fratios)) {
906 arizona_fll_err(fll, "Unable to find FRATIO for Fref=%uHz\n",
911 cfg->n = target / (ratio * Fref);
914 gcd_fll = gcd(target, ratio * Fref);
915 arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll);
917 cfg->theta = (target - (cfg->n * ratio * Fref))
919 cfg->lambda = (ratio * Fref) / gcd_fll;
925 arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n",
926 cfg->n, cfg->theta, cfg->lambda);
927 arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
928 cfg->fratio, cfg->fratio, cfg->outdiv, cfg->refdiv);
934 static void arizona_apply_fll(struct arizona *arizona, unsigned int base,
935 struct arizona_fll_cfg *cfg, int source)
937 regmap_update_bits(arizona->regmap, base + 3,
938 ARIZONA_FLL1_THETA_MASK, cfg->theta);
939 regmap_update_bits(arizona->regmap, base + 4,
940 ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda);
941 regmap_update_bits(arizona->regmap, base + 5,
942 ARIZONA_FLL1_FRATIO_MASK,
943 cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT);
944 regmap_update_bits(arizona->regmap, base + 6,
945 ARIZONA_FLL1_CLK_REF_DIV_MASK |
946 ARIZONA_FLL1_CLK_REF_SRC_MASK,
947 cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
948 source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
950 regmap_update_bits(arizona->regmap, base + 2,
951 ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
952 ARIZONA_FLL1_CTRL_UPD | cfg->n);
955 int arizona_set_fll(struct arizona_fll *fll, int source,
956 unsigned int Fref, unsigned int Fout)
958 struct arizona *arizona = fll->arizona;
959 struct arizona_fll_cfg cfg, sync;
960 unsigned int reg, val;
965 if (fll->fref == Fref && fll->fout == Fout)
968 ret = regmap_read(arizona->regmap, fll->base + 1, ®);
970 arizona_fll_err(fll, "Failed to read current state: %d\n",
974 ena = reg & ARIZONA_FLL1_ENA;
977 /* Do we have a 32kHz reference? */
978 regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val);
979 switch (val & ARIZONA_CLK_32K_SRC_MASK) {
980 case ARIZONA_CLK_SRC_MCLK1:
981 case ARIZONA_CLK_SRC_MCLK2:
982 syncsrc = val & ARIZONA_CLK_32K_SRC_MASK;
988 if (source == syncsrc)
992 ret = arizona_calc_fll(fll, &sync, Fref, Fout);
996 ret = arizona_calc_fll(fll, &cfg, 32768, Fout);
1000 ret = arizona_calc_fll(fll, &cfg, Fref, Fout);
1005 regmap_update_bits(arizona->regmap, fll->base + 1,
1006 ARIZONA_FLL1_ENA, 0);
1007 regmap_update_bits(arizona->regmap, fll->base + 0x11,
1008 ARIZONA_FLL1_SYNC_ENA, 0);
1011 pm_runtime_put_autosuspend(arizona->dev);
1019 regmap_update_bits(arizona->regmap, fll->base + 5,
1020 ARIZONA_FLL1_OUTDIV_MASK,
1021 cfg.outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
1024 arizona_apply_fll(arizona, fll->base, &cfg, syncsrc);
1025 arizona_apply_fll(arizona, fll->base + 0x10, &sync, source);
1027 arizona_apply_fll(arizona, fll->base, &cfg, source);
1031 pm_runtime_get(arizona->dev);
1033 /* Clear any pending completions */
1034 try_wait_for_completion(&fll->ok);
1036 regmap_update_bits(arizona->regmap, fll->base + 1,
1037 ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
1039 regmap_update_bits(arizona->regmap, fll->base + 0x11,
1040 ARIZONA_FLL1_SYNC_ENA,
1041 ARIZONA_FLL1_SYNC_ENA);
1043 ret = wait_for_completion_timeout(&fll->ok,
1044 msecs_to_jiffies(250));
1046 arizona_fll_warn(fll, "Timed out waiting for lock\n");
1053 EXPORT_SYMBOL_GPL(arizona_set_fll);
1055 int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
1056 int ok_irq, struct arizona_fll *fll)
1060 init_completion(&fll->lock);
1061 init_completion(&fll->ok);
1065 fll->arizona = arizona;
1067 snprintf(fll->lock_name, sizeof(fll->lock_name), "FLL%d lock", id);
1068 snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name),
1069 "FLL%d clock OK", id);
1071 ret = arizona_request_irq(arizona, lock_irq, fll->lock_name,
1072 arizona_fll_lock, fll);
1074 dev_err(arizona->dev, "Failed to get FLL%d lock IRQ: %d\n",
1078 ret = arizona_request_irq(arizona, ok_irq, fll->clock_ok_name,
1079 arizona_fll_clock_ok, fll);
1081 dev_err(arizona->dev, "Failed to get FLL%d clock OK IRQ: %d\n",
1087 EXPORT_SYMBOL_GPL(arizona_init_fll);
1089 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
1090 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1091 MODULE_LICENSE("GPL");