2 * arizona.c - Wolfson Arizona class device shared support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/gcd.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/tlv.h>
21 #include <linux/mfd/arizona/core.h>
22 #include <linux/mfd/arizona/registers.h>
26 #define ARIZONA_AIF_BCLK_CTRL 0x00
27 #define ARIZONA_AIF_TX_PIN_CTRL 0x01
28 #define ARIZONA_AIF_RX_PIN_CTRL 0x02
29 #define ARIZONA_AIF_RATE_CTRL 0x03
30 #define ARIZONA_AIF_FORMAT 0x04
31 #define ARIZONA_AIF_TX_BCLK_RATE 0x05
32 #define ARIZONA_AIF_RX_BCLK_RATE 0x06
33 #define ARIZONA_AIF_FRAME_CTRL_1 0x07
34 #define ARIZONA_AIF_FRAME_CTRL_2 0x08
35 #define ARIZONA_AIF_FRAME_CTRL_3 0x09
36 #define ARIZONA_AIF_FRAME_CTRL_4 0x0A
37 #define ARIZONA_AIF_FRAME_CTRL_5 0x0B
38 #define ARIZONA_AIF_FRAME_CTRL_6 0x0C
39 #define ARIZONA_AIF_FRAME_CTRL_7 0x0D
40 #define ARIZONA_AIF_FRAME_CTRL_8 0x0E
41 #define ARIZONA_AIF_FRAME_CTRL_9 0x0F
42 #define ARIZONA_AIF_FRAME_CTRL_10 0x10
43 #define ARIZONA_AIF_FRAME_CTRL_11 0x11
44 #define ARIZONA_AIF_FRAME_CTRL_12 0x12
45 #define ARIZONA_AIF_FRAME_CTRL_13 0x13
46 #define ARIZONA_AIF_FRAME_CTRL_14 0x14
47 #define ARIZONA_AIF_FRAME_CTRL_15 0x15
48 #define ARIZONA_AIF_FRAME_CTRL_16 0x16
49 #define ARIZONA_AIF_FRAME_CTRL_17 0x17
50 #define ARIZONA_AIF_FRAME_CTRL_18 0x18
51 #define ARIZONA_AIF_TX_ENABLES 0x19
52 #define ARIZONA_AIF_RX_ENABLES 0x1A
53 #define ARIZONA_AIF_FORCE_WRITE 0x1B
55 #define ARIZONA_FLL_VCO_CORNER 141900000
56 #define ARIZONA_FLL_MAX_FREF 13500000
57 #define ARIZONA_FLL_MIN_FVCO 90000000
58 #define ARIZONA_FLL_MAX_FRATIO 16
59 #define ARIZONA_FLL_MAX_REFDIV 8
60 #define ARIZONA_FLL_MIN_OUTDIV 2
61 #define ARIZONA_FLL_MAX_OUTDIV 7
63 #define ARIZONA_FMT_DSP_MODE_A 0
64 #define ARIZONA_FMT_DSP_MODE_B 1
65 #define ARIZONA_FMT_I2S_MODE 2
66 #define ARIZONA_FMT_LEFT_JUSTIFIED_MODE 3
68 #define arizona_fll_err(_fll, fmt, ...) \
69 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
70 #define arizona_fll_warn(_fll, fmt, ...) \
71 dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
72 #define arizona_fll_dbg(_fll, fmt, ...) \
73 dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
75 #define arizona_aif_err(_dai, fmt, ...) \
76 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
77 #define arizona_aif_warn(_dai, fmt, ...) \
78 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
79 #define arizona_aif_dbg(_dai, fmt, ...) \
80 dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
82 static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
83 struct snd_kcontrol *kcontrol,
86 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
87 struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
88 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
89 bool manual_ena = false;
92 switch (arizona->type) {
94 switch (arizona->rev) {
106 case SND_SOC_DAPM_PRE_PMU:
107 if (!priv->spk_ena && manual_ena) {
108 regmap_write_async(arizona->regmap, 0x4f5, 0x25a);
109 priv->spk_ena_pending = true;
112 case SND_SOC_DAPM_POST_PMU:
113 val = snd_soc_read(codec, ARIZONA_INTERRUPT_RAW_STATUS_3);
114 if (val & ARIZONA_SPK_OVERHEAT_STS) {
115 dev_crit(arizona->dev,
116 "Speaker not enabled due to temperature\n");
120 regmap_update_bits_async(arizona->regmap,
121 ARIZONA_OUTPUT_ENABLES_1,
122 1 << w->shift, 1 << w->shift);
124 if (priv->spk_ena_pending) {
126 regmap_write_async(arizona->regmap, 0x4f5, 0xda);
127 priv->spk_ena_pending = false;
131 case SND_SOC_DAPM_PRE_PMD:
135 regmap_write_async(arizona->regmap,
139 regmap_update_bits_async(arizona->regmap,
140 ARIZONA_OUTPUT_ENABLES_1,
143 case SND_SOC_DAPM_POST_PMD:
146 regmap_write_async(arizona->regmap,
155 static irqreturn_t arizona_thermal_warn(int irq, void *data)
157 struct arizona *arizona = data;
161 ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
164 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
166 } else if (val & ARIZONA_SPK_OVERHEAT_WARN_STS) {
167 dev_crit(arizona->dev, "Thermal warning\n");
173 static irqreturn_t arizona_thermal_shutdown(int irq, void *data)
175 struct arizona *arizona = data;
179 ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
182 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
184 } else if (val & ARIZONA_SPK_OVERHEAT_STS) {
185 dev_crit(arizona->dev, "Thermal shutdown\n");
186 ret = regmap_update_bits(arizona->regmap,
187 ARIZONA_OUTPUT_ENABLES_1,
189 ARIZONA_OUT4R_ENA, 0);
191 dev_crit(arizona->dev,
192 "Failed to disable speaker outputs: %d\n",
199 static const struct snd_soc_dapm_widget arizona_spkl =
200 SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
201 ARIZONA_OUT4L_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
202 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
204 static const struct snd_soc_dapm_widget arizona_spkr =
205 SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM,
206 ARIZONA_OUT4R_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
207 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
209 int arizona_init_spk(struct snd_soc_codec *codec)
211 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
212 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
213 struct arizona *arizona = priv->arizona;
216 ret = snd_soc_dapm_new_controls(dapm, &arizona_spkl, 1);
220 switch (arizona->type) {
224 ret = snd_soc_dapm_new_controls(dapm, &arizona_spkr, 1);
230 ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT_WARN,
231 "Thermal warning", arizona_thermal_warn,
234 dev_err(arizona->dev,
235 "Failed to get thermal warning IRQ: %d\n",
238 ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT,
239 "Thermal shutdown", arizona_thermal_shutdown,
242 dev_err(arizona->dev,
243 "Failed to get thermal shutdown IRQ: %d\n",
248 EXPORT_SYMBOL_GPL(arizona_init_spk);
250 static const struct snd_soc_dapm_route arizona_mono_routes[] = {
251 { "OUT1R", NULL, "OUT1L" },
252 { "OUT2R", NULL, "OUT2L" },
253 { "OUT3R", NULL, "OUT3L" },
254 { "OUT4R", NULL, "OUT4L" },
255 { "OUT5R", NULL, "OUT5L" },
256 { "OUT6R", NULL, "OUT6L" },
259 int arizona_init_mono(struct snd_soc_codec *codec)
261 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
262 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
263 struct arizona *arizona = priv->arizona;
266 for (i = 0; i < ARIZONA_MAX_OUTPUT; ++i) {
267 if (arizona->pdata.out_mono[i])
268 snd_soc_dapm_add_routes(dapm,
269 &arizona_mono_routes[i], 1);
274 EXPORT_SYMBOL_GPL(arizona_init_mono);
276 int arizona_init_gpio(struct snd_soc_codec *codec)
278 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
279 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
280 struct arizona *arizona = priv->arizona;
283 switch (arizona->type) {
286 snd_soc_dapm_disable_pin(dapm, "DRC2 Signal Activity");
292 snd_soc_dapm_disable_pin(dapm, "DRC1 Signal Activity");
294 for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
295 switch (arizona->pdata.gpio_defaults[i] & ARIZONA_GPN_FN_MASK) {
296 case ARIZONA_GP_FN_DRC1_SIGNAL_DETECT:
297 snd_soc_dapm_enable_pin(dapm, "DRC1 Signal Activity");
299 case ARIZONA_GP_FN_DRC2_SIGNAL_DETECT:
300 snd_soc_dapm_enable_pin(dapm, "DRC2 Signal Activity");
309 EXPORT_SYMBOL_GPL(arizona_init_gpio);
311 const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = {
416 EXPORT_SYMBOL_GPL(arizona_mixer_texts);
418 int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = {
424 0x0c, /* Noise mixer */
425 0x0d, /* Comfort noise */
498 0xa0, /* ISRC1INT1 */
502 0xa4, /* ISRC1DEC1 */
506 0xa8, /* ISRC2DEC1 */
510 0xac, /* ISRC2INT1 */
514 0xb0, /* ISRC3DEC1 */
518 0xb4, /* ISRC3INT1 */
523 EXPORT_SYMBOL_GPL(arizona_mixer_values);
525 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0);
526 EXPORT_SYMBOL_GPL(arizona_mixer_tlv);
528 const char *arizona_rate_text[ARIZONA_RATE_ENUM_SIZE] = {
529 "SYNCCLK rate", "8kHz", "16kHz", "ASYNCCLK rate",
531 EXPORT_SYMBOL_GPL(arizona_rate_text);
533 const int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE] = {
536 EXPORT_SYMBOL_GPL(arizona_rate_val);
539 const struct soc_enum arizona_isrc_fsh[] = {
540 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_1,
541 ARIZONA_ISRC1_FSH_SHIFT, 0xf,
542 ARIZONA_RATE_ENUM_SIZE,
543 arizona_rate_text, arizona_rate_val),
544 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_1,
545 ARIZONA_ISRC2_FSH_SHIFT, 0xf,
546 ARIZONA_RATE_ENUM_SIZE,
547 arizona_rate_text, arizona_rate_val),
548 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_1,
549 ARIZONA_ISRC3_FSH_SHIFT, 0xf,
550 ARIZONA_RATE_ENUM_SIZE,
551 arizona_rate_text, arizona_rate_val),
553 EXPORT_SYMBOL_GPL(arizona_isrc_fsh);
555 const struct soc_enum arizona_isrc_fsl[] = {
556 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2,
557 ARIZONA_ISRC1_FSL_SHIFT, 0xf,
558 ARIZONA_RATE_ENUM_SIZE,
559 arizona_rate_text, arizona_rate_val),
560 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2,
561 ARIZONA_ISRC2_FSL_SHIFT, 0xf,
562 ARIZONA_RATE_ENUM_SIZE,
563 arizona_rate_text, arizona_rate_val),
564 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2,
565 ARIZONA_ISRC3_FSL_SHIFT, 0xf,
566 ARIZONA_RATE_ENUM_SIZE,
567 arizona_rate_text, arizona_rate_val),
569 EXPORT_SYMBOL_GPL(arizona_isrc_fsl);
571 const struct soc_enum arizona_asrc_rate1 =
572 SOC_VALUE_ENUM_SINGLE(ARIZONA_ASRC_RATE1,
573 ARIZONA_ASRC_RATE1_SHIFT, 0xf,
574 ARIZONA_RATE_ENUM_SIZE - 1,
575 arizona_rate_text, arizona_rate_val);
576 EXPORT_SYMBOL_GPL(arizona_asrc_rate1);
578 static const char *arizona_vol_ramp_text[] = {
579 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
580 "15ms/6dB", "30ms/6dB",
583 SOC_ENUM_SINGLE_DECL(arizona_in_vd_ramp,
584 ARIZONA_INPUT_VOLUME_RAMP,
585 ARIZONA_IN_VD_RAMP_SHIFT,
586 arizona_vol_ramp_text);
587 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp);
589 SOC_ENUM_SINGLE_DECL(arizona_in_vi_ramp,
590 ARIZONA_INPUT_VOLUME_RAMP,
591 ARIZONA_IN_VI_RAMP_SHIFT,
592 arizona_vol_ramp_text);
593 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp);
595 SOC_ENUM_SINGLE_DECL(arizona_out_vd_ramp,
596 ARIZONA_OUTPUT_VOLUME_RAMP,
597 ARIZONA_OUT_VD_RAMP_SHIFT,
598 arizona_vol_ramp_text);
599 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp);
601 SOC_ENUM_SINGLE_DECL(arizona_out_vi_ramp,
602 ARIZONA_OUTPUT_VOLUME_RAMP,
603 ARIZONA_OUT_VI_RAMP_SHIFT,
604 arizona_vol_ramp_text);
605 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp);
607 static const char *arizona_lhpf_mode_text[] = {
608 "Low-pass", "High-pass"
611 SOC_ENUM_SINGLE_DECL(arizona_lhpf1_mode,
613 ARIZONA_LHPF1_MODE_SHIFT,
614 arizona_lhpf_mode_text);
615 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode);
617 SOC_ENUM_SINGLE_DECL(arizona_lhpf2_mode,
619 ARIZONA_LHPF2_MODE_SHIFT,
620 arizona_lhpf_mode_text);
621 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode);
623 SOC_ENUM_SINGLE_DECL(arizona_lhpf3_mode,
625 ARIZONA_LHPF3_MODE_SHIFT,
626 arizona_lhpf_mode_text);
627 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode);
629 SOC_ENUM_SINGLE_DECL(arizona_lhpf4_mode,
631 ARIZONA_LHPF4_MODE_SHIFT,
632 arizona_lhpf_mode_text);
633 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode);
635 static const char *arizona_ng_hold_text[] = {
636 "30ms", "120ms", "250ms", "500ms",
639 SOC_ENUM_SINGLE_DECL(arizona_ng_hold,
640 ARIZONA_NOISE_GATE_CONTROL,
641 ARIZONA_NGATE_HOLD_SHIFT,
642 arizona_ng_hold_text);
643 EXPORT_SYMBOL_GPL(arizona_ng_hold);
645 static const char * const arizona_in_hpf_cut_text[] = {
646 "2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz"
649 SOC_ENUM_SINGLE_DECL(arizona_in_hpf_cut_enum,
651 ARIZONA_IN_HPF_CUT_SHIFT,
652 arizona_in_hpf_cut_text);
653 EXPORT_SYMBOL_GPL(arizona_in_hpf_cut_enum);
655 static const char * const arizona_in_dmic_osr_text[] = {
656 "1.536MHz", "3.072MHz", "6.144MHz", "768kHz",
659 const struct soc_enum arizona_in_dmic_osr[] = {
660 SOC_ENUM_SINGLE(ARIZONA_IN1L_CONTROL, ARIZONA_IN1_OSR_SHIFT,
661 ARRAY_SIZE(arizona_in_dmic_osr_text),
662 arizona_in_dmic_osr_text),
663 SOC_ENUM_SINGLE(ARIZONA_IN2L_CONTROL, ARIZONA_IN2_OSR_SHIFT,
664 ARRAY_SIZE(arizona_in_dmic_osr_text),
665 arizona_in_dmic_osr_text),
666 SOC_ENUM_SINGLE(ARIZONA_IN3L_CONTROL, ARIZONA_IN3_OSR_SHIFT,
667 ARRAY_SIZE(arizona_in_dmic_osr_text),
668 arizona_in_dmic_osr_text),
669 SOC_ENUM_SINGLE(ARIZONA_IN4L_CONTROL, ARIZONA_IN4_OSR_SHIFT,
670 ARRAY_SIZE(arizona_in_dmic_osr_text),
671 arizona_in_dmic_osr_text),
673 EXPORT_SYMBOL_GPL(arizona_in_dmic_osr);
675 static void arizona_in_set_vu(struct snd_soc_codec *codec, int ena)
677 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
686 for (i = 0; i < priv->num_inputs; i++)
687 snd_soc_update_bits(codec,
688 ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 4),
692 int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
695 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
696 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
700 reg = ARIZONA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8);
702 reg = ARIZONA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8);
705 case SND_SOC_DAPM_PRE_PMU:
708 case SND_SOC_DAPM_POST_PMU:
709 snd_soc_update_bits(codec, reg, ARIZONA_IN1L_MUTE, 0);
711 /* If this is the last input pending then allow VU */
713 if (priv->in_pending == 0) {
715 arizona_in_set_vu(codec, 1);
718 case SND_SOC_DAPM_PRE_PMD:
719 snd_soc_update_bits(codec, reg,
720 ARIZONA_IN1L_MUTE | ARIZONA_IN_VU,
721 ARIZONA_IN1L_MUTE | ARIZONA_IN_VU);
723 case SND_SOC_DAPM_POST_PMD:
724 /* Disable volume updates if no inputs are enabled */
725 reg = snd_soc_read(codec, ARIZONA_INPUT_ENABLES);
727 arizona_in_set_vu(codec, 0);
732 EXPORT_SYMBOL_GPL(arizona_in_ev);
734 int arizona_out_ev(struct snd_soc_dapm_widget *w,
735 struct snd_kcontrol *kcontrol,
738 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
739 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
742 case SND_SOC_DAPM_PRE_PMU:
744 case ARIZONA_OUT1L_ENA_SHIFT:
745 case ARIZONA_OUT1R_ENA_SHIFT:
746 case ARIZONA_OUT2L_ENA_SHIFT:
747 case ARIZONA_OUT2R_ENA_SHIFT:
748 case ARIZONA_OUT3L_ENA_SHIFT:
749 case ARIZONA_OUT3R_ENA_SHIFT:
750 priv->out_up_pending++;
751 priv->out_up_delay += 17;
757 case SND_SOC_DAPM_POST_PMU:
759 case ARIZONA_OUT1L_ENA_SHIFT:
760 case ARIZONA_OUT1R_ENA_SHIFT:
761 case ARIZONA_OUT2L_ENA_SHIFT:
762 case ARIZONA_OUT2R_ENA_SHIFT:
763 case ARIZONA_OUT3L_ENA_SHIFT:
764 case ARIZONA_OUT3R_ENA_SHIFT:
765 priv->out_up_pending--;
766 if (!priv->out_up_pending) {
767 msleep(priv->out_up_delay);
768 priv->out_up_delay = 0;
776 case SND_SOC_DAPM_PRE_PMD:
778 case ARIZONA_OUT1L_ENA_SHIFT:
779 case ARIZONA_OUT1R_ENA_SHIFT:
780 case ARIZONA_OUT2L_ENA_SHIFT:
781 case ARIZONA_OUT2R_ENA_SHIFT:
782 case ARIZONA_OUT3L_ENA_SHIFT:
783 case ARIZONA_OUT3R_ENA_SHIFT:
784 priv->out_down_pending++;
785 priv->out_down_delay++;
791 case SND_SOC_DAPM_POST_PMD:
793 case ARIZONA_OUT1L_ENA_SHIFT:
794 case ARIZONA_OUT1R_ENA_SHIFT:
795 case ARIZONA_OUT2L_ENA_SHIFT:
796 case ARIZONA_OUT2R_ENA_SHIFT:
797 case ARIZONA_OUT3L_ENA_SHIFT:
798 case ARIZONA_OUT3R_ENA_SHIFT:
799 priv->out_down_pending--;
800 if (!priv->out_down_pending) {
801 msleep(priv->out_down_delay);
802 priv->out_down_delay = 0;
813 EXPORT_SYMBOL_GPL(arizona_out_ev);
815 int arizona_hp_ev(struct snd_soc_dapm_widget *w,
816 struct snd_kcontrol *kcontrol,
819 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
820 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
821 struct arizona *arizona = priv->arizona;
822 unsigned int mask = 1 << w->shift;
826 case SND_SOC_DAPM_POST_PMU:
829 case SND_SOC_DAPM_PRE_PMD:
832 case SND_SOC_DAPM_PRE_PMU:
833 case SND_SOC_DAPM_POST_PMD:
834 return arizona_out_ev(w, kcontrol, event);
839 /* Store the desired state for the HP outputs */
840 priv->arizona->hp_ena &= ~mask;
841 priv->arizona->hp_ena |= val;
843 /* Force off if HPDET clamp is active */
844 if (priv->arizona->hpdet_clamp)
847 regmap_update_bits_async(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1,
850 return arizona_out_ev(w, kcontrol, event);
852 EXPORT_SYMBOL_GPL(arizona_hp_ev);
854 static int arizona_dvfs_enable(struct snd_soc_codec *codec)
856 const struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
857 struct arizona *arizona = priv->arizona;
860 ret = regulator_set_voltage(arizona->dcvdd, 1800000, 1800000);
862 dev_err(codec->dev, "Failed to boost DCVDD: %d\n", ret);
866 ret = regmap_update_bits(arizona->regmap,
867 ARIZONA_DYNAMIC_FREQUENCY_SCALING_1,
868 ARIZONA_SUBSYS_MAX_FREQ,
869 ARIZONA_SUBSYS_MAX_FREQ);
871 dev_err(codec->dev, "Failed to enable subsys max: %d\n", ret);
872 regulator_set_voltage(arizona->dcvdd, 1200000, 1800000);
879 static int arizona_dvfs_disable(struct snd_soc_codec *codec)
881 const struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
882 struct arizona *arizona = priv->arizona;
885 ret = regmap_update_bits(arizona->regmap,
886 ARIZONA_DYNAMIC_FREQUENCY_SCALING_1,
887 ARIZONA_SUBSYS_MAX_FREQ, 0);
889 dev_err(codec->dev, "Failed to disable subsys max: %d\n", ret);
893 ret = regulator_set_voltage(arizona->dcvdd, 1200000, 1800000);
895 dev_err(codec->dev, "Failed to unboost DCVDD: %d\n", ret);
902 int arizona_dvfs_up(struct snd_soc_codec *codec, unsigned int flags)
904 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
907 mutex_lock(&priv->dvfs_lock);
909 if (!priv->dvfs_cached && !priv->dvfs_reqs) {
910 ret = arizona_dvfs_enable(codec);
915 priv->dvfs_reqs |= flags;
917 mutex_unlock(&priv->dvfs_lock);
920 EXPORT_SYMBOL_GPL(arizona_dvfs_up);
922 int arizona_dvfs_down(struct snd_soc_codec *codec, unsigned int flags)
924 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
925 unsigned int old_reqs;
928 mutex_lock(&priv->dvfs_lock);
930 old_reqs = priv->dvfs_reqs;
931 priv->dvfs_reqs &= ~flags;
933 if (!priv->dvfs_cached && old_reqs && !priv->dvfs_reqs)
934 ret = arizona_dvfs_disable(codec);
936 mutex_unlock(&priv->dvfs_lock);
939 EXPORT_SYMBOL_GPL(arizona_dvfs_down);
941 int arizona_dvfs_sysclk_ev(struct snd_soc_dapm_widget *w,
942 struct snd_kcontrol *kcontrol, int event)
944 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
945 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
948 mutex_lock(&priv->dvfs_lock);
951 case SND_SOC_DAPM_POST_PMU:
953 ret = arizona_dvfs_enable(codec);
955 priv->dvfs_cached = false;
957 case SND_SOC_DAPM_PRE_PMD:
958 /* We must ensure DVFS is disabled before the codec goes into
959 * suspend so that we are never in an illegal state of DVFS
960 * enabled without enough DCVDD
962 priv->dvfs_cached = true;
965 ret = arizona_dvfs_disable(codec);
971 mutex_unlock(&priv->dvfs_lock);
974 EXPORT_SYMBOL_GPL(arizona_dvfs_sysclk_ev);
976 void arizona_init_dvfs(struct arizona_priv *priv)
978 mutex_init(&priv->dvfs_lock);
980 EXPORT_SYMBOL_GPL(arizona_init_dvfs);
982 static unsigned int arizona_sysclk_48k_rates[] = {
992 static unsigned int arizona_sysclk_44k1_rates[] = {
1002 static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk,
1005 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1007 unsigned int *rates;
1008 int ref, div, refclk;
1011 case ARIZONA_CLK_OPCLK:
1012 reg = ARIZONA_OUTPUT_SYSTEM_CLOCK;
1013 refclk = priv->sysclk;
1015 case ARIZONA_CLK_ASYNC_OPCLK:
1016 reg = ARIZONA_OUTPUT_ASYNC_CLOCK;
1017 refclk = priv->asyncclk;
1024 rates = arizona_sysclk_44k1_rates;
1026 rates = arizona_sysclk_48k_rates;
1028 for (ref = 0; ref < ARRAY_SIZE(arizona_sysclk_48k_rates) &&
1029 rates[ref] <= refclk; ref++) {
1031 while (rates[ref] / div >= freq && div < 32) {
1032 if (rates[ref] / div == freq) {
1033 dev_dbg(codec->dev, "Configured %dHz OPCLK\n",
1035 snd_soc_update_bits(codec, reg,
1036 ARIZONA_OPCLK_DIV_MASK |
1037 ARIZONA_OPCLK_SEL_MASK,
1039 ARIZONA_OPCLK_DIV_SHIFT) |
1047 dev_err(codec->dev, "Unable to generate %dHz OPCLK\n", freq);
1051 int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1052 int source, unsigned int freq, int dir)
1054 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1055 struct arizona *arizona = priv->arizona;
1058 unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK;
1059 unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT;
1063 case ARIZONA_CLK_SYSCLK:
1065 reg = ARIZONA_SYSTEM_CLOCK_1;
1066 clk = &priv->sysclk;
1067 mask |= ARIZONA_SYSCLK_FRAC;
1069 case ARIZONA_CLK_ASYNCCLK:
1071 reg = ARIZONA_ASYNC_CLOCK_1;
1072 clk = &priv->asyncclk;
1074 case ARIZONA_CLK_OPCLK:
1075 case ARIZONA_CLK_ASYNC_OPCLK:
1076 return arizona_set_opclk(codec, clk_id, freq);
1087 val |= ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1091 val |= ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1095 val |= ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1099 val |= ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1103 val |= ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1107 val |= ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
1110 dev_dbg(arizona->dev, "%s cleared\n", name);
1120 val |= ARIZONA_SYSCLK_FRAC;
1122 dev_dbg(arizona->dev, "%s set to %uHz", name, freq);
1124 return regmap_update_bits(arizona->regmap, reg, mask, val);
1126 EXPORT_SYMBOL_GPL(arizona_set_sysclk);
1128 static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1130 struct snd_soc_codec *codec = dai->codec;
1131 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1132 struct arizona *arizona = priv->arizona;
1133 int lrclk, bclk, mode, base;
1135 base = dai->driver->base;
1140 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1141 case SND_SOC_DAIFMT_DSP_A:
1142 mode = ARIZONA_FMT_DSP_MODE_A;
1144 case SND_SOC_DAIFMT_DSP_B:
1145 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK)
1146 != SND_SOC_DAIFMT_CBM_CFM) {
1147 arizona_aif_err(dai, "DSP_B not valid in slave mode\n");
1150 mode = ARIZONA_FMT_DSP_MODE_B;
1152 case SND_SOC_DAIFMT_I2S:
1153 mode = ARIZONA_FMT_I2S_MODE;
1155 case SND_SOC_DAIFMT_LEFT_J:
1156 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK)
1157 != SND_SOC_DAIFMT_CBM_CFM) {
1158 arizona_aif_err(dai, "LEFT_J not valid in slave mode\n");
1161 mode = ARIZONA_FMT_LEFT_JUSTIFIED_MODE;
1164 arizona_aif_err(dai, "Unsupported DAI format %d\n",
1165 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1169 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1170 case SND_SOC_DAIFMT_CBS_CFS:
1172 case SND_SOC_DAIFMT_CBS_CFM:
1173 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
1175 case SND_SOC_DAIFMT_CBM_CFS:
1176 bclk |= ARIZONA_AIF1_BCLK_MSTR;
1178 case SND_SOC_DAIFMT_CBM_CFM:
1179 bclk |= ARIZONA_AIF1_BCLK_MSTR;
1180 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
1183 arizona_aif_err(dai, "Unsupported master mode %d\n",
1184 fmt & SND_SOC_DAIFMT_MASTER_MASK);
1188 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1189 case SND_SOC_DAIFMT_NB_NF:
1191 case SND_SOC_DAIFMT_IB_IF:
1192 bclk |= ARIZONA_AIF1_BCLK_INV;
1193 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
1195 case SND_SOC_DAIFMT_IB_NF:
1196 bclk |= ARIZONA_AIF1_BCLK_INV;
1198 case SND_SOC_DAIFMT_NB_IF:
1199 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
1205 regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_BCLK_CTRL,
1206 ARIZONA_AIF1_BCLK_INV |
1207 ARIZONA_AIF1_BCLK_MSTR,
1209 regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_TX_PIN_CTRL,
1210 ARIZONA_AIF1TX_LRCLK_INV |
1211 ARIZONA_AIF1TX_LRCLK_MSTR, lrclk);
1212 regmap_update_bits_async(arizona->regmap,
1213 base + ARIZONA_AIF_RX_PIN_CTRL,
1214 ARIZONA_AIF1RX_LRCLK_INV |
1215 ARIZONA_AIF1RX_LRCLK_MSTR, lrclk);
1216 regmap_update_bits(arizona->regmap, base + ARIZONA_AIF_FORMAT,
1217 ARIZONA_AIF1_FMT_MASK, mode);
1222 static const int arizona_48k_bclk_rates[] = {
1244 static const unsigned int arizona_48k_rates[] = {
1262 static const struct snd_pcm_hw_constraint_list arizona_48k_constraint = {
1263 .count = ARRAY_SIZE(arizona_48k_rates),
1264 .list = arizona_48k_rates,
1267 static const int arizona_44k1_bclk_rates[] = {
1289 static const unsigned int arizona_44k1_rates[] = {
1299 static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint = {
1300 .count = ARRAY_SIZE(arizona_44k1_rates),
1301 .list = arizona_44k1_rates,
1304 static int arizona_sr_vals[] = {
1331 static int arizona_startup(struct snd_pcm_substream *substream,
1332 struct snd_soc_dai *dai)
1334 struct snd_soc_codec *codec = dai->codec;
1335 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1336 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1337 const struct snd_pcm_hw_constraint_list *constraint;
1338 unsigned int base_rate;
1340 switch (dai_priv->clk) {
1341 case ARIZONA_CLK_SYSCLK:
1342 base_rate = priv->sysclk;
1344 case ARIZONA_CLK_ASYNCCLK:
1345 base_rate = priv->asyncclk;
1354 if (base_rate % 8000)
1355 constraint = &arizona_44k1_constraint;
1357 constraint = &arizona_48k_constraint;
1359 return snd_pcm_hw_constraint_list(substream->runtime, 0,
1360 SNDRV_PCM_HW_PARAM_RATE,
1364 static void arizona_wm5102_set_dac_comp(struct snd_soc_codec *codec,
1367 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1368 struct arizona *arizona = priv->arizona;
1369 struct reg_sequence dac_comp[] = {
1371 { ARIZONA_DAC_COMP_1, 0 },
1372 { ARIZONA_DAC_COMP_2, 0 },
1376 mutex_lock(&arizona->dac_comp_lock);
1378 dac_comp[1].def = arizona->dac_comp_coeff;
1380 dac_comp[2].def = arizona->dac_comp_enabled;
1382 mutex_unlock(&arizona->dac_comp_lock);
1384 regmap_multi_reg_write(arizona->regmap,
1386 ARRAY_SIZE(dac_comp));
1389 static int arizona_hw_params_rate(struct snd_pcm_substream *substream,
1390 struct snd_pcm_hw_params *params,
1391 struct snd_soc_dai *dai)
1393 struct snd_soc_codec *codec = dai->codec;
1394 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1395 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1396 int base = dai->driver->base;
1400 * We will need to be more flexible than this in future,
1401 * currently we use a single sample rate for SYSCLK.
1403 for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
1404 if (arizona_sr_vals[i] == params_rate(params))
1406 if (i == ARRAY_SIZE(arizona_sr_vals)) {
1407 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1408 params_rate(params));
1413 switch (priv->arizona->type) {
1416 if (arizona_sr_vals[sr_val] >= 88200)
1417 ret = arizona_dvfs_up(codec, ARIZONA_DVFS_SR1_RQ);
1419 ret = arizona_dvfs_down(codec, ARIZONA_DVFS_SR1_RQ);
1422 arizona_aif_err(dai, "Failed to change DVFS %d\n", ret);
1430 switch (dai_priv->clk) {
1431 case ARIZONA_CLK_SYSCLK:
1432 switch (priv->arizona->type) {
1434 arizona_wm5102_set_dac_comp(codec,
1435 params_rate(params));
1441 snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1,
1442 ARIZONA_SAMPLE_RATE_1_MASK, sr_val);
1444 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1445 ARIZONA_AIF1_RATE_MASK, 0);
1447 case ARIZONA_CLK_ASYNCCLK:
1448 snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
1449 ARIZONA_ASYNC_SAMPLE_RATE_1_MASK, sr_val);
1451 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1452 ARIZONA_AIF1_RATE_MASK,
1453 8 << ARIZONA_AIF1_RATE_SHIFT);
1456 arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
1463 static bool arizona_aif_cfg_changed(struct snd_soc_codec *codec,
1464 int base, int bclk, int lrclk, int frame)
1468 val = snd_soc_read(codec, base + ARIZONA_AIF_BCLK_CTRL);
1469 if (bclk != (val & ARIZONA_AIF1_BCLK_FREQ_MASK))
1472 val = snd_soc_read(codec, base + ARIZONA_AIF_TX_BCLK_RATE);
1473 if (lrclk != (val & ARIZONA_AIF1TX_BCPF_MASK))
1476 val = snd_soc_read(codec, base + ARIZONA_AIF_FRAME_CTRL_1);
1477 if (frame != (val & (ARIZONA_AIF1TX_WL_MASK |
1478 ARIZONA_AIF1TX_SLOT_LEN_MASK)))
1484 static int arizona_hw_params(struct snd_pcm_substream *substream,
1485 struct snd_pcm_hw_params *params,
1486 struct snd_soc_dai *dai)
1488 struct snd_soc_codec *codec = dai->codec;
1489 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1490 struct arizona *arizona = priv->arizona;
1491 int base = dai->driver->base;
1494 int channels = params_channels(params);
1495 int chan_limit = arizona->pdata.max_channels_clocked[dai->id - 1];
1496 int tdm_width = arizona->tdm_width[dai->id - 1];
1497 int tdm_slots = arizona->tdm_slots[dai->id - 1];
1498 int bclk, lrclk, wl, frame, bclk_target;
1500 unsigned int aif_tx_state, aif_rx_state;
1502 if (params_rate(params) % 8000)
1503 rates = &arizona_44k1_bclk_rates[0];
1505 rates = &arizona_48k_bclk_rates[0];
1507 wl = params_width(params);
1510 arizona_aif_dbg(dai, "Configuring for %d %d bit TDM slots\n",
1511 tdm_slots, tdm_width);
1512 bclk_target = tdm_slots * tdm_width * params_rate(params);
1513 channels = tdm_slots;
1515 bclk_target = snd_soc_params_to_bclk(params);
1519 if (chan_limit && chan_limit < channels) {
1520 arizona_aif_dbg(dai, "Limiting to %d channels\n", chan_limit);
1521 bclk_target /= channels;
1522 bclk_target *= chan_limit;
1525 /* Force multiple of 2 channels for I2S mode */
1526 val = snd_soc_read(codec, base + ARIZONA_AIF_FORMAT);
1527 val &= ARIZONA_AIF1_FMT_MASK;
1528 if ((channels & 1) && (val == ARIZONA_FMT_I2S_MODE)) {
1529 arizona_aif_dbg(dai, "Forcing stereo mode\n");
1530 bclk_target /= channels;
1531 bclk_target *= channels + 1;
1534 for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) {
1535 if (rates[i] >= bclk_target &&
1536 rates[i] % params_rate(params) == 0) {
1541 if (i == ARRAY_SIZE(arizona_44k1_bclk_rates)) {
1542 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1543 params_rate(params));
1547 lrclk = rates[bclk] / params_rate(params);
1549 arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
1550 rates[bclk], rates[bclk] / lrclk);
1552 frame = wl << ARIZONA_AIF1TX_WL_SHIFT | tdm_width;
1554 reconfig = arizona_aif_cfg_changed(codec, base, bclk, lrclk, frame);
1557 /* Save AIF TX/RX state */
1558 aif_tx_state = snd_soc_read(codec,
1559 base + ARIZONA_AIF_TX_ENABLES);
1560 aif_rx_state = snd_soc_read(codec,
1561 base + ARIZONA_AIF_RX_ENABLES);
1562 /* Disable AIF TX/RX before reconfiguring it */
1563 regmap_update_bits_async(arizona->regmap,
1564 base + ARIZONA_AIF_TX_ENABLES, 0xff, 0x0);
1565 regmap_update_bits(arizona->regmap,
1566 base + ARIZONA_AIF_RX_ENABLES, 0xff, 0x0);
1569 ret = arizona_hw_params_rate(substream, params, dai);
1574 regmap_update_bits_async(arizona->regmap,
1575 base + ARIZONA_AIF_BCLK_CTRL,
1576 ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
1577 regmap_update_bits_async(arizona->regmap,
1578 base + ARIZONA_AIF_TX_BCLK_RATE,
1579 ARIZONA_AIF1TX_BCPF_MASK, lrclk);
1580 regmap_update_bits_async(arizona->regmap,
1581 base + ARIZONA_AIF_RX_BCLK_RATE,
1582 ARIZONA_AIF1RX_BCPF_MASK, lrclk);
1583 regmap_update_bits_async(arizona->regmap,
1584 base + ARIZONA_AIF_FRAME_CTRL_1,
1585 ARIZONA_AIF1TX_WL_MASK |
1586 ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
1587 regmap_update_bits(arizona->regmap,
1588 base + ARIZONA_AIF_FRAME_CTRL_2,
1589 ARIZONA_AIF1RX_WL_MASK |
1590 ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
1595 /* Restore AIF TX/RX state */
1596 regmap_update_bits_async(arizona->regmap,
1597 base + ARIZONA_AIF_TX_ENABLES,
1598 0xff, aif_tx_state);
1599 regmap_update_bits(arizona->regmap,
1600 base + ARIZONA_AIF_RX_ENABLES,
1601 0xff, aif_rx_state);
1606 static const char *arizona_dai_clk_str(int clk_id)
1609 case ARIZONA_CLK_SYSCLK:
1611 case ARIZONA_CLK_ASYNCCLK:
1614 return "Unknown clock";
1618 static int arizona_dai_set_sysclk(struct snd_soc_dai *dai,
1619 int clk_id, unsigned int freq, int dir)
1621 struct snd_soc_codec *codec = dai->codec;
1622 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1623 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1624 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1625 struct snd_soc_dapm_route routes[2];
1628 case ARIZONA_CLK_SYSCLK:
1629 case ARIZONA_CLK_ASYNCCLK:
1635 if (clk_id == dai_priv->clk)
1639 dev_err(codec->dev, "Can't change clock on active DAI %d\n",
1644 dev_dbg(codec->dev, "Setting AIF%d to %s\n", dai->id + 1,
1645 arizona_dai_clk_str(clk_id));
1647 memset(&routes, 0, sizeof(routes));
1648 routes[0].sink = dai->driver->capture.stream_name;
1649 routes[1].sink = dai->driver->playback.stream_name;
1651 routes[0].source = arizona_dai_clk_str(dai_priv->clk);
1652 routes[1].source = arizona_dai_clk_str(dai_priv->clk);
1653 snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes));
1655 routes[0].source = arizona_dai_clk_str(clk_id);
1656 routes[1].source = arizona_dai_clk_str(clk_id);
1657 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
1659 dai_priv->clk = clk_id;
1661 return snd_soc_dapm_sync(dapm);
1664 static int arizona_set_tristate(struct snd_soc_dai *dai, int tristate)
1666 struct snd_soc_codec *codec = dai->codec;
1667 int base = dai->driver->base;
1671 reg = ARIZONA_AIF1_TRI;
1675 return snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1676 ARIZONA_AIF1_TRI, reg);
1679 static void arizona_set_channels_to_mask(struct snd_soc_dai *dai,
1681 int channels, unsigned int mask)
1683 struct snd_soc_codec *codec = dai->codec;
1684 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1685 struct arizona *arizona = priv->arizona;
1688 for (i = 0; i < channels; ++i) {
1689 slot = ffs(mask) - 1;
1693 regmap_write(arizona->regmap, base + i, slot);
1695 mask &= ~(1 << slot);
1699 arizona_aif_warn(dai, "Too many channels in TDM mask\n");
1702 static int arizona_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1703 unsigned int rx_mask, int slots, int slot_width)
1705 struct snd_soc_codec *codec = dai->codec;
1706 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1707 struct arizona *arizona = priv->arizona;
1708 int base = dai->driver->base;
1709 int rx_max_chan = dai->driver->playback.channels_max;
1710 int tx_max_chan = dai->driver->capture.channels_max;
1712 /* Only support TDM for the physical AIFs */
1713 if (dai->id > ARIZONA_MAX_AIF)
1717 tx_mask = (1 << tx_max_chan) - 1;
1718 rx_mask = (1 << rx_max_chan) - 1;
1721 arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_3,
1722 tx_max_chan, tx_mask);
1723 arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_11,
1724 rx_max_chan, rx_mask);
1726 arizona->tdm_width[dai->id - 1] = slot_width;
1727 arizona->tdm_slots[dai->id - 1] = slots;
1732 const struct snd_soc_dai_ops arizona_dai_ops = {
1733 .startup = arizona_startup,
1734 .set_fmt = arizona_set_fmt,
1735 .set_tdm_slot = arizona_set_tdm_slot,
1736 .hw_params = arizona_hw_params,
1737 .set_sysclk = arizona_dai_set_sysclk,
1738 .set_tristate = arizona_set_tristate,
1740 EXPORT_SYMBOL_GPL(arizona_dai_ops);
1742 const struct snd_soc_dai_ops arizona_simple_dai_ops = {
1743 .startup = arizona_startup,
1744 .hw_params = arizona_hw_params_rate,
1745 .set_sysclk = arizona_dai_set_sysclk,
1747 EXPORT_SYMBOL_GPL(arizona_simple_dai_ops);
1749 int arizona_init_dai(struct arizona_priv *priv, int id)
1751 struct arizona_dai_priv *dai_priv = &priv->dai[id];
1753 dai_priv->clk = ARIZONA_CLK_SYSCLK;
1757 EXPORT_SYMBOL_GPL(arizona_init_dai);
1765 { 0, 64000, 4, 16 },
1766 { 64000, 128000, 3, 8 },
1767 { 128000, 256000, 2, 4 },
1768 { 256000, 1000000, 1, 2 },
1769 { 1000000, 13500000, 0, 1 },
1778 { 256000, 1000000, 2 },
1779 { 1000000, 13500000, 4 },
1782 struct arizona_fll_cfg {
1792 static int arizona_validate_fll(struct arizona_fll *fll,
1796 unsigned int Fvco_min;
1798 if (fll->fout && Fout != fll->fout) {
1799 arizona_fll_err(fll,
1800 "Can't change output on active FLL\n");
1804 if (Fref / ARIZONA_FLL_MAX_REFDIV > ARIZONA_FLL_MAX_FREF) {
1805 arizona_fll_err(fll,
1806 "Can't scale %dMHz in to <=13.5MHz\n",
1811 Fvco_min = ARIZONA_FLL_MIN_FVCO * fll->vco_mult;
1812 if (Fout * ARIZONA_FLL_MAX_OUTDIV < Fvco_min) {
1813 arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n",
1821 static int arizona_find_fratio(unsigned int Fref, int *fratio)
1825 /* Find an appropriate FLL_FRATIO */
1826 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1827 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1829 *fratio = fll_fratios[i].fratio;
1830 return fll_fratios[i].ratio;
1837 static int arizona_calc_fratio(struct arizona_fll *fll,
1838 struct arizona_fll_cfg *cfg,
1839 unsigned int target,
1840 unsigned int Fref, bool sync)
1842 int init_ratio, ratio;
1845 /* Fref must be <=13.5MHz, find initial refdiv */
1848 while (Fref > ARIZONA_FLL_MAX_FREF) {
1853 if (div > ARIZONA_FLL_MAX_REFDIV)
1857 /* Find an appropriate FLL_FRATIO */
1858 init_ratio = arizona_find_fratio(Fref, &cfg->fratio);
1859 if (init_ratio < 0) {
1860 arizona_fll_err(fll, "Unable to find FRATIO for Fref=%uHz\n",
1865 switch (fll->arizona->type) {
1868 if (fll->arizona->rev < 3 || sync)
1875 cfg->fratio = init_ratio - 1;
1877 /* Adjust FRATIO/refdiv to avoid integer mode if possible */
1878 refdiv = cfg->refdiv;
1880 while (div <= ARIZONA_FLL_MAX_REFDIV) {
1881 for (ratio = init_ratio; ratio <= ARIZONA_FLL_MAX_FRATIO;
1883 if ((ARIZONA_FLL_VCO_CORNER / 2) /
1884 (fll->vco_mult * ratio) < Fref)
1887 if (target % (ratio * Fref)) {
1888 cfg->refdiv = refdiv;
1889 cfg->fratio = ratio - 1;
1894 for (ratio = init_ratio - 1; ratio > 0; ratio--) {
1895 if (target % (ratio * Fref)) {
1896 cfg->refdiv = refdiv;
1897 cfg->fratio = ratio - 1;
1905 init_ratio = arizona_find_fratio(Fref, NULL);
1908 arizona_fll_warn(fll, "Falling back to integer mode operation\n");
1909 return cfg->fratio + 1;
1912 static int arizona_calc_fll(struct arizona_fll *fll,
1913 struct arizona_fll_cfg *cfg,
1914 unsigned int Fref, bool sync)
1916 unsigned int target, div, gcd_fll;
1919 arizona_fll_dbg(fll, "Fref=%u Fout=%u\n", Fref, fll->fout);
1921 /* Fvco should be over the targt; don't check the upper bound */
1922 div = ARIZONA_FLL_MIN_OUTDIV;
1923 while (fll->fout * div < ARIZONA_FLL_MIN_FVCO * fll->vco_mult) {
1925 if (div > ARIZONA_FLL_MAX_OUTDIV)
1928 target = fll->fout * div / fll->vco_mult;
1931 arizona_fll_dbg(fll, "Fvco=%dHz\n", target);
1933 /* Find an appropriate FLL_FRATIO and refdiv */
1934 ratio = arizona_calc_fratio(fll, cfg, target, Fref, sync);
1938 /* Apply the division for our remaining calculations */
1939 Fref = Fref / (1 << cfg->refdiv);
1941 cfg->n = target / (ratio * Fref);
1943 if (target % (ratio * Fref)) {
1944 gcd_fll = gcd(target, ratio * Fref);
1945 arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll);
1947 cfg->theta = (target - (cfg->n * ratio * Fref))
1949 cfg->lambda = (ratio * Fref) / gcd_fll;
1955 /* Round down to 16bit range with cost of accuracy lost.
1956 * Denominator must be bigger than numerator so we only
1959 while (cfg->lambda >= (1 << 16)) {
1964 for (i = 0; i < ARRAY_SIZE(fll_gains); i++) {
1965 if (fll_gains[i].min <= Fref && Fref <= fll_gains[i].max) {
1966 cfg->gain = fll_gains[i].gain;
1970 if (i == ARRAY_SIZE(fll_gains)) {
1971 arizona_fll_err(fll, "Unable to find gain for Fref=%uHz\n",
1976 arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n",
1977 cfg->n, cfg->theta, cfg->lambda);
1978 arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
1979 cfg->fratio, cfg->fratio, cfg->outdiv, cfg->refdiv);
1980 arizona_fll_dbg(fll, "GAIN=%d\n", cfg->gain);
1986 static void arizona_apply_fll(struct arizona *arizona, unsigned int base,
1987 struct arizona_fll_cfg *cfg, int source,
1990 regmap_update_bits_async(arizona->regmap, base + 3,
1991 ARIZONA_FLL1_THETA_MASK, cfg->theta);
1992 regmap_update_bits_async(arizona->regmap, base + 4,
1993 ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda);
1994 regmap_update_bits_async(arizona->regmap, base + 5,
1995 ARIZONA_FLL1_FRATIO_MASK,
1996 cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT);
1997 regmap_update_bits_async(arizona->regmap, base + 6,
1998 ARIZONA_FLL1_CLK_REF_DIV_MASK |
1999 ARIZONA_FLL1_CLK_REF_SRC_MASK,
2000 cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
2001 source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
2004 regmap_update_bits(arizona->regmap, base + 0x7,
2005 ARIZONA_FLL1_GAIN_MASK,
2006 cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
2008 regmap_update_bits(arizona->regmap, base + 0x5,
2009 ARIZONA_FLL1_OUTDIV_MASK,
2010 cfg->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
2011 regmap_update_bits(arizona->regmap, base + 0x9,
2012 ARIZONA_FLL1_GAIN_MASK,
2013 cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
2016 regmap_update_bits_async(arizona->regmap, base + 2,
2017 ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
2018 ARIZONA_FLL1_CTRL_UPD | cfg->n);
2021 static int arizona_is_enabled_fll(struct arizona_fll *fll)
2023 struct arizona *arizona = fll->arizona;
2027 ret = regmap_read(arizona->regmap, fll->base + 1, ®);
2029 arizona_fll_err(fll, "Failed to read current state: %d\n",
2034 return reg & ARIZONA_FLL1_ENA;
2037 static int arizona_enable_fll(struct arizona_fll *fll)
2039 struct arizona *arizona = fll->arizona;
2040 bool use_sync = false;
2041 int already_enabled = arizona_is_enabled_fll(fll);
2042 struct arizona_fll_cfg cfg;
2046 if (already_enabled < 0)
2047 return already_enabled;
2049 if (already_enabled) {
2050 /* Facilitate smooth refclk across the transition */
2051 regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x9,
2052 ARIZONA_FLL1_GAIN_MASK, 0);
2053 regmap_update_bits_async(fll->arizona->regmap, fll->base + 1,
2054 ARIZONA_FLL1_FREERUN,
2055 ARIZONA_FLL1_FREERUN);
2059 * If we have both REFCLK and SYNCCLK then enable both,
2060 * otherwise apply the SYNCCLK settings to REFCLK.
2062 if (fll->ref_src >= 0 && fll->ref_freq &&
2063 fll->ref_src != fll->sync_src) {
2064 arizona_calc_fll(fll, &cfg, fll->ref_freq, false);
2066 arizona_apply_fll(arizona, fll->base, &cfg, fll->ref_src,
2068 if (fll->sync_src >= 0) {
2069 arizona_calc_fll(fll, &cfg, fll->sync_freq, true);
2071 arizona_apply_fll(arizona, fll->base + 0x10, &cfg,
2072 fll->sync_src, true);
2075 } else if (fll->sync_src >= 0) {
2076 arizona_calc_fll(fll, &cfg, fll->sync_freq, false);
2078 arizona_apply_fll(arizona, fll->base, &cfg,
2079 fll->sync_src, false);
2081 regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
2082 ARIZONA_FLL1_SYNC_ENA, 0);
2084 arizona_fll_err(fll, "No clocks provided\n");
2089 * Increase the bandwidth if we're not using a low frequency
2092 if (use_sync && fll->sync_freq > 100000)
2093 regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
2094 ARIZONA_FLL1_SYNC_BW, 0);
2096 regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
2097 ARIZONA_FLL1_SYNC_BW,
2098 ARIZONA_FLL1_SYNC_BW);
2100 if (!already_enabled)
2101 pm_runtime_get(arizona->dev);
2103 regmap_update_bits_async(arizona->regmap, fll->base + 1,
2104 ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
2106 regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
2107 ARIZONA_FLL1_SYNC_ENA,
2108 ARIZONA_FLL1_SYNC_ENA);
2110 if (already_enabled)
2111 regmap_update_bits_async(arizona->regmap, fll->base + 1,
2112 ARIZONA_FLL1_FREERUN, 0);
2114 arizona_fll_dbg(fll, "Waiting for FLL lock...\n");
2116 for (i = 0; i < 15; i++) {
2118 usleep_range(200, 400);
2122 regmap_read(arizona->regmap,
2123 ARIZONA_INTERRUPT_RAW_STATUS_5,
2125 if (val & (ARIZONA_FLL1_CLOCK_OK_STS << (fll->id - 1)))
2129 arizona_fll_warn(fll, "Timed out waiting for lock\n");
2131 arizona_fll_dbg(fll, "FLL locked (%d polls)\n", i);
2136 static void arizona_disable_fll(struct arizona_fll *fll)
2138 struct arizona *arizona = fll->arizona;
2141 regmap_update_bits_async(arizona->regmap, fll->base + 1,
2142 ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN);
2143 regmap_update_bits_check(arizona->regmap, fll->base + 1,
2144 ARIZONA_FLL1_ENA, 0, &change);
2145 regmap_update_bits(arizona->regmap, fll->base + 0x11,
2146 ARIZONA_FLL1_SYNC_ENA, 0);
2147 regmap_update_bits_async(arizona->regmap, fll->base + 1,
2148 ARIZONA_FLL1_FREERUN, 0);
2151 pm_runtime_put_autosuspend(arizona->dev);
2154 int arizona_set_fll_refclk(struct arizona_fll *fll, int source,
2155 unsigned int Fref, unsigned int Fout)
2159 if (fll->ref_src == source && fll->ref_freq == Fref)
2162 if (fll->fout && Fref > 0) {
2163 ret = arizona_validate_fll(fll, Fref, fll->fout);
2168 fll->ref_src = source;
2169 fll->ref_freq = Fref;
2171 if (fll->fout && Fref > 0) {
2172 ret = arizona_enable_fll(fll);
2177 EXPORT_SYMBOL_GPL(arizona_set_fll_refclk);
2179 int arizona_set_fll(struct arizona_fll *fll, int source,
2180 unsigned int Fref, unsigned int Fout)
2184 if (fll->sync_src == source &&
2185 fll->sync_freq == Fref && fll->fout == Fout)
2189 if (fll->ref_src >= 0) {
2190 ret = arizona_validate_fll(fll, fll->ref_freq, Fout);
2195 ret = arizona_validate_fll(fll, Fref, Fout);
2200 fll->sync_src = source;
2201 fll->sync_freq = Fref;
2205 ret = arizona_enable_fll(fll);
2207 arizona_disable_fll(fll);
2211 EXPORT_SYMBOL_GPL(arizona_set_fll);
2213 int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
2214 int ok_irq, struct arizona_fll *fll)
2220 fll->arizona = arizona;
2221 fll->sync_src = ARIZONA_FLL_SRC_NONE;
2223 /* Configure default refclk to 32kHz if we have one */
2224 regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val);
2225 switch (val & ARIZONA_CLK_32K_SRC_MASK) {
2226 case ARIZONA_CLK_SRC_MCLK1:
2227 case ARIZONA_CLK_SRC_MCLK2:
2228 fll->ref_src = val & ARIZONA_CLK_32K_SRC_MASK;
2231 fll->ref_src = ARIZONA_FLL_SRC_NONE;
2233 fll->ref_freq = 32768;
2235 snprintf(fll->lock_name, sizeof(fll->lock_name), "FLL%d lock", id);
2236 snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name),
2237 "FLL%d clock OK", id);
2239 regmap_update_bits(arizona->regmap, fll->base + 1,
2240 ARIZONA_FLL1_FREERUN, 0);
2244 EXPORT_SYMBOL_GPL(arizona_init_fll);
2247 * arizona_set_output_mode - Set the mode of the specified output
2249 * @codec: Device to configure
2250 * @output: Output number
2251 * @diff: True to set the output to differential mode
2253 * Some systems use external analogue switches to connect more
2254 * analogue devices to the CODEC than are supported by the device. In
2255 * some systems this requires changing the switched output from single
2256 * ended to differential mode dynamically at runtime, an operation
2257 * supported using this function.
2259 * Most systems have a single static configuration and should use
2260 * platform data instead.
2262 int arizona_set_output_mode(struct snd_soc_codec *codec, int output, bool diff)
2264 unsigned int reg, val;
2266 if (output < 1 || output > 6)
2269 reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8;
2272 val = ARIZONA_OUT1_MONO;
2276 return snd_soc_update_bits(codec, reg, ARIZONA_OUT1_MONO, val);
2278 EXPORT_SYMBOL_GPL(arizona_set_output_mode);
2280 static const struct soc_enum arizona_adsp2_rate_enum[] = {
2281 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1,
2282 ARIZONA_DSP1_RATE_SHIFT, 0xf,
2283 ARIZONA_RATE_ENUM_SIZE,
2284 arizona_rate_text, arizona_rate_val),
2285 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1,
2286 ARIZONA_DSP1_RATE_SHIFT, 0xf,
2287 ARIZONA_RATE_ENUM_SIZE,
2288 arizona_rate_text, arizona_rate_val),
2289 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1,
2290 ARIZONA_DSP1_RATE_SHIFT, 0xf,
2291 ARIZONA_RATE_ENUM_SIZE,
2292 arizona_rate_text, arizona_rate_val),
2293 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1,
2294 ARIZONA_DSP1_RATE_SHIFT, 0xf,
2295 ARIZONA_RATE_ENUM_SIZE,
2296 arizona_rate_text, arizona_rate_val),
2299 const struct snd_kcontrol_new arizona_adsp2_rate_controls[] = {
2300 SOC_ENUM("DSP1 Rate", arizona_adsp2_rate_enum[0]),
2301 SOC_ENUM("DSP2 Rate", arizona_adsp2_rate_enum[1]),
2302 SOC_ENUM("DSP3 Rate", arizona_adsp2_rate_enum[2]),
2303 SOC_ENUM("DSP4 Rate", arizona_adsp2_rate_enum[3]),
2305 EXPORT_SYMBOL_GPL(arizona_adsp2_rate_controls);
2307 static bool arizona_eq_filter_unstable(bool mode, __be16 _a, __be16 _b)
2309 s16 a = be16_to_cpu(_a);
2310 s16 b = be16_to_cpu(_b);
2313 return abs(a) >= 4096;
2318 return (abs((a << 16) / (4096 - b)) >= 4096 << 4);
2322 int arizona_eq_coeff_put(struct snd_kcontrol *kcontrol,
2323 struct snd_ctl_elem_value *ucontrol)
2325 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2326 struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
2327 struct soc_bytes *params = (void *)kcontrol->private_value;
2333 len = params->num_regs * regmap_get_val_bytes(arizona->regmap);
2335 data = kmemdup(ucontrol->value.bytes.data, len, GFP_KERNEL | GFP_DMA);
2339 data[0] &= cpu_to_be16(ARIZONA_EQ1_B1_MODE);
2341 if (arizona_eq_filter_unstable(!!data[0], data[1], data[2]) ||
2342 arizona_eq_filter_unstable(true, data[4], data[5]) ||
2343 arizona_eq_filter_unstable(true, data[8], data[9]) ||
2344 arizona_eq_filter_unstable(true, data[12], data[13]) ||
2345 arizona_eq_filter_unstable(false, data[16], data[17])) {
2346 dev_err(arizona->dev, "Rejecting unstable EQ coefficients\n");
2351 ret = regmap_read(arizona->regmap, params->base, &val);
2355 val &= ~ARIZONA_EQ1_B1_MODE;
2356 data[0] |= cpu_to_be16(val);
2358 ret = regmap_raw_write(arizona->regmap, params->base, data, len);
2364 EXPORT_SYMBOL_GPL(arizona_eq_coeff_put);
2366 int arizona_lhpf_coeff_put(struct snd_kcontrol *kcontrol,
2367 struct snd_ctl_elem_value *ucontrol)
2369 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2370 struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
2371 __be16 *data = (__be16 *)ucontrol->value.bytes.data;
2372 s16 val = be16_to_cpu(*data);
2374 if (abs(val) >= 4096) {
2375 dev_err(arizona->dev, "Rejecting unstable LHPF coefficients\n");
2379 return snd_soc_bytes_put(kcontrol, ucontrol);
2381 EXPORT_SYMBOL_GPL(arizona_lhpf_coeff_put);
2383 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
2384 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2385 MODULE_LICENSE("GPL");